2 * Copyright (C) 2010 - 2011 Samsung Electronics Co., Ltd.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
14 #include <linux/platform_device.h>
15 #include <linux/sched.h>
16 #include <linux/spinlock.h>
17 #include <linux/types.h>
18 #include <linux/videodev2.h>
21 #include <media/media-entity.h>
22 #include <media/videobuf2-core.h>
23 #include <media/v4l2-ctrls.h>
24 #include <media/v4l2-device.h>
25 #include <media/v4l2-mem2mem.h>
26 #include <media/v4l2-mediabus.h>
27 #include <media/s5p_fimc.h>
29 #include "regs-fimc.h"
31 #define err(fmt, args...) \
32 printk(KERN_ERR "%s:%d: " fmt "\n", __func__, __LINE__, ##args)
34 #define dbg(fmt, args...) \
35 pr_debug("%s:%d: " fmt "\n", __func__, __LINE__, ##args)
37 /* Time to wait for next frame VSYNC interrupt while stopping operation. */
38 #define FIMC_SHUTDOWN_TIMEOUT ((100*HZ)/1000)
39 #define MAX_FIMC_CLOCKS 2
40 #define FIMC_MODULE_NAME "s5p-fimc"
41 #define FIMC_MAX_DEVS 4
42 #define FIMC_MAX_OUT_BUFS 4
43 #define SCALER_MAX_HRATIO 64
44 #define SCALER_MAX_VRATIO 64
45 #define DMA_MIN_SIZE 8
47 /* indices to the clocks array */
69 #define fimc_m2m_active(dev) test_bit(ST_M2M_RUN, &(dev)->state)
70 #define fimc_m2m_pending(dev) test_bit(ST_M2M_PEND, &(dev)->state)
72 #define fimc_capture_running(dev) test_bit(ST_CAPT_RUN, &(dev)->state)
73 #define fimc_capture_pending(dev) test_bit(ST_CAPT_PEND, &(dev)->state)
74 #define fimc_capture_busy(dev) test_bit(ST_CAPT_BUSY, &(dev)->state)
84 S5P_FIMC_RGB565 = 0x10,
88 S5P_FIMC_YCBCR420 = 0x20,
93 S5P_FIMC_YCBCR444_LOCAL,
96 #define fimc_fmt_is_rgb(x) ((x) & 0x10)
98 /* Cb/Cr chrominance components order for 2 plane Y/CbCr 4:2:2 formats. */
99 #define S5P_FIMC_LSB_CRCB S5P_CIOCTRL_ORDER422_2P_LSB_CRCB
101 /* The embedded image effect selection */
102 #define S5P_FIMC_EFFECT_ORIGINAL S5P_CIIMGEFF_FIN_BYPASS
103 #define S5P_FIMC_EFFECT_ARBITRARY S5P_CIIMGEFF_FIN_ARBITRARY
104 #define S5P_FIMC_EFFECT_NEGATIVE S5P_CIIMGEFF_FIN_NEGATIVE
105 #define S5P_FIMC_EFFECT_ARTFREEZE S5P_CIIMGEFF_FIN_ARTFREEZE
106 #define S5P_FIMC_EFFECT_EMBOSSING S5P_CIIMGEFF_FIN_EMBOSSING
107 #define S5P_FIMC_EFFECT_SIKHOUETTE S5P_CIIMGEFF_FIN_SILHOUETTE
109 /* The hardware context state. */
110 #define FIMC_PARAMS (1 << 0)
111 #define FIMC_SRC_ADDR (1 << 1)
112 #define FIMC_DST_ADDR (1 << 2)
113 #define FIMC_SRC_FMT (1 << 3)
114 #define FIMC_DST_FMT (1 << 4)
115 #define FIMC_CTX_M2M (1 << 5)
116 #define FIMC_CTX_CAP (1 << 6)
117 #define FIMC_CTX_SHUT (1 << 7)
119 /* Image conversion flags */
120 #define FIMC_IN_DMA_ACCESS_TILED (1 << 0)
121 #define FIMC_IN_DMA_ACCESS_LINEAR (0 << 0)
122 #define FIMC_OUT_DMA_ACCESS_TILED (1 << 1)
123 #define FIMC_OUT_DMA_ACCESS_LINEAR (0 << 1)
124 #define FIMC_SCAN_MODE_PROGRESSIVE (0 << 2)
125 #define FIMC_SCAN_MODE_INTERLACED (1 << 2)
127 * YCbCr data dynamic range for RGB-YUV color conversion.
128 * Y/Cb/Cr: (0 ~ 255) */
129 #define FIMC_COLOR_RANGE_WIDE (0 << 3)
130 /* Y (16 ~ 235), Cb/Cr (16 ~ 240) */
131 #define FIMC_COLOR_RANGE_NARROW (1 << 3)
134 * struct fimc_fmt - the driver's internal color format data
135 * @mbus_code: Media Bus pixel code, -1 if not applicable
136 * @name: format description
137 * @fourcc: the fourcc code for this format, 0 if not applicable
138 * @color: the corresponding fimc_color_fmt
139 * @memplanes: number of physically non-contiguous data planes
140 * @colplanes: number of physically contiguous data planes
141 * @depth: per plane driver's private 'number of bits per pixel'
142 * @flags: flags indicating which operation mode format applies to
145 enum v4l2_mbus_pixelcode mbus_code;
151 u8 depth[VIDEO_MAX_PLANES];
153 #define FMT_FLAGS_CAM (1 << 0)
154 #define FMT_FLAGS_M2M (1 << 1)
158 * struct fimc_dma_offset - pixel offset information for DMA
159 * @y_h: y value horizontal offset
160 * @y_v: y value vertical offset
161 * @cb_h: cb value horizontal offset
162 * @cb_v: cb value vertical offset
163 * @cr_h: cr value horizontal offset
164 * @cr_v: cr value vertical offset
166 struct fimc_dma_offset {
176 * struct fimc_effect - color effect information
178 * @pat_cb: cr value when type is "arbitrary"
179 * @pat_cr: cr value when type is "arbitrary"
188 * struct fimc_scaler - the configuration data for FIMC inetrnal scaler
189 * @scaleup_h: flag indicating scaling up horizontally
190 * @scaleup_v: flag indicating scaling up vertically
191 * @copy_mode: flag indicating transparent DMA transfer (no scaling
192 * and color format conversion)
193 * @enabled: flag indicating if the scaler is used
194 * @hfactor: horizontal shift factor
195 * @vfactor: vertical shift factor
196 * @pre_hratio: horizontal ratio of the prescaler
197 * @pre_vratio: vertical ratio of the prescaler
198 * @pre_dst_width: the prescaler's destination width
199 * @pre_dst_height: the prescaler's destination height
200 * @main_hratio: the main scaler's horizontal ratio
201 * @main_vratio: the main scaler's vertical ratio
202 * @real_width: source pixel (width - offset)
203 * @real_height: source pixel (height - offset)
206 unsigned int scaleup_h:1;
207 unsigned int scaleup_v:1;
208 unsigned int copy_mode:1;
209 unsigned int enabled:1;
223 * struct fimc_addr - the FIMC physical address set for DMA
224 * @y: luminance plane physical address
225 * @cb: Cb plane physical address
226 * @cr: Cr plane physical address
235 * struct fimc_vid_buffer - the driver's video buffer
236 * @vb: v4l videobuf buffer
237 * @list: linked list structure for buffer queue
238 * @paddr: precalculated physical address set
239 * @index: buffer index for the output DMA engine
241 struct fimc_vid_buffer {
242 struct vb2_buffer vb;
243 struct list_head list;
244 struct fimc_addr paddr;
249 * struct fimc_frame - source/target frame properties
250 * @f_width: image full width (virtual screen size)
251 * @f_height: image full height (virtual screen size)
252 * @o_width: original image width as set by S_FMT
253 * @o_height: original image height as set by S_FMT
254 * @offs_h: image horizontal pixel offset
255 * @offs_v: image vertical pixel offset
256 * @width: image pixel width
257 * @height: image pixel weight
258 * @payload: image size in bytes (w x h x bpp)
259 * @paddr: image frame buffer physical addresses
260 * @dma_offset: DMA offset in bytes
261 * @fmt: fimc color format pointer
272 unsigned long payload[VIDEO_MAX_PLANES];
273 struct fimc_addr paddr;
274 struct fimc_dma_offset dma_offset;
275 struct fimc_fmt *fmt;
279 * struct fimc_m2m_device - v4l2 memory-to-memory device data
280 * @vfd: the video device node for v4l2 m2m mode
281 * @m2m_dev: v4l2 memory-to-memory device data
282 * @ctx: hardware context data
283 * @refcnt: the reference counter
285 struct fimc_m2m_device {
286 struct video_device *vfd;
287 struct v4l2_m2m_dev *m2m_dev;
288 struct fimc_ctx *ctx;
293 * struct fimc_vid_cap - camera capture device information
294 * @ctx: hardware context data
295 * @vfd: video device node for camera capture mode
296 * @sd: pointer to camera sensor subdevice currently in use
297 * @vd_pad: fimc video capture node pad
298 * @fmt: Media Bus format configured at selected image sensor
299 * @pending_buf_q: the pending buffer queue head
300 * @active_buf_q: the queue head of buffers scheduled in hardware
301 * @vbq: the capture am video buffer queue
302 * @active_buf_cnt: number of video buffers scheduled in hardware
303 * @buf_index: index for managing the output DMA buffers
304 * @frame_count: the frame counter for statistics
305 * @reqbufs_count: the number of buffers requested in REQBUFS ioctl
306 * @input_index: input (camera sensor) index
307 * @refcnt: driver's private reference counter
308 * @user_subdev_api: true if subdevs are not configured by the host driver
310 struct fimc_vid_cap {
311 struct fimc_ctx *ctx;
312 struct vb2_alloc_ctx *alloc_ctx;
313 struct video_device *vfd;
314 struct v4l2_subdev *sd;;
315 struct media_pad vd_pad;
316 struct v4l2_mbus_framefmt fmt;
317 struct list_head pending_buf_q;
318 struct list_head active_buf_q;
319 struct vb2_queue vbq;
322 unsigned int frame_count;
323 unsigned int reqbufs_count;
326 bool user_subdev_api;
330 * struct fimc_pix_limit - image pixel size limits in various IP configurations
332 * @scaler_en_w: max input pixel width when the scaler is enabled
333 * @scaler_dis_w: max input pixel width when the scaler is disabled
334 * @in_rot_en_h: max input width with the input rotator is on
335 * @in_rot_dis_w: max input width with the input rotator is off
336 * @out_rot_en_w: max output width with the output rotator on
337 * @out_rot_dis_w: max output width with the output rotator off
339 struct fimc_pix_limit {
349 * struct samsung_fimc_variant - camera interface variant information
351 * @pix_hoff: indicate whether horizontal offset is in pixels or in bytes
352 * @has_inp_rot: set if has input rotator
353 * @has_out_rot: set if has output rotator
354 * @has_cistatus2: 1 if CISTATUS2 register is present in this IP revision
355 * @has_mainscaler_ext: 1 if extended mainscaler ratios in CIEXTEN register
356 * are present in this IP revision
357 * @has_cam_if: set if this instance has a camera input interface
358 * @pix_limit: pixel size constraints for the scaler
359 * @min_inp_pixsize: minimum input pixel size
360 * @min_out_pixsize: minimum output pixel size
361 * @hor_offs_align: horizontal pixel offset aligment
362 * @out_buf_count: the number of buffers in output DMA sequence
364 struct samsung_fimc_variant {
365 unsigned int pix_hoff:1;
366 unsigned int has_inp_rot:1;
367 unsigned int has_out_rot:1;
368 unsigned int has_cistatus2:1;
369 unsigned int has_mainscaler_ext:1;
370 unsigned int has_cam_if:1;
371 struct fimc_pix_limit *pix_limit;
379 * struct samsung_fimc_driverdata - per device type driver data for init time.
381 * @variant: the variant information for this driver.
382 * @dev_cnt: number of fimc sub-devices available in SoC
383 * @lclk_frequency: fimc bus clock frequency
385 struct samsung_fimc_driverdata {
386 struct samsung_fimc_variant *variant[FIMC_MAX_DEVS];
387 unsigned long lclk_frequency;
391 struct fimc_pipeline {
392 struct media_pipeline *pipe;
393 struct v4l2_subdev *sensor;
394 struct v4l2_subdev *csis;
400 * struct fimc_dev - abstraction for FIMC entity
401 * @slock: the spinlock protecting this data structure
402 * @lock: the mutex protecting this data structure
403 * @pdev: pointer to the FIMC platform device
404 * @pdata: pointer to the device platform data
405 * @variant: the IP variant information
406 * @id: FIMC device index (0..FIMC_MAX_DEVS)
407 * @num_clocks: the number of clocks managed by this device instance
408 * @clock: clocks required for FIMC operation
409 * @regs: the mapped hardware registers
410 * @regs_res: the resource claimed for IO registers
411 * @irq: FIMC interrupt number
412 * @irq_queue: interrupt handler waitqueue
413 * @v4l2_dev: root v4l2_device
414 * @m2m: memory-to-memory V4L2 device information
415 * @vid_cap: camera capture device information
416 * @state: flags used to synchronize m2m and capture mode operation
417 * @alloc_ctx: videobuf2 memory allocator context
418 * @pipeline: fimc video capture pipeline data structure
423 struct platform_device *pdev;
424 struct s5p_platform_fimc *pdata;
425 struct samsung_fimc_variant *variant;
428 struct clk *clock[MAX_FIMC_CLOCKS];
430 struct resource *regs_res;
432 wait_queue_head_t irq_queue;
433 struct v4l2_device *v4l2_dev;
434 struct fimc_m2m_device m2m;
435 struct fimc_vid_cap vid_cap;
437 struct vb2_alloc_ctx *alloc_ctx;
438 struct fimc_pipeline pipeline;
442 * fimc_ctx - the device context data
443 * @slock: spinlock protecting this data structure
444 * @s_frame: source frame properties
445 * @d_frame: destination frame properties
446 * @out_order_1p: output 1-plane YCBCR order
447 * @out_order_2p: output 2-plane YCBCR order
448 * @in_order_1p input 1-plane YCBCR order
449 * @in_order_2p: input 2-plane YCBCR order
450 * @in_path: input mode (DMA or camera)
451 * @out_path: output mode (DMA or FIFO)
452 * @scaler: image scaler properties
453 * @effect: image effect
454 * @rotation: image clockwise rotation in degrees
455 * @hflip: indicates image horizontal flip if set
456 * @vflip: indicates image vertical flip if set
457 * @flags: additional flags for image conversion
458 * @state: flags to keep track of user configuration
459 * @fimc_dev: the FIMC device this context applies to
460 * @m2m_ctx: memory-to-memory device context
461 * @fh: v4l2 file handle
462 * @ctrl_handler: v4l2 controls handler
463 * @ctrl_rotate image rotation control
464 * @ctrl_hflip horizontal flip control
465 * @ctrl_vflip vartical flip control
466 * @ctrls_rdy: true if the control handler is initialized
470 struct fimc_frame s_frame;
471 struct fimc_frame d_frame;
476 enum fimc_datapath in_path;
477 enum fimc_datapath out_path;
478 struct fimc_scaler scaler;
479 struct fimc_effect effect;
481 unsigned int hflip:1;
482 unsigned int vflip:1;
485 struct fimc_dev *fimc_dev;
486 struct v4l2_m2m_ctx *m2m_ctx;
488 struct v4l2_ctrl_handler ctrl_handler;
489 struct v4l2_ctrl *ctrl_rotate;
490 struct v4l2_ctrl *ctrl_hflip;
491 struct v4l2_ctrl *ctrl_vflip;
495 #define fh_to_ctx(__fh) container_of(__fh, struct fimc_ctx, fh)
497 static inline bool fimc_capture_active(struct fimc_dev *fimc)
502 spin_lock_irqsave(&fimc->slock, flags);
503 ret = !!(fimc->state & (1 << ST_CAPT_RUN) ||
504 fimc->state & (1 << ST_CAPT_PEND));
505 spin_unlock_irqrestore(&fimc->slock, flags);
509 static inline void fimc_ctx_state_lock_set(u32 state, struct fimc_ctx *ctx)
513 spin_lock_irqsave(&ctx->slock, flags);
515 spin_unlock_irqrestore(&ctx->slock, flags);
518 static inline bool fimc_ctx_state_is_set(u32 mask, struct fimc_ctx *ctx)
523 spin_lock_irqsave(&ctx->slock, flags);
524 ret = (ctx->state & mask) == mask;
525 spin_unlock_irqrestore(&ctx->slock, flags);
529 static inline int tiled_fmt(struct fimc_fmt *fmt)
531 return fmt->fourcc == V4L2_PIX_FMT_NV12MT;
534 static inline void fimc_hw_clear_irq(struct fimc_dev *dev)
536 u32 cfg = readl(dev->regs + S5P_CIGCTRL);
537 cfg |= S5P_CIGCTRL_IRQ_CLR;
538 writel(cfg, dev->regs + S5P_CIGCTRL);
541 static inline void fimc_hw_enable_scaler(struct fimc_dev *dev, bool on)
543 u32 cfg = readl(dev->regs + S5P_CISCCTRL);
545 cfg |= S5P_CISCCTRL_SCALERSTART;
547 cfg &= ~S5P_CISCCTRL_SCALERSTART;
548 writel(cfg, dev->regs + S5P_CISCCTRL);
551 static inline void fimc_hw_activate_input_dma(struct fimc_dev *dev, bool on)
553 u32 cfg = readl(dev->regs + S5P_MSCTRL);
555 cfg |= S5P_MSCTRL_ENVID;
557 cfg &= ~S5P_MSCTRL_ENVID;
558 writel(cfg, dev->regs + S5P_MSCTRL);
561 static inline void fimc_hw_dis_capture(struct fimc_dev *dev)
563 u32 cfg = readl(dev->regs + S5P_CIIMGCPT);
564 cfg &= ~(S5P_CIIMGCPT_IMGCPTEN | S5P_CIIMGCPT_IMGCPTEN_SC);
565 writel(cfg, dev->regs + S5P_CIIMGCPT);
569 * fimc_hw_set_dma_seq - configure output DMA buffer sequence
570 * @mask: each bit corresponds to one of 32 output buffer registers set
571 * 1 to include buffer in the sequence, 0 to disable
573 * This function mask output DMA ring buffers, i.e. it allows to configure
574 * which of the output buffer address registers will be used by the DMA
577 static inline void fimc_hw_set_dma_seq(struct fimc_dev *dev, u32 mask)
579 writel(mask, dev->regs + S5P_CIFCNTSEQ);
582 static inline struct fimc_frame *ctx_get_frame(struct fimc_ctx *ctx,
583 enum v4l2_buf_type type)
585 struct fimc_frame *frame;
587 if (V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE == type) {
588 if (fimc_ctx_state_is_set(FIMC_CTX_M2M, ctx))
589 frame = &ctx->s_frame;
591 return ERR_PTR(-EINVAL);
592 } else if (V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE == type) {
593 frame = &ctx->d_frame;
595 v4l2_err(ctx->fimc_dev->v4l2_dev,
596 "Wrong buffer/video queue type (%d)\n", type);
597 return ERR_PTR(-EINVAL);
603 /* Return an index to the buffer actually being written. */
604 static inline u32 fimc_hw_get_frame_index(struct fimc_dev *dev)
608 if (dev->variant->has_cistatus2) {
609 reg = readl(dev->regs + S5P_CISTATUS2) & 0x3F;
610 return reg > 0 ? --reg : reg;
612 reg = readl(dev->regs + S5P_CISTATUS);
613 return (reg & S5P_CISTATUS_FRAMECNT_MASK) >>
614 S5P_CISTATUS_FRAMECNT_SHIFT;
618 /* -----------------------------------------------------*/
620 void fimc_hw_reset(struct fimc_dev *fimc);
621 void fimc_hw_set_rotation(struct fimc_ctx *ctx);
622 void fimc_hw_set_target_format(struct fimc_ctx *ctx);
623 void fimc_hw_set_out_dma(struct fimc_ctx *ctx);
624 void fimc_hw_en_lastirq(struct fimc_dev *fimc, int enable);
625 void fimc_hw_en_irq(struct fimc_dev *fimc, int enable);
626 void fimc_hw_set_prescaler(struct fimc_ctx *ctx);
627 void fimc_hw_set_mainscaler(struct fimc_ctx *ctx);
628 void fimc_hw_en_capture(struct fimc_ctx *ctx);
629 void fimc_hw_set_effect(struct fimc_ctx *ctx);
630 void fimc_hw_set_in_dma(struct fimc_ctx *ctx);
631 void fimc_hw_set_input_path(struct fimc_ctx *ctx);
632 void fimc_hw_set_output_path(struct fimc_ctx *ctx);
633 void fimc_hw_set_input_addr(struct fimc_dev *fimc, struct fimc_addr *paddr);
634 void fimc_hw_set_output_addr(struct fimc_dev *fimc, struct fimc_addr *paddr,
636 int fimc_hw_set_camera_source(struct fimc_dev *fimc,
637 struct s5p_fimc_isp_info *cam);
638 int fimc_hw_set_camera_offset(struct fimc_dev *fimc, struct fimc_frame *f);
639 int fimc_hw_set_camera_polarity(struct fimc_dev *fimc,
640 struct s5p_fimc_isp_info *cam);
641 int fimc_hw_set_camera_type(struct fimc_dev *fimc,
642 struct s5p_fimc_isp_info *cam);
644 /* -----------------------------------------------------*/
646 int fimc_vidioc_enum_fmt_mplane(struct file *file, void *priv,
647 struct v4l2_fmtdesc *f);
648 int fimc_try_fmt_mplane(struct fimc_ctx *ctx, struct v4l2_format *f);
649 int fimc_try_crop(struct fimc_ctx *ctx, struct v4l2_crop *cr);
650 int fimc_ctrls_create(struct fimc_ctx *ctx);
651 void fimc_ctrls_delete(struct fimc_ctx *ctx);
652 void fimc_ctrls_activate(struct fimc_ctx *ctx, bool active);
653 int fimc_fill_format(struct fimc_frame *frame, struct v4l2_format *f);
655 struct fimc_fmt *find_format(struct v4l2_format *f, unsigned int mask);
656 struct fimc_fmt *find_mbus_format(struct v4l2_mbus_framefmt *f,
659 int fimc_check_scaler_ratio(int sw, int sh, int dw, int dh, int rot);
660 int fimc_set_scaler_info(struct fimc_ctx *ctx);
661 int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags);
662 int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
663 struct fimc_frame *frame, struct fimc_addr *paddr);
664 int fimc_register_m2m_device(struct fimc_dev *fimc,
665 struct v4l2_device *v4l2_dev);
666 void fimc_unregister_m2m_device(struct fimc_dev *fimc);
667 int fimc_register_driver(void);
668 void fimc_unregister_driver(void);
670 /* -----------------------------------------------------*/
672 int fimc_register_capture_device(struct fimc_dev *fimc,
673 struct v4l2_device *v4l2_dev);
674 void fimc_unregister_capture_device(struct fimc_dev *fimc);
675 int fimc_capture_ctrls_create(struct fimc_dev *fimc);
676 int fimc_vid_cap_buf_queue(struct fimc_dev *fimc,
677 struct fimc_vid_buffer *fimc_vb);
678 int fimc_capture_suspend(struct fimc_dev *fimc);
679 int fimc_capture_resume(struct fimc_dev *fimc);
681 /* Locking: the caller holds fimc->slock */
682 static inline void fimc_activate_capture(struct fimc_ctx *ctx)
684 fimc_hw_enable_scaler(ctx->fimc_dev, ctx->scaler.enabled);
685 fimc_hw_en_capture(ctx);
688 static inline void fimc_deactivate_capture(struct fimc_dev *fimc)
690 fimc_hw_en_lastirq(fimc, true);
691 fimc_hw_dis_capture(fimc);
692 fimc_hw_enable_scaler(fimc, false);
693 fimc_hw_en_lastirq(fimc, false);
697 * Add buf to the capture active buffers queue.
698 * Locking: Need to be called with fimc_dev::slock held.
700 static inline void active_queue_add(struct fimc_vid_cap *vid_cap,
701 struct fimc_vid_buffer *buf)
703 list_add_tail(&buf->list, &vid_cap->active_buf_q);
704 vid_cap->active_buf_cnt++;
708 * Pop a video buffer from the capture active buffers queue
709 * Locking: Need to be called with fimc_dev::slock held.
711 static inline struct fimc_vid_buffer *
712 active_queue_pop(struct fimc_vid_cap *vid_cap)
714 struct fimc_vid_buffer *buf;
715 buf = list_entry(vid_cap->active_buf_q.next,
716 struct fimc_vid_buffer, list);
717 list_del(&buf->list);
718 vid_cap->active_buf_cnt--;
722 /* Add video buffer to the capture pending buffers queue */
723 static inline void fimc_pending_queue_add(struct fimc_vid_cap *vid_cap,
724 struct fimc_vid_buffer *buf)
726 list_add_tail(&buf->list, &vid_cap->pending_buf_q);
729 /* Add video buffer to the capture pending buffers queue */
730 static inline struct fimc_vid_buffer *
731 pending_queue_pop(struct fimc_vid_cap *vid_cap)
733 struct fimc_vid_buffer *buf;
734 buf = list_entry(vid_cap->pending_buf_q.next,
735 struct fimc_vid_buffer, list);
736 list_del(&buf->list);
740 #endif /* FIMC_CORE_H_ */