2 * OmniVision OV96xx Camera Driver
4 * Copyright (C) 2009 Marek Vasut <marek.vasut@gmail.com>
6 * Based on ov772x camera driver:
8 * Copyright (C) 2008 Renesas Solutions Corp.
9 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
11 * Based on ov7670 and soc_camera_platform driver,
13 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
14 * Copyright (C) 2008 Magnus Damm
15 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/i2c.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/videodev2.h>
29 #include <media/soc_camera.h>
30 #include <media/soc_mediabus.h>
31 #include <media/v4l2-chip-ident.h>
32 #include <media/v4l2-common.h>
36 #define to_ov9640_sensor(sd) container_of(sd, struct ov9640_priv, subdev)
38 /* default register setup */
39 static const struct ov9640_reg ov9640_regs_dflt[] = {
40 { OV9640_COM5, OV9640_COM5_SYSCLK | OV9640_COM5_LONGEXP },
41 { OV9640_COM6, OV9640_COM6_OPT_BLC | OV9640_COM6_ADBLC_BIAS |
42 OV9640_COM6_FMT_RST | OV9640_COM6_ADBLC_OPTEN },
43 { OV9640_PSHFT, OV9640_PSHFT_VAL(0x01) },
44 { OV9640_ACOM, OV9640_ACOM_2X_ANALOG | OV9640_ACOM_RSVD },
45 { OV9640_TSLB, OV9640_TSLB_YUYV_UYVY },
46 { OV9640_COM16, OV9640_COM16_RB_AVG },
49 { 0x6c, 0x40 }, { 0x6d, 0x30 }, { 0x6e, 0x4b }, { 0x6f, 0x60 },
50 { 0x70, 0x70 }, { 0x71, 0x70 }, { 0x72, 0x70 }, { 0x73, 0x70 },
51 { 0x74, 0x60 }, { 0x75, 0x60 }, { 0x76, 0x50 }, { 0x77, 0x48 },
52 { 0x78, 0x3a }, { 0x79, 0x2e }, { 0x7a, 0x28 }, { 0x7b, 0x22 },
55 { 0x7c, 0x04 }, { 0x7d, 0x07 }, { 0x7e, 0x10 }, { 0x7f, 0x28 },
56 { 0x80, 0x36 }, { 0x81, 0x44 }, { 0x82, 0x52 }, { 0x83, 0x60 },
57 { 0x84, 0x6c }, { 0x85, 0x78 }, { 0x86, 0x8c }, { 0x87, 0x9e },
58 { 0x88, 0xbb }, { 0x89, 0xd2 }, { 0x8a, 0xe6 },
62 * NOTE: for YUV, alter the following registers:
63 * COM12 |= OV9640_COM12_YUV_AVG
65 * for RGB, alter the following registers:
66 * COM7 |= OV9640_COM7_RGB
67 * COM13 |= OV9640_COM13_RGB_AVG
68 * COM15 |= proper RGB color encoding mode
70 static const struct ov9640_reg ov9640_regs_qqcif[] = {
71 { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x0f) },
72 { OV9640_COM1, OV9640_COM1_QQFMT | OV9640_COM1_HREF_2SKIP },
73 { OV9640_COM4, OV9640_COM4_QQ_VP | OV9640_COM4_RSVD },
74 { OV9640_COM7, OV9640_COM7_QCIF },
75 { OV9640_COM12, OV9640_COM12_RSVD },
76 { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
77 { OV9640_COM15, OV9640_COM15_OR_10F0 },
80 static const struct ov9640_reg ov9640_regs_qqvga[] = {
81 { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x07) },
82 { OV9640_COM1, OV9640_COM1_QQFMT | OV9640_COM1_HREF_2SKIP },
83 { OV9640_COM4, OV9640_COM4_QQ_VP | OV9640_COM4_RSVD },
84 { OV9640_COM7, OV9640_COM7_QVGA },
85 { OV9640_COM12, OV9640_COM12_RSVD },
86 { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
87 { OV9640_COM15, OV9640_COM15_OR_10F0 },
90 static const struct ov9640_reg ov9640_regs_qcif[] = {
91 { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x07) },
92 { OV9640_COM4, OV9640_COM4_QQ_VP | OV9640_COM4_RSVD },
93 { OV9640_COM7, OV9640_COM7_QCIF },
94 { OV9640_COM12, OV9640_COM12_RSVD },
95 { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
96 { OV9640_COM15, OV9640_COM15_OR_10F0 },
99 static const struct ov9640_reg ov9640_regs_qvga[] = {
100 { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x03) },
101 { OV9640_COM4, OV9640_COM4_QQ_VP | OV9640_COM4_RSVD },
102 { OV9640_COM7, OV9640_COM7_QVGA },
103 { OV9640_COM12, OV9640_COM12_RSVD },
104 { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
105 { OV9640_COM15, OV9640_COM15_OR_10F0 },
108 static const struct ov9640_reg ov9640_regs_cif[] = {
109 { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x03) },
110 { OV9640_COM3, OV9640_COM3_VP },
111 { OV9640_COM7, OV9640_COM7_CIF },
112 { OV9640_COM12, OV9640_COM12_RSVD },
113 { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
114 { OV9640_COM15, OV9640_COM15_OR_10F0 },
117 static const struct ov9640_reg ov9640_regs_vga[] = {
118 { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x01) },
119 { OV9640_COM3, OV9640_COM3_VP },
120 { OV9640_COM7, OV9640_COM7_VGA },
121 { OV9640_COM12, OV9640_COM12_RSVD },
122 { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
123 { OV9640_COM15, OV9640_COM15_OR_10F0 },
126 static const struct ov9640_reg ov9640_regs_sxga[] = {
127 { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x01) },
128 { OV9640_COM3, OV9640_COM3_VP },
130 { OV9640_COM12, OV9640_COM12_RSVD },
131 { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
132 { OV9640_COM15, OV9640_COM15_OR_10F0 },
135 static const struct ov9640_reg ov9640_regs_yuv[] = {
136 { OV9640_MTX1, 0x58 },
137 { OV9640_MTX2, 0x48 },
138 { OV9640_MTX3, 0x10 },
139 { OV9640_MTX4, 0x28 },
140 { OV9640_MTX5, 0x48 },
141 { OV9640_MTX6, 0x70 },
142 { OV9640_MTX7, 0x40 },
143 { OV9640_MTX8, 0x40 },
144 { OV9640_MTX9, 0x40 },
145 { OV9640_MTXS, 0x0f },
148 static const struct ov9640_reg ov9640_regs_rgb[] = {
149 { OV9640_MTX1, 0x71 },
150 { OV9640_MTX2, 0x3e },
151 { OV9640_MTX3, 0x0c },
152 { OV9640_MTX4, 0x33 },
153 { OV9640_MTX5, 0x72 },
154 { OV9640_MTX6, 0x00 },
155 { OV9640_MTX7, 0x2b },
156 { OV9640_MTX8, 0x66 },
157 { OV9640_MTX9, 0xd2 },
158 { OV9640_MTXS, 0x65 },
161 static enum v4l2_mbus_pixelcode ov9640_codes[] = {
162 V4L2_MBUS_FMT_UYVY8_2X8,
163 V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE,
164 V4L2_MBUS_FMT_RGB565_2X8_LE,
167 static const struct v4l2_queryctrl ov9640_controls[] = {
169 .id = V4L2_CID_VFLIP,
170 .type = V4L2_CTRL_TYPE_BOOLEAN,
171 .name = "Flip Vertically",
178 .id = V4L2_CID_HFLIP,
179 .type = V4L2_CTRL_TYPE_BOOLEAN,
180 .name = "Flip Horizontally",
188 /* read a register */
189 static int ov9640_reg_read(struct i2c_client *client, u8 reg, u8 *val)
193 struct i2c_msg msg = {
194 .addr = client->addr,
200 ret = i2c_transfer(client->adapter, &msg, 1);
204 msg.flags = I2C_M_RD;
205 ret = i2c_transfer(client->adapter, &msg, 1);
213 dev_err(&client->dev, "Failed reading register 0x%02x!\n", reg);
217 /* write a register */
218 static int ov9640_reg_write(struct i2c_client *client, u8 reg, u8 val)
222 unsigned char data[2] = { reg, val };
223 struct i2c_msg msg = {
224 .addr = client->addr,
230 ret = i2c_transfer(client->adapter, &msg, 1);
232 dev_err(&client->dev, "Failed writing register 0x%02x!\n", reg);
236 /* we have to read the register back ... no idea why, maybe HW bug */
237 ret = ov9640_reg_read(client, reg, &_val);
239 dev_err(&client->dev,
240 "Failed reading back register 0x%02x!\n", reg);
246 /* Read a register, alter its bits, write it back */
247 static int ov9640_reg_rmw(struct i2c_client *client, u8 reg, u8 set, u8 unset)
252 ret = ov9640_reg_read(client, reg, &val);
254 dev_err(&client->dev,
255 "[Read]-Modify-Write of register %02x failed!\n", reg);
262 ret = ov9640_reg_write(client, reg, val);
264 dev_err(&client->dev,
265 "Read-Modify-[Write] of register %02x failed!\n", reg);
270 /* Soft reset the camera. This has nothing to do with the RESET pin! */
271 static int ov9640_reset(struct i2c_client *client)
275 ret = ov9640_reg_write(client, OV9640_COM7, OV9640_COM7_SCCB_RESET);
277 dev_err(&client->dev,
278 "An error occurred while entering soft reset!\n");
283 /* Start/Stop streaming from the device */
284 static int ov9640_s_stream(struct v4l2_subdev *sd, int enable)
289 /* Alter bus settings on camera side */
290 static int ov9640_set_bus_param(struct soc_camera_device *icd,
296 /* Request bus settings on camera side */
297 static unsigned long ov9640_query_bus_param(struct soc_camera_device *icd)
299 struct soc_camera_link *icl = to_soc_camera_link(icd);
302 * REVISIT: the camera probably can do 10 bit transfers, but I don't
303 * have those pins connected on my hardware.
305 unsigned long flags = SOCAM_PCLK_SAMPLE_RISING | SOCAM_MASTER |
306 SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_HSYNC_ACTIVE_HIGH |
307 SOCAM_DATA_ACTIVE_HIGH | SOCAM_DATAWIDTH_8;
309 return soc_camera_apply_sensor_flags(icl, flags);
312 /* Get status of additional camera capabilities */
313 static int ov9640_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
315 struct ov9640_priv *priv = to_ov9640_sensor(sd);
319 ctrl->value = priv->flag_vflip;
322 ctrl->value = priv->flag_hflip;
328 /* Set status of additional camera capabilities */
329 static int ov9640_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
331 struct i2c_client *client = v4l2_get_subdevdata(sd);
332 struct ov9640_priv *priv = to_ov9640_sensor(sd);
338 priv->flag_vflip = ctrl->value;
340 ret = ov9640_reg_rmw(client, OV9640_MVFP,
343 ret = ov9640_reg_rmw(client, OV9640_MVFP,
347 priv->flag_hflip = ctrl->value;
349 ret = ov9640_reg_rmw(client, OV9640_MVFP,
352 ret = ov9640_reg_rmw(client, OV9640_MVFP,
360 /* Get chip identification */
361 static int ov9640_g_chip_ident(struct v4l2_subdev *sd,
362 struct v4l2_dbg_chip_ident *id)
364 struct ov9640_priv *priv = to_ov9640_sensor(sd);
366 id->ident = priv->model;
367 id->revision = priv->revision;
372 #ifdef CONFIG_VIDEO_ADV_DEBUG
373 static int ov9640_get_register(struct v4l2_subdev *sd,
374 struct v4l2_dbg_register *reg)
376 struct i2c_client *client = v4l2_get_subdevdata(sd);
380 if (reg->reg & ~0xff)
385 ret = ov9640_reg_read(client, reg->reg, &val);
389 reg->val = (__u64)val;
394 static int ov9640_set_register(struct v4l2_subdev *sd,
395 struct v4l2_dbg_register *reg)
397 struct i2c_client *client = v4l2_get_subdevdata(sd);
399 if (reg->reg & ~0xff || reg->val & ~0xff)
402 return ov9640_reg_write(client, reg->reg, reg->val);
406 /* select nearest higher resolution for capture */
407 static void ov9640_res_roundup(u32 *width, u32 *height)
410 enum { QQCIF, QQVGA, QCIF, QVGA, CIF, VGA, SXGA };
411 int res_x[] = { 88, 160, 176, 320, 352, 640, 1280 };
412 int res_y[] = { 72, 120, 144, 240, 288, 480, 960 };
414 for (i = 0; i < ARRAY_SIZE(res_x); i++) {
415 if (res_x[i] >= *width && res_y[i] >= *height) {
422 *width = res_x[SXGA];
423 *height = res_y[SXGA];
426 /* Prepare necessary register changes depending on color encoding */
427 static void ov9640_alter_regs(enum v4l2_mbus_pixelcode code,
428 struct ov9640_reg_alt *alt)
432 case V4L2_MBUS_FMT_UYVY8_2X8:
433 alt->com12 = OV9640_COM12_YUV_AVG;
434 alt->com13 = OV9640_COM13_Y_DELAY_EN |
435 OV9640_COM13_YUV_DLY(0x01);
437 case V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE:
438 alt->com7 = OV9640_COM7_RGB;
439 alt->com13 = OV9640_COM13_RGB_AVG;
440 alt->com15 = OV9640_COM15_RGB_555;
442 case V4L2_MBUS_FMT_RGB565_2X8_LE:
443 alt->com7 = OV9640_COM7_RGB;
444 alt->com13 = OV9640_COM13_RGB_AVG;
445 alt->com15 = OV9640_COM15_RGB_565;
450 /* Setup registers according to resolution and color encoding */
451 static int ov9640_write_regs(struct i2c_client *client, u32 width,
452 enum v4l2_mbus_pixelcode code, struct ov9640_reg_alt *alts)
454 const struct ov9640_reg *ov9640_regs, *matrix_regs;
455 int ov9640_regs_len, matrix_regs_len;
459 /* select register configuration for given resolution */
462 ov9640_regs = ov9640_regs_qqcif;
463 ov9640_regs_len = ARRAY_SIZE(ov9640_regs_qqcif);
466 ov9640_regs = ov9640_regs_qqvga;
467 ov9640_regs_len = ARRAY_SIZE(ov9640_regs_qqvga);
470 ov9640_regs = ov9640_regs_qcif;
471 ov9640_regs_len = ARRAY_SIZE(ov9640_regs_qcif);
474 ov9640_regs = ov9640_regs_qvga;
475 ov9640_regs_len = ARRAY_SIZE(ov9640_regs_qvga);
478 ov9640_regs = ov9640_regs_cif;
479 ov9640_regs_len = ARRAY_SIZE(ov9640_regs_cif);
482 ov9640_regs = ov9640_regs_vga;
483 ov9640_regs_len = ARRAY_SIZE(ov9640_regs_vga);
486 ov9640_regs = ov9640_regs_sxga;
487 ov9640_regs_len = ARRAY_SIZE(ov9640_regs_sxga);
490 dev_err(&client->dev, "Failed to select resolution!\n");
494 /* select color matrix configuration for given color encoding */
495 if (code == V4L2_MBUS_FMT_UYVY8_2X8) {
496 matrix_regs = ov9640_regs_yuv;
497 matrix_regs_len = ARRAY_SIZE(ov9640_regs_yuv);
499 matrix_regs = ov9640_regs_rgb;
500 matrix_regs_len = ARRAY_SIZE(ov9640_regs_rgb);
503 /* write register settings into the module */
504 for (i = 0; i < ov9640_regs_len; i++) {
505 val = ov9640_regs[i].val;
507 switch (ov9640_regs[i].reg) {
522 ret = ov9640_reg_write(client, ov9640_regs[i].reg, val);
527 /* write color matrix configuration into the module */
528 for (i = 0; i < matrix_regs_len; i++) {
529 ret = ov9640_reg_write(client, matrix_regs[i].reg,
538 /* program default register values */
539 static int ov9640_prog_dflt(struct i2c_client *client)
543 for (i = 0; i < ARRAY_SIZE(ov9640_regs_dflt); i++) {
544 ret = ov9640_reg_write(client, ov9640_regs_dflt[i].reg,
545 ov9640_regs_dflt[i].val);
550 /* wait for the changes to actually happen, 140ms are not enough yet */
556 /* set the format we will capture in */
557 static int ov9640_s_fmt(struct v4l2_subdev *sd,
558 struct v4l2_mbus_framefmt *mf)
560 struct i2c_client *client = v4l2_get_subdevdata(sd);
561 struct ov9640_reg_alt alts = {0};
562 enum v4l2_colorspace cspace;
563 enum v4l2_mbus_pixelcode code = mf->code;
566 ov9640_res_roundup(&mf->width, &mf->height);
567 ov9640_alter_regs(mf->code, &alts);
569 ov9640_reset(client);
571 ret = ov9640_prog_dflt(client);
576 case V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE:
577 case V4L2_MBUS_FMT_RGB565_2X8_LE:
578 cspace = V4L2_COLORSPACE_SRGB;
581 code = V4L2_MBUS_FMT_UYVY8_2X8;
582 case V4L2_MBUS_FMT_UYVY8_2X8:
583 cspace = V4L2_COLORSPACE_JPEG;
586 ret = ov9640_write_regs(client, mf->width, code, &alts);
589 mf->colorspace = cspace;
595 static int ov9640_try_fmt(struct v4l2_subdev *sd,
596 struct v4l2_mbus_framefmt *mf)
598 ov9640_res_roundup(&mf->width, &mf->height);
600 mf->field = V4L2_FIELD_NONE;
603 case V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE:
604 case V4L2_MBUS_FMT_RGB565_2X8_LE:
605 mf->colorspace = V4L2_COLORSPACE_SRGB;
608 mf->code = V4L2_MBUS_FMT_UYVY8_2X8;
609 case V4L2_MBUS_FMT_UYVY8_2X8:
610 mf->colorspace = V4L2_COLORSPACE_JPEG;
616 static int ov9640_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
617 enum v4l2_mbus_pixelcode *code)
619 if (index >= ARRAY_SIZE(ov9640_codes))
622 *code = ov9640_codes[index];
626 static int ov9640_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
631 a->c.height = H_SXGA;
632 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
637 static int ov9640_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
641 a->bounds.width = W_SXGA;
642 a->bounds.height = H_SXGA;
643 a->defrect = a->bounds;
644 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
645 a->pixelaspect.numerator = 1;
646 a->pixelaspect.denominator = 1;
653 static int ov9640_video_probe(struct soc_camera_device *icd,
654 struct i2c_client *client)
656 struct v4l2_subdev *sd = i2c_get_clientdata(client);
657 struct ov9640_priv *priv = to_ov9640_sensor(sd);
658 u8 pid, ver, midh, midl;
662 /* We must have a parent by now. And it cannot be a wrong one. */
663 BUG_ON(!icd->parent ||
664 to_soc_camera_host(icd->parent)->nr != icd->iface);
667 * check and show product ID and manufacturer ID
670 ret = ov9640_reg_read(client, OV9640_PID, &pid);
674 ret = ov9640_reg_read(client, OV9640_VER, &ver);
678 ret = ov9640_reg_read(client, OV9640_MIDH, &midh);
682 ret = ov9640_reg_read(client, OV9640_MIDL, &midl);
686 switch (VERSION(pid, ver)) {
689 priv->model = V4L2_IDENT_OV9640;
693 priv->model = V4L2_IDENT_OV9640;
697 dev_err(&client->dev, "Product ID error %x:%x\n", pid, ver);
702 dev_info(&client->dev, "%s Product ID %0x:%0x Manufacturer ID %x:%x\n",
703 devname, pid, ver, midh, midl);
709 static struct soc_camera_ops ov9640_ops = {
710 .set_bus_param = ov9640_set_bus_param,
711 .query_bus_param = ov9640_query_bus_param,
712 .controls = ov9640_controls,
713 .num_controls = ARRAY_SIZE(ov9640_controls),
716 static struct v4l2_subdev_core_ops ov9640_core_ops = {
717 .g_ctrl = ov9640_g_ctrl,
718 .s_ctrl = ov9640_s_ctrl,
719 .g_chip_ident = ov9640_g_chip_ident,
720 #ifdef CONFIG_VIDEO_ADV_DEBUG
721 .g_register = ov9640_get_register,
722 .s_register = ov9640_set_register,
727 static int ov9640_g_mbus_config(struct v4l2_subdev *sd,
728 struct v4l2_mbus_config *cfg)
730 struct i2c_client *client = v4l2_get_subdevdata(sd);
731 struct soc_camera_device *icd = client->dev.platform_data;
732 struct soc_camera_link *icl = to_soc_camera_link(icd);
734 cfg->flags = V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_MASTER |
735 V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_HIGH |
736 V4L2_MBUS_DATA_ACTIVE_HIGH;
737 cfg->type = V4L2_MBUS_PARALLEL;
738 cfg->flags = soc_camera_apply_board_flags(icl, cfg);
743 static struct v4l2_subdev_video_ops ov9640_video_ops = {
744 .s_stream = ov9640_s_stream,
745 .s_mbus_fmt = ov9640_s_fmt,
746 .try_mbus_fmt = ov9640_try_fmt,
747 .enum_mbus_fmt = ov9640_enum_fmt,
748 .cropcap = ov9640_cropcap,
749 .g_crop = ov9640_g_crop,
750 .g_mbus_config = ov9640_g_mbus_config,
753 static struct v4l2_subdev_ops ov9640_subdev_ops = {
754 .core = &ov9640_core_ops,
755 .video = &ov9640_video_ops,
759 * i2c_driver function
761 static int ov9640_probe(struct i2c_client *client,
762 const struct i2c_device_id *did)
764 struct ov9640_priv *priv;
765 struct soc_camera_device *icd = client->dev.platform_data;
766 struct soc_camera_link *icl;
770 dev_err(&client->dev, "Missing soc-camera data!\n");
774 icl = to_soc_camera_link(icd);
776 dev_err(&client->dev, "Missing platform_data for driver\n");
780 priv = kzalloc(sizeof(struct ov9640_priv), GFP_KERNEL);
782 dev_err(&client->dev,
783 "Failed to allocate memory for private data!\n");
787 v4l2_i2c_subdev_init(&priv->subdev, client, &ov9640_subdev_ops);
789 icd->ops = &ov9640_ops;
791 ret = ov9640_video_probe(icd, client);
801 static int ov9640_remove(struct i2c_client *client)
803 struct v4l2_subdev *sd = i2c_get_clientdata(client);
804 struct ov9640_priv *priv = to_ov9640_sensor(sd);
810 static const struct i2c_device_id ov9640_id[] = {
814 MODULE_DEVICE_TABLE(i2c, ov9640_id);
816 static struct i2c_driver ov9640_i2c_driver = {
820 .probe = ov9640_probe,
821 .remove = ov9640_remove,
822 .id_table = ov9640_id,
825 static int __init ov9640_module_init(void)
827 return i2c_add_driver(&ov9640_i2c_driver);
830 static void __exit ov9640_module_exit(void)
832 i2c_del_driver(&ov9640_i2c_driver);
835 module_init(ov9640_module_init);
836 module_exit(ov9640_module_exit);
838 MODULE_DESCRIPTION("SoC Camera driver for OmniVision OV96xx");
839 MODULE_AUTHOR("Marek Vasut <marek.vasut@gmail.com>");
840 MODULE_LICENSE("GPL v2");