2 * V4L2 Driver for i.MX27/i.MX25 camera host
4 * Copyright (C) 2008, Sascha Hauer, Pengutronix
5 * Copyright (C) 2010, Baruch Siach, Orex Computed Radiography
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/init.h>
14 #include <linux/module.h>
16 #include <linux/delay.h>
17 #include <linux/slab.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/errno.h>
21 #include <linux/interrupt.h>
22 #include <linux/kernel.h>
24 #include <linux/moduleparam.h>
25 #include <linux/time.h>
26 #include <linux/version.h>
27 #include <linux/device.h>
28 #include <linux/platform_device.h>
29 #include <linux/mutex.h>
30 #include <linux/clk.h>
32 #include <media/v4l2-common.h>
33 #include <media/v4l2-dev.h>
34 #include <media/videobuf-core.h>
35 #include <media/videobuf-dma-contig.h>
36 #include <media/soc_camera.h>
37 #include <media/soc_mediabus.h>
39 #include <linux/videodev2.h>
41 #include <mach/mx2_cam.h>
42 #ifdef CONFIG_MACH_MX27
43 #include <mach/dma-mx1-mx2.h>
45 #include <mach/hardware.h>
49 #define MX2_CAM_DRV_NAME "mx2-camera"
50 #define MX2_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5)
51 #define MX2_CAM_DRIVER_DESCRIPTION "i.MX2x_Camera"
54 #define CSICR1_RESET_VAL 0x40000800
55 #define CSICR2_RESET_VAL 0x0
56 #define CSICR3_RESET_VAL 0x0
58 /* csi control reg 1 */
59 #define CSICR1_SWAP16_EN (1 << 31)
60 #define CSICR1_EXT_VSYNC (1 << 30)
61 #define CSICR1_EOF_INTEN (1 << 29)
62 #define CSICR1_PRP_IF_EN (1 << 28)
63 #define CSICR1_CCIR_MODE (1 << 27)
64 #define CSICR1_COF_INTEN (1 << 26)
65 #define CSICR1_SF_OR_INTEN (1 << 25)
66 #define CSICR1_RF_OR_INTEN (1 << 24)
67 #define CSICR1_STATFF_LEVEL (3 << 22)
68 #define CSICR1_STATFF_INTEN (1 << 21)
69 #define CSICR1_RXFF_LEVEL(l) (((l) & 3) << 19) /* MX27 */
70 #define CSICR1_FB2_DMA_INTEN (1 << 20) /* MX25 */
71 #define CSICR1_FB1_DMA_INTEN (1 << 19) /* MX25 */
72 #define CSICR1_RXFF_INTEN (1 << 18)
73 #define CSICR1_SOF_POL (1 << 17)
74 #define CSICR1_SOF_INTEN (1 << 16)
75 #define CSICR1_MCLKDIV(d) (((d) & 0xF) << 12)
76 #define CSICR1_HSYNC_POL (1 << 11)
77 #define CSICR1_CCIR_EN (1 << 10)
78 #define CSICR1_MCLKEN (1 << 9)
79 #define CSICR1_FCC (1 << 8)
80 #define CSICR1_PACK_DIR (1 << 7)
81 #define CSICR1_CLR_STATFIFO (1 << 6)
82 #define CSICR1_CLR_RXFIFO (1 << 5)
83 #define CSICR1_GCLK_MODE (1 << 4)
84 #define CSICR1_INV_DATA (1 << 3)
85 #define CSICR1_INV_PCLK (1 << 2)
86 #define CSICR1_REDGE (1 << 1)
88 #define SHIFT_STATFF_LEVEL 22
89 #define SHIFT_RXFF_LEVEL 19
90 #define SHIFT_MCLKDIV 12
93 #define CSICR3_FRMCNT (0xFFFF << 16)
94 #define CSICR3_FRMCNT_RST (1 << 15)
95 #define CSICR3_DMA_REFLASH_RFF (1 << 14)
96 #define CSICR3_DMA_REFLASH_SFF (1 << 13)
97 #define CSICR3_DMA_REQ_EN_RFF (1 << 12)
98 #define CSICR3_DMA_REQ_EN_SFF (1 << 11)
99 #define CSICR3_RXFF_LEVEL(l) (((l) & 7) << 4) /* MX25 */
100 #define CSICR3_CSI_SUP (1 << 3)
101 #define CSICR3_ZERO_PACK_EN (1 << 2)
102 #define CSICR3_ECC_INT_EN (1 << 1)
103 #define CSICR3_ECC_AUTO_EN (1 << 0)
105 #define SHIFT_FRMCNT 16
108 #define CSISR_SFF_OR_INT (1 << 25)
109 #define CSISR_RFF_OR_INT (1 << 24)
110 #define CSISR_STATFF_INT (1 << 21)
111 #define CSISR_DMA_TSF_FB2_INT (1 << 20) /* MX25 */
112 #define CSISR_DMA_TSF_FB1_INT (1 << 19) /* MX25 */
113 #define CSISR_RXFF_INT (1 << 18)
114 #define CSISR_EOF_INT (1 << 17)
115 #define CSISR_SOF_INT (1 << 16)
116 #define CSISR_F2_INT (1 << 15)
117 #define CSISR_F1_INT (1 << 14)
118 #define CSISR_COF_INT (1 << 13)
119 #define CSISR_ECC_INT (1 << 1)
120 #define CSISR_DRDY (1 << 0)
124 #define CSISR (cpu_is_mx27() ? 0x08 : 0x18)
125 #define CSISTATFIFO 0x0c
126 #define CSIRFIFO 0x10
127 #define CSIRXCNT 0x14
128 #define CSICR3 (cpu_is_mx27() ? 0x1C : 0x08)
129 #define CSIDMASA_STATFIFO 0x20
130 #define CSIDMATA_STATFIFO 0x24
131 #define CSIDMASA_FB1 0x28
132 #define CSIDMASA_FB2 0x2c
133 #define CSIFBUF_PARA 0x30
134 #define CSIIMAG_PARA 0x34
137 #define PRP_CNTL 0x00
138 #define PRP_INTR_CNTL 0x04
139 #define PRP_INTRSTATUS 0x08
140 #define PRP_SOURCE_Y_PTR 0x0c
141 #define PRP_SOURCE_CB_PTR 0x10
142 #define PRP_SOURCE_CR_PTR 0x14
143 #define PRP_DEST_RGB1_PTR 0x18
144 #define PRP_DEST_RGB2_PTR 0x1c
145 #define PRP_DEST_Y_PTR 0x20
146 #define PRP_DEST_CB_PTR 0x24
147 #define PRP_DEST_CR_PTR 0x28
148 #define PRP_SRC_FRAME_SIZE 0x2c
149 #define PRP_DEST_CH1_LINE_STRIDE 0x30
150 #define PRP_SRC_PIXEL_FORMAT_CNTL 0x34
151 #define PRP_CH1_PIXEL_FORMAT_CNTL 0x38
152 #define PRP_CH1_OUT_IMAGE_SIZE 0x3c
153 #define PRP_CH2_OUT_IMAGE_SIZE 0x40
154 #define PRP_SRC_LINE_STRIDE 0x44
155 #define PRP_CSC_COEF_012 0x48
156 #define PRP_CSC_COEF_345 0x4c
157 #define PRP_CSC_COEF_678 0x50
158 #define PRP_CH1_RZ_HORI_COEF1 0x54
159 #define PRP_CH1_RZ_HORI_COEF2 0x58
160 #define PRP_CH1_RZ_HORI_VALID 0x5c
161 #define PRP_CH1_RZ_VERT_COEF1 0x60
162 #define PRP_CH1_RZ_VERT_COEF2 0x64
163 #define PRP_CH1_RZ_VERT_VALID 0x68
164 #define PRP_CH2_RZ_HORI_COEF1 0x6c
165 #define PRP_CH2_RZ_HORI_COEF2 0x70
166 #define PRP_CH2_RZ_HORI_VALID 0x74
167 #define PRP_CH2_RZ_VERT_COEF1 0x78
168 #define PRP_CH2_RZ_VERT_COEF2 0x7c
169 #define PRP_CH2_RZ_VERT_VALID 0x80
171 #define PRP_CNTL_CH1EN (1 << 0)
172 #define PRP_CNTL_CH2EN (1 << 1)
173 #define PRP_CNTL_CSIEN (1 << 2)
174 #define PRP_CNTL_DATA_IN_YUV420 (0 << 3)
175 #define PRP_CNTL_DATA_IN_YUV422 (1 << 3)
176 #define PRP_CNTL_DATA_IN_RGB16 (2 << 3)
177 #define PRP_CNTL_DATA_IN_RGB32 (3 << 3)
178 #define PRP_CNTL_CH1_OUT_RGB8 (0 << 5)
179 #define PRP_CNTL_CH1_OUT_RGB16 (1 << 5)
180 #define PRP_CNTL_CH1_OUT_RGB32 (2 << 5)
181 #define PRP_CNTL_CH1_OUT_YUV422 (3 << 5)
182 #define PRP_CNTL_CH2_OUT_YUV420 (0 << 7)
183 #define PRP_CNTL_CH2_OUT_YUV422 (1 << 7)
184 #define PRP_CNTL_CH2_OUT_YUV444 (2 << 7)
185 #define PRP_CNTL_CH1_LEN (1 << 9)
186 #define PRP_CNTL_CH2_LEN (1 << 10)
187 #define PRP_CNTL_SKIP_FRAME (1 << 11)
188 #define PRP_CNTL_SWRST (1 << 12)
189 #define PRP_CNTL_CLKEN (1 << 13)
190 #define PRP_CNTL_WEN (1 << 14)
191 #define PRP_CNTL_CH1BYP (1 << 15)
192 #define PRP_CNTL_IN_TSKIP(x) ((x) << 16)
193 #define PRP_CNTL_CH1_TSKIP(x) ((x) << 19)
194 #define PRP_CNTL_CH2_TSKIP(x) ((x) << 22)
195 #define PRP_CNTL_INPUT_FIFO_LEVEL(x) ((x) << 25)
196 #define PRP_CNTL_RZ_FIFO_LEVEL(x) ((x) << 27)
197 #define PRP_CNTL_CH2B1EN (1 << 29)
198 #define PRP_CNTL_CH2B2EN (1 << 30)
199 #define PRP_CNTL_CH2FEN (1 << 31)
201 /* IRQ Enable and status register */
202 #define PRP_INTR_RDERR (1 << 0)
203 #define PRP_INTR_CH1WERR (1 << 1)
204 #define PRP_INTR_CH2WERR (1 << 2)
205 #define PRP_INTR_CH1FC (1 << 3)
206 #define PRP_INTR_CH2FC (1 << 5)
207 #define PRP_INTR_LBOVF (1 << 7)
208 #define PRP_INTR_CH2OVF (1 << 8)
210 #define mx27_camera_emma(pcdev) (cpu_is_mx27() && pcdev->use_emma)
212 #define MAX_VIDEO_MEM 16
214 struct mx2_camera_dev {
216 struct soc_camera_host soc_host;
217 struct soc_camera_device *icd;
218 struct clk *clk_csi, *clk_emma;
220 unsigned int irq_csi, irq_emma;
221 void __iomem *base_csi, *base_emma;
222 unsigned long base_dma;
224 struct mx2_camera_platform_data *pdata;
225 struct resource *res_csi, *res_emma;
226 unsigned long platform_flags;
228 struct list_head capture;
229 struct list_head active_bufs;
234 struct mx2_buffer *active;
235 struct mx2_buffer *fb1_active;
236 struct mx2_buffer *fb2_active;
242 void *discard_buffer;
243 dma_addr_t discard_buffer_dma;
247 /* buffer for one video frame */
249 /* common v4l buffer stuff -- must be first */
250 struct videobuf_buffer vb;
252 enum v4l2_mbus_pixelcode code;
257 static void mx2_camera_deactivate(struct mx2_camera_dev *pcdev)
261 clk_disable(pcdev->clk_csi);
262 writel(0, pcdev->base_csi + CSICR1);
263 if (mx27_camera_emma(pcdev)) {
264 writel(0, pcdev->base_emma + PRP_CNTL);
265 } else if (cpu_is_mx25()) {
266 spin_lock_irqsave(&pcdev->lock, flags);
267 pcdev->fb1_active = NULL;
268 pcdev->fb2_active = NULL;
269 writel(0, pcdev->base_csi + CSIDMASA_FB1);
270 writel(0, pcdev->base_csi + CSIDMASA_FB2);
271 spin_unlock_irqrestore(&pcdev->lock, flags);
276 * The following two functions absolutely depend on the fact, that
277 * there can be only one camera on mx2 camera sensor interface
279 static int mx2_camera_add_device(struct soc_camera_device *icd)
281 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
282 struct mx2_camera_dev *pcdev = ici->priv;
289 ret = clk_enable(pcdev->clk_csi);
293 csicr1 = CSICR1_MCLKEN;
295 if (mx27_camera_emma(pcdev)) {
296 csicr1 |= CSICR1_PRP_IF_EN | CSICR1_FCC |
297 CSICR1_RXFF_LEVEL(0);
298 } else if (cpu_is_mx27())
299 csicr1 |= CSICR1_SOF_INTEN | CSICR1_RXFF_LEVEL(2);
301 pcdev->csicr1 = csicr1;
302 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
306 dev_info(icd->dev.parent, "Camera driver attached to camera %d\n",
312 static void mx2_camera_remove_device(struct soc_camera_device *icd)
314 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
315 struct mx2_camera_dev *pcdev = ici->priv;
317 BUG_ON(icd != pcdev->icd);
319 dev_info(icd->dev.parent, "Camera driver detached from camera %d\n",
322 mx2_camera_deactivate(pcdev);
324 if (pcdev->discard_buffer) {
325 dma_free_coherent(ici->v4l2_dev.dev, pcdev->discard_size,
326 pcdev->discard_buffer,
327 pcdev->discard_buffer_dma);
328 pcdev->discard_buffer = NULL;
334 #ifdef CONFIG_MACH_MX27
335 static void mx27_camera_dma_enable(struct mx2_camera_dev *pcdev)
339 imx_dma_enable(pcdev->dma);
341 tmp = readl(pcdev->base_csi + CSICR1);
342 tmp |= CSICR1_RF_OR_INTEN;
343 writel(tmp, pcdev->base_csi + CSICR1);
346 static irqreturn_t mx27_camera_irq(int irq_csi, void *data)
348 struct mx2_camera_dev *pcdev = data;
349 u32 status = readl(pcdev->base_csi + CSISR);
351 if (status & CSISR_SOF_INT && pcdev->active) {
354 tmp = readl(pcdev->base_csi + CSICR1);
355 writel(tmp | CSICR1_CLR_RXFIFO, pcdev->base_csi + CSICR1);
356 mx27_camera_dma_enable(pcdev);
359 writel(CSISR_SOF_INT | CSISR_RFF_OR_INT, pcdev->base_csi + CSISR);
364 static irqreturn_t mx27_camera_irq(int irq_csi, void *data)
368 #endif /* CONFIG_MACH_MX27 */
370 static void mx25_camera_frame_done(struct mx2_camera_dev *pcdev, int fb,
373 struct videobuf_buffer *vb;
374 struct mx2_buffer *buf;
375 struct mx2_buffer **fb_active = fb == 1 ? &pcdev->fb1_active :
377 u32 fb_reg = fb == 1 ? CSIDMASA_FB1 : CSIDMASA_FB2;
380 spin_lock_irqsave(&pcdev->lock, flags);
382 if (*fb_active == NULL)
385 vb = &(*fb_active)->vb;
386 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
387 vb, vb->baddr, vb->bsize);
390 do_gettimeofday(&vb->ts);
395 if (list_empty(&pcdev->capture)) {
397 writel(0, pcdev->base_csi + fb_reg);
399 buf = list_entry(pcdev->capture.next, struct mx2_buffer,
402 list_del(&vb->queue);
403 vb->state = VIDEOBUF_ACTIVE;
404 writel(videobuf_to_dma_contig(vb), pcdev->base_csi + fb_reg);
410 spin_unlock_irqrestore(&pcdev->lock, flags);
413 static irqreturn_t mx25_camera_irq(int irq_csi, void *data)
415 struct mx2_camera_dev *pcdev = data;
416 u32 status = readl(pcdev->base_csi + CSISR);
418 if (status & CSISR_DMA_TSF_FB1_INT)
419 mx25_camera_frame_done(pcdev, 1, VIDEOBUF_DONE);
420 else if (status & CSISR_DMA_TSF_FB2_INT)
421 mx25_camera_frame_done(pcdev, 2, VIDEOBUF_DONE);
423 /* FIXME: handle CSISR_RFF_OR_INT */
425 writel(status, pcdev->base_csi + CSISR);
431 * Videobuf operations
433 static int mx2_videobuf_setup(struct videobuf_queue *vq, unsigned int *count,
436 struct soc_camera_device *icd = vq->priv_data;
437 int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
438 icd->current_fmt->host_fmt);
440 dev_dbg(&icd->dev, "count=%d, size=%d\n", *count, *size);
442 if (bytes_per_line < 0)
443 return bytes_per_line;
445 *size = bytes_per_line * icd->user_height;
449 if (*size * *count > MAX_VIDEO_MEM * 1024 * 1024)
450 *count = (MAX_VIDEO_MEM * 1024 * 1024) / *size;
455 static void free_buffer(struct videobuf_queue *vq, struct mx2_buffer *buf)
457 struct soc_camera_device *icd = vq->priv_data;
458 struct videobuf_buffer *vb = &buf->vb;
460 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
461 vb, vb->baddr, vb->bsize);
464 * This waits until this buffer is out of danger, i.e., until it is no
465 * longer in state VIDEOBUF_QUEUED or VIDEOBUF_ACTIVE
467 videobuf_waiton(vq, vb, 0, 0);
469 videobuf_dma_contig_free(vq, vb);
470 dev_dbg(&icd->dev, "%s freed\n", __func__);
472 vb->state = VIDEOBUF_NEEDS_INIT;
475 static int mx2_videobuf_prepare(struct videobuf_queue *vq,
476 struct videobuf_buffer *vb, enum v4l2_field field)
478 struct soc_camera_device *icd = vq->priv_data;
479 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
480 int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
481 icd->current_fmt->host_fmt);
484 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
485 vb, vb->baddr, vb->bsize);
487 if (bytes_per_line < 0)
488 return bytes_per_line;
492 * This can be useful if you want to see if we actually fill
493 * the buffer with something
495 memset((void *)vb->baddr, 0xaa, vb->bsize);
498 if (buf->code != icd->current_fmt->code ||
499 vb->width != icd->user_width ||
500 vb->height != icd->user_height ||
501 vb->field != field) {
502 buf->code = icd->current_fmt->code;
503 vb->width = icd->user_width;
504 vb->height = icd->user_height;
506 vb->state = VIDEOBUF_NEEDS_INIT;
509 vb->size = bytes_per_line * vb->height;
510 if (vb->baddr && vb->bsize < vb->size) {
515 if (vb->state == VIDEOBUF_NEEDS_INIT) {
516 ret = videobuf_iolock(vq, vb, NULL);
520 vb->state = VIDEOBUF_PREPARED;
526 free_buffer(vq, buf);
531 static void mx2_videobuf_queue(struct videobuf_queue *vq,
532 struct videobuf_buffer *vb)
534 struct soc_camera_device *icd = vq->priv_data;
535 struct soc_camera_host *ici =
536 to_soc_camera_host(icd->dev.parent);
537 struct mx2_camera_dev *pcdev = ici->priv;
538 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
541 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
542 vb, vb->baddr, vb->bsize);
544 spin_lock_irqsave(&pcdev->lock, flags);
546 vb->state = VIDEOBUF_QUEUED;
547 list_add_tail(&vb->queue, &pcdev->capture);
549 if (mx27_camera_emma(pcdev)) {
551 #ifdef CONFIG_MACH_MX27
552 } else if (cpu_is_mx27()) {
555 if (pcdev->active == NULL) {
556 ret = imx_dma_setup_single(pcdev->dma,
557 videobuf_to_dma_contig(vb), vb->size,
558 (u32)pcdev->base_dma + 0x10,
561 vb->state = VIDEOBUF_ERROR;
566 vb->state = VIDEOBUF_ACTIVE;
570 } else { /* cpu_is_mx25() */
571 u32 csicr3, dma_inten = 0;
573 if (pcdev->fb1_active == NULL) {
574 writel(videobuf_to_dma_contig(vb),
575 pcdev->base_csi + CSIDMASA_FB1);
576 pcdev->fb1_active = buf;
577 dma_inten = CSICR1_FB1_DMA_INTEN;
578 } else if (pcdev->fb2_active == NULL) {
579 writel(videobuf_to_dma_contig(vb),
580 pcdev->base_csi + CSIDMASA_FB2);
581 pcdev->fb2_active = buf;
582 dma_inten = CSICR1_FB2_DMA_INTEN;
586 list_del(&vb->queue);
587 vb->state = VIDEOBUF_ACTIVE;
589 csicr3 = readl(pcdev->base_csi + CSICR3);
592 writel(csicr3 | CSICR3_DMA_REFLASH_RFF,
593 pcdev->base_csi + CSICR3);
595 /* clear & enable interrupts */
596 writel(dma_inten, pcdev->base_csi + CSISR);
597 pcdev->csicr1 |= dma_inten;
598 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
601 csicr3 |= CSICR3_DMA_REQ_EN_RFF | CSICR3_RXFF_LEVEL(1);
602 writel(csicr3, pcdev->base_csi + CSICR3);
607 spin_unlock_irqrestore(&pcdev->lock, flags);
610 static void mx2_videobuf_release(struct videobuf_queue *vq,
611 struct videobuf_buffer *vb)
613 struct soc_camera_device *icd = vq->priv_data;
614 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
615 struct mx2_camera_dev *pcdev = ici->priv;
616 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
620 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
621 vb, vb->baddr, vb->bsize);
624 case VIDEOBUF_ACTIVE:
625 dev_info(&icd->dev, "%s (active)\n", __func__);
627 case VIDEOBUF_QUEUED:
628 dev_info(&icd->dev, "%s (queued)\n", __func__);
630 case VIDEOBUF_PREPARED:
631 dev_info(&icd->dev, "%s (prepared)\n", __func__);
634 dev_info(&icd->dev, "%s (unknown) %d\n", __func__,
641 * Terminate only queued but inactive buffers. Active buffers are
642 * released when they become inactive after videobuf_waiton().
644 * FIXME: implement forced termination of active buffers for mx27 and
645 * mx27 eMMA, so that the user won't get stuck in an uninterruptible
646 * state. This requires a specific handling for each of the these DMA
649 spin_lock_irqsave(&pcdev->lock, flags);
650 if (vb->state == VIDEOBUF_QUEUED) {
651 list_del(&vb->queue);
652 vb->state = VIDEOBUF_ERROR;
653 } else if (cpu_is_mx25() && vb->state == VIDEOBUF_ACTIVE) {
654 if (pcdev->fb1_active == buf) {
655 pcdev->csicr1 &= ~CSICR1_FB1_DMA_INTEN;
656 writel(0, pcdev->base_csi + CSIDMASA_FB1);
657 pcdev->fb1_active = NULL;
658 } else if (pcdev->fb2_active == buf) {
659 pcdev->csicr1 &= ~CSICR1_FB2_DMA_INTEN;
660 writel(0, pcdev->base_csi + CSIDMASA_FB2);
661 pcdev->fb2_active = NULL;
663 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
664 vb->state = VIDEOBUF_ERROR;
666 spin_unlock_irqrestore(&pcdev->lock, flags);
668 free_buffer(vq, buf);
671 static struct videobuf_queue_ops mx2_videobuf_ops = {
672 .buf_setup = mx2_videobuf_setup,
673 .buf_prepare = mx2_videobuf_prepare,
674 .buf_queue = mx2_videobuf_queue,
675 .buf_release = mx2_videobuf_release,
678 static void mx2_camera_init_videobuf(struct videobuf_queue *q,
679 struct soc_camera_device *icd)
681 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
682 struct mx2_camera_dev *pcdev = ici->priv;
684 videobuf_queue_dma_contig_init(q, &mx2_videobuf_ops, pcdev->dev,
685 &pcdev->lock, V4L2_BUF_TYPE_VIDEO_CAPTURE,
686 V4L2_FIELD_NONE, sizeof(struct mx2_buffer), icd, NULL);
689 #define MX2_BUS_FLAGS (SOCAM_DATAWIDTH_8 | \
691 SOCAM_VSYNC_ACTIVE_HIGH | \
692 SOCAM_VSYNC_ACTIVE_LOW | \
693 SOCAM_HSYNC_ACTIVE_HIGH | \
694 SOCAM_HSYNC_ACTIVE_LOW | \
695 SOCAM_PCLK_SAMPLE_RISING | \
696 SOCAM_PCLK_SAMPLE_FALLING | \
697 SOCAM_DATA_ACTIVE_HIGH | \
698 SOCAM_DATA_ACTIVE_LOW)
700 static int mx27_camera_emma_prp_reset(struct mx2_camera_dev *pcdev)
705 cntl = readl(pcdev->base_emma + PRP_CNTL);
706 writel(PRP_CNTL_SWRST, pcdev->base_emma + PRP_CNTL);
707 while (count++ < 100) {
708 if (!(readl(pcdev->base_emma + PRP_CNTL) & PRP_CNTL_SWRST))
717 static void mx27_camera_emma_buf_init(struct soc_camera_device *icd,
720 struct soc_camera_host *ici =
721 to_soc_camera_host(icd->dev.parent);
722 struct mx2_camera_dev *pcdev = ici->priv;
724 writel(pcdev->discard_buffer_dma,
725 pcdev->base_emma + PRP_DEST_RGB1_PTR);
726 writel(pcdev->discard_buffer_dma,
727 pcdev->base_emma + PRP_DEST_RGB2_PTR);
730 * We only use the EMMA engine to get rid of the broken
731 * DMA Engine. No color space consversion at the moment.
732 * We set the incomming and outgoing pixelformat to an
733 * 16 Bit wide format and adjust the bytesperline
734 * accordingly. With this configuration the inputdata
735 * will not be changed by the emma and could be any type
736 * of 16 Bit Pixelformat.
738 writel(PRP_CNTL_CH1EN |
740 PRP_CNTL_DATA_IN_RGB16 |
741 PRP_CNTL_CH1_OUT_RGB16 |
744 PRP_CNTL_CH1_TSKIP(0) |
745 PRP_CNTL_IN_TSKIP(0),
746 pcdev->base_emma + PRP_CNTL);
748 writel(((bytesperline >> 1) << 16) | icd->user_height,
749 pcdev->base_emma + PRP_SRC_FRAME_SIZE);
750 writel(((bytesperline >> 1) << 16) | icd->user_height,
751 pcdev->base_emma + PRP_CH1_OUT_IMAGE_SIZE);
753 pcdev->base_emma + PRP_DEST_CH1_LINE_STRIDE);
754 writel(0x2ca00565, /* RGB565 */
755 pcdev->base_emma + PRP_SRC_PIXEL_FORMAT_CNTL);
756 writel(0x2ca00565, /* RGB565 */
757 pcdev->base_emma + PRP_CH1_PIXEL_FORMAT_CNTL);
759 /* Enable interrupts */
760 writel(PRP_INTR_RDERR |
767 pcdev->base_emma + PRP_INTR_CNTL);
770 static int mx2_camera_set_bus_param(struct soc_camera_device *icd,
773 struct soc_camera_host *ici =
774 to_soc_camera_host(icd->dev.parent);
775 struct mx2_camera_dev *pcdev = ici->priv;
776 unsigned long camera_flags, common_flags;
779 u32 csicr1 = pcdev->csicr1;
781 camera_flags = icd->ops->query_bus_param(icd);
783 common_flags = soc_camera_bus_param_compatible(camera_flags,
788 if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) &&
789 (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) {
790 if (pcdev->platform_flags & MX2_CAMERA_HSYNC_HIGH)
791 common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW;
793 common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH;
796 if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) &&
797 (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) {
798 if (pcdev->platform_flags & MX2_CAMERA_PCLK_SAMPLE_RISING)
799 common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING;
801 common_flags &= ~SOCAM_PCLK_SAMPLE_RISING;
804 ret = icd->ops->set_bus_param(icd, common_flags);
808 if (common_flags & SOCAM_PCLK_SAMPLE_RISING)
809 csicr1 |= CSICR1_REDGE;
810 if (common_flags & SOCAM_VSYNC_ACTIVE_HIGH)
811 csicr1 |= CSICR1_SOF_POL;
812 if (common_flags & SOCAM_HSYNC_ACTIVE_HIGH)
813 csicr1 |= CSICR1_HSYNC_POL;
814 if (pcdev->platform_flags & MX2_CAMERA_SWAP16)
815 csicr1 |= CSICR1_SWAP16_EN;
816 if (pcdev->platform_flags & MX2_CAMERA_EXT_VSYNC)
817 csicr1 |= CSICR1_EXT_VSYNC;
818 if (pcdev->platform_flags & MX2_CAMERA_CCIR)
819 csicr1 |= CSICR1_CCIR_EN;
820 if (pcdev->platform_flags & MX2_CAMERA_CCIR_INTERLACE)
821 csicr1 |= CSICR1_CCIR_MODE;
822 if (pcdev->platform_flags & MX2_CAMERA_GATED_CLOCK)
823 csicr1 |= CSICR1_GCLK_MODE;
824 if (pcdev->platform_flags & MX2_CAMERA_INV_DATA)
825 csicr1 |= CSICR1_INV_DATA;
826 if (pcdev->platform_flags & MX2_CAMERA_PACK_DIR_MSB)
827 csicr1 |= CSICR1_PACK_DIR;
829 pcdev->csicr1 = csicr1;
831 bytesperline = soc_mbus_bytes_per_line(icd->user_width,
832 icd->current_fmt->host_fmt);
833 if (bytesperline < 0)
836 if (mx27_camera_emma(pcdev)) {
837 ret = mx27_camera_emma_prp_reset(pcdev);
841 if (pcdev->discard_buffer)
842 dma_free_coherent(ici->v4l2_dev.dev,
843 pcdev->discard_size, pcdev->discard_buffer,
844 pcdev->discard_buffer_dma);
847 * I didn't manage to properly enable/disable the prp
848 * on a per frame basis during running transfers,
849 * thus we allocate a buffer here and use it to
850 * discard frames when no buffer is available.
851 * Feel free to work on this ;)
853 pcdev->discard_size = icd->user_height * bytesperline;
854 pcdev->discard_buffer = dma_alloc_coherent(ici->v4l2_dev.dev,
855 pcdev->discard_size, &pcdev->discard_buffer_dma,
857 if (!pcdev->discard_buffer)
860 mx27_camera_emma_buf_init(icd, bytesperline);
861 } else if (cpu_is_mx25()) {
862 writel((bytesperline * icd->user_height) >> 2,
863 pcdev->base_csi + CSIRXCNT);
864 writel((bytesperline << 16) | icd->user_height,
865 pcdev->base_csi + CSIIMAG_PARA);
868 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
873 static int mx2_camera_set_crop(struct soc_camera_device *icd,
876 struct v4l2_rect *rect = &a->c;
877 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
878 struct v4l2_mbus_framefmt mf;
881 soc_camera_limit_side(&rect->left, &rect->width, 0, 2, 4096);
882 soc_camera_limit_side(&rect->top, &rect->height, 0, 2, 4096);
884 ret = v4l2_subdev_call(sd, video, s_crop, a);
888 /* The capture device might have changed its output */
889 ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf);
893 dev_dbg(icd->dev.parent, "Sensor cropped %dx%d\n",
894 mf.width, mf.height);
896 icd->user_width = mf.width;
897 icd->user_height = mf.height;
902 static int mx2_camera_set_fmt(struct soc_camera_device *icd,
903 struct v4l2_format *f)
905 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
906 const struct soc_camera_format_xlate *xlate;
907 struct v4l2_pix_format *pix = &f->fmt.pix;
908 struct v4l2_mbus_framefmt mf;
911 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
913 dev_warn(icd->dev.parent, "Format %x not found\n",
918 mf.width = pix->width;
919 mf.height = pix->height;
920 mf.field = pix->field;
921 mf.colorspace = pix->colorspace;
922 mf.code = xlate->code;
924 ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
925 if (ret < 0 && ret != -ENOIOCTLCMD)
928 if (mf.code != xlate->code)
931 pix->width = mf.width;
932 pix->height = mf.height;
933 pix->field = mf.field;
934 pix->colorspace = mf.colorspace;
935 icd->current_fmt = xlate;
940 static int mx2_camera_try_fmt(struct soc_camera_device *icd,
941 struct v4l2_format *f)
943 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
944 const struct soc_camera_format_xlate *xlate;
945 struct v4l2_pix_format *pix = &f->fmt.pix;
946 struct v4l2_mbus_framefmt mf;
947 __u32 pixfmt = pix->pixelformat;
948 unsigned int width_limit;
951 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
952 if (pixfmt && !xlate) {
953 dev_warn(icd->dev.parent, "Format %x not found\n", pixfmt);
957 /* FIXME: implement MX27 limits */
959 /* limit to MX25 hardware capabilities */
961 if (xlate->host_fmt->bits_per_sample <= 8)
962 width_limit = 0xffff * 4;
964 width_limit = 0xffff * 2;
965 /* CSIIMAG_PARA limit */
966 if (pix->width > width_limit)
967 pix->width = width_limit;
968 if (pix->height > 0xffff)
969 pix->height = 0xffff;
971 pix->bytesperline = soc_mbus_bytes_per_line(pix->width,
973 if (pix->bytesperline < 0)
974 return pix->bytesperline;
975 pix->sizeimage = pix->height * pix->bytesperline;
976 if (pix->sizeimage > (4 * 0x3ffff)) { /* CSIRXCNT limit */
977 dev_warn(icd->dev.parent,
978 "Image size (%u) above limit\n",
984 /* limit to sensor capabilities */
985 mf.width = pix->width;
986 mf.height = pix->height;
987 mf.field = pix->field;
988 mf.colorspace = pix->colorspace;
989 mf.code = xlate->code;
991 ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf);
995 if (mf.field == V4L2_FIELD_ANY)
996 mf.field = V4L2_FIELD_NONE;
997 if (mf.field != V4L2_FIELD_NONE) {
998 dev_err(icd->dev.parent, "Field type %d unsupported.\n",
1003 pix->width = mf.width;
1004 pix->height = mf.height;
1005 pix->field = mf.field;
1006 pix->colorspace = mf.colorspace;
1011 static int mx2_camera_querycap(struct soc_camera_host *ici,
1012 struct v4l2_capability *cap)
1014 /* cap->name is set by the friendly caller:-> */
1015 strlcpy(cap->card, MX2_CAM_DRIVER_DESCRIPTION, sizeof(cap->card));
1016 cap->version = MX2_CAM_VERSION_CODE;
1017 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1022 static int mx2_camera_reqbufs(struct soc_camera_device *icd,
1023 struct v4l2_requestbuffers *p)
1027 for (i = 0; i < p->count; i++) {
1028 struct mx2_buffer *buf = container_of(icd->vb_vidq.bufs[i],
1029 struct mx2_buffer, vb);
1030 INIT_LIST_HEAD(&buf->vb.queue);
1036 #ifdef CONFIG_MACH_MX27
1037 static void mx27_camera_frame_done(struct mx2_camera_dev *pcdev, int state)
1039 struct videobuf_buffer *vb;
1040 struct mx2_buffer *buf;
1041 unsigned long flags;
1044 spin_lock_irqsave(&pcdev->lock, flags);
1046 if (!pcdev->active) {
1047 dev_err(pcdev->dev, "%s called with no active buffer!\n",
1052 vb = &pcdev->active->vb;
1053 buf = container_of(vb, struct mx2_buffer, vb);
1054 WARN_ON(list_empty(&vb->queue));
1055 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
1056 vb, vb->baddr, vb->bsize);
1058 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
1059 list_del_init(&vb->queue);
1061 do_gettimeofday(&vb->ts);
1066 if (list_empty(&pcdev->capture)) {
1067 pcdev->active = NULL;
1071 pcdev->active = list_entry(pcdev->capture.next,
1072 struct mx2_buffer, vb.queue);
1074 vb = &pcdev->active->vb;
1075 vb->state = VIDEOBUF_ACTIVE;
1077 ret = imx_dma_setup_single(pcdev->dma, videobuf_to_dma_contig(vb),
1078 vb->size, (u32)pcdev->base_dma + 0x10, DMA_MODE_READ);
1081 vb->state = VIDEOBUF_ERROR;
1082 pcdev->active = NULL;
1087 spin_unlock_irqrestore(&pcdev->lock, flags);
1090 static void mx27_camera_dma_err_callback(int channel, void *data, int err)
1092 struct mx2_camera_dev *pcdev = data;
1094 mx27_camera_frame_done(pcdev, VIDEOBUF_ERROR);
1097 static void mx27_camera_dma_callback(int channel, void *data)
1099 struct mx2_camera_dev *pcdev = data;
1101 mx27_camera_frame_done(pcdev, VIDEOBUF_DONE);
1104 #define DMA_REQ_CSI_RX 31 /* FIXME: Add this to a resource */
1106 static int __devinit mx27_camera_dma_init(struct platform_device *pdev,
1107 struct mx2_camera_dev *pcdev)
1111 pcdev->dma = imx_dma_request_by_prio("CSI RX DMA", DMA_PRIO_HIGH);
1112 if (pcdev->dma < 0) {
1113 dev_err(&pdev->dev, "%s failed to request DMA channel\n",
1118 err = imx_dma_setup_handlers(pcdev->dma, mx27_camera_dma_callback,
1119 mx27_camera_dma_err_callback, pcdev);
1121 dev_err(&pdev->dev, "%s failed to set DMA callback\n",
1126 err = imx_dma_config_channel(pcdev->dma,
1127 IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_FIFO,
1128 IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
1131 dev_err(&pdev->dev, "%s failed to config DMA channel\n",
1136 imx_dma_config_burstlen(pcdev->dma, 64);
1141 imx_dma_free(pcdev->dma);
1145 #endif /* CONFIG_MACH_MX27 */
1147 static unsigned int mx2_camera_poll(struct file *file, poll_table *pt)
1149 struct soc_camera_device *icd = file->private_data;
1151 return videobuf_poll_stream(file, &icd->vb_vidq, pt);
1154 static struct soc_camera_host_ops mx2_soc_camera_host_ops = {
1155 .owner = THIS_MODULE,
1156 .add = mx2_camera_add_device,
1157 .remove = mx2_camera_remove_device,
1158 .set_fmt = mx2_camera_set_fmt,
1159 .set_crop = mx2_camera_set_crop,
1160 .try_fmt = mx2_camera_try_fmt,
1161 .init_videobuf = mx2_camera_init_videobuf,
1162 .reqbufs = mx2_camera_reqbufs,
1163 .poll = mx2_camera_poll,
1164 .querycap = mx2_camera_querycap,
1165 .set_bus_param = mx2_camera_set_bus_param,
1168 static void mx27_camera_frame_done_emma(struct mx2_camera_dev *pcdev,
1169 int bufnum, int state)
1171 struct mx2_buffer *buf;
1172 struct videobuf_buffer *vb;
1175 if (!list_empty(&pcdev->active_bufs)) {
1176 buf = list_entry(pcdev->active_bufs.next,
1177 struct mx2_buffer, vb.queue);
1179 BUG_ON(buf->bufnum != bufnum);
1183 phys = videobuf_to_dma_contig(vb);
1184 if (readl(pcdev->base_emma + PRP_DEST_RGB1_PTR + 4 * bufnum)
1186 dev_err(pcdev->dev, "%p != %p\n", phys,
1187 readl(pcdev->base_emma +
1192 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, vb,
1193 vb->baddr, vb->bsize);
1195 list_del(&vb->queue);
1197 do_gettimeofday(&vb->ts);
1203 if (list_empty(&pcdev->capture)) {
1204 writel(pcdev->discard_buffer_dma, pcdev->base_emma +
1205 PRP_DEST_RGB1_PTR + 4 * bufnum);
1209 buf = list_entry(pcdev->capture.next,
1210 struct mx2_buffer, vb.queue);
1212 buf->bufnum = !bufnum;
1214 list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
1217 vb->state = VIDEOBUF_ACTIVE;
1219 phys = videobuf_to_dma_contig(vb);
1220 writel(phys, pcdev->base_emma + PRP_DEST_RGB1_PTR + 4 * bufnum);
1223 static irqreturn_t mx27_camera_emma_irq(int irq_emma, void *data)
1225 struct mx2_camera_dev *pcdev = data;
1226 unsigned int status = readl(pcdev->base_emma + PRP_INTRSTATUS);
1227 struct mx2_buffer *buf;
1229 if (status & (1 << 7)) { /* overflow */
1232 * We only disable channel 1 here since this is the only
1235 * FIXME: the correct DMA overflow handling should be resetting
1236 * the buffer, returning an error frame, and continuing with
1239 cntl = readl(pcdev->base_emma + PRP_CNTL);
1240 writel(cntl & ~PRP_CNTL_CH1EN, pcdev->base_emma + PRP_CNTL);
1241 writel(cntl, pcdev->base_emma + PRP_CNTL);
1243 if ((status & (3 << 5)) == (3 << 5)
1244 && !list_empty(&pcdev->active_bufs)) {
1246 * Both buffers have triggered, process the one we're expecting
1249 buf = list_entry(pcdev->active_bufs.next,
1250 struct mx2_buffer, vb.queue);
1251 mx27_camera_frame_done_emma(pcdev, buf->bufnum, VIDEOBUF_DONE);
1252 status &= ~(1 << (6 - buf->bufnum)); /* mark processed */
1254 if (status & (1 << 6))
1255 mx27_camera_frame_done_emma(pcdev, 0, VIDEOBUF_DONE);
1256 if (status & (1 << 5))
1257 mx27_camera_frame_done_emma(pcdev, 1, VIDEOBUF_DONE);
1259 writel(status, pcdev->base_emma + PRP_INTRSTATUS);
1264 static int __devinit mx27_camera_emma_init(struct mx2_camera_dev *pcdev)
1266 struct resource *res_emma = pcdev->res_emma;
1269 if (!request_mem_region(res_emma->start, resource_size(res_emma),
1270 MX2_CAM_DRV_NAME)) {
1275 pcdev->base_emma = ioremap(res_emma->start, resource_size(res_emma));
1276 if (!pcdev->base_emma) {
1281 err = request_irq(pcdev->irq_emma, mx27_camera_emma_irq, 0,
1282 MX2_CAM_DRV_NAME, pcdev);
1284 dev_err(pcdev->dev, "Camera EMMA interrupt register failed \n");
1288 pcdev->clk_emma = clk_get(NULL, "emma");
1289 if (IS_ERR(pcdev->clk_emma)) {
1290 err = PTR_ERR(pcdev->clk_emma);
1294 clk_enable(pcdev->clk_emma);
1296 err = mx27_camera_emma_prp_reset(pcdev);
1298 goto exit_clk_emma_put;
1303 clk_disable(pcdev->clk_emma);
1304 clk_put(pcdev->clk_emma);
1306 free_irq(pcdev->irq_emma, pcdev);
1308 iounmap(pcdev->base_emma);
1310 release_mem_region(res_emma->start, resource_size(res_emma));
1315 static int __devinit mx2_camera_probe(struct platform_device *pdev)
1317 struct mx2_camera_dev *pcdev;
1318 struct resource *res_csi, *res_emma;
1319 void __iomem *base_csi;
1320 int irq_csi, irq_emma;
1321 irq_handler_t mx2_cam_irq_handler = cpu_is_mx25() ? mx25_camera_irq
1325 dev_dbg(&pdev->dev, "initialising\n");
1327 res_csi = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1328 irq_csi = platform_get_irq(pdev, 0);
1329 if (res_csi == NULL || irq_csi < 0) {
1330 dev_err(&pdev->dev, "Missing platform resources data\n");
1335 pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL);
1337 dev_err(&pdev->dev, "Could not allocate pcdev\n");
1342 pcdev->clk_csi = clk_get(&pdev->dev, NULL);
1343 if (IS_ERR(pcdev->clk_csi)) {
1344 err = PTR_ERR(pcdev->clk_csi);
1348 dev_dbg(&pdev->dev, "Camera clock frequency: %ld\n",
1349 clk_get_rate(pcdev->clk_csi));
1351 /* Initialize DMA */
1352 #ifdef CONFIG_MACH_MX27
1353 if (cpu_is_mx27()) {
1354 err = mx27_camera_dma_init(pdev, pcdev);
1358 #endif /* CONFIG_MACH_MX27 */
1360 pcdev->res_csi = res_csi;
1361 pcdev->pdata = pdev->dev.platform_data;
1365 pcdev->platform_flags = pcdev->pdata->flags;
1367 rate = clk_round_rate(pcdev->clk_csi, pcdev->pdata->clk * 2);
1372 err = clk_set_rate(pcdev->clk_csi, rate);
1377 INIT_LIST_HEAD(&pcdev->capture);
1378 INIT_LIST_HEAD(&pcdev->active_bufs);
1379 spin_lock_init(&pcdev->lock);
1382 * Request the regions.
1384 if (!request_mem_region(res_csi->start, resource_size(res_csi),
1385 MX2_CAM_DRV_NAME)) {
1390 base_csi = ioremap(res_csi->start, resource_size(res_csi));
1395 pcdev->irq_csi = irq_csi;
1396 pcdev->base_csi = base_csi;
1397 pcdev->base_dma = res_csi->start;
1398 pcdev->dev = &pdev->dev;
1400 err = request_irq(pcdev->irq_csi, mx2_cam_irq_handler, 0,
1401 MX2_CAM_DRV_NAME, pcdev);
1403 dev_err(pcdev->dev, "Camera interrupt register failed \n");
1407 if (cpu_is_mx27()) {
1409 res_emma = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1410 irq_emma = platform_get_irq(pdev, 1);
1412 if (res_emma && irq_emma >= 0) {
1413 dev_info(&pdev->dev, "Using EMMA\n");
1414 pcdev->use_emma = 1;
1415 pcdev->res_emma = res_emma;
1416 pcdev->irq_emma = irq_emma;
1417 if (mx27_camera_emma_init(pcdev))
1422 pcdev->soc_host.drv_name = MX2_CAM_DRV_NAME,
1423 pcdev->soc_host.ops = &mx2_soc_camera_host_ops,
1424 pcdev->soc_host.priv = pcdev;
1425 pcdev->soc_host.v4l2_dev.dev = &pdev->dev;
1426 pcdev->soc_host.nr = pdev->id;
1427 err = soc_camera_host_register(&pcdev->soc_host);
1429 goto exit_free_emma;
1431 dev_info(&pdev->dev, "MX2 Camera (CSI) driver probed, clock frequency: %ld\n",
1432 clk_get_rate(pcdev->clk_csi));
1437 if (mx27_camera_emma(pcdev)) {
1438 free_irq(pcdev->irq_emma, pcdev);
1439 clk_disable(pcdev->clk_emma);
1440 clk_put(pcdev->clk_emma);
1441 iounmap(pcdev->base_emma);
1442 release_mem_region(res_emma->start, resource_size(res_emma));
1445 free_irq(pcdev->irq_csi, pcdev);
1449 release_mem_region(res_csi->start, resource_size(res_csi));
1451 #ifdef CONFIG_MACH_MX27
1453 imx_dma_free(pcdev->dma);
1455 clk_put(pcdev->clk_csi);
1456 #endif /* CONFIG_MACH_MX27 */
1463 static int __devexit mx2_camera_remove(struct platform_device *pdev)
1465 struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
1466 struct mx2_camera_dev *pcdev = container_of(soc_host,
1467 struct mx2_camera_dev, soc_host);
1468 struct resource *res;
1470 clk_put(pcdev->clk_csi);
1471 #ifdef CONFIG_MACH_MX27
1473 imx_dma_free(pcdev->dma);
1474 #endif /* CONFIG_MACH_MX27 */
1475 free_irq(pcdev->irq_csi, pcdev);
1476 if (mx27_camera_emma(pcdev))
1477 free_irq(pcdev->irq_emma, pcdev);
1479 soc_camera_host_unregister(&pcdev->soc_host);
1481 iounmap(pcdev->base_csi);
1483 if (mx27_camera_emma(pcdev)) {
1484 clk_disable(pcdev->clk_emma);
1485 clk_put(pcdev->clk_emma);
1486 iounmap(pcdev->base_emma);
1487 res = pcdev->res_emma;
1488 release_mem_region(res->start, resource_size(res));
1491 res = pcdev->res_csi;
1492 release_mem_region(res->start, resource_size(res));
1496 dev_info(&pdev->dev, "MX2 Camera driver unloaded\n");
1501 static struct platform_driver mx2_camera_driver = {
1503 .name = MX2_CAM_DRV_NAME,
1505 .remove = __devexit_p(mx2_camera_remove),
1509 static int __init mx2_camera_init(void)
1511 return platform_driver_probe(&mx2_camera_driver, &mx2_camera_probe);
1514 static void __exit mx2_camera_exit(void)
1516 return platform_driver_unregister(&mx2_camera_driver);
1519 module_init(mx2_camera_init);
1520 module_exit(mx2_camera_exit);
1522 MODULE_DESCRIPTION("i.MX27/i.MX25 SoC Camera Host driver");
1523 MODULE_AUTHOR("Sascha Hauer <sha@pengutronix.de>");
1524 MODULE_LICENSE("GPL");