2 * Driver for the Conexant CX23885 PCIe bridge
4 * Copyright (c) 2006 Steven Toth <stoth@hauppauge.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #include <linux/init.h>
23 #include <linux/list.h>
24 #include <linux/module.h>
25 #include <linux/moduleparam.h>
26 #include <linux/kmod.h>
27 #include <linux/kernel.h>
28 #include <linux/slab.h>
29 #include <linux/interrupt.h>
30 #include <linux/delay.h>
31 #include <asm/div64.h>
35 MODULE_DESCRIPTION("Driver for cx23885 based TV cards");
36 MODULE_AUTHOR("Steven Toth <stoth@hauppauge.com>");
37 MODULE_LICENSE("GPL");
39 static unsigned int debug;
40 module_param(debug,int,0644);
41 MODULE_PARM_DESC(debug,"enable debug messages");
43 static unsigned int card[] = {[0 ... (CX23885_MAXBOARDS - 1)] = UNSET };
44 module_param_array(card, int, NULL, 0444);
45 MODULE_PARM_DESC(card,"card type");
47 #define dprintk(level, fmt, arg...)\
48 do { if (debug >= level)\
49 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
52 static unsigned int cx23885_devcount;
54 static DEFINE_MUTEX(devlist);
55 LIST_HEAD(cx23885_devlist);
57 #define NO_SYNC_LINE (-1U)
59 /* FIXME, these allocations will change when
60 * analog arrives. The be reviewed.
62 * 1 line = 16 bytes of CDT
64 * cdt size = 16 * linesize
69 * 0x00000000 0x00008fff FIFO clusters
70 * 0x00010000 0x000104af Channel Management Data Structures
71 * 0x000104b0 0x000104ff Free
72 * 0x00010500 0x000108bf 15 channels * iqsize
73 * 0x000108c0 0x000108ff Free
74 * 0x00010900 0x00010e9f IQ's + Cluster Descriptor Tables
75 * 15 channels * (iqsize + (maxlines * linesize))
76 * 0x00010ea0 0x00010xxx Free
79 static struct sram_channel cx23887_sram_channels[] = {
82 .cmds_start = 0x10000,
83 .ctrl_start = 0x105b0,
87 .ptr1_reg = DMA1_PTR1,
88 .ptr2_reg = DMA1_PTR2,
89 .cnt1_reg = DMA1_CNT1,
90 .cnt2_reg = DMA1_CNT2,
99 .ptr1_reg = DMA2_PTR1,
100 .ptr2_reg = DMA2_PTR2,
101 .cnt1_reg = DMA2_CNT1,
102 .cnt2_reg = DMA2_CNT2,
106 .cmds_start = 0x100A0,
107 .ctrl_start = 0x10670,
109 .fifo_start = 0x5000,
111 .ptr1_reg = DMA3_PTR1,
112 .ptr2_reg = DMA3_PTR2,
113 .cnt1_reg = DMA3_CNT1,
114 .cnt2_reg = DMA3_CNT2,
123 .ptr1_reg = DMA4_PTR1,
124 .ptr2_reg = DMA4_PTR2,
125 .cnt1_reg = DMA4_CNT1,
126 .cnt2_reg = DMA4_CNT2,
135 .ptr1_reg = DMA5_PTR1,
136 .ptr2_reg = DMA5_PTR2,
137 .cnt1_reg = DMA5_CNT1,
138 .cnt2_reg = DMA5_CNT2,
142 .cmds_start = 0x10140,
143 .ctrl_start = 0x10680,
145 .fifo_start = 0x6000,
147 .ptr1_reg = DMA5_PTR1,
148 .ptr2_reg = DMA5_PTR2,
149 .cnt1_reg = DMA5_CNT1,
150 .cnt2_reg = DMA5_CNT2,
159 .ptr1_reg = DMA6_PTR1,
160 .ptr2_reg = DMA6_PTR2,
161 .cnt1_reg = DMA6_CNT1,
162 .cnt2_reg = DMA6_CNT2,
171 .ptr1_reg = DMA7_PTR1,
172 .ptr2_reg = DMA7_PTR2,
173 .cnt1_reg = DMA7_CNT1,
174 .cnt2_reg = DMA7_CNT2,
183 .ptr1_reg = DMA8_PTR1,
184 .ptr2_reg = DMA8_PTR2,
185 .cnt1_reg = DMA8_CNT1,
186 .cnt2_reg = DMA8_CNT2,
190 static int cx23885_risc_decode(u32 risc)
192 static char *instr[16] = {
193 [RISC_SYNC >> 28] = "sync",
194 [RISC_WRITE >> 28] = "write",
195 [RISC_WRITEC >> 28] = "writec",
196 [RISC_READ >> 28] = "read",
197 [RISC_READC >> 28] = "readc",
198 [RISC_JUMP >> 28] = "jump",
199 [RISC_SKIP >> 28] = "skip",
200 [RISC_WRITERM >> 28] = "writerm",
201 [RISC_WRITECM >> 28] = "writecm",
202 [RISC_WRITECR >> 28] = "writecr",
204 static int incr[16] = {
205 [RISC_WRITE >> 28] = 3,
206 [RISC_JUMP >> 28] = 3,
207 [RISC_SKIP >> 28] = 1,
208 [RISC_SYNC >> 28] = 1,
209 [RISC_WRITERM >> 28] = 3,
210 [RISC_WRITECM >> 28] = 3,
211 [RISC_WRITECR >> 28] = 4,
213 static char *bits[] = {
214 "12", "13", "14", "resync",
215 "cnt0", "cnt1", "18", "19",
216 "20", "21", "22", "23",
217 "irq1", "irq2", "eol", "sol",
221 printk("0x%08x [ %s", risc,
222 instr[risc >> 28] ? instr[risc >> 28] : "INVALID");
223 for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--)
224 if (risc & (1 << (i + 12)))
225 printk(" %s", bits[i]);
226 printk(" count=%d ]\n", risc & 0xfff);
227 return incr[risc >> 28] ? incr[risc >> 28] : 1;
230 void cx23885_wakeup(struct cx23885_tsport *port,
231 struct cx23885_dmaqueue *q, u32 count)
233 struct cx23885_dev *dev = port->dev;
234 struct cx23885_buffer *buf;
237 for (bc = 0;; bc++) {
238 if (list_empty(&q->active))
240 buf = list_entry(q->active.next,
241 struct cx23885_buffer, vb.queue);
243 /* count comes from the hw and is is 16bit wide --
244 * this trick handles wrap-arounds correctly for
245 * up to 32767 buffers in flight... */
246 if ((s16) (count - buf->count) < 0)
249 do_gettimeofday(&buf->vb.ts);
250 dprintk(2, "[%p/%d] wakeup reg=%d buf=%d\n", buf, buf->vb.i,
252 buf->vb.state = VIDEOBUF_DONE;
253 list_del(&buf->vb.queue);
254 wake_up(&buf->vb.done);
256 if (list_empty(&q->active)) {
257 del_timer(&q->timeout);
259 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
262 printk("%s: %d buffers handled (should be 1)\n",
266 int cx23885_sram_channel_setup(struct cx23885_dev *dev,
267 struct sram_channel *ch,
268 unsigned int bpl, u32 risc)
270 unsigned int i, lines;
273 if (ch->cmds_start == 0)
275 dprintk(1, "%s() Erasing channel [%s]\n", __func__,
277 cx_write(ch->ptr1_reg, 0);
278 cx_write(ch->ptr2_reg, 0);
279 cx_write(ch->cnt2_reg, 0);
280 cx_write(ch->cnt1_reg, 0);
283 dprintk(1, "%s() Configuring channel [%s]\n", __func__,
287 bpl = (bpl + 7) & ~7; /* alignment */
289 lines = ch->fifo_size / bpl;
294 cx_write(8 + 0, RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
299 for (i = 0; i < lines; i++) {
300 dprintk(2, "%s() 0x%08x <- 0x%08x\n", __func__, cdt + 16*i,
301 ch->fifo_start + bpl*i);
302 cx_write(cdt + 16*i, ch->fifo_start + bpl*i);
303 cx_write(cdt + 16*i + 4, 0);
304 cx_write(cdt + 16*i + 8, 0);
305 cx_write(cdt + 16*i + 12, 0);
310 cx_write(ch->cmds_start + 0, 8);
312 cx_write(ch->cmds_start + 0, risc);
313 cx_write(ch->cmds_start + 4, 0); /* 64 bits 63-32 */
314 cx_write(ch->cmds_start + 8, cdt);
315 cx_write(ch->cmds_start + 12, (lines*16) >> 3);
316 cx_write(ch->cmds_start + 16, ch->ctrl_start);
318 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2) );
320 cx_write(ch->cmds_start + 20, 64 >> 2);
321 for (i = 24; i < 80; i += 4)
322 cx_write(ch->cmds_start + i, 0);
325 cx_write(ch->ptr1_reg, ch->fifo_start);
326 cx_write(ch->ptr2_reg, cdt);
327 cx_write(ch->cnt2_reg, (lines*16) >> 3);
328 cx_write(ch->cnt1_reg, (bpl >> 3) -1);
330 dprintk(2,"[bridge %d] sram setup %s: bpl=%d lines=%d\n",
339 void cx23885_sram_channel_dump(struct cx23885_dev *dev,
340 struct sram_channel *ch)
342 static char *name[] = {
359 unsigned int i, j, n;
361 printk("%s: %s - dma channel status dump\n",
362 dev->name, ch->name);
363 for (i = 0; i < ARRAY_SIZE(name); i++)
364 printk("%s: cmds: %-15s: 0x%08x\n",
366 cx_read(ch->cmds_start + 4*i));
368 for (i = 0; i < 4; i++) {
369 risc = cx_read(ch->cmds_start + 4 * (i + 14));
370 printk("%s: risc%d: ", dev->name, i);
371 cx23885_risc_decode(risc);
373 for (i = 0; i < (64 >> 2); i += n) {
374 risc = cx_read(ch->ctrl_start + 4 * i);
375 /* No consideration for bits 63-32 */
377 printk("%s: (0x%08x) iq %x: ", dev->name,
378 ch->ctrl_start + 4 * i, i);
379 n = cx23885_risc_decode(risc);
380 for (j = 1; j < n; j++) {
381 risc = cx_read(ch->ctrl_start + 4 * (i + j));
382 printk("%s: iq %x: 0x%08x [ arg #%d ]\n",
383 dev->name, i+j, risc, j);
387 printk("%s: fifo: 0x%08x -> 0x%x\n",
388 dev->name, ch->fifo_start, ch->fifo_start+ch->fifo_size);
389 printk("%s: ctrl: 0x%08x -> 0x%x\n",
390 dev->name, ch->ctrl_start, ch->ctrl_start + 6*16);
391 printk("%s: ptr1_reg: 0x%08x\n",
392 dev->name, cx_read(ch->ptr1_reg));
393 printk("%s: ptr2_reg: 0x%08x\n",
394 dev->name, cx_read(ch->ptr2_reg));
395 printk("%s: cnt1_reg: 0x%08x\n",
396 dev->name, cx_read(ch->cnt1_reg));
397 printk("%s: cnt2_reg: 0x%08x\n",
398 dev->name, cx_read(ch->cnt2_reg));
401 static void cx23885_risc_disasm(struct cx23885_tsport *port,
402 struct btcx_riscmem *risc)
404 struct cx23885_dev *dev = port->dev;
405 unsigned int i, j, n;
407 printk("%s: risc disasm: %p [dma=0x%08lx]\n",
408 dev->name, risc->cpu, (unsigned long)risc->dma);
409 for (i = 0; i < (risc->size >> 2); i += n) {
410 printk("%s: %04d: ", dev->name, i);
411 n = cx23885_risc_decode(le32_to_cpu(risc->cpu[i]));
412 for (j = 1; j < n; j++)
413 printk("%s: %04d: 0x%08x [ arg #%d ]\n",
414 dev->name, i + j, risc->cpu[i + j], j);
415 if (risc->cpu[i] == cpu_to_le32(RISC_JUMP))
420 static void cx23885_shutdown(struct cx23885_dev *dev)
422 /* disable RISC controller */
423 cx_write(DEV_CNTRL2, 0);
425 /* Disable all IR activity */
426 cx_write(IR_CNTRL_REG, 0);
428 /* Disable Video A/B activity */
429 cx_write(VID_A_DMA_CTL, 0);
430 cx_write(VID_B_DMA_CTL, 0);
431 cx_write(VID_C_DMA_CTL, 0);
433 /* Disable Audio activity */
434 cx_write(AUD_INT_DMA_CTL, 0);
435 cx_write(AUD_EXT_DMA_CTL, 0);
437 /* Disable Serial port */
438 cx_write(UART_CTL, 0);
440 /* Disable Interrupts */
441 cx_write(PCI_INT_MSK, 0);
442 cx_write(VID_A_INT_MSK, 0);
443 cx_write(VID_B_INT_MSK, 0);
444 cx_write(VID_C_INT_MSK, 0);
445 cx_write(AUDIO_INT_INT_MSK, 0);
446 cx_write(AUDIO_EXT_INT_MSK, 0);
450 static void cx23885_reset(struct cx23885_dev *dev)
452 dprintk(1, "%s()\n", __func__);
454 cx23885_shutdown(dev);
456 cx_write(PCI_INT_STAT, 0xffffffff);
457 cx_write(VID_A_INT_STAT, 0xffffffff);
458 cx_write(VID_B_INT_STAT, 0xffffffff);
459 cx_write(VID_C_INT_STAT, 0xffffffff);
460 cx_write(AUDIO_INT_INT_STAT, 0xffffffff);
461 cx_write(AUDIO_EXT_INT_STAT, 0xffffffff);
462 cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000);
463 cx_write(PAD_CTRL, 0x00500300);
467 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH01],
469 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH02], 128, 0);
470 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH03],
472 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH04], 128, 0);
473 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH05], 128, 0);
474 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH06],
476 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH07], 128, 0);
477 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH08], 128, 0);
478 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH09], 128, 0);
480 cx23885_gpio_setup(dev);
484 static int cx23885_pci_quirks(struct cx23885_dev *dev)
486 dprintk(1, "%s()\n", __func__);
488 /* The cx23885 bridge has a weird bug which causes NMI to be asserted
489 * when DMA begins if RDR_TLCTL0 bit4 is not cleared. It does not
490 * occur on the cx23887 bridge.
492 if(dev->bridge == CX23885_BRIDGE_885)
493 cx_clear(RDR_TLCTL0, 1 << 4);
498 static int get_resources(struct cx23885_dev *dev)
500 if (request_mem_region(pci_resource_start(dev->pci,0),
501 pci_resource_len(dev->pci,0),
505 printk(KERN_ERR "%s: can't get MMIO memory @ 0x%llx\n",
506 dev->name, (unsigned long long)pci_resource_start(dev->pci,0));
511 static void cx23885_timeout(unsigned long data);
512 int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
513 u32 reg, u32 mask, u32 value);
515 static int cx23885_init_tsport(struct cx23885_dev *dev, struct cx23885_tsport *port, int portno)
517 dprintk(1, "%s(portno=%d)\n", __func__, portno);
519 /* Transport bus init dma queue - Common settings */
520 port->dma_ctl_val = 0x11; /* Enable RISC controller and Fifo */
521 port->ts_int_msk_val = 0x1111; /* TS port bits for RISC */
522 port->vld_misc_val = 0x0;
523 port->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4);
525 spin_lock_init(&port->slock);
529 INIT_LIST_HEAD(&port->mpegq.active);
530 INIT_LIST_HEAD(&port->mpegq.queued);
531 port->mpegq.timeout.function = cx23885_timeout;
532 port->mpegq.timeout.data = (unsigned long)port;
533 init_timer(&port->mpegq.timeout);
537 port->reg_gpcnt = VID_B_GPCNT;
538 port->reg_gpcnt_ctl = VID_B_GPCNT_CTL;
539 port->reg_dma_ctl = VID_B_DMA_CTL;
540 port->reg_lngth = VID_B_LNGTH;
541 port->reg_hw_sop_ctrl = VID_B_HW_SOP_CTL;
542 port->reg_gen_ctrl = VID_B_GEN_CTL;
543 port->reg_bd_pkt_status = VID_B_BD_PKT_STATUS;
544 port->reg_sop_status = VID_B_SOP_STATUS;
545 port->reg_fifo_ovfl_stat = VID_B_FIFO_OVFL_STAT;
546 port->reg_vld_misc = VID_B_VLD_MISC;
547 port->reg_ts_clk_en = VID_B_TS_CLK_EN;
548 port->reg_src_sel = VID_B_SRC_SEL;
549 port->reg_ts_int_msk = VID_B_INT_MSK;
550 port->reg_ts_int_stat = VID_B_INT_STAT;
551 port->sram_chno = SRAM_CH03; /* VID_B */
552 port->pci_irqmask = 0x02; /* VID_B bit1 */
555 port->reg_gpcnt = VID_C_GPCNT;
556 port->reg_gpcnt_ctl = VID_C_GPCNT_CTL;
557 port->reg_dma_ctl = VID_C_DMA_CTL;
558 port->reg_lngth = VID_C_LNGTH;
559 port->reg_hw_sop_ctrl = VID_C_HW_SOP_CTL;
560 port->reg_gen_ctrl = VID_C_GEN_CTL;
561 port->reg_bd_pkt_status = VID_C_BD_PKT_STATUS;
562 port->reg_sop_status = VID_C_SOP_STATUS;
563 port->reg_fifo_ovfl_stat = VID_C_FIFO_OVFL_STAT;
564 port->reg_vld_misc = VID_C_VLD_MISC;
565 port->reg_ts_clk_en = VID_C_TS_CLK_EN;
566 port->reg_src_sel = 0;
567 port->reg_ts_int_msk = VID_C_INT_MSK;
568 port->reg_ts_int_stat = VID_C_INT_STAT;
569 port->sram_chno = SRAM_CH06; /* VID_C */
570 port->pci_irqmask = 0x04; /* VID_C bit2 */
576 cx23885_risc_stopper(dev->pci, &port->mpegq.stopper,
577 port->reg_dma_ctl, port->dma_ctl_val, 0x00);
582 static void cx23885_dev_checkrevision(struct cx23885_dev *dev)
584 switch (cx_read(RDR_CFG2) & 0xff) {
587 dev->hwrevision = 0xa0;
591 dev->hwrevision = 0xa1;
595 dev->hwrevision = 0xb0;
599 dev->hwrevision = 0xc0;
603 dev->hwrevision = 0xc0;
606 dev->hwrevision = 0xb1;
609 printk(KERN_ERR "%s() New hardware revision found 0x%x\n",
610 __func__, dev->hwrevision);
613 printk(KERN_INFO "%s() Hardware revision = 0x%02x\n",
614 __func__, dev->hwrevision);
616 printk(KERN_ERR "%s() Hardware revision unknown 0x%x\n",
617 __func__, dev->hwrevision);
620 static int cx23885_dev_setup(struct cx23885_dev *dev)
624 mutex_init(&dev->lock);
626 atomic_inc(&dev->refcount);
628 dev->nr = cx23885_devcount++;
629 dev->sram_channels = cx23887_sram_channels;
630 sprintf(dev->name, "cx23885[%d]", dev->nr);
632 mutex_lock(&devlist);
633 list_add_tail(&dev->devlist, &cx23885_devlist);
634 mutex_unlock(&devlist);
636 /* Configure the internal memory */
637 if(dev->pci->device == 0x8880) {
638 dev->bridge = CX23885_BRIDGE_887;
639 /* Apply a sensible clock frequency for the PCIe bridge */
640 dev->clk_freq = 25000000;
642 if(dev->pci->device == 0x8852) {
643 dev->bridge = CX23885_BRIDGE_885;
644 /* Apply a sensible clock frequency for the PCIe bridge */
645 dev->clk_freq = 28000000;
649 dprintk(1, "%s() Memory configured for PCIe bridge type %d\n",
650 __func__, dev->bridge);
654 if (card[dev->nr] < cx23885_bcount)
655 dev->board = card[dev->nr];
656 for (i = 0; UNSET == dev->board && i < cx23885_idcount; i++)
657 if (dev->pci->subsystem_vendor == cx23885_subids[i].subvendor &&
658 dev->pci->subsystem_device == cx23885_subids[i].subdevice)
659 dev->board = cx23885_subids[i].card;
660 if (UNSET == dev->board) {
661 dev->board = CX23885_BOARD_UNKNOWN;
662 cx23885_card_list(dev);
665 /* If the user specific a clk freq override, apply it */
666 if (cx23885_boards[dev->board].clk_freq > 0)
667 dev->clk_freq = cx23885_boards[dev->board].clk_freq;
669 dev->pci_bus = dev->pci->bus->number;
670 dev->pci_slot = PCI_SLOT(dev->pci->devfn);
671 dev->pci_irqmask = 0x001f00;
673 /* External Master 1 Bus */
674 dev->i2c_bus[0].nr = 0;
675 dev->i2c_bus[0].dev = dev;
676 dev->i2c_bus[0].reg_stat = I2C1_STAT;
677 dev->i2c_bus[0].reg_ctrl = I2C1_CTRL;
678 dev->i2c_bus[0].reg_addr = I2C1_ADDR;
679 dev->i2c_bus[0].reg_rdata = I2C1_RDATA;
680 dev->i2c_bus[0].reg_wdata = I2C1_WDATA;
681 dev->i2c_bus[0].i2c_period = (0x9d << 24); /* 100kHz */
683 /* External Master 2 Bus */
684 dev->i2c_bus[1].nr = 1;
685 dev->i2c_bus[1].dev = dev;
686 dev->i2c_bus[1].reg_stat = I2C2_STAT;
687 dev->i2c_bus[1].reg_ctrl = I2C2_CTRL;
688 dev->i2c_bus[1].reg_addr = I2C2_ADDR;
689 dev->i2c_bus[1].reg_rdata = I2C2_RDATA;
690 dev->i2c_bus[1].reg_wdata = I2C2_WDATA;
691 dev->i2c_bus[1].i2c_period = (0x9d << 24); /* 100kHz */
693 /* Internal Master 3 Bus */
694 dev->i2c_bus[2].nr = 2;
695 dev->i2c_bus[2].dev = dev;
696 dev->i2c_bus[2].reg_stat = I2C3_STAT;
697 dev->i2c_bus[2].reg_ctrl = I2C3_CTRL;
698 dev->i2c_bus[2].reg_addr = I2C3_ADDR;
699 dev->i2c_bus[2].reg_rdata = I2C3_RDATA;
700 dev->i2c_bus[2].reg_wdata = I2C3_WDATA;
701 dev->i2c_bus[2].i2c_period = (0x07 << 24); /* 1.95MHz */
703 if ((cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) ||
704 (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER))
705 cx23885_init_tsport(dev, &dev->ts1, 1);
707 if ((cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) ||
708 (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER))
709 cx23885_init_tsport(dev, &dev->ts2, 2);
711 if (get_resources(dev) < 0) {
712 printk(KERN_ERR "CORE %s No more PCIe resources for "
713 "subsystem: %04x:%04x\n",
714 dev->name, dev->pci->subsystem_vendor,
715 dev->pci->subsystem_device);
722 dev->lmmio = ioremap(pci_resource_start(dev->pci,0),
723 pci_resource_len(dev->pci,0));
725 dev->bmmio = (u8 __iomem *)dev->lmmio;
727 printk(KERN_INFO "CORE %s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
728 dev->name, dev->pci->subsystem_vendor,
729 dev->pci->subsystem_device, cx23885_boards[dev->board].name,
730 dev->board, card[dev->nr] == dev->board ?
731 "insmod option" : "autodetected");
733 cx23885_pci_quirks(dev);
735 /* Assume some sensible defaults */
736 dev->tuner_type = cx23885_boards[dev->board].tuner_type;
737 dev->tuner_addr = cx23885_boards[dev->board].tuner_addr;
738 dev->radio_type = cx23885_boards[dev->board].radio_type;
739 dev->radio_addr = cx23885_boards[dev->board].radio_addr;
741 dprintk(1, "%s() tuner_type = 0x%x tuner_addr = 0x%x\n",
742 __func__, dev->tuner_type, dev->tuner_addr);
743 dprintk(1, "%s() radio_type = 0x%x radio_addr = 0x%x\n",
744 __func__, dev->radio_type, dev->radio_addr);
749 cx23885_i2c_register(&dev->i2c_bus[0]);
750 cx23885_i2c_register(&dev->i2c_bus[1]);
751 cx23885_i2c_register(&dev->i2c_bus[2]);
752 cx23885_card_setup(dev);
753 cx23885_call_i2c_clients (&dev->i2c_bus[0], TUNER_SET_STANDBY, NULL);
754 cx23885_ir_init(dev);
756 if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO) {
757 if (cx23885_video_register(dev) < 0) {
758 printk(KERN_ERR "%s() Failed to register analog "
759 "video adapters on VID_A\n", __func__);
763 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) {
764 if (cx23885_dvb_register(&dev->ts1) < 0) {
765 printk(KERN_ERR "%s() Failed to register dvb adapters on VID_B\n",
769 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
770 if (cx23885_417_register(dev) < 0) {
772 "%s() Failed to register 417 on VID_B\n",
777 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) {
778 if (cx23885_dvb_register(&dev->ts2) < 0) {
780 "%s() Failed to register dvb on VID_C\n",
784 if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER) {
785 if (cx23885_417_register(dev) < 0) {
787 "%s() Failed to register 417 on VID_C\n",
792 cx23885_dev_checkrevision(dev);
797 static void cx23885_dev_unregister(struct cx23885_dev *dev)
799 release_mem_region(pci_resource_start(dev->pci,0),
800 pci_resource_len(dev->pci,0));
802 if (!atomic_dec_and_test(&dev->refcount))
805 if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO)
806 cx23885_video_unregister(dev);
808 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
809 cx23885_dvb_unregister(&dev->ts1);
811 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
812 cx23885_417_unregister(dev);
814 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
815 cx23885_dvb_unregister(&dev->ts2);
817 if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER)
818 cx23885_417_unregister(dev);
820 cx23885_i2c_unregister(&dev->i2c_bus[2]);
821 cx23885_i2c_unregister(&dev->i2c_bus[1]);
822 cx23885_i2c_unregister(&dev->i2c_bus[0]);
827 static __le32* cx23885_risc_field(__le32 *rp, struct scatterlist *sglist,
828 unsigned int offset, u32 sync_line,
829 unsigned int bpl, unsigned int padding,
832 struct scatterlist *sg;
833 unsigned int line, todo;
835 /* sync instruction */
836 if (sync_line != NO_SYNC_LINE)
837 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
841 for (line = 0; line < lines; line++) {
842 while (offset && offset >= sg_dma_len(sg)) {
843 offset -= sg_dma_len(sg);
846 if (bpl <= sg_dma_len(sg)-offset) {
847 /* fits into current chunk */
848 *(rp++)=cpu_to_le32(RISC_WRITE|RISC_SOL|RISC_EOL|bpl);
849 *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset);
850 *(rp++)=cpu_to_le32(0); /* bits 63-32 */
853 /* scanline needs to be split */
855 *(rp++)=cpu_to_le32(RISC_WRITE|RISC_SOL|
856 (sg_dma_len(sg)-offset));
857 *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset);
858 *(rp++)=cpu_to_le32(0); /* bits 63-32 */
859 todo -= (sg_dma_len(sg)-offset);
862 while (todo > sg_dma_len(sg)) {
863 *(rp++)=cpu_to_le32(RISC_WRITE|
865 *(rp++)=cpu_to_le32(sg_dma_address(sg));
866 *(rp++)=cpu_to_le32(0); /* bits 63-32 */
867 todo -= sg_dma_len(sg);
870 *(rp++)=cpu_to_le32(RISC_WRITE|RISC_EOL|todo);
871 *(rp++)=cpu_to_le32(sg_dma_address(sg));
872 *(rp++)=cpu_to_le32(0); /* bits 63-32 */
881 int cx23885_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
882 struct scatterlist *sglist, unsigned int top_offset,
883 unsigned int bottom_offset, unsigned int bpl,
884 unsigned int padding, unsigned int lines)
886 u32 instructions, fields;
891 if (UNSET != top_offset)
893 if (UNSET != bottom_offset)
896 /* estimate risc mem: worst case is one write per page border +
897 one write per scan line + syncs + jump (all 2 dwords). Padding
898 can cause next bpl to start close to a page border. First DMA
899 region may be smaller than PAGE_SIZE */
900 /* write and jump need and extra dword */
901 instructions = fields * (1 + ((bpl + padding) * lines) / PAGE_SIZE + lines);
903 if ((rc = btcx_riscmem_alloc(pci,risc,instructions*12)) < 0)
906 /* write risc instructions */
908 if (UNSET != top_offset)
909 rp = cx23885_risc_field(rp, sglist, top_offset, 0,
910 bpl, padding, lines);
911 if (UNSET != bottom_offset)
912 rp = cx23885_risc_field(rp, sglist, bottom_offset, 0x200,
913 bpl, padding, lines);
915 /* save pointer to jmp instruction address */
917 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof (*risc->cpu) > risc->size);
921 static int cx23885_risc_databuffer(struct pci_dev *pci,
922 struct btcx_riscmem *risc,
923 struct scatterlist *sglist,
931 /* estimate risc mem: worst case is one write per page border +
932 one write per scan line + syncs + jump (all 2 dwords). Here
933 there is no padding and no sync. First DMA region may be smaller
935 /* Jump and write need an extra dword */
936 instructions = 1 + (bpl * lines) / PAGE_SIZE + lines;
939 if ((rc = btcx_riscmem_alloc(pci,risc,instructions*12)) < 0)
942 /* write risc instructions */
944 rp = cx23885_risc_field(rp, sglist, 0, NO_SYNC_LINE, bpl, 0, lines);
946 /* save pointer to jmp instruction address */
948 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof (*risc->cpu) > risc->size);
952 int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
953 u32 reg, u32 mask, u32 value)
958 if ((rc = btcx_riscmem_alloc(pci, risc, 4*16)) < 0)
961 /* write risc instructions */
963 *(rp++) = cpu_to_le32(RISC_WRITECR | RISC_IRQ2);
964 *(rp++) = cpu_to_le32(reg);
965 *(rp++) = cpu_to_le32(value);
966 *(rp++) = cpu_to_le32(mask);
967 *(rp++) = cpu_to_le32(RISC_JUMP);
968 *(rp++) = cpu_to_le32(risc->dma);
969 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
973 void cx23885_free_buffer(struct videobuf_queue *q, struct cx23885_buffer *buf)
975 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
977 BUG_ON(in_interrupt());
978 videobuf_waiton(&buf->vb, 0, 0);
979 videobuf_dma_unmap(q, dma);
980 videobuf_dma_free(dma);
981 btcx_riscmem_free(to_pci_dev(q->dev), &buf->risc);
982 buf->vb.state = VIDEOBUF_NEEDS_INIT;
985 static void cx23885_tsport_reg_dump(struct cx23885_tsport *port)
987 struct cx23885_dev *dev = port->dev;
989 dprintk(1, "%s() Register Dump\n", __func__);
990 dprintk(1, "%s() DEV_CNTRL2 0x%08X\n", __func__,
991 cx_read(DEV_CNTRL2));
992 dprintk(1, "%s() PCI_INT_MSK 0x%08X\n", __func__,
993 cx_read(PCI_INT_MSK));
994 dprintk(1, "%s() AUD_INT_INT_MSK 0x%08X\n", __func__,
995 cx_read(AUDIO_INT_INT_MSK));
996 dprintk(1, "%s() AUD_INT_DMA_CTL 0x%08X\n", __func__,
997 cx_read(AUD_INT_DMA_CTL));
998 dprintk(1, "%s() AUD_EXT_INT_MSK 0x%08X\n", __func__,
999 cx_read(AUDIO_EXT_INT_MSK));
1000 dprintk(1, "%s() AUD_EXT_DMA_CTL 0x%08X\n", __func__,
1001 cx_read(AUD_EXT_DMA_CTL));
1002 dprintk(1, "%s() PAD_CTRL 0x%08X\n", __func__,
1004 dprintk(1, "%s() ALT_PIN_OUT_SEL 0x%08X\n", __func__,
1005 cx_read(ALT_PIN_OUT_SEL));
1006 dprintk(1, "%s() GPIO2 0x%08X\n", __func__,
1008 dprintk(1, "%s() gpcnt(0x%08X) 0x%08X\n", __func__,
1009 port->reg_gpcnt, cx_read(port->reg_gpcnt));
1010 dprintk(1, "%s() gpcnt_ctl(0x%08X) 0x%08x\n", __func__,
1011 port->reg_gpcnt_ctl, cx_read(port->reg_gpcnt_ctl));
1012 dprintk(1, "%s() dma_ctl(0x%08X) 0x%08x\n", __func__,
1013 port->reg_dma_ctl, cx_read(port->reg_dma_ctl));
1014 dprintk(1, "%s() src_sel(0x%08X) 0x%08x\n", __func__,
1015 port->reg_src_sel, cx_read(port->reg_src_sel));
1016 dprintk(1, "%s() lngth(0x%08X) 0x%08x\n", __func__,
1017 port->reg_lngth, cx_read(port->reg_lngth));
1018 dprintk(1, "%s() hw_sop_ctrl(0x%08X) 0x%08x\n", __func__,
1019 port->reg_hw_sop_ctrl, cx_read(port->reg_hw_sop_ctrl));
1020 dprintk(1, "%s() gen_ctrl(0x%08X) 0x%08x\n", __func__,
1021 port->reg_gen_ctrl, cx_read(port->reg_gen_ctrl));
1022 dprintk(1, "%s() bd_pkt_status(0x%08X) 0x%08x\n", __func__,
1023 port->reg_bd_pkt_status, cx_read(port->reg_bd_pkt_status));
1024 dprintk(1, "%s() sop_status(0x%08X) 0x%08x\n", __func__,
1025 port->reg_sop_status, cx_read(port->reg_sop_status));
1026 dprintk(1, "%s() fifo_ovfl_stat(0x%08X) 0x%08x\n", __func__,
1027 port->reg_fifo_ovfl_stat, cx_read(port->reg_fifo_ovfl_stat));
1028 dprintk(1, "%s() vld_misc(0x%08X) 0x%08x\n", __func__,
1029 port->reg_vld_misc, cx_read(port->reg_vld_misc));
1030 dprintk(1, "%s() ts_clk_en(0x%08X) 0x%08x\n", __func__,
1031 port->reg_ts_clk_en, cx_read(port->reg_ts_clk_en));
1032 dprintk(1, "%s() ts_int_msk(0x%08X) 0x%08x\n", __func__,
1033 port->reg_ts_int_msk, cx_read(port->reg_ts_int_msk));
1036 static int cx23885_start_dma(struct cx23885_tsport *port,
1037 struct cx23885_dmaqueue *q,
1038 struct cx23885_buffer *buf)
1040 struct cx23885_dev *dev = port->dev;
1043 dprintk(1, "%s() w: %d, h: %d, f: %d\n", __func__,
1044 buf->vb.width, buf->vb.height, buf->vb.field);
1046 /* setup fifo + format */
1047 cx23885_sram_channel_setup(dev,
1048 &dev->sram_channels[ port->sram_chno ],
1049 port->ts_packet_size, buf->risc.dma);
1051 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ] );
1052 cx23885_risc_disasm(port, &buf->risc);
1055 /* write TS length to chip */
1056 cx_write(port->reg_lngth, buf->vb.width);
1058 if ( (!(cx23885_boards[dev->board].portb & CX23885_MPEG_DVB)) &&
1059 (!(cx23885_boards[dev->board].portc & CX23885_MPEG_DVB)) ) {
1060 printk( "%s() Failed. Unsupported value in .portb/c (0x%08x)/(0x%08x)\n",
1062 cx23885_boards[dev->board].portb,
1063 cx23885_boards[dev->board].portc );
1067 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1068 cx23885_av_clk(dev, 0);
1072 /* If the port supports SRC SELECT, configure it */
1073 if(port->reg_src_sel)
1074 cx_write(port->reg_src_sel, port->src_sel_val);
1076 cx_write(port->reg_hw_sop_ctrl, port->hw_sop_ctrl_val);
1077 cx_write(port->reg_ts_clk_en, port->ts_clk_en_val);
1078 cx_write(port->reg_vld_misc, port->vld_misc_val);
1079 cx_write(port->reg_gen_ctrl, port->gen_ctrl_val);
1082 // NOTE: this is 2 (reserved) for portb, does it matter?
1083 /* reset counter to zero */
1084 cx_write(port->reg_gpcnt_ctl, 3);
1087 /* Set VIDB pins to input */
1088 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) {
1089 reg = cx_read(PAD_CTRL);
1090 reg &= ~0x3; /* Clear TS1_OE & TS1_SOP_OE */
1091 cx_write(PAD_CTRL, reg);
1094 /* Set VIDC pins to input */
1095 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) {
1096 reg = cx_read(PAD_CTRL);
1097 reg &= ~0x4; /* Clear TS2_SOP_OE */
1098 cx_write(PAD_CTRL, reg);
1101 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
1103 reg = cx_read(PAD_CTRL);
1104 reg = reg & ~0x1; /* Clear TS1_OE */
1106 /* FIXME, bit 2 writing here is questionable */
1107 /* set TS1_SOP_OE and TS1_OE_HI */
1109 cx_write(PAD_CTRL, reg);
1111 /* FIXME and these two registers should be documented. */
1112 cx_write(CLK_DELAY, cx_read(CLK_DELAY) | 0x80000011);
1113 cx_write(ALT_PIN_OUT_SEL, 0x10100045);
1116 switch(dev->bridge) {
1117 case CX23885_BRIDGE_885:
1118 case CX23885_BRIDGE_887:
1120 dprintk(1, "%s() enabling TS int's and DMA\n", __func__ );
1121 cx_set(port->reg_ts_int_msk, port->ts_int_msk_val);
1122 cx_set(port->reg_dma_ctl, port->dma_ctl_val);
1123 cx_set(PCI_INT_MSK, dev->pci_irqmask | port->pci_irqmask);
1129 cx_set(DEV_CNTRL2, (1<<5)); /* Enable RISC controller */
1131 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1132 cx23885_av_clk(dev, 1);
1135 cx23885_tsport_reg_dump(port);
1140 static int cx23885_stop_dma(struct cx23885_tsport *port)
1142 struct cx23885_dev *dev = port->dev;
1145 dprintk(1, "%s()\n", __func__);
1147 /* Stop interrupts and DMA */
1148 cx_clear(port->reg_ts_int_msk, port->ts_int_msk_val);
1149 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1151 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
1153 reg = cx_read(PAD_CTRL);
1158 /* clear TS1_SOP_OE and TS1_OE_HI */
1160 cx_write(PAD_CTRL, reg);
1161 cx_write(port->reg_src_sel, 0);
1162 cx_write(port->reg_gen_ctrl, 8);
1166 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1167 cx23885_av_clk(dev, 0);
1172 int cx23885_restart_queue(struct cx23885_tsport *port,
1173 struct cx23885_dmaqueue *q)
1175 struct cx23885_dev *dev = port->dev;
1176 struct cx23885_buffer *buf;
1178 dprintk(5, "%s()\n", __func__);
1179 if (list_empty(&q->active))
1181 struct cx23885_buffer *prev;
1184 dprintk(5, "%s() queue is empty\n", __func__);
1187 if (list_empty(&q->queued))
1189 buf = list_entry(q->queued.next, struct cx23885_buffer,
1192 list_del(&buf->vb.queue);
1193 list_add_tail(&buf->vb.queue, &q->active);
1194 cx23885_start_dma(port, q, buf);
1195 buf->vb.state = VIDEOBUF_ACTIVE;
1196 buf->count = q->count++;
1197 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT);
1198 dprintk(5, "[%p/%d] restart_queue - first active\n",
1201 } else if (prev->vb.width == buf->vb.width &&
1202 prev->vb.height == buf->vb.height &&
1203 prev->fmt == buf->fmt) {
1204 list_del(&buf->vb.queue);
1205 list_add_tail(&buf->vb.queue, &q->active);
1206 buf->vb.state = VIDEOBUF_ACTIVE;
1207 buf->count = q->count++;
1208 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1209 prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1210 dprintk(5,"[%p/%d] restart_queue - move to active\n",
1220 buf = list_entry(q->active.next, struct cx23885_buffer, vb.queue);
1221 dprintk(2, "restart_queue [%p/%d]: restart dma\n",
1223 cx23885_start_dma(port, q, buf);
1224 list_for_each_entry(buf, &q->active, vb.queue)
1225 buf->count = q->count++;
1226 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
1230 /* ------------------------------------------------------------------ */
1232 int cx23885_buf_prepare(struct videobuf_queue *q, struct cx23885_tsport *port,
1233 struct cx23885_buffer *buf, enum v4l2_field field)
1235 struct cx23885_dev *dev = port->dev;
1236 int size = port->ts_packet_size * port->ts_packet_count;
1239 dprintk(1, "%s: %p\n", __func__, buf);
1240 if (0 != buf->vb.baddr && buf->vb.bsize < size)
1243 if (VIDEOBUF_NEEDS_INIT == buf->vb.state) {
1244 buf->vb.width = port->ts_packet_size;
1245 buf->vb.height = port->ts_packet_count;
1246 buf->vb.size = size;
1247 buf->vb.field = field /*V4L2_FIELD_TOP*/;
1249 if (0 != (rc = videobuf_iolock(q, &buf->vb, NULL)))
1251 cx23885_risc_databuffer(dev->pci, &buf->risc,
1252 videobuf_to_dma(&buf->vb)->sglist,
1253 buf->vb.width, buf->vb.height);
1255 buf->vb.state = VIDEOBUF_PREPARED;
1259 cx23885_free_buffer(q, buf);
1263 void cx23885_buf_queue(struct cx23885_tsport *port, struct cx23885_buffer *buf)
1265 struct cx23885_buffer *prev;
1266 struct cx23885_dev *dev = port->dev;
1267 struct cx23885_dmaqueue *cx88q = &port->mpegq;
1269 /* add jump to stopper */
1270 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
1271 buf->risc.jmp[1] = cpu_to_le32(cx88q->stopper.dma);
1272 buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
1274 if (list_empty(&cx88q->active)) {
1275 dprintk( 1, "queue is empty - first active\n" );
1276 list_add_tail(&buf->vb.queue, &cx88q->active);
1277 cx23885_start_dma(port, cx88q, buf);
1278 buf->vb.state = VIDEOBUF_ACTIVE;
1279 buf->count = cx88q->count++;
1280 mod_timer(&cx88q->timeout, jiffies + BUFFER_TIMEOUT);
1281 dprintk(1, "[%p/%d] %s - first active\n",
1282 buf, buf->vb.i, __func__);
1284 dprintk( 1, "queue is not empty - append to active\n" );
1285 prev = list_entry(cx88q->active.prev, struct cx23885_buffer,
1287 list_add_tail(&buf->vb.queue, &cx88q->active);
1288 buf->vb.state = VIDEOBUF_ACTIVE;
1289 buf->count = cx88q->count++;
1290 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1291 prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1292 dprintk( 1, "[%p/%d] %s - append to active\n",
1293 buf, buf->vb.i, __func__);
1297 /* ----------------------------------------------------------- */
1299 static void do_cancel_buffers(struct cx23885_tsport *port, char *reason,
1302 struct cx23885_dev *dev = port->dev;
1303 struct cx23885_dmaqueue *q = &port->mpegq;
1304 struct cx23885_buffer *buf;
1305 unsigned long flags;
1307 spin_lock_irqsave(&port->slock, flags);
1308 while (!list_empty(&q->active)) {
1309 buf = list_entry(q->active.next, struct cx23885_buffer,
1311 list_del(&buf->vb.queue);
1312 buf->vb.state = VIDEOBUF_ERROR;
1313 wake_up(&buf->vb.done);
1314 dprintk(1, "[%p/%d] %s - dma=0x%08lx\n",
1315 buf, buf->vb.i, reason, (unsigned long)buf->risc.dma);
1318 dprintk(1, "restarting queue\n" );
1319 cx23885_restart_queue(port, q);
1321 spin_unlock_irqrestore(&port->slock, flags);
1324 void cx23885_cancel_buffers(struct cx23885_tsport *port)
1326 struct cx23885_dev *dev = port->dev;
1327 struct cx23885_dmaqueue *q = &port->mpegq;
1329 dprintk(1, "%s()\n", __FUNCTION__);
1330 del_timer_sync(&q->timeout);
1331 cx23885_stop_dma(port);
1332 do_cancel_buffers(port, "cancel", 0);
1335 static void cx23885_timeout(unsigned long data)
1337 struct cx23885_tsport *port = (struct cx23885_tsport *)data;
1338 struct cx23885_dev *dev = port->dev;
1340 dprintk(1, "%s()\n",__func__);
1343 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ]);
1345 cx23885_stop_dma(port);
1346 do_cancel_buffers(port, "timeout", 1);
1349 int cx23885_irq_417(struct cx23885_dev *dev, u32 status)
1351 /* FIXME: port1 assumption here. */
1352 struct cx23885_tsport *port = &dev->ts1;
1359 count = cx_read(port->reg_gpcnt);
1360 dprintk(7, "status: 0x%08x mask: 0x%08x count: 0x%x\n",
1361 status, cx_read(port->reg_ts_int_msk), count);
1363 if ((status & VID_B_MSK_BAD_PKT) ||
1364 (status & VID_B_MSK_OPC_ERR) ||
1365 (status & VID_B_MSK_VBI_OPC_ERR) ||
1366 (status & VID_B_MSK_SYNC) ||
1367 (status & VID_B_MSK_VBI_SYNC) ||
1368 (status & VID_B_MSK_OF) ||
1369 (status & VID_B_MSK_VBI_OF)) {
1370 printk(KERN_ERR "%s: V4L mpeg risc op code error, status "
1371 "= 0x%x\n", dev->name, status);
1372 if (status & VID_B_MSK_BAD_PKT)
1373 dprintk(1, " VID_B_MSK_BAD_PKT\n");
1374 if (status & VID_B_MSK_OPC_ERR)
1375 dprintk(1, " VID_B_MSK_OPC_ERR\n");
1376 if (status & VID_B_MSK_VBI_OPC_ERR)
1377 dprintk(1, " VID_B_MSK_VBI_OPC_ERR\n");
1378 if (status & VID_B_MSK_SYNC)
1379 dprintk(1, " VID_B_MSK_SYNC\n");
1380 if (status & VID_B_MSK_VBI_SYNC)
1381 dprintk(1, " VID_B_MSK_VBI_SYNC\n");
1382 if (status & VID_B_MSK_OF)
1383 dprintk(1, " VID_B_MSK_OF\n");
1384 if (status & VID_B_MSK_VBI_OF)
1385 dprintk(1, " VID_B_MSK_VBI_OF\n");
1387 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1388 cx23885_sram_channel_dump(dev,
1389 &dev->sram_channels[port->sram_chno]);
1390 cx23885_417_check_encoder(dev);
1391 } else if (status & VID_B_MSK_RISCI1) {
1392 dprintk(7, " VID_B_MSK_RISCI1\n");
1393 spin_lock(&port->slock);
1394 cx23885_wakeup(port, &port->mpegq, count);
1395 spin_unlock(&port->slock);
1396 } else if (status & VID_B_MSK_RISCI2) {
1397 dprintk(7, " VID_B_MSK_RISCI2\n");
1398 spin_lock(&port->slock);
1399 cx23885_restart_queue(port, &port->mpegq);
1400 spin_unlock(&port->slock);
1403 cx_write(port->reg_ts_int_stat, status);
1410 static int cx23885_irq_ts(struct cx23885_tsport *port, u32 status)
1412 struct cx23885_dev *dev = port->dev;
1416 if ((status & VID_BC_MSK_OPC_ERR) ||
1417 (status & VID_BC_MSK_BAD_PKT) ||
1418 (status & VID_BC_MSK_SYNC) ||
1419 (status & VID_BC_MSK_OF))
1421 if (status & VID_BC_MSK_OPC_ERR)
1422 dprintk(7, " (VID_BC_MSK_OPC_ERR 0x%08x)\n", VID_BC_MSK_OPC_ERR);
1423 if (status & VID_BC_MSK_BAD_PKT)
1424 dprintk(7, " (VID_BC_MSK_BAD_PKT 0x%08x)\n", VID_BC_MSK_BAD_PKT);
1425 if (status & VID_BC_MSK_SYNC)
1426 dprintk(7, " (VID_BC_MSK_SYNC 0x%08x)\n", VID_BC_MSK_SYNC);
1427 if (status & VID_BC_MSK_OF)
1428 dprintk(7, " (VID_BC_MSK_OF 0x%08x)\n", VID_BC_MSK_OF);
1430 printk(KERN_ERR "%s: mpeg risc op code error\n", dev->name);
1432 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1433 cx23885_sram_channel_dump(dev,
1434 &dev->sram_channels[port->sram_chno]);
1436 } else if (status & VID_BC_MSK_RISCI1) {
1438 dprintk(7, " (RISCI1 0x%08x)\n", VID_BC_MSK_RISCI1);
1440 spin_lock(&port->slock);
1441 count = cx_read(port->reg_gpcnt);
1442 cx23885_wakeup(port, &port->mpegq, count);
1443 spin_unlock(&port->slock);
1445 } else if (status & VID_BC_MSK_RISCI2) {
1447 dprintk(7, " (RISCI2 0x%08x)\n", VID_BC_MSK_RISCI2);
1449 spin_lock(&port->slock);
1450 cx23885_restart_queue(port, &port->mpegq);
1451 spin_unlock(&port->slock);
1455 cx_write(port->reg_ts_int_stat, status);
1462 static irqreturn_t cx23885_irq(int irq, void *dev_id)
1464 struct cx23885_dev *dev = dev_id;
1465 struct cx23885_tsport *ts1 = &dev->ts1;
1466 struct cx23885_tsport *ts2 = &dev->ts2;
1467 u32 pci_status, pci_mask;
1468 u32 vida_status, vida_mask;
1469 u32 ts1_status, ts1_mask;
1470 u32 ts2_status, ts2_mask;
1471 int vida_count = 0, ts1_count = 0, ts2_count = 0, handled = 0;
1473 pci_status = cx_read(PCI_INT_STAT);
1474 pci_mask = cx_read(PCI_INT_MSK);
1475 vida_status = cx_read(VID_A_INT_STAT);
1476 vida_mask = cx_read(VID_A_INT_MSK);
1477 ts1_status = cx_read(VID_B_INT_STAT);
1478 ts1_mask = cx_read(VID_B_INT_MSK);
1479 ts2_status = cx_read(VID_C_INT_STAT);
1480 ts2_mask = cx_read(VID_C_INT_MSK);
1482 if ( (pci_status == 0) && (ts2_status == 0) && (ts1_status == 0) )
1485 vida_count = cx_read(VID_A_GPCNT);
1486 ts1_count = cx_read(ts1->reg_gpcnt);
1487 ts2_count = cx_read(ts2->reg_gpcnt);
1488 dprintk(7, "pci_status: 0x%08x pci_mask: 0x%08x\n",
1489 pci_status, pci_mask);
1490 dprintk(7, "vida_status: 0x%08x vida_mask: 0x%08x count: 0x%x\n",
1491 vida_status, vida_mask, vida_count);
1492 dprintk(7, "ts1_status: 0x%08x ts1_mask: 0x%08x count: 0x%x\n",
1493 ts1_status, ts1_mask, ts1_count);
1494 dprintk(7, "ts2_status: 0x%08x ts2_mask: 0x%08x count: 0x%x\n",
1495 ts2_status, ts2_mask, ts2_count);
1497 if ( (pci_status & PCI_MSK_RISC_RD) ||
1498 (pci_status & PCI_MSK_RISC_WR) ||
1499 (pci_status & PCI_MSK_AL_RD) ||
1500 (pci_status & PCI_MSK_AL_WR) ||
1501 (pci_status & PCI_MSK_APB_DMA) ||
1502 (pci_status & PCI_MSK_VID_C) ||
1503 (pci_status & PCI_MSK_VID_B) ||
1504 (pci_status & PCI_MSK_VID_A) ||
1505 (pci_status & PCI_MSK_AUD_INT) ||
1506 (pci_status & PCI_MSK_AUD_EXT) )
1509 if (pci_status & PCI_MSK_RISC_RD)
1510 dprintk(7, " (PCI_MSK_RISC_RD 0x%08x)\n", PCI_MSK_RISC_RD);
1511 if (pci_status & PCI_MSK_RISC_WR)
1512 dprintk(7, " (PCI_MSK_RISC_WR 0x%08x)\n", PCI_MSK_RISC_WR);
1513 if (pci_status & PCI_MSK_AL_RD)
1514 dprintk(7, " (PCI_MSK_AL_RD 0x%08x)\n", PCI_MSK_AL_RD);
1515 if (pci_status & PCI_MSK_AL_WR)
1516 dprintk(7, " (PCI_MSK_AL_WR 0x%08x)\n", PCI_MSK_AL_WR);
1517 if (pci_status & PCI_MSK_APB_DMA)
1518 dprintk(7, " (PCI_MSK_APB_DMA 0x%08x)\n", PCI_MSK_APB_DMA);
1519 if (pci_status & PCI_MSK_VID_C)
1520 dprintk(7, " (PCI_MSK_VID_C 0x%08x)\n", PCI_MSK_VID_C);
1521 if (pci_status & PCI_MSK_VID_B)
1522 dprintk(7, " (PCI_MSK_VID_B 0x%08x)\n", PCI_MSK_VID_B);
1523 if (pci_status & PCI_MSK_VID_A)
1524 dprintk(7, " (PCI_MSK_VID_A 0x%08x)\n", PCI_MSK_VID_A);
1525 if (pci_status & PCI_MSK_AUD_INT)
1526 dprintk(7, " (PCI_MSK_AUD_INT 0x%08x)\n", PCI_MSK_AUD_INT);
1527 if (pci_status & PCI_MSK_AUD_EXT)
1528 dprintk(7, " (PCI_MSK_AUD_EXT 0x%08x)\n", PCI_MSK_AUD_EXT);
1533 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
1534 handled += cx23885_irq_ts(ts1, ts1_status);
1536 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1537 handled += cx23885_irq_417(dev, ts1_status);
1541 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
1542 handled += cx23885_irq_ts(ts2, ts2_status);
1544 if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER)
1545 handled += cx23885_irq_417(dev, ts2_status);
1549 handled += cx23885_video_irq(dev, vida_status);
1552 cx_write(PCI_INT_STAT, pci_status);
1554 return IRQ_RETVAL(handled);
1557 static int __devinit cx23885_initdev(struct pci_dev *pci_dev,
1558 const struct pci_device_id *pci_id)
1560 struct cx23885_dev *dev;
1563 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1569 if (pci_enable_device(pci_dev)) {
1574 if (cx23885_dev_setup(dev) < 0) {
1579 /* print pci info */
1580 pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev);
1581 pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat);
1582 printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, "
1583 "latency: %d, mmio: 0x%llx\n", dev->name,
1584 pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
1586 (unsigned long long)pci_resource_start(pci_dev, 0));
1588 pci_set_master(pci_dev);
1589 if (!pci_dma_supported(pci_dev, 0xffffffff)) {
1590 printk("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name);
1595 err = request_irq(pci_dev->irq, cx23885_irq,
1596 IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
1598 printk(KERN_ERR "%s: can't get IRQ %d\n",
1599 dev->name, pci_dev->irq);
1603 pci_set_drvdata(pci_dev, dev);
1607 cx23885_dev_unregister(dev);
1613 static void __devexit cx23885_finidev(struct pci_dev *pci_dev)
1615 struct cx23885_dev *dev = pci_get_drvdata(pci_dev);
1617 cx23885_shutdown(dev);
1619 pci_disable_device(pci_dev);
1621 /* unregister stuff */
1622 free_irq(pci_dev->irq, dev);
1623 pci_set_drvdata(pci_dev, NULL);
1625 mutex_lock(&devlist);
1626 list_del(&dev->devlist);
1627 mutex_unlock(&devlist);
1629 cx23885_dev_unregister(dev);
1633 static struct pci_device_id cx23885_pci_tbl[] = {
1638 .subvendor = PCI_ANY_ID,
1639 .subdevice = PCI_ANY_ID,
1644 .subvendor = PCI_ANY_ID,
1645 .subdevice = PCI_ANY_ID,
1647 /* --- end of list --- */
1650 MODULE_DEVICE_TABLE(pci, cx23885_pci_tbl);
1652 static struct pci_driver cx23885_pci_driver = {
1654 .id_table = cx23885_pci_tbl,
1655 .probe = cx23885_initdev,
1656 .remove = __devexit_p(cx23885_finidev),
1662 static int cx23885_init(void)
1664 printk(KERN_INFO "cx23885 driver version %d.%d.%d loaded\n",
1665 (CX23885_VERSION_CODE >> 16) & 0xff,
1666 (CX23885_VERSION_CODE >> 8) & 0xff,
1667 CX23885_VERSION_CODE & 0xff);
1669 printk(KERN_INFO "cx23885: snapshot date %04d-%02d-%02d\n",
1670 SNAPSHOT/10000, (SNAPSHOT/100)%100, SNAPSHOT%100);
1672 return pci_register_driver(&cx23885_pci_driver);
1675 static void cx23885_fini(void)
1677 pci_unregister_driver(&cx23885_pci_driver);
1680 module_init(cx23885_init);
1681 module_exit(cx23885_fini);
1683 /* ----------------------------------------------------------- */
1688 * kate: eol "unix"; indent-width 3; remove-trailing-space on; replace-trailing-space-save on; tab-width 8; replace-tabs off; space-indent off; mixed-indent off