2 cx231xx_avcore.c - driver for Conexant Cx23100/101/102
3 USB video capture devices
5 Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
7 This program contains the specific code to control the avdecoder chip and
8 other related usb control functions for cx231xx based chipset.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/init.h>
26 #include <linux/list.h>
27 #include <linux/module.h>
28 #include <linux/kernel.h>
29 #include <linux/bitmap.h>
30 #include <linux/usb.h>
31 #include <linux/i2c.h>
33 #include <linux/mutex.h>
34 #include <media/tuner.h>
36 #include <media/v4l2-common.h>
37 #include <media/v4l2-ioctl.h>
38 #include <media/v4l2-chip-ident.h>
41 #include "cx231xx-dif.h"
43 #define TUNER_MODE_FM_RADIO 0
44 /******************************************************************************
45 -: BLOCK ARRANGEMENT :-
46 I2S block ----------------------|
49 Analog Front End --> Direct IF -|-> Cx25840 --> Audio
50 [video & audio] | [Audio]
55 *******************************************************************************/
56 /******************************************************************************
59 ******************************************************************************/
60 static int verve_write_byte(struct cx231xx *dev, u8 saddr, u8 data)
62 return cx231xx_write_i2c_data(dev, VERVE_I2C_ADDRESS,
66 static int verve_read_byte(struct cx231xx *dev, u8 saddr, u8 *data)
71 status = cx231xx_read_i2c_data(dev, VERVE_I2C_ADDRESS,
76 void initGPIO(struct cx231xx *dev)
78 u32 _gpio_direction = 0;
82 _gpio_direction = _gpio_direction & 0xFC0003FF;
83 _gpio_direction = _gpio_direction | 0x03FDFC00;
84 cx231xx_send_gpio_cmd(dev, _gpio_direction, (u8 *)&value, 4, 0, 0);
86 verve_read_byte(dev, 0x07, &val);
87 cx231xx_info(" verve_read_byte address0x07=0x%x\n", val);
88 verve_write_byte(dev, 0x07, 0xF4);
89 verve_read_byte(dev, 0x07, &val);
90 cx231xx_info(" verve_read_byte address0x07=0x%x\n", val);
92 cx231xx_capture_start(dev, 1, 2);
94 cx231xx_mode_register(dev, EP_MODE_SET, 0x0500FE00);
95 cx231xx_mode_register(dev, GBULK_BIT_EN, 0xFFFDFFFF);
98 void uninitGPIO(struct cx231xx *dev)
100 u8 value[4] = { 0, 0, 0, 0 };
102 cx231xx_capture_start(dev, 0, 2);
103 verve_write_byte(dev, 0x07, 0x14);
104 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
108 /******************************************************************************
109 * A F E - B L O C K C O N T R O L functions *
110 * [ANALOG FRONT END] *
111 ******************************************************************************/
112 static int afe_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
114 return cx231xx_write_i2c_data(dev, AFE_DEVICE_ADDRESS,
118 static int afe_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
123 status = cx231xx_read_i2c_data(dev, AFE_DEVICE_ADDRESS,
129 int cx231xx_afe_init_super_block(struct cx231xx *dev, u32 ref_count)
133 u8 afe_power_status = 0;
136 /* super block initialize */
137 temp = (u8) (ref_count & 0xff);
138 status = afe_write_byte(dev, SUP_BLK_TUNE2, temp);
142 status = afe_read_byte(dev, SUP_BLK_TUNE2, &afe_power_status);
146 temp = (u8) ((ref_count & 0x300) >> 8);
148 status = afe_write_byte(dev, SUP_BLK_TUNE1, temp);
152 status = afe_write_byte(dev, SUP_BLK_PLL2, 0x0f);
157 while (afe_power_status != 0x18) {
158 status = afe_write_byte(dev, SUP_BLK_PWRDN, 0x18);
161 ": Init Super Block failed in send cmd\n");
165 status = afe_read_byte(dev, SUP_BLK_PWRDN, &afe_power_status);
166 afe_power_status &= 0xff;
169 ": Init Super Block failed in receive cmd\n");
175 ": Init Super Block force break in loop !!!!\n");
184 /* start tuning filter */
185 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x40);
192 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x00);
197 int cx231xx_afe_init_channels(struct cx231xx *dev)
201 /* power up all 3 channels, clear pd_buffer */
202 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 0x00);
203 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 0x00);
204 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 0x00);
206 /* Enable quantizer calibration */
207 status = afe_write_byte(dev, ADC_COM_QUANT, 0x02);
209 /* channel initialize, force modulator (fb) reset */
210 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x17);
211 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x17);
212 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x17);
214 /* start quantilizer calibration */
215 status = afe_write_byte(dev, ADC_CAL_ATEST_CH1, 0x10);
216 status = afe_write_byte(dev, ADC_CAL_ATEST_CH2, 0x10);
217 status = afe_write_byte(dev, ADC_CAL_ATEST_CH3, 0x10);
220 /* exit modulator (fb) reset */
221 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x07);
222 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x07);
223 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x07);
225 /* enable the pre_clamp in each channel for single-ended input */
226 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 0xf0);
227 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH2, 0xf0);
228 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 0xf0);
230 /* use diode instead of resistor, so set term_en to 0, res_en to 0 */
231 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
232 ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00);
233 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
234 ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00);
235 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
236 ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00);
238 /* dynamic element matching off */
239 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH1, 0x03);
240 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH2, 0x03);
241 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, 0x03);
246 int cx231xx_afe_setup_AFE_for_baseband(struct cx231xx *dev)
251 status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH2, &c_value);
252 c_value &= (~(0x50));
253 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, c_value);
259 The Analog Front End in Cx231xx has 3 channels. These
260 channels are used to share between different inputs
261 like tuner, s-video and composite inputs.
263 channel 1 ----- pin 1 to pin4(in reg is 1-4)
264 channel 2 ----- pin 5 to pin8(in reg is 5-8)
265 channel 3 ----- pin 9 to pin 12(in reg is 9-11)
267 int cx231xx_afe_set_input_mux(struct cx231xx *dev, u32 input_mux)
269 u8 ch1_setting = (u8) input_mux;
270 u8 ch2_setting = (u8) (input_mux >> 8);
271 u8 ch3_setting = (u8) (input_mux >> 16);
275 if (ch1_setting != 0) {
276 status = afe_read_byte(dev, ADC_INPUT_CH1, &value);
277 value &= (!INPUT_SEL_MASK);
278 value |= (ch1_setting - 1) << 4;
280 status = afe_write_byte(dev, ADC_INPUT_CH1, value);
283 if (ch2_setting != 0) {
284 status = afe_read_byte(dev, ADC_INPUT_CH2, &value);
285 value &= (!INPUT_SEL_MASK);
286 value |= (ch2_setting - 1) << 4;
288 status = afe_write_byte(dev, ADC_INPUT_CH2, value);
291 /* For ch3_setting, the value to put in the register is
292 7 less than the input number */
293 if (ch3_setting != 0) {
294 status = afe_read_byte(dev, ADC_INPUT_CH3, &value);
295 value &= (!INPUT_SEL_MASK);
296 value |= (ch3_setting - 1) << 4;
298 status = afe_write_byte(dev, ADC_INPUT_CH3, value);
304 int cx231xx_afe_set_mode(struct cx231xx *dev, enum AFE_MODE mode)
309 * FIXME: We need to implement the AFE code for LOW IF and for HI IF.
310 * Currently, only baseband works.
314 case AFE_MODE_LOW_IF:
315 cx231xx_Setup_AFE_for_LowIF(dev);
317 case AFE_MODE_BASEBAND:
318 status = cx231xx_afe_setup_AFE_for_baseband(dev);
320 case AFE_MODE_EU_HI_IF:
321 /* SetupAFEforEuHiIF(); */
323 case AFE_MODE_US_HI_IF:
324 /* SetupAFEforUsHiIF(); */
326 case AFE_MODE_JAPAN_HI_IF:
327 /* SetupAFEforJapanHiIF(); */
331 if ((mode != dev->afe_mode) &&
332 (dev->video_input == CX231XX_VMUX_TELEVISION))
333 status = cx231xx_afe_adjust_ref_count(dev,
334 CX231XX_VMUX_TELEVISION);
336 dev->afe_mode = mode;
341 int cx231xx_afe_update_power_control(struct cx231xx *dev,
344 u8 afe_power_status = 0;
347 switch (dev->model) {
348 case CX231XX_BOARD_CNXT_CARRAERA:
349 case CX231XX_BOARD_CNXT_RDE_250:
350 case CX231XX_BOARD_CNXT_SHELBY:
351 case CX231XX_BOARD_CNXT_RDU_250:
352 case CX231XX_BOARD_CNXT_RDE_253S:
353 case CX231XX_BOARD_CNXT_RDU_253S:
354 case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
355 case CX231XX_BOARD_HAUPPAUGE_EXETER:
356 case CX231XX_BOARD_HAUPPAUGE_USBLIVE2:
357 if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
358 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
359 FLD_PWRDN_ENABLE_PLL)) {
360 status = afe_write_byte(dev, SUP_BLK_PWRDN,
361 FLD_PWRDN_TUNING_BIAS |
362 FLD_PWRDN_ENABLE_PLL);
363 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
369 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
371 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
373 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
375 } else if (avmode == POLARIS_AVMODE_DIGITAL) {
376 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
378 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
380 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
383 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
385 afe_power_status |= FLD_PWRDN_PD_BANDGAP |
388 status |= afe_write_byte(dev, SUP_BLK_PWRDN,
390 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
391 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
392 FLD_PWRDN_ENABLE_PLL)) {
393 status = afe_write_byte(dev, SUP_BLK_PWRDN,
394 FLD_PWRDN_TUNING_BIAS |
395 FLD_PWRDN_ENABLE_PLL);
396 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
402 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
404 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
406 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
409 cx231xx_info("Invalid AV mode input\n");
414 if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
415 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
416 FLD_PWRDN_ENABLE_PLL)) {
417 status = afe_write_byte(dev, SUP_BLK_PWRDN,
418 FLD_PWRDN_TUNING_BIAS |
419 FLD_PWRDN_ENABLE_PLL);
420 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
426 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
428 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
430 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
432 } else if (avmode == POLARIS_AVMODE_DIGITAL) {
433 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
435 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
437 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
440 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
442 afe_power_status |= FLD_PWRDN_PD_BANDGAP |
445 status |= afe_write_byte(dev, SUP_BLK_PWRDN,
447 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
448 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
449 FLD_PWRDN_ENABLE_PLL)) {
450 status = afe_write_byte(dev, SUP_BLK_PWRDN,
451 FLD_PWRDN_TUNING_BIAS |
452 FLD_PWRDN_ENABLE_PLL);
453 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
459 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
461 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
463 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
466 cx231xx_info("Invalid AV mode input\n");
474 int cx231xx_afe_adjust_ref_count(struct cx231xx *dev, u32 video_input)
480 dev->video_input = video_input;
482 if (video_input == CX231XX_VMUX_TELEVISION) {
483 status = afe_read_byte(dev, ADC_INPUT_CH3, &input_mode);
484 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3,
487 status = afe_read_byte(dev, ADC_INPUT_CH1, &input_mode);
488 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH1,
492 input_mode = (ntf_mode & 0x3) | ((input_mode & 0x6) << 1);
494 switch (input_mode) {
496 dev->afe_ref_count = 0x23C;
499 dev->afe_ref_count = 0x24C;
502 dev->afe_ref_count = 0x258;
505 dev->afe_ref_count = 0x260;
511 status = cx231xx_afe_init_super_block(dev, dev->afe_ref_count);
516 /******************************************************************************
517 * V I D E O / A U D I O D E C O D E R C O N T R O L functions *
518 ******************************************************************************/
519 static int vid_blk_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
521 return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
525 static int vid_blk_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
530 status = cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
536 static int vid_blk_write_word(struct cx231xx *dev, u16 saddr, u32 data)
538 return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
542 static int vid_blk_read_word(struct cx231xx *dev, u16 saddr, u32 *data)
544 return cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
547 int cx231xx_check_fw(struct cx231xx *dev)
551 status = vid_blk_read_byte(dev, DL_CTL_ADDRESS_LOW, &temp);
559 int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input)
563 switch (INPUT(input)->type) {
564 case CX231XX_VMUX_COMPOSITE1:
565 case CX231XX_VMUX_SVIDEO:
566 if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
567 (dev->power_mode != POLARIS_AVMODE_ENXTERNAL_AV)) {
569 status = cx231xx_set_power_mode(dev,
570 POLARIS_AVMODE_ENXTERNAL_AV);
572 cx231xx_errdev("%s: set_power_mode : Failed to"
573 " set Power - errCode [%d]!\n",
578 status = cx231xx_set_decoder_video_input(dev,
582 case CX231XX_VMUX_TELEVISION:
583 case CX231XX_VMUX_CABLE:
584 if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
585 (dev->power_mode != POLARIS_AVMODE_ANALOGT_TV)) {
587 status = cx231xx_set_power_mode(dev,
588 POLARIS_AVMODE_ANALOGT_TV);
590 cx231xx_errdev("%s: set_power_mode:Failed"
591 " to set Power - errCode [%d]!\n",
596 if (dev->tuner_type == TUNER_NXP_TDA18271)
597 status = cx231xx_set_decoder_video_input(dev,
598 CX231XX_VMUX_TELEVISION,
601 status = cx231xx_set_decoder_video_input(dev,
602 CX231XX_VMUX_COMPOSITE1,
607 cx231xx_errdev("%s: set_power_mode : Unknown Input %d !\n",
608 __func__, INPUT(input)->type);
612 /* save the selection */
613 dev->video_input = input;
618 int cx231xx_set_decoder_video_input(struct cx231xx *dev,
619 u8 pin_type, u8 input)
624 if (pin_type != dev->video_input) {
625 status = cx231xx_afe_adjust_ref_count(dev, pin_type);
627 cx231xx_errdev("%s: adjust_ref_count :Failed to set"
628 "AFE input mux - errCode [%d]!\n",
634 /* call afe block to set video inputs */
635 status = cx231xx_afe_set_input_mux(dev, input);
637 cx231xx_errdev("%s: set_input_mux :Failed to set"
638 " AFE input mux - errCode [%d]!\n",
644 case CX231XX_VMUX_COMPOSITE1:
645 status = vid_blk_read_word(dev, AFE_CTRL, &value);
646 value |= (0 << 13) | (1 << 4);
649 /* set [24:23] [22:15] to 0 */
650 value &= (~(0x1ff8000));
651 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */
653 status = vid_blk_write_word(dev, AFE_CTRL, value);
655 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
657 status = vid_blk_write_word(dev, OUT_CTRL1, value);
659 /* Set output mode */
660 status = cx231xx_read_modify_write_i2c_dword(dev,
664 dev->board.output_mode);
666 /* Tell DIF object to go to baseband mode */
667 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
669 cx231xx_errdev("%s: cx231xx_dif set to By pass"
670 " mode- errCode [%d]!\n",
675 /* Read the DFE_CTRL1 register */
676 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
678 /* enable the VBI_GATE_EN */
679 value |= FLD_VBI_GATE_EN;
681 /* Enable the auto-VGA enable */
682 value |= FLD_VGA_AUTO_EN;
685 status = vid_blk_write_word(dev, DFE_CTRL1, value);
687 /* Disable auto config of registers */
688 status = cx231xx_read_modify_write_i2c_dword(dev,
690 MODE_CTRL, FLD_ACFG_DIS,
691 cx231xx_set_field(FLD_ACFG_DIS, 1));
693 /* Set CVBS input mode */
694 status = cx231xx_read_modify_write_i2c_dword(dev,
696 MODE_CTRL, FLD_INPUT_MODE,
697 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0));
699 case CX231XX_VMUX_SVIDEO:
700 /* Disable the use of DIF */
702 status = vid_blk_read_word(dev, AFE_CTRL, &value);
704 /* set [24:23] [22:15] to 0 */
705 value &= (~(0x1ff8000));
706 /* set FUNC_MODE[24:23] = 2
707 IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */
709 status = vid_blk_write_word(dev, AFE_CTRL, value);
711 /* Tell DIF object to go to baseband mode */
712 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
714 cx231xx_errdev("%s: cx231xx_dif set to By pass"
715 " mode- errCode [%d]!\n",
720 /* Read the DFE_CTRL1 register */
721 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
723 /* enable the VBI_GATE_EN */
724 value |= FLD_VBI_GATE_EN;
726 /* Enable the auto-VGA enable */
727 value |= FLD_VGA_AUTO_EN;
730 status = vid_blk_write_word(dev, DFE_CTRL1, value);
732 /* Disable auto config of registers */
733 status = cx231xx_read_modify_write_i2c_dword(dev,
735 MODE_CTRL, FLD_ACFG_DIS,
736 cx231xx_set_field(FLD_ACFG_DIS, 1));
738 /* Set YC input mode */
739 status = cx231xx_read_modify_write_i2c_dword(dev,
743 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_YC_1));
746 status = vid_blk_read_word(dev, AFE_CTRL, &value);
747 value |= FLD_CHROMA_IN_SEL; /* set the chroma in select */
749 /* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8)
750 This sets them to use video
751 rather than audio. Only one of the two will be in use. */
752 value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3);
754 status = vid_blk_write_word(dev, AFE_CTRL, value);
756 status = cx231xx_afe_set_mode(dev, AFE_MODE_BASEBAND);
758 case CX231XX_VMUX_TELEVISION:
759 case CX231XX_VMUX_CABLE:
761 switch (dev->model) {
762 case CX231XX_BOARD_CNXT_CARRAERA:
763 case CX231XX_BOARD_CNXT_RDE_250:
764 case CX231XX_BOARD_CNXT_SHELBY:
765 case CX231XX_BOARD_CNXT_RDU_250:
766 /* Disable the use of DIF */
768 status = vid_blk_read_word(dev, AFE_CTRL, &value);
769 value |= (0 << 13) | (1 << 4);
772 /* set [24:23] [22:15] to 0 */
773 value &= (~(0x1FF8000));
774 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */
776 status = vid_blk_write_word(dev, AFE_CTRL, value);
778 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
780 status = vid_blk_write_word(dev, OUT_CTRL1, value);
782 /* Set output mode */
783 status = cx231xx_read_modify_write_i2c_dword(dev,
785 OUT_CTRL1, FLD_OUT_MODE,
786 dev->board.output_mode);
788 /* Tell DIF object to go to baseband mode */
789 status = cx231xx_dif_set_standard(dev,
792 cx231xx_errdev("%s: cx231xx_dif set to By pass"
793 " mode- errCode [%d]!\n",
798 /* Read the DFE_CTRL1 register */
799 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
801 /* enable the VBI_GATE_EN */
802 value |= FLD_VBI_GATE_EN;
804 /* Enable the auto-VGA enable */
805 value |= FLD_VGA_AUTO_EN;
808 status = vid_blk_write_word(dev, DFE_CTRL1, value);
810 /* Disable auto config of registers */
811 status = cx231xx_read_modify_write_i2c_dword(dev,
813 MODE_CTRL, FLD_ACFG_DIS,
814 cx231xx_set_field(FLD_ACFG_DIS, 1));
816 /* Set CVBS input mode */
817 status = cx231xx_read_modify_write_i2c_dword(dev,
819 MODE_CTRL, FLD_INPUT_MODE,
820 cx231xx_set_field(FLD_INPUT_MODE,
824 /* Enable the DIF for the tuner */
826 /* Reinitialize the DIF */
827 status = cx231xx_dif_set_standard(dev, dev->norm);
829 cx231xx_errdev("%s: cx231xx_dif set to By pass"
830 " mode- errCode [%d]!\n",
835 /* Make sure bypass is cleared */
836 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &value);
838 /* Clear the bypass bit */
839 value &= ~FLD_DIF_DIF_BYPASS;
841 /* Enable the use of the DIF block */
842 status = vid_blk_write_word(dev, DIF_MISC_CTRL, value);
844 /* Read the DFE_CTRL1 register */
845 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
847 /* Disable the VBI_GATE_EN */
848 value &= ~FLD_VBI_GATE_EN;
850 /* Enable the auto-VGA enable, AGC, and
851 set the skip count to 2 */
852 value |= FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | 0x00200000;
855 status = vid_blk_write_word(dev, DFE_CTRL1, value);
857 /* Wait until AGC locks up */
860 /* Disable the auto-VGA enable AGC */
861 value &= ~(FLD_VGA_AUTO_EN);
864 status = vid_blk_write_word(dev, DFE_CTRL1, value);
866 /* Enable Polaris B0 AGC output */
867 status = vid_blk_read_word(dev, PIN_CTRL, &value);
868 value |= (FLD_OEF_AGC_RF) |
869 (FLD_OEF_AGC_IFVGA) |
871 status = vid_blk_write_word(dev, PIN_CTRL, value);
873 /* Set output mode */
874 status = cx231xx_read_modify_write_i2c_dword(dev,
876 OUT_CTRL1, FLD_OUT_MODE,
877 dev->board.output_mode);
879 /* Disable auto config of registers */
880 status = cx231xx_read_modify_write_i2c_dword(dev,
882 MODE_CTRL, FLD_ACFG_DIS,
883 cx231xx_set_field(FLD_ACFG_DIS, 1));
885 /* Set CVBS input mode */
886 status = cx231xx_read_modify_write_i2c_dword(dev,
888 MODE_CTRL, FLD_INPUT_MODE,
889 cx231xx_set_field(FLD_INPUT_MODE,
892 /* Set some bits in AFE_CTRL so that channel 2 or 3
893 * is ready to receive audio */
894 /* Clear clamp for channels 2 and 3 (bit 16-17) */
895 /* Clear droop comp (bit 19-20) */
896 /* Set VGA_SEL (for audio control) (bit 7-8) */
897 status = vid_blk_read_word(dev, AFE_CTRL, &value);
899 /*Set Func mode:01-DIF 10-baseband 11-YUV*/
900 value &= (~(FLD_FUNC_MODE));
903 value |= FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2;
905 status = vid_blk_write_word(dev, AFE_CTRL, value);
907 if (dev->tuner_type == TUNER_NXP_TDA18271) {
908 status = vid_blk_read_word(dev, PIN_CTRL,
910 status = vid_blk_write_word(dev, PIN_CTRL,
911 (value & 0xFFFFFFEF));
920 /* Set raw VBI mode */
921 status = cx231xx_read_modify_write_i2c_dword(dev,
923 OUT_CTRL1, FLD_VBIHACTRAW_EN,
924 cx231xx_set_field(FLD_VBIHACTRAW_EN, 1));
926 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
929 status = vid_blk_write_word(dev, OUT_CTRL1, value);
935 void cx231xx_enable656(struct cx231xx *dev)
939 /*enable TS1 data[0:7] as output to export 656*/
941 status = vid_blk_write_byte(dev, TS1_PIN_CTL0, 0xFF);
943 /*enable TS1 clock as output to export 656*/
945 status = vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp);
948 status = vid_blk_write_byte(dev, TS1_PIN_CTL1, temp);
951 EXPORT_SYMBOL_GPL(cx231xx_enable656);
953 void cx231xx_disable656(struct cx231xx *dev)
959 status = vid_blk_write_byte(dev, TS1_PIN_CTL0, 0x00);
961 status = vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp);
964 status = vid_blk_write_byte(dev, TS1_PIN_CTL1, temp);
966 EXPORT_SYMBOL_GPL(cx231xx_disable656);
969 * Handle any video-mode specific overrides that are different
970 * on a per video standards basis after touching the MODE_CTRL
971 * register which resets many values for autodetect
973 int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev)
977 cx231xx_info("do_mode_ctrl_overrides : 0x%x\n",
978 (unsigned int)dev->norm);
980 /* Change the DFE_CTRL3 bp_percent to fix flagging */
981 status = vid_blk_write_word(dev, DFE_CTRL3, 0xCD3F0280);
983 if (dev->norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M)) {
984 cx231xx_info("do_mode_ctrl_overrides NTSC\n");
986 /* Move the close caption lines out of active video,
987 adjust the active video start point */
988 status = cx231xx_read_modify_write_i2c_dword(dev,
991 FLD_VBLANK_CNT, 0x18);
992 status = cx231xx_read_modify_write_i2c_dword(dev,
997 status = cx231xx_read_modify_write_i2c_dword(dev,
1003 status = cx231xx_read_modify_write_i2c_dword(dev,
1004 VID_BLK_I2C_ADDRESS,
1008 (FLD_HBLANK_CNT, 0x79));
1010 } else if (dev->norm & V4L2_STD_SECAM) {
1011 cx231xx_info("do_mode_ctrl_overrides SECAM\n");
1012 status = cx231xx_read_modify_write_i2c_dword(dev,
1013 VID_BLK_I2C_ADDRESS,
1015 FLD_VBLANK_CNT, 0x24);
1016 status = cx231xx_read_modify_write_i2c_dword(dev,
1017 VID_BLK_I2C_ADDRESS,
1023 /* Adjust the active video horizontal start point */
1024 status = cx231xx_read_modify_write_i2c_dword(dev,
1025 VID_BLK_I2C_ADDRESS,
1029 (FLD_HBLANK_CNT, 0x85));
1031 cx231xx_info("do_mode_ctrl_overrides PAL\n");
1032 status = cx231xx_read_modify_write_i2c_dword(dev,
1033 VID_BLK_I2C_ADDRESS,
1035 FLD_VBLANK_CNT, 0x24);
1036 status = cx231xx_read_modify_write_i2c_dword(dev,
1037 VID_BLK_I2C_ADDRESS,
1043 /* Adjust the active video horizontal start point */
1044 status = cx231xx_read_modify_write_i2c_dword(dev,
1045 VID_BLK_I2C_ADDRESS,
1049 (FLD_HBLANK_CNT, 0x85));
1056 int cx231xx_unmute_audio(struct cx231xx *dev)
1058 return vid_blk_write_byte(dev, PATH1_VOL_CTL, 0x24);
1060 EXPORT_SYMBOL_GPL(cx231xx_unmute_audio);
1062 int stopAudioFirmware(struct cx231xx *dev)
1064 return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x03);
1067 int restartAudioFirmware(struct cx231xx *dev)
1069 return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x13);
1072 int cx231xx_set_audio_input(struct cx231xx *dev, u8 input)
1075 enum AUDIO_INPUT ainput = AUDIO_INPUT_LINE;
1077 switch (INPUT(input)->amux) {
1078 case CX231XX_AMUX_VIDEO:
1079 ainput = AUDIO_INPUT_TUNER_TV;
1081 case CX231XX_AMUX_LINE_IN:
1082 status = cx231xx_i2s_blk_set_audio_input(dev, input);
1083 ainput = AUDIO_INPUT_LINE;
1089 status = cx231xx_set_audio_decoder_input(dev, ainput);
1094 int cx231xx_set_audio_decoder_input(struct cx231xx *dev,
1095 enum AUDIO_INPUT audio_input)
1102 /* Put it in soft reset */
1103 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
1105 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
1107 switch (audio_input) {
1108 case AUDIO_INPUT_LINE:
1109 /* setup AUD_IO control from Merlin paralle output */
1110 value = cx231xx_set_field(FLD_AUD_CHAN1_SRC,
1111 AUD_CHAN_SRC_PARALLEL);
1112 status = vid_blk_write_word(dev, AUD_IO_CTRL, value);
1114 /* setup input to Merlin, SRC2 connect to AC97
1115 bypass upsample-by-2, slave mode, sony mode, left justify
1116 adr 091c, dat 01000000 */
1117 status = vid_blk_read_word(dev, AC97_CTL, &dwval);
1119 status = vid_blk_write_word(dev, AC97_CTL,
1120 (dwval | FLD_AC97_UP2X_BYPASS));
1122 /* select the parallel1 and SRC3 */
1123 status = vid_blk_write_word(dev, BAND_OUT_SEL,
1124 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x0) |
1125 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x0) |
1126 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x0));
1128 /* unmute all, AC97 in, independence mode
1129 adr 08d0, data 0x00063073 */
1130 status = vid_blk_write_word(dev, DL_CTL, 0x3000001);
1131 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063073);
1133 /* set AVC maximum threshold, adr 08d4, dat ffff0024 */
1134 status = vid_blk_read_word(dev, PATH1_VOL_CTL, &dwval);
1135 status = vid_blk_write_word(dev, PATH1_VOL_CTL,
1136 (dwval | FLD_PATH1_AVC_THRESHOLD));
1138 /* set SC maximum threshold, adr 08ec, dat ffffb3a3 */
1139 status = vid_blk_read_word(dev, PATH1_SC_CTL, &dwval);
1140 status = vid_blk_write_word(dev, PATH1_SC_CTL,
1141 (dwval | FLD_PATH1_SC_THRESHOLD));
1144 case AUDIO_INPUT_TUNER_TV:
1146 status = stopAudioFirmware(dev);
1147 /* Setup SRC sources and clocks */
1148 status = vid_blk_write_word(dev, BAND_OUT_SEL,
1149 cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00) |
1150 cx231xx_set_field(FLD_SRC6_CLK_SEL, 0x01) |
1151 cx231xx_set_field(FLD_SRC5_IN_SEL, 0x00) |
1152 cx231xx_set_field(FLD_SRC5_CLK_SEL, 0x02) |
1153 cx231xx_set_field(FLD_SRC4_IN_SEL, 0x02) |
1154 cx231xx_set_field(FLD_SRC4_CLK_SEL, 0x03) |
1155 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x00) |
1156 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x00) |
1157 cx231xx_set_field(FLD_BASEBAND_BYPASS_CTL, 0x00) |
1158 cx231xx_set_field(FLD_AC97_SRC_SEL, 0x03) |
1159 cx231xx_set_field(FLD_I2S_SRC_SEL, 0x00) |
1160 cx231xx_set_field(FLD_PARALLEL2_SRC_SEL, 0x02) |
1161 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x01));
1163 /* Setup the AUD_IO control */
1164 status = vid_blk_write_word(dev, AUD_IO_CTRL,
1165 cx231xx_set_field(FLD_I2S_PORT_DIR, 0x00) |
1166 cx231xx_set_field(FLD_I2S_OUT_SRC, 0x00) |
1167 cx231xx_set_field(FLD_AUD_CHAN3_SRC, 0x00) |
1168 cx231xx_set_field(FLD_AUD_CHAN2_SRC, 0x00) |
1169 cx231xx_set_field(FLD_AUD_CHAN1_SRC, 0x03));
1171 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F063870);
1173 /* setAudioStandard(_audio_standard); */
1174 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063870);
1176 status = restartAudioFirmware(dev);
1178 switch (dev->board.tuner_type) {
1180 /* SIF passthrough at 28.6363 MHz sample rate */
1181 status = cx231xx_read_modify_write_i2c_dword(dev,
1182 VID_BLK_I2C_ADDRESS,
1185 cx231xx_set_field(FLD_SIF_EN, 1));
1187 case TUNER_NXP_TDA18271:
1188 /* Normal mode: SIF passthrough at 14.32 MHz */
1189 status = cx231xx_read_modify_write_i2c_dword(dev,
1190 VID_BLK_I2C_ADDRESS,
1193 cx231xx_set_field(FLD_SIF_EN, 0));
1196 /* This is just a casual suggestion to people adding
1197 new boards in case they use a tuner type we don't
1198 currently know about */
1199 printk(KERN_INFO "Unknown tuner type configuring SIF");
1204 case AUDIO_INPUT_TUNER_FM:
1205 /* use SIF for FM radio
1207 setAudioStandard(_audio_standard);
1211 case AUDIO_INPUT_MUTE:
1212 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F011012);
1216 /* Take it out of soft reset */
1217 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
1219 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
1224 /******************************************************************************
1225 * C H I P Specific C O N T R O L functions *
1226 ******************************************************************************/
1227 int cx231xx_init_ctrl_pin_status(struct cx231xx *dev)
1232 status = vid_blk_read_word(dev, PIN_CTRL, &value);
1233 value |= (~dev->board.ctl_pin_status_mask);
1234 status = vid_blk_write_word(dev, PIN_CTRL, value);
1239 int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev,
1240 u8 analog_or_digital)
1244 /* first set the direction to output */
1245 status = cx231xx_set_gpio_direction(dev,
1247 agc_analog_digital_select_gpio, 1);
1249 /* 0 - demod ; 1 - Analog mode */
1250 status = cx231xx_set_gpio_value(dev,
1251 dev->board.agc_analog_digital_select_gpio,
1257 int cx231xx_enable_i2c_for_tuner(struct cx231xx *dev, u8 I2CIndex)
1259 u8 value[4] = { 0, 0, 0, 0 };
1262 cx231xx_info("Changing the i2c port for tuner to %d\n", I2CIndex);
1264 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER,
1265 PWR_CTL_EN, value, 4);
1269 if (I2CIndex == I2C_1) {
1270 if (value[0] & I2C_DEMOD_EN) {
1271 value[0] &= ~I2C_DEMOD_EN;
1272 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1273 PWR_CTL_EN, value, 4);
1276 if (!(value[0] & I2C_DEMOD_EN)) {
1277 value[0] |= I2C_DEMOD_EN;
1278 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1279 PWR_CTL_EN, value, 4);
1286 EXPORT_SYMBOL_GPL(cx231xx_enable_i2c_for_tuner);
1287 void update_HH_register_after_set_DIF(struct cx231xx *dev)
1293 vid_blk_write_word(dev, PIN_CTRL, 0xA0FFF82F);
1294 vid_blk_write_word(dev, DIF_MISC_CTRL, 0x0A203F11);
1295 vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0x1BEFBF06);
1297 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1298 vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390);
1299 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1303 void cx231xx_dump_HH_reg(struct cx231xx *dev)
1310 status = vid_blk_write_word(dev, 0x104, value);
1312 for (i = 0x100; i < 0x140; i++) {
1313 status = vid_blk_read_word(dev, i, &value);
1314 cx231xx_info("reg0x%x=0x%x\n", i, value);
1318 for (i = 0x300; i < 0x400; i++) {
1319 status = vid_blk_read_word(dev, i, &value);
1320 cx231xx_info("reg0x%x=0x%x\n", i, value);
1324 for (i = 0x400; i < 0x440; i++) {
1325 status = vid_blk_read_word(dev, i, &value);
1326 cx231xx_info("reg0x%x=0x%x\n", i, value);
1330 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1331 cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value);
1332 vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390);
1333 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1334 cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value);
1337 void cx231xx_dump_SC_reg(struct cx231xx *dev)
1339 u8 value[4] = { 0, 0, 0, 0 };
1341 cx231xx_info("cx231xx_dump_SC_reg %s!\n", __TIME__);
1343 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, BOARD_CFG_STAT,
1345 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", BOARD_CFG_STAT, value[0],
1346 value[1], value[2], value[3]);
1347 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS_MODE_REG,
1349 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS_MODE_REG, value[0],
1350 value[1], value[2], value[3]);
1351 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_CFG_REG,
1353 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_CFG_REG, value[0],
1354 value[1], value[2], value[3]);
1355 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_LENGTH_REG,
1357 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_LENGTH_REG, value[0],
1358 value[1], value[2], value[3]);
1360 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_CFG_REG,
1362 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_CFG_REG, value[0],
1363 value[1], value[2], value[3]);
1364 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_LENGTH_REG,
1366 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_LENGTH_REG, value[0],
1367 value[1], value[2], value[3]);
1368 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET,
1370 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", EP_MODE_SET, value[0],
1371 value[1], value[2], value[3]);
1372 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN1,
1374 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN1, value[0],
1375 value[1], value[2], value[3]);
1377 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN2,
1379 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN2, value[0],
1380 value[1], value[2], value[3]);
1381 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN3,
1383 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN3, value[0],
1384 value[1], value[2], value[3]);
1385 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK0,
1387 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK0, value[0],
1388 value[1], value[2], value[3]);
1389 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK1,
1391 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK1, value[0],
1392 value[1], value[2], value[3]);
1394 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK2,
1396 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK2, value[0],
1397 value[1], value[2], value[3]);
1398 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_GAIN,
1400 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_GAIN, value[0],
1401 value[1], value[2], value[3]);
1402 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_CAR_REG,
1404 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_CAR_REG, value[0],
1405 value[1], value[2], value[3]);
1406 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG1,
1408 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG1, value[0],
1409 value[1], value[2], value[3]);
1411 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG2,
1413 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG2, value[0],
1414 value[1], value[2], value[3]);
1415 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
1417 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", PWR_CTL_EN, value[0],
1418 value[1], value[2], value[3]);
1423 void cx231xx_Setup_AFE_for_LowIF(struct cx231xx *dev)
1431 status = afe_read_byte(dev, ADC_STATUS2_CH3, &value);
1432 value = (value & 0xFE)|0x01;
1433 status = afe_write_byte(dev, ADC_STATUS2_CH3, value);
1435 status = afe_read_byte(dev, ADC_STATUS2_CH3, &value);
1436 value = (value & 0xFE)|0x00;
1437 status = afe_write_byte(dev, ADC_STATUS2_CH3, value);
1441 config colibri to lo-if mode
1443 FIXME: ntf_mode = 2'b00 by default. But set 0x1 would reduce
1444 the diff IF input by half,
1446 for low-if agc defect
1449 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, &value);
1450 value = (value & 0xFC)|0x00;
1451 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, value);
1453 status = afe_read_byte(dev, ADC_INPUT_CH3, &value);
1454 value = (value & 0xF9)|0x02;
1455 status = afe_write_byte(dev, ADC_INPUT_CH3, value);
1457 status = afe_read_byte(dev, ADC_FB_FRCRST_CH3, &value);
1458 value = (value & 0xFB)|0x04;
1459 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, value);
1461 status = afe_read_byte(dev, ADC_DCSERVO_DEM_CH3, &value);
1462 value = (value & 0xFC)|0x03;
1463 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, value);
1465 status = afe_read_byte(dev, ADC_CTRL_DAC1_CH3, &value);
1466 value = (value & 0xFB)|0x04;
1467 status = afe_write_byte(dev, ADC_CTRL_DAC1_CH3, value);
1469 status = afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value);
1470 value = (value & 0xF8)|0x06;
1471 status = afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value);
1473 status = afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value);
1474 value = (value & 0x8F)|0x40;
1475 status = afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value);
1477 status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH3, &value);
1478 value = (value & 0xDF)|0x20;
1479 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, value);
1482 void cx231xx_set_Colibri_For_LowIF(struct cx231xx *dev, u32 if_freq,
1483 u8 spectral_invert, u32 mode)
1486 u32 colibri_carrier_offset = 0;
1488 u32 func_mode = 0x01; /* Device has an DIF if this function is called */
1490 u8 value[4] = { 0, 0, 0, 0 };
1492 cx231xx_info("Enter cx231xx_set_Colibri_For_LowIF()\n");
1493 value[0] = (u8) 0x6F;
1494 value[1] = (u8) 0x6F;
1495 value[2] = (u8) 0x6F;
1496 value[3] = (u8) 0x6F;
1497 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1498 PWR_CTL_EN, value, 4);
1501 /*Set colibri for low IF*/
1502 status = cx231xx_afe_set_mode(dev, AFE_MODE_LOW_IF);
1505 /* Set C2HH for low IF operation.*/
1506 standard = dev->norm;
1507 status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
1508 func_mode, standard);
1511 /* Get colibri offsets.*/
1512 colibri_carrier_offset = cx231xx_Get_Colibri_CarrierOffset(mode,
1515 cx231xx_info("colibri_carrier_offset=%d, standard=0x%x\n",
1516 colibri_carrier_offset, standard);
1518 /* Set the band Pass filter for DIF*/
1519 cx231xx_set_DIF_bandpass(dev, (if_freq+colibri_carrier_offset)
1520 , spectral_invert, mode);
1524 u32 cx231xx_Get_Colibri_CarrierOffset(u32 mode, u32 standerd)
1526 u32 colibri_carrier_offset = 0;
1529 if (mode == TUNER_MODE_FM_RADIO) {
1530 colibri_carrier_offset = 1100000;
1531 } else if (standerd & (V4L2_STD_NTSC | V4L2_STD_NTSC_M_JP)) {
1532 colibri_carrier_offset = 4832000; /*4.83MHz */
1533 } else if (standerd & (V4L2_STD_PAL_B | V4L2_STD_PAL_G)) {
1534 colibri_carrier_offset = 2700000; /*2.70MHz */
1535 } else if (standerd & (V4L2_STD_PAL_D | V4L2_STD_PAL_I
1536 | V4L2_STD_SECAM)) {
1537 colibri_carrier_offset = 2100000; /*2.10MHz */
1541 return colibri_carrier_offset;
1544 void cx231xx_set_DIF_bandpass(struct cx231xx *dev, u32 if_freq,
1545 u8 spectral_invert, u32 mode)
1548 unsigned long pll_freq_word;
1550 u32 dif_misc_ctrl_value = 0;
1551 u64 pll_freq_u64 = 0;
1555 cx231xx_info("if_freq=%d;spectral_invert=0x%x;mode=0x%x\n",
1556 if_freq, spectral_invert, mode);
1559 if (mode == TUNER_MODE_FM_RADIO) {
1560 pll_freq_word = 0x905A1CAC;
1561 status = vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word);
1563 } else /*KSPROPERTY_TUNER_MODE_TV*/{
1564 /* Calculate the PLL frequency word based on the adjusted if_freq*/
1565 pll_freq_word = if_freq;
1566 pll_freq_u64 = (u64)pll_freq_word << 28L;
1567 do_div(pll_freq_u64, 50000000);
1568 pll_freq_word = (u32)pll_freq_u64;
1569 /*pll_freq_word = 0x3463497;*/
1570 status = vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word);
1572 if (spectral_invert) {
1574 /* Enable Spectral Invert*/
1575 status = vid_blk_read_word(dev, DIF_MISC_CTRL,
1576 &dif_misc_ctrl_value);
1577 dif_misc_ctrl_value = dif_misc_ctrl_value | 0x00200000;
1578 status = vid_blk_write_word(dev, DIF_MISC_CTRL,
1579 dif_misc_ctrl_value);
1582 /* Disable Spectral Invert*/
1583 status = vid_blk_read_word(dev, DIF_MISC_CTRL,
1584 &dif_misc_ctrl_value);
1585 dif_misc_ctrl_value = dif_misc_ctrl_value & 0xFFDFFFFF;
1586 status = vid_blk_write_word(dev, DIF_MISC_CTRL,
1587 dif_misc_ctrl_value);
1590 if_freq = (if_freq/100000)*100000;
1592 if (if_freq < 3000000)
1595 if (if_freq > 16000000)
1599 cx231xx_info("Enter IF=%d\n",
1600 sizeof(Dif_set_array)/sizeof(struct dif_settings));
1601 for (i = 0; i < sizeof(Dif_set_array)/sizeof(struct dif_settings); i++) {
1602 if (Dif_set_array[i].if_freq == if_freq) {
1603 status = vid_blk_write_word(dev,
1604 Dif_set_array[i].register_address, Dif_set_array[i].value);
1610 /******************************************************************************
1611 * D I F - B L O C K C O N T R O L functions *
1612 ******************************************************************************/
1613 int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode,
1614 u32 function_mode, u32 standard)
1619 if (mode == V4L2_TUNER_RADIO) {
1621 /* lo if big signal */
1622 status = cx231xx_reg_mask_write(dev,
1623 VID_BLK_I2C_ADDRESS, 32,
1624 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1625 /* FUNC_MODE = DIF */
1626 status = cx231xx_reg_mask_write(dev,
1627 VID_BLK_I2C_ADDRESS, 32,
1628 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode);
1630 status = cx231xx_reg_mask_write(dev,
1631 VID_BLK_I2C_ADDRESS, 32,
1632 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF);
1634 status = cx231xx_reg_mask_write(dev,
1635 VID_BLK_I2C_ADDRESS, 32,
1636 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1637 } else if (standard != DIF_USE_BASEBAND) {
1638 if (standard & V4L2_STD_MN) {
1639 /* lo if big signal */
1640 status = cx231xx_reg_mask_write(dev,
1641 VID_BLK_I2C_ADDRESS, 32,
1642 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1643 /* FUNC_MODE = DIF */
1644 status = cx231xx_reg_mask_write(dev,
1645 VID_BLK_I2C_ADDRESS, 32,
1646 AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1649 status = cx231xx_reg_mask_write(dev,
1650 VID_BLK_I2C_ADDRESS, 32,
1651 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb);
1653 status = cx231xx_reg_mask_write(dev,
1654 VID_BLK_I2C_ADDRESS, 32,
1655 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1656 /* 0x124, AUD_CHAN1_SRC = 0x3 */
1657 status = cx231xx_reg_mask_write(dev,
1658 VID_BLK_I2C_ADDRESS, 32,
1659 AUD_IO_CTRL, 0, 31, 0x00000003);
1660 } else if ((standard == V4L2_STD_PAL_I) |
1661 (standard & V4L2_STD_PAL_D) |
1662 (standard & V4L2_STD_SECAM)) {
1664 /* lo if big signal */
1665 status = cx231xx_reg_mask_write(dev,
1666 VID_BLK_I2C_ADDRESS, 32,
1667 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1668 /* FUNC_MODE = DIF */
1669 status = cx231xx_reg_mask_write(dev,
1670 VID_BLK_I2C_ADDRESS, 32,
1671 AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1674 status = cx231xx_reg_mask_write(dev,
1675 VID_BLK_I2C_ADDRESS, 32,
1676 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF);
1678 status = cx231xx_reg_mask_write(dev,
1679 VID_BLK_I2C_ADDRESS, 32,
1680 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1682 /* default PAL BG */
1684 /* lo if big signal */
1685 status = cx231xx_reg_mask_write(dev,
1686 VID_BLK_I2C_ADDRESS, 32,
1687 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1688 /* FUNC_MODE = DIF */
1689 status = cx231xx_reg_mask_write(dev,
1690 VID_BLK_I2C_ADDRESS, 32,
1691 AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1694 status = cx231xx_reg_mask_write(dev,
1695 VID_BLK_I2C_ADDRESS, 32,
1696 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE);
1698 status = cx231xx_reg_mask_write(dev,
1699 VID_BLK_I2C_ADDRESS, 32,
1700 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1707 int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
1710 u32 dif_misc_ctrl_value = 0;
1713 cx231xx_info("%s: setStandard to %x\n", __func__, standard);
1715 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &dif_misc_ctrl_value);
1716 if (standard != DIF_USE_BASEBAND)
1717 dev->norm = standard;
1719 switch (dev->model) {
1720 case CX231XX_BOARD_CNXT_CARRAERA:
1721 case CX231XX_BOARD_CNXT_RDE_250:
1722 case CX231XX_BOARD_CNXT_SHELBY:
1723 case CX231XX_BOARD_CNXT_RDU_250:
1724 case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
1725 case CX231XX_BOARD_HAUPPAUGE_EXETER:
1728 case CX231XX_BOARD_CNXT_RDE_253S:
1729 case CX231XX_BOARD_CNXT_RDU_253S:
1736 status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
1737 func_mode, standard);
1739 if (standard == DIF_USE_BASEBAND) { /* base band */
1740 /* There is a different SRC_PHASE_INC value
1741 for baseband vs. DIF */
1742 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0xDF7DF83);
1743 status = vid_blk_read_word(dev, DIF_MISC_CTRL,
1744 &dif_misc_ctrl_value);
1745 dif_misc_ctrl_value |= FLD_DIF_DIF_BYPASS;
1746 status = vid_blk_write_word(dev, DIF_MISC_CTRL,
1747 dif_misc_ctrl_value);
1748 } else if (standard & V4L2_STD_PAL_D) {
1749 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1750 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1751 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1752 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1753 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1754 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1755 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1756 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1757 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1758 DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1759 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1760 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1761 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1762 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1763 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1764 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1765 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1766 DIF_AGC_IF_INT_CURRENT, 0, 31,
1768 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1769 DIF_AGC_RF_CURRENT, 0, 31,
1771 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1772 DIF_VIDEO_AGC_CTRL, 0, 31,
1774 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1775 DIF_VID_AUD_OVERRIDE, 0, 31,
1777 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1778 DIF_AV_SEP_CTRL, 0, 31, 0x3F3934EA);
1779 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1780 DIF_COMP_FLT_CTRL, 0, 31,
1782 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1783 DIF_SRC_PHASE_INC, 0, 31,
1785 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1786 DIF_SRC_GAIN_CONTROL, 0, 31,
1788 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1789 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1790 /* Save the Spec Inversion value */
1791 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1792 dif_misc_ctrl_value |= 0x3a023F11;
1793 } else if (standard & V4L2_STD_PAL_I) {
1794 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1795 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1796 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1797 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1798 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1799 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1800 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1801 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1802 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1803 DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1804 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1805 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1806 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1807 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1808 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1809 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1810 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1811 DIF_AGC_IF_INT_CURRENT, 0, 31,
1813 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1814 DIF_AGC_RF_CURRENT, 0, 31,
1816 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1817 DIF_VIDEO_AGC_CTRL, 0, 31,
1819 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1820 DIF_VID_AUD_OVERRIDE, 0, 31,
1822 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1823 DIF_AV_SEP_CTRL, 0, 31, 0x5F39A934);
1824 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1825 DIF_COMP_FLT_CTRL, 0, 31,
1827 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1828 DIF_SRC_PHASE_INC, 0, 31,
1830 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1831 DIF_SRC_GAIN_CONTROL, 0, 31,
1833 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1834 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1835 /* Save the Spec Inversion value */
1836 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1837 dif_misc_ctrl_value |= 0x3a033F11;
1838 } else if (standard & V4L2_STD_PAL_M) {
1839 /* improved Low Frequency Phase Noise */
1840 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
1841 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
1842 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
1843 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1844 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
1845 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1847 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1849 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1851 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1853 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x012c405d);
1854 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1856 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1858 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1860 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
1862 /* Save the Spec Inversion value */
1863 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1864 dif_misc_ctrl_value |= 0x3A0A3F10;
1865 } else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) {
1866 /* improved Low Frequency Phase Noise */
1867 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
1868 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
1869 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
1870 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1871 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
1872 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1874 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1876 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1878 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1880 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL,
1882 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1884 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1886 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1888 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
1890 /* Save the Spec Inversion value */
1891 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1892 dif_misc_ctrl_value = 0x3A093F10;
1893 } else if (standard &
1894 (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G |
1895 V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) {
1897 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1898 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1899 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1900 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1901 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1902 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1903 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1904 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1905 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1906 DIF_AGC_IF_REF, 0, 31, 0x888C0380);
1907 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1908 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
1909 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1910 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
1911 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1912 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
1913 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1914 DIF_AGC_IF_INT_CURRENT, 0, 31,
1916 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1917 DIF_AGC_RF_CURRENT, 0, 31,
1919 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1920 DIF_VID_AUD_OVERRIDE, 0, 31,
1922 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1923 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
1924 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1925 DIF_COMP_FLT_CTRL, 0, 31,
1927 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1928 DIF_SRC_PHASE_INC, 0, 31,
1930 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1931 DIF_SRC_GAIN_CONTROL, 0, 31,
1933 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1934 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1935 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1936 DIF_VIDEO_AGC_CTRL, 0, 31,
1939 /* Save the Spec Inversion value */
1940 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1941 dif_misc_ctrl_value |= 0x3a023F11;
1942 } else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) {
1943 /* Is it SECAM_L1? */
1944 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1945 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1946 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1947 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1948 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1949 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1950 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1951 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1952 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1953 DIF_AGC_IF_REF, 0, 31, 0x888C0380);
1954 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1955 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
1956 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1957 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
1958 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1959 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
1960 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1961 DIF_AGC_IF_INT_CURRENT, 0, 31,
1963 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1964 DIF_AGC_RF_CURRENT, 0, 31,
1966 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1967 DIF_VID_AUD_OVERRIDE, 0, 31,
1969 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1970 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
1971 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1972 DIF_COMP_FLT_CTRL, 0, 31,
1974 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1975 DIF_SRC_PHASE_INC, 0, 31,
1977 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1978 DIF_SRC_GAIN_CONTROL, 0, 31,
1980 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1981 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1982 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1983 DIF_VIDEO_AGC_CTRL, 0, 31,
1986 /* Save the Spec Inversion value */
1987 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1988 dif_misc_ctrl_value |= 0x3a023F11;
1990 } else if (standard & V4L2_STD_NTSC_M) {
1991 /* V4L2_STD_NTSC_M (75 IRE Setup) Or
1992 V4L2_STD_NTSC_M_JP (Japan, 0 IRE Setup) */
1994 /* For NTSC the centre frequency of video coming out of
1995 sidewinder is around 7.1MHz or 3.6MHz depending on the
1996 spectral inversion. so for a non spectrally inverted channel
1997 the pll freq word is 0x03420c49
2000 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0x6503BC0C);
2001 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xBD038C85);
2002 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1DB4640A);
2003 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
2004 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C0380);
2005 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
2007 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
2009 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
2011 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
2013 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x01296e1f);
2015 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
2017 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
2019 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
2022 status = vid_blk_write_word(dev, DIF_AGC_CTRL_IF, 0xC2262600);
2023 status = vid_blk_write_word(dev, DIF_AGC_CTRL_INT,
2025 status = vid_blk_write_word(dev, DIF_AGC_CTRL_RF, 0xC2262600);
2027 /* Save the Spec Inversion value */
2028 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
2029 dif_misc_ctrl_value |= 0x3a003F10;
2031 /* default PAL BG */
2032 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2033 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
2034 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2035 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
2036 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2037 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
2038 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2039 DIF_PLL_CTRL3, 0, 31, 0x00008800);
2040 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2041 DIF_AGC_IF_REF, 0, 31, 0x444C1380);
2042 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2043 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
2044 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2045 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
2046 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2047 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
2048 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2049 DIF_AGC_IF_INT_CURRENT, 0, 31,
2051 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2052 DIF_AGC_RF_CURRENT, 0, 31,
2054 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2055 DIF_VIDEO_AGC_CTRL, 0, 31,
2057 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2058 DIF_VID_AUD_OVERRIDE, 0, 31,
2060 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2061 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC);
2062 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2063 DIF_COMP_FLT_CTRL, 0, 31,
2065 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2066 DIF_SRC_PHASE_INC, 0, 31,
2068 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2069 DIF_SRC_GAIN_CONTROL, 0, 31,
2071 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2072 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
2073 /* Save the Spec Inversion value */
2074 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
2075 dif_misc_ctrl_value |= 0x3a013F11;
2078 /* The AGC values should be the same for all standards,
2079 AUD_SRC_SEL[19] should always be disabled */
2080 dif_misc_ctrl_value &= ~FLD_DIF_AUD_SRC_SEL;
2082 /* It is still possible to get Set Standard calls even when we
2084 This is done to override the value for FM. */
2085 if (dev->active_mode == V4L2_TUNER_RADIO)
2086 dif_misc_ctrl_value = 0x7a080000;
2088 /* Write the calculated value for misc ontrol register */
2089 status = vid_blk_write_word(dev, DIF_MISC_CTRL, dif_misc_ctrl_value);
2094 int cx231xx_tuner_pre_channel_change(struct cx231xx *dev)
2099 /* Set the RF and IF k_agc values to 3 */
2100 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
2101 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
2102 dwval |= 0x33000000;
2104 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
2109 int cx231xx_tuner_post_channel_change(struct cx231xx *dev)
2113 cx231xx_info("cx231xx_tuner_post_channel_change dev->tuner_type =0%d\n",
2115 /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for
2116 * SECAM L/B/D standards */
2117 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
2118 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
2120 if (dev->norm & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_B |
2121 V4L2_STD_SECAM_D)) {
2122 if (dev->tuner_type == TUNER_NXP_TDA18271) {
2123 dwval &= ~FLD_DIF_IF_REF;
2124 dwval |= 0x88000300;
2126 dwval |= 0x88000000;
2128 if (dev->tuner_type == TUNER_NXP_TDA18271) {
2129 dwval &= ~FLD_DIF_IF_REF;
2130 dwval |= 0xCC000300;
2132 dwval |= 0x44000000;
2135 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
2140 /******************************************************************************
2141 * I 2 S - B L O C K C O N T R O L functions *
2142 ******************************************************************************/
2143 int cx231xx_i2s_blk_initialize(struct cx231xx *dev)
2148 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2149 CH_PWR_CTRL1, 1, &value, 1);
2150 /* enables clock to delta-sigma and decimation filter */
2152 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2153 CH_PWR_CTRL1, 1, value, 1);
2154 /* power up all channel */
2155 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2156 CH_PWR_CTRL2, 1, 0x00, 1);
2161 int cx231xx_i2s_blk_update_power_control(struct cx231xx *dev,
2162 enum AV_MODE avmode)
2167 if (avmode != POLARIS_AVMODE_ENXTERNAL_AV) {
2168 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2169 CH_PWR_CTRL2, 1, &value, 1);
2171 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2172 CH_PWR_CTRL2, 1, value, 1);
2174 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2175 CH_PWR_CTRL2, 1, 0x00, 1);
2181 /* set i2s_blk for audio input types */
2182 int cx231xx_i2s_blk_set_audio_input(struct cx231xx *dev, u8 audio_input)
2186 switch (audio_input) {
2187 case CX231XX_AMUX_LINE_IN:
2188 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2189 CH_PWR_CTRL2, 1, 0x00, 1);
2190 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2191 CH_PWR_CTRL1, 1, 0x80, 1);
2193 case CX231XX_AMUX_VIDEO:
2198 dev->ctl_ainput = audio_input;
2203 /******************************************************************************
2204 * P O W E R C O N T R O L functions *
2205 ******************************************************************************/
2206 int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode)
2208 u8 value[4] = { 0, 0, 0, 0 };
2212 if (dev->power_mode != mode)
2213 dev->power_mode = mode;
2215 cx231xx_info(" setPowerMode::mode = %d, No Change req.\n",
2220 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
2225 tmp = *((u32 *) value);
2228 case POLARIS_AVMODE_ENXTERNAL_AV:
2230 tmp &= (~PWR_MODE_MASK);
2233 value[0] = (u8) tmp;
2234 value[1] = (u8) (tmp >> 8);
2235 value[2] = (u8) (tmp >> 16);
2236 value[3] = (u8) (tmp >> 24);
2237 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2238 PWR_CTL_EN, value, 4);
2239 msleep(PWR_SLEEP_INTERVAL);
2242 value[0] = (u8) tmp;
2243 value[1] = (u8) (tmp >> 8);
2244 value[2] = (u8) (tmp >> 16);
2245 value[3] = (u8) (tmp >> 24);
2247 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
2249 msleep(PWR_SLEEP_INTERVAL);
2251 tmp |= POLARIS_AVMODE_ENXTERNAL_AV;
2252 value[0] = (u8) tmp;
2253 value[1] = (u8) (tmp >> 8);
2254 value[2] = (u8) (tmp >> 16);
2255 value[3] = (u8) (tmp >> 24);
2256 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2257 PWR_CTL_EN, value, 4);
2259 /* reset state of xceive tuner */
2260 dev->xc_fw_load_done = 0;
2263 case POLARIS_AVMODE_ANALOGT_TV:
2265 tmp |= PWR_DEMOD_EN;
2266 tmp |= (I2C_DEMOD_EN);
2267 value[0] = (u8) tmp;
2268 value[1] = (u8) (tmp >> 8);
2269 value[2] = (u8) (tmp >> 16);
2270 value[3] = (u8) (tmp >> 24);
2271 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2272 PWR_CTL_EN, value, 4);
2273 msleep(PWR_SLEEP_INTERVAL);
2275 if (!(tmp & PWR_TUNER_EN)) {
2276 tmp |= (PWR_TUNER_EN);
2277 value[0] = (u8) tmp;
2278 value[1] = (u8) (tmp >> 8);
2279 value[2] = (u8) (tmp >> 16);
2280 value[3] = (u8) (tmp >> 24);
2281 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2282 PWR_CTL_EN, value, 4);
2283 msleep(PWR_SLEEP_INTERVAL);
2286 if (!(tmp & PWR_AV_EN)) {
2288 value[0] = (u8) tmp;
2289 value[1] = (u8) (tmp >> 8);
2290 value[2] = (u8) (tmp >> 16);
2291 value[3] = (u8) (tmp >> 24);
2292 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2293 PWR_CTL_EN, value, 4);
2294 msleep(PWR_SLEEP_INTERVAL);
2296 if (!(tmp & PWR_ISO_EN)) {
2298 value[0] = (u8) tmp;
2299 value[1] = (u8) (tmp >> 8);
2300 value[2] = (u8) (tmp >> 16);
2301 value[3] = (u8) (tmp >> 24);
2302 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2303 PWR_CTL_EN, value, 4);
2304 msleep(PWR_SLEEP_INTERVAL);
2307 if (!(tmp & POLARIS_AVMODE_ANALOGT_TV)) {
2308 tmp |= POLARIS_AVMODE_ANALOGT_TV;
2309 value[0] = (u8) tmp;
2310 value[1] = (u8) (tmp >> 8);
2311 value[2] = (u8) (tmp >> 16);
2312 value[3] = (u8) (tmp >> 24);
2313 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2314 PWR_CTL_EN, value, 4);
2315 msleep(PWR_SLEEP_INTERVAL);
2318 if ((dev->model == CX231XX_BOARD_CNXT_CARRAERA) ||
2319 (dev->model == CX231XX_BOARD_CNXT_RDE_250) ||
2320 (dev->model == CX231XX_BOARD_CNXT_SHELBY) ||
2321 (dev->model == CX231XX_BOARD_CNXT_RDU_250)) {
2322 /* tuner path to channel 1 from port 3 */
2323 cx231xx_enable_i2c_for_tuner(dev, I2C_3);
2325 /* reset the Tuner */
2326 cx231xx_gpio_set(dev, dev->board.tuner_gpio);
2328 if (dev->cx231xx_reset_analog_tuner)
2329 dev->cx231xx_reset_analog_tuner(dev);
2330 } else if ((dev->model == CX231XX_BOARD_CNXT_RDE_253S) ||
2331 (dev->model == CX231XX_BOARD_CNXT_VIDEO_GRABBER) ||
2332 (dev->model == CX231XX_BOARD_CNXT_RDU_253S) ||
2333 (dev->model == CX231XX_BOARD_HAUPPAUGE_EXETER)) {
2334 /* tuner path to channel 1 from port 3 */
2335 cx231xx_enable_i2c_for_tuner(dev, I2C_3);
2336 if (dev->cx231xx_reset_analog_tuner)
2337 dev->cx231xx_reset_analog_tuner(dev);
2342 case POLARIS_AVMODE_DIGITAL:
2343 if (!(tmp & PWR_TUNER_EN)) {
2344 tmp |= (PWR_TUNER_EN);
2345 value[0] = (u8) tmp;
2346 value[1] = (u8) (tmp >> 8);
2347 value[2] = (u8) (tmp >> 16);
2348 value[3] = (u8) (tmp >> 24);
2349 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2350 PWR_CTL_EN, value, 4);
2351 msleep(PWR_SLEEP_INTERVAL);
2353 if (!(tmp & PWR_AV_EN)) {
2355 value[0] = (u8) tmp;
2356 value[1] = (u8) (tmp >> 8);
2357 value[2] = (u8) (tmp >> 16);
2358 value[3] = (u8) (tmp >> 24);
2359 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2360 PWR_CTL_EN, value, 4);
2361 msleep(PWR_SLEEP_INTERVAL);
2363 if (!(tmp & PWR_ISO_EN)) {
2365 value[0] = (u8) tmp;
2366 value[1] = (u8) (tmp >> 8);
2367 value[2] = (u8) (tmp >> 16);
2368 value[3] = (u8) (tmp >> 24);
2369 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2370 PWR_CTL_EN, value, 4);
2371 msleep(PWR_SLEEP_INTERVAL);
2374 tmp &= (~PWR_AV_MODE);
2375 tmp |= POLARIS_AVMODE_DIGITAL | I2C_DEMOD_EN;
2376 value[0] = (u8) tmp;
2377 value[1] = (u8) (tmp >> 8);
2378 value[2] = (u8) (tmp >> 16);
2379 value[3] = (u8) (tmp >> 24);
2380 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2381 PWR_CTL_EN, value, 4);
2382 msleep(PWR_SLEEP_INTERVAL);
2384 if (!(tmp & PWR_DEMOD_EN)) {
2385 tmp |= PWR_DEMOD_EN;
2386 value[0] = (u8) tmp;
2387 value[1] = (u8) (tmp >> 8);
2388 value[2] = (u8) (tmp >> 16);
2389 value[3] = (u8) (tmp >> 24);
2390 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2391 PWR_CTL_EN, value, 4);
2392 msleep(PWR_SLEEP_INTERVAL);
2395 if ((dev->model == CX231XX_BOARD_CNXT_CARRAERA) ||
2396 (dev->model == CX231XX_BOARD_CNXT_RDE_250) ||
2397 (dev->model == CX231XX_BOARD_CNXT_SHELBY) ||
2398 (dev->model == CX231XX_BOARD_CNXT_RDU_250)) {
2399 /* tuner path to channel 1 from port 3 */
2400 cx231xx_enable_i2c_for_tuner(dev, I2C_3);
2402 /* reset the Tuner */
2403 cx231xx_gpio_set(dev, dev->board.tuner_gpio);
2405 if (dev->cx231xx_reset_analog_tuner)
2406 dev->cx231xx_reset_analog_tuner(dev);
2407 } else if ((dev->model == CX231XX_BOARD_CNXT_RDE_253S) ||
2408 (dev->model == CX231XX_BOARD_CNXT_VIDEO_GRABBER) ||
2409 (dev->model == CX231XX_BOARD_CNXT_RDU_253S)) {
2410 /* tuner path to channel 1 from port 3 */
2411 cx231xx_enable_i2c_for_tuner(dev, I2C_3);
2412 if (dev->cx231xx_reset_analog_tuner)
2413 dev->cx231xx_reset_analog_tuner(dev);
2414 } else if (dev->model == CX231XX_BOARD_HAUPPAUGE_EXETER) {
2415 /* tuner path to channel 1 from port 1 ?? */
2416 cx231xx_enable_i2c_for_tuner(dev, I2C_1);
2418 if (dev->cx231xx_reset_analog_tuner)
2419 dev->cx231xx_reset_analog_tuner(dev);
2428 msleep(PWR_SLEEP_INTERVAL);
2430 /* For power saving, only enable Pwr_resetout_n
2431 when digital TV is selected. */
2432 if (mode == POLARIS_AVMODE_DIGITAL) {
2433 tmp |= PWR_RESETOUT_EN;
2434 value[0] = (u8) tmp;
2435 value[1] = (u8) (tmp >> 8);
2436 value[2] = (u8) (tmp >> 16);
2437 value[3] = (u8) (tmp >> 24);
2438 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2439 PWR_CTL_EN, value, 4);
2440 msleep(PWR_SLEEP_INTERVAL);
2443 /* update power control for afe */
2444 status = cx231xx_afe_update_power_control(dev, mode);
2446 /* update power control for i2s_blk */
2447 status = cx231xx_i2s_blk_update_power_control(dev, mode);
2449 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
2455 int cx231xx_power_suspend(struct cx231xx *dev)
2457 u8 value[4] = { 0, 0, 0, 0 };
2461 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
2466 tmp = *((u32 *) value);
2467 tmp &= (~PWR_MODE_MASK);
2469 value[0] = (u8) tmp;
2470 value[1] = (u8) (tmp >> 8);
2471 value[2] = (u8) (tmp >> 16);
2472 value[3] = (u8) (tmp >> 24);
2473 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
2479 /******************************************************************************
2480 * S T R E A M C O N T R O L functions *
2481 ******************************************************************************/
2482 int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask)
2484 u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
2488 cx231xx_info("cx231xx_start_stream():: ep_mask = %x\n", ep_mask);
2489 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET,
2494 tmp = *((u32 *) value);
2496 value[0] = (u8) tmp;
2497 value[1] = (u8) (tmp >> 8);
2498 value[2] = (u8) (tmp >> 16);
2499 value[3] = (u8) (tmp >> 24);
2501 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
2507 int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask)
2509 u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
2513 cx231xx_info("cx231xx_stop_stream():: ep_mask = %x\n", ep_mask);
2515 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, value, 4);
2519 tmp = *((u32 *) value);
2521 value[0] = (u8) tmp;
2522 value[1] = (u8) (tmp >> 8);
2523 value[2] = (u8) (tmp >> 16);
2524 value[3] = (u8) (tmp >> 24);
2526 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
2532 int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type)
2536 u8 val[4] = { 0, 0, 0, 0 };
2538 if (dev->udev->speed == USB_SPEED_HIGH) {
2539 switch (media_type) {
2540 case 81: /* audio */
2541 cx231xx_info("%s: Audio enter HANC\n", __func__);
2543 cx231xx_mode_register(dev, TS_MODE_REG, 0x9300);
2547 cx231xx_info("%s: set vanc registers\n", __func__);
2548 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x300);
2551 case 3: /* sliced cc */
2552 cx231xx_info("%s: set hanc registers\n", __func__);
2554 cx231xx_mode_register(dev, TS_MODE_REG, 0x1300);
2558 cx231xx_info("%s: set video registers\n", __func__);
2559 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
2563 cx231xx_info("%s: set ts1 registers", __func__);
2565 if (dev->model == CX231XX_BOARD_CNXT_VIDEO_GRABBER) {
2566 cx231xx_info(" MPEG\n");
2567 value &= 0xFFFFFFFC;
2570 status = cx231xx_mode_register(dev, TS_MODE_REG, value);
2576 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2577 TS1_CFG_REG, val, 4);
2583 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2584 TS1_LENGTH_REG, val, 4);
2587 cx231xx_info(" BDA\n");
2588 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
2589 status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x010);
2593 case 6: /* ts1 parallel mode */
2594 cx231xx_info("%s: set ts1 parrallel mode registers\n",
2596 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
2597 status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400);
2601 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
2607 int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type)
2611 struct pcb_config *pcb_config;
2613 /* get EP for media type */
2614 pcb_config = (struct pcb_config *)&dev->current_pcb_config;
2616 if (pcb_config->config_num == 1) {
2617 switch (media_type) {
2619 ep_mask = ENABLE_EP4; /* ep4 [00:1000] */
2622 ep_mask = ENABLE_EP3; /* ep3 [00:0100] */
2625 ep_mask = ENABLE_EP5; /* ep5 [01:0000] */
2627 case 3: /* Sliced_cc */
2628 ep_mask = ENABLE_EP6; /* ep6 [10:0000] */
2631 case 6: /* ts1 parallel mode */
2632 ep_mask = ENABLE_EP1; /* ep1 [00:0001] */
2635 ep_mask = ENABLE_EP2; /* ep2 [00:0010] */
2639 } else if (pcb_config->config_num > 1) {
2640 switch (media_type) {
2642 ep_mask = ENABLE_EP4; /* ep4 [00:1000] */
2645 ep_mask = ENABLE_EP3; /* ep3 [00:0100] */
2648 ep_mask = ENABLE_EP5; /* ep5 [01:0000] */
2650 case 3: /* Sliced_cc */
2651 ep_mask = ENABLE_EP6; /* ep6 [10:0000] */
2654 case 6: /* ts1 parallel mode */
2655 ep_mask = ENABLE_EP1; /* ep1 [00:0001] */
2658 ep_mask = ENABLE_EP2; /* ep2 [00:0010] */
2665 rc = cx231xx_initialize_stream_xfer(dev, media_type);
2670 /* enable video capture */
2672 rc = cx231xx_start_stream(dev, ep_mask);
2674 /* disable video capture */
2676 rc = cx231xx_stop_stream(dev, ep_mask);
2679 if (dev->mode == CX231XX_ANALOG_MODE)
2680 ;/* do any in Analog mode */
2682 ;/* do any in digital mode */
2686 EXPORT_SYMBOL_GPL(cx231xx_capture_start);
2688 /*****************************************************************************
2689 * G P I O B I T control functions *
2690 ******************************************************************************/
2691 int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 *gpio_val)
2695 status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 0);
2700 int cx231xx_get_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 *gpio_val)
2704 status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 1);
2710 * cx231xx_set_gpio_direction
2711 * Sets the direction of the GPIO pin to input or output
2714 * pin_number : The GPIO Pin number to program the direction for
2716 * pin_value : The Direction of the GPIO Pin under reference.
2717 * 0 = Input direction
2718 * 1 = Output direction
2720 int cx231xx_set_gpio_direction(struct cx231xx *dev,
2721 int pin_number, int pin_value)
2726 /* Check for valid pin_number - if 32 , bail out */
2727 if (pin_number >= 32)
2732 value = dev->gpio_dir & (~(1 << pin_number)); /* clear */
2734 value = dev->gpio_dir | (1 << pin_number);
2736 status = cx231xx_set_gpio_bit(dev, value, (u8 *) &dev->gpio_val);
2738 /* cache the value for future */
2739 dev->gpio_dir = value;
2745 * cx231xx_set_gpio_value
2746 * Sets the value of the GPIO pin to Logic high or low. The Pin under
2747 * reference should ALREADY BE SET IN OUTPUT MODE !!!!!!!!!
2750 * pin_number : The GPIO Pin number to program the direction for
2751 * pin_value : The value of the GPIO Pin under reference.
2755 int cx231xx_set_gpio_value(struct cx231xx *dev, int pin_number, int pin_value)
2760 /* Check for valid pin_number - if 0xFF , bail out */
2761 if (pin_number >= 32)
2764 /* first do a sanity check - if the Pin is not output, make it output */
2765 if ((dev->gpio_dir & (1 << pin_number)) == 0x00) {
2766 /* It was in input mode */
2767 value = dev->gpio_dir | (1 << pin_number);
2768 dev->gpio_dir = value;
2769 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2770 (u8 *) &dev->gpio_val);
2775 value = dev->gpio_val & (~(1 << pin_number));
2777 value = dev->gpio_val | (1 << pin_number);
2779 /* store the value */
2780 dev->gpio_val = value;
2782 /* toggle bit0 of GP_IO */
2783 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2788 /*****************************************************************************
2789 * G P I O I2C related functions *
2790 ******************************************************************************/
2791 int cx231xx_gpio_i2c_start(struct cx231xx *dev)
2795 /* set SCL to output 1 ; set SDA to output 1 */
2796 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2797 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2798 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2799 dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
2801 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2805 /* set SCL to output 1; set SDA to output 0 */
2806 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2807 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2809 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2813 /* set SCL to output 0; set SDA to output 0 */
2814 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2815 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2817 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2824 int cx231xx_gpio_i2c_end(struct cx231xx *dev)
2828 /* set SCL to output 0; set SDA to output 0 */
2829 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2830 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2832 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2833 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2835 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2839 /* set SCL to output 1; set SDA to output 0 */
2840 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2841 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2843 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2847 /* set SCL to input ,release SCL cable control
2848 set SDA to input ,release SDA cable control */
2849 dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
2850 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2853 cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2860 int cx231xx_gpio_i2c_write_byte(struct cx231xx *dev, u8 data)
2865 /* set SCL to output ; set SDA to output */
2866 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2867 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2869 for (i = 0; i < 8; i++) {
2870 if (((data << i) & 0x80) == 0) {
2871 /* set SCL to output 0; set SDA to output 0 */
2872 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2873 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2874 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2875 (u8 *)&dev->gpio_val);
2877 /* set SCL to output 1; set SDA to output 0 */
2878 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2879 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2880 (u8 *)&dev->gpio_val);
2882 /* set SCL to output 0; set SDA to output 0 */
2883 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2884 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2885 (u8 *)&dev->gpio_val);
2887 /* set SCL to output 0; set SDA to output 1 */
2888 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2889 dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
2890 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2891 (u8 *)&dev->gpio_val);
2893 /* set SCL to output 1; set SDA to output 1 */
2894 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2895 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2896 (u8 *)&dev->gpio_val);
2898 /* set SCL to output 0; set SDA to output 1 */
2899 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2900 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2901 (u8 *)&dev->gpio_val);
2907 int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 *buf)
2911 u32 gpio_logic_value = 0;
2915 for (i = 0; i < 8; i++) { /* send write I2c addr */
2917 /* set SCL to output 0; set SDA to input */
2918 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2919 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2920 (u8 *)&dev->gpio_val);
2922 /* set SCL to output 1; set SDA to input */
2923 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2924 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2925 (u8 *)&dev->gpio_val);
2927 /* get SDA data bit */
2928 gpio_logic_value = dev->gpio_val;
2929 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
2930 (u8 *)&dev->gpio_val);
2931 if ((dev->gpio_val & (1 << dev->board.tuner_sda_gpio)) != 0)
2932 value |= (1 << (8 - i - 1));
2934 dev->gpio_val = gpio_logic_value;
2937 /* set SCL to output 0,finish the read latest SCL signal.
2938 !!!set SDA to input, never to modify SDA direction at
2940 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2941 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2943 /* store the value */
2944 *buf = value & 0xff;
2949 int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev)
2952 u32 gpio_logic_value = 0;
2956 /* clock stretch; set SCL to input; set SDA to input;
2957 get SCL value till SCL = 1 */
2958 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2959 dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
2961 gpio_logic_value = dev->gpio_val;
2962 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2966 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
2967 (u8 *)&dev->gpio_val);
2969 } while (((dev->gpio_val &
2970 (1 << dev->board.tuner_scl_gpio)) == 0) &&
2974 cx231xx_info("No ACK after %d msec -GPIO I2C failed!",
2979 * through clock stretch, slave has given a SCL signal,
2980 * so the SDA data can be directly read.
2982 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2984 if ((dev->gpio_val & 1 << dev->board.tuner_sda_gpio) == 0) {
2985 dev->gpio_val = gpio_logic_value;
2986 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2989 dev->gpio_val = gpio_logic_value;
2990 dev->gpio_val |= (1 << dev->board.tuner_sda_gpio);
2993 /* read SDA end, set the SCL to output 0, after this operation,
2994 SDA direction can be changed. */
2995 dev->gpio_val = gpio_logic_value;
2996 dev->gpio_dir |= (1 << dev->board.tuner_scl_gpio);
2997 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2998 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3003 int cx231xx_gpio_i2c_write_ack(struct cx231xx *dev)
3007 /* set SDA to ouput */
3008 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
3009 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3011 /* set SCL = 0 (output); set SDA = 0 (output) */
3012 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
3013 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
3014 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3016 /* set SCL = 1 (output); set SDA = 0 (output) */
3017 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
3018 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3020 /* set SCL = 0 (output); set SDA = 0 (output) */
3021 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
3022 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3024 /* set SDA to input,and then the slave will read data from SDA. */
3025 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
3026 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3031 int cx231xx_gpio_i2c_write_nak(struct cx231xx *dev)
3035 /* set scl to output ; set sda to input */
3036 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
3037 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
3038 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3040 /* set scl to output 0; set sda to input */
3041 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
3042 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3044 /* set scl to output 1; set sda to input */
3045 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
3046 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3051 /*****************************************************************************
3052 * G P I O I2C related functions *
3053 ******************************************************************************/
3054 /* cx231xx_gpio_i2c_read
3055 * Function to read data from gpio based I2C interface
3057 int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len)
3063 mutex_lock(&dev->gpio_i2c_lock);
3066 status = cx231xx_gpio_i2c_start(dev);
3068 /* write dev_addr */
3069 status = cx231xx_gpio_i2c_write_byte(dev, (dev_addr << 1) + 1);
3072 status = cx231xx_gpio_i2c_read_ack(dev);
3075 for (i = 0; i < len; i++) {
3078 status = cx231xx_gpio_i2c_read_byte(dev, &buf[i]);
3080 if ((i + 1) != len) {
3081 /* only do write ack if we more length */
3082 status = cx231xx_gpio_i2c_write_ack(dev);
3086 /* write NAK - inform reads are complete */
3087 status = cx231xx_gpio_i2c_write_nak(dev);
3090 status = cx231xx_gpio_i2c_end(dev);
3092 /* release the lock */
3093 mutex_unlock(&dev->gpio_i2c_lock);
3098 /* cx231xx_gpio_i2c_write
3099 * Function to write data to gpio based I2C interface
3101 int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len)
3107 mutex_lock(&dev->gpio_i2c_lock);
3110 status = cx231xx_gpio_i2c_start(dev);
3112 /* write dev_addr */
3113 status = cx231xx_gpio_i2c_write_byte(dev, dev_addr << 1);
3116 status = cx231xx_gpio_i2c_read_ack(dev);
3118 for (i = 0; i < len; i++) {
3120 status = cx231xx_gpio_i2c_write_byte(dev, buf[i]);
3123 status = cx231xx_gpio_i2c_read_ack(dev);
3127 status = cx231xx_gpio_i2c_end(dev);
3129 /* release the lock */
3130 mutex_unlock(&dev->gpio_i2c_lock);