drivers/media/platform/soc_camera/mx2_camera.c

   1 /*
   2  * V4L2 Driver for i.MX27/i.MX25 camera host
   3  *
   4  * Copyright (C) 2008, Sascha Hauer, Pengutronix
   5  * Copyright (C) 2010, Baruch Siach, Orex Computed Radiography
   6  * Copyright (C) 2012, Javier Martin, Vista Silicon S.L.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/init.h>
  15 #include <linux/module.h>
  16 #include <linux/io.h>
  17 #include <linux/delay.h>
  18 #include <linux/slab.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/errno.h>
  21 #include <linux/fs.h>
  22 #include <linux/gcd.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/kernel.h>
  25 #include <linux/math64.h>
  26 #include <linux/mm.h>
  27 #include <linux/moduleparam.h>
  28 #include <linux/time.h>
  29 #include <linux/device.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/mutex.h>
  32 #include <linux/clk.h>
  33
  34 #include <media/v4l2-common.h>
  35 #include <media/v4l2-dev.h>
  36 #include <media/videobuf2-core.h>
  37 #include <media/videobuf2-dma-contig.h>
  38 #include <media/soc_camera.h>
  39 #include <media/soc_mediabus.h>
  40
  41 #include <linux/videodev2.h>
  42
  43 #include <linux/platform_data/camera-mx2.h>
  44 #include <mach/hardware.h>
  45
  46 #include <asm/dma.h>
  47
  48 #define MX2_CAM_DRV_NAME "mx2-camera"
  49 #define MX2_CAM_VERSION "0.0.6"
  50 #define MX2_CAM_DRIVER_DESCRIPTION "i.MX2x_Camera"
  51
  52 /* reset values */
  53 #define CSICR1_RESET_VAL        0x40000800
  54 #define CSICR2_RESET_VAL        0x0
  55 #define CSICR3_RESET_VAL        0x0
  56
  57 /* csi control reg 1 */
  58 #define CSICR1_SWAP16_EN        (1 << 31)
  59 #define CSICR1_EXT_VSYNC        (1 << 30)
  60 #define CSICR1_EOF_INTEN        (1 << 29)
  61 #define CSICR1_PRP_IF_EN        (1 << 28)
  62 #define CSICR1_CCIR_MODE        (1 << 27)
  63 #define CSICR1_COF_INTEN        (1 << 26)
  64 #define CSICR1_SF_OR_INTEN      (1 << 25)
  65 #define CSICR1_RF_OR_INTEN      (1 << 24)
  66 #define CSICR1_STATFF_LEVEL     (3 << 22)
  67 #define CSICR1_STATFF_INTEN     (1 << 21)
  68 #define CSICR1_RXFF_LEVEL(l)    (((l) & 3) << 19)       /* MX27 */
  69 #define CSICR1_FB2_DMA_INTEN    (1 << 20)               /* MX25 */
  70 #define CSICR1_FB1_DMA_INTEN    (1 << 19)               /* MX25 */
  71 #define CSICR1_RXFF_INTEN       (1 << 18)
  72 #define CSICR1_SOF_POL          (1 << 17)
  73 #define CSICR1_SOF_INTEN        (1 << 16)
  74 #define CSICR1_MCLKDIV(d)       (((d) & 0xF) << 12)
  75 #define CSICR1_HSYNC_POL        (1 << 11)
  76 #define CSICR1_CCIR_EN          (1 << 10)
  77 #define CSICR1_MCLKEN           (1 << 9)
  78 #define CSICR1_FCC              (1 << 8)
  79 #define CSICR1_PACK_DIR         (1 << 7)
  80 #define CSICR1_CLR_STATFIFO     (1 << 6)
  81 #define CSICR1_CLR_RXFIFO       (1 << 5)
  82 #define CSICR1_GCLK_MODE        (1 << 4)
  83 #define CSICR1_INV_DATA         (1 << 3)
  84 #define CSICR1_INV_PCLK         (1 << 2)
  85 #define CSICR1_REDGE            (1 << 1)
  86 #define CSICR1_FMT_MASK         (CSICR1_PACK_DIR | CSICR1_SWAP16_EN)
  87
  88 #define SHIFT_STATFF_LEVEL      22
  89 #define SHIFT_RXFF_LEVEL        19
  90 #define SHIFT_MCLKDIV           12
  91
  92 /* control reg 3 */
  93 #define CSICR3_FRMCNT           (0xFFFF << 16)
  94 #define CSICR3_FRMCNT_RST       (1 << 15)
  95 #define CSICR3_DMA_REFLASH_RFF  (1 << 14)
  96 #define CSICR3_DMA_REFLASH_SFF  (1 << 13)
  97 #define CSICR3_DMA_REQ_EN_RFF   (1 << 12)
  98 #define CSICR3_DMA_REQ_EN_SFF   (1 << 11)
  99 #define CSICR3_RXFF_LEVEL(l)    (((l) & 7) << 4)        /* MX25 */
 100 #define CSICR3_CSI_SUP          (1 << 3)
 101 #define CSICR3_ZERO_PACK_EN     (1 << 2)
 102 #define CSICR3_ECC_INT_EN       (1 << 1)
 103 #define CSICR3_ECC_AUTO_EN      (1 << 0)
 104
 105 #define SHIFT_FRMCNT            16
 106
 107 /* csi status reg */
 108 #define CSISR_SFF_OR_INT        (1 << 25)
 109 #define CSISR_RFF_OR_INT        (1 << 24)
 110 #define CSISR_STATFF_INT        (1 << 21)
 111 #define CSISR_DMA_TSF_FB2_INT   (1 << 20)       /* MX25 */
 112 #define CSISR_DMA_TSF_FB1_INT   (1 << 19)       /* MX25 */
 113 #define CSISR_RXFF_INT          (1 << 18)
 114 #define CSISR_EOF_INT           (1 << 17)
 115 #define CSISR_SOF_INT           (1 << 16)
 116 #define CSISR_F2_INT            (1 << 15)
 117 #define CSISR_F1_INT            (1 << 14)
 118 #define CSISR_COF_INT           (1 << 13)
 119 #define CSISR_ECC_INT           (1 << 1)
 120 #define CSISR_DRDY              (1 << 0)
 121
 122 #define CSICR1                  0x00
 123 #define CSICR2                  0x04
 124 #define CSISR                   (cpu_is_mx27() ? 0x08 : 0x18)
 125 #define CSISTATFIFO             0x0c
 126 #define CSIRFIFO                0x10
 127 #define CSIRXCNT                0x14
 128 #define CSICR3                  (cpu_is_mx27() ? 0x1C : 0x08)
 129 #define CSIDMASA_STATFIFO       0x20
 130 #define CSIDMATA_STATFIFO       0x24
 131 #define CSIDMASA_FB1            0x28
 132 #define CSIDMASA_FB2            0x2c
 133 #define CSIFBUF_PARA            0x30
 134 #define CSIIMAG_PARA            0x34
 135
 136 /* EMMA PrP */
 137 #define PRP_CNTL                        0x00
 138 #define PRP_INTR_CNTL                   0x04
 139 #define PRP_INTRSTATUS                  0x08
 140 #define PRP_SOURCE_Y_PTR                0x0c
 141 #define PRP_SOURCE_CB_PTR               0x10
 142 #define PRP_SOURCE_CR_PTR               0x14
 143 #define PRP_DEST_RGB1_PTR               0x18
 144 #define PRP_DEST_RGB2_PTR               0x1c
 145 #define PRP_DEST_Y_PTR                  0x20
 146 #define PRP_DEST_CB_PTR                 0x24
 147 #define PRP_DEST_CR_PTR                 0x28
 148 #define PRP_SRC_FRAME_SIZE              0x2c
 149 #define PRP_DEST_CH1_LINE_STRIDE        0x30
 150 #define PRP_SRC_PIXEL_FORMAT_CNTL       0x34
 151 #define PRP_CH1_PIXEL_FORMAT_CNTL       0x38
 152 #define PRP_CH1_OUT_IMAGE_SIZE          0x3c
 153 #define PRP_CH2_OUT_IMAGE_SIZE          0x40
 154 #define PRP_SRC_LINE_STRIDE             0x44
 155 #define PRP_CSC_COEF_012                0x48
 156 #define PRP_CSC_COEF_345                0x4c
 157 #define PRP_CSC_COEF_678                0x50
 158 #define PRP_CH1_RZ_HORI_COEF1           0x54
 159 #define PRP_CH1_RZ_HORI_COEF2           0x58
 160 #define PRP_CH1_RZ_HORI_VALID           0x5c
 161 #define PRP_CH1_RZ_VERT_COEF1           0x60
 162 #define PRP_CH1_RZ_VERT_COEF2           0x64
 163 #define PRP_CH1_RZ_VERT_VALID           0x68
 164 #define PRP_CH2_RZ_HORI_COEF1           0x6c
 165 #define PRP_CH2_RZ_HORI_COEF2           0x70
 166 #define PRP_CH2_RZ_HORI_VALID           0x74
 167 #define PRP_CH2_RZ_VERT_COEF1           0x78
 168 #define PRP_CH2_RZ_VERT_COEF2           0x7c
 169 #define PRP_CH2_RZ_VERT_VALID           0x80
 170
 171 #define PRP_CNTL_CH1EN          (1 << 0)
 172 #define PRP_CNTL_CH2EN          (1 << 1)
 173 #define PRP_CNTL_CSIEN          (1 << 2)
 174 #define PRP_CNTL_DATA_IN_YUV420 (0 << 3)
 175 #define PRP_CNTL_DATA_IN_YUV422 (1 << 3)
 176 #define PRP_CNTL_DATA_IN_RGB16  (2 << 3)
 177 #define PRP_CNTL_DATA_IN_RGB32  (3 << 3)
 178 #define PRP_CNTL_CH1_OUT_RGB8   (0 << 5)
 179 #define PRP_CNTL_CH1_OUT_RGB16  (1 << 5)
 180 #define PRP_CNTL_CH1_OUT_RGB32  (2 << 5)
 181 #define PRP_CNTL_CH1_OUT_YUV422 (3 << 5)
 182 #define PRP_CNTL_CH2_OUT_YUV420 (0 << 7)
 183 #define PRP_CNTL_CH2_OUT_YUV422 (1 << 7)
 184 #define PRP_CNTL_CH2_OUT_YUV444 (2 << 7)
 185 #define PRP_CNTL_CH1_LEN        (1 << 9)
 186 #define PRP_CNTL_CH2_LEN        (1 << 10)
 187 #define PRP_CNTL_SKIP_FRAME     (1 << 11)
 188 #define PRP_CNTL_SWRST          (1 << 12)
 189 #define PRP_CNTL_CLKEN          (1 << 13)
 190 #define PRP_CNTL_WEN            (1 << 14)
 191 #define PRP_CNTL_CH1BYP         (1 << 15)
 192 #define PRP_CNTL_IN_TSKIP(x)    ((x) << 16)
 193 #define PRP_CNTL_CH1_TSKIP(x)   ((x) << 19)
 194 #define PRP_CNTL_CH2_TSKIP(x)   ((x) << 22)
 195 #define PRP_CNTL_INPUT_FIFO_LEVEL(x)    ((x) << 25)
 196 #define PRP_CNTL_RZ_FIFO_LEVEL(x)       ((x) << 27)
 197 #define PRP_CNTL_CH2B1EN        (1 << 29)
 198 #define PRP_CNTL_CH2B2EN        (1 << 30)
 199 #define PRP_CNTL_CH2FEN         (1 << 31)
 200
 201 /* IRQ Enable and status register */
 202 #define PRP_INTR_RDERR          (1 << 0)
 203 #define PRP_INTR_CH1WERR        (1 << 1)
 204 #define PRP_INTR_CH2WERR        (1 << 2)
 205 #define PRP_INTR_CH1FC          (1 << 3)
 206 #define PRP_INTR_CH2FC          (1 << 5)
 207 #define PRP_INTR_LBOVF          (1 << 7)
 208 #define PRP_INTR_CH2OVF         (1 << 8)
 209
 210 /* Resizing registers */
 211 #define PRP_RZ_VALID_TBL_LEN(x) ((x) << 24)
 212 #define PRP_RZ_VALID_BILINEAR   (1 << 31)
 213
 214 #define MAX_VIDEO_MEM   16
 215
 216 #define RESIZE_NUM_MIN  1
 217 #define RESIZE_NUM_MAX  20
 218 #define BC_COEF         3
 219 #define SZ_COEF         (1 << BC_COEF)
 220
 221 #define RESIZE_DIR_H    0
 222 #define RESIZE_DIR_V    1
 223
 224 #define RESIZE_ALGO_BILINEAR 0
 225 #define RESIZE_ALGO_AVERAGING 1
 226
 227 struct mx2_prp_cfg {
 228         int channel;
 229         u32 in_fmt;
 230         u32 out_fmt;
 231         u32 src_pixel;
 232         u32 ch1_pixel;
 233         u32 irq_flags;
 234         u32 csicr1;
 235 };
 236
 237 /* prp resizing parameters */
 238 struct emma_prp_resize {
 239         int             algo; /* type of algorithm used */
 240         int             len; /* number of coefficients */
 241         unsigned char   s[RESIZE_NUM_MAX]; /* table of coefficients */
 242 };
 243
 244 /* prp configuration for a client-host fmt pair */
 245 struct mx2_fmt_cfg {
 246         enum v4l2_mbus_pixelcode        in_fmt;
 247         u32                             out_fmt;
 248         struct mx2_prp_cfg              cfg;
 249 };
 250
 251 enum mx2_buffer_state {
 252         MX2_STATE_QUEUED,
 253         MX2_STATE_ACTIVE,
 254         MX2_STATE_DONE,
 255 };
 256
 257 struct mx2_buf_internal {
 258         struct list_head        queue;
 259         int                     bufnum;
 260         bool                    discard;
 261 };
 262
 263 /* buffer for one video frame */
 264 struct mx2_buffer {
 265         /* common v4l buffer stuff -- must be first */
 266         struct vb2_buffer               vb;
 267         enum mx2_buffer_state           state;
 268         struct mx2_buf_internal         internal;
 269 };
 270
 271 struct mx2_camera_dev {
 272         struct device           *dev;
 273         struct soc_camera_host  soc_host;
 274         struct soc_camera_device *icd;
 275         struct clk              *clk_csi, *clk_emma_ahb, *clk_emma_ipg;
 276
 277         void __iomem            *base_csi, *base_emma;
 278
 279         struct mx2_camera_platform_data *pdata;
 280         unsigned long           platform_flags;
 281
 282         struct list_head        capture;
 283         struct list_head        active_bufs;
 284         struct list_head        discard;
 285
 286         spinlock_t              lock;
 287
 288         int                     dma;
 289         struct mx2_buffer       *active;
 290         struct mx2_buffer       *fb1_active;
 291         struct mx2_buffer       *fb2_active;
 292
 293         u32                     csicr1;
 294
 295         struct mx2_buf_internal buf_discard[2];
 296         void                    *discard_buffer;
 297         dma_addr_t              discard_buffer_dma;
 298         size_t                  discard_size;
 299         struct mx2_fmt_cfg      *emma_prp;
 300         struct emma_prp_resize  resizing[2];
 301         unsigned int            s_width, s_height;
 302         u32                     frame_count;
 303         struct vb2_alloc_ctx    *alloc_ctx;
 304 };
 305
 306 static struct mx2_buffer *mx2_ibuf_to_buf(struct mx2_buf_internal *int_buf)
 307 {
 308         return container_of(int_buf, struct mx2_buffer, internal);
 309 }
 310
 311 static struct mx2_fmt_cfg mx27_emma_prp_table[] = {
 312         /*
 313          * This is a generic configuration which is valid for most
 314          * prp input-output format combinations.
 315          * We set the incomming and outgoing pixelformat to a
 316          * 16 Bit wide format and adjust the bytesperline
 317          * accordingly. With this configuration the inputdata
 318          * will not be changed by the emma and could be any type
 319          * of 16 Bit Pixelformat.
 320          */
 321         {
 322                 .in_fmt         = 0,
 323                 .out_fmt        = 0,
 324                 .cfg            = {
 325                         .channel        = 1,
 326                         .in_fmt         = PRP_CNTL_DATA_IN_RGB16,
 327                         .out_fmt        = PRP_CNTL_CH1_OUT_RGB16,
 328                         .src_pixel      = 0x2ca00565, /* RGB565 */
 329                         .ch1_pixel      = 0x2ca00565, /* RGB565 */
 330                         .irq_flags      = PRP_INTR_RDERR | PRP_INTR_CH1WERR |
 331                                                 PRP_INTR_CH1FC | PRP_INTR_LBOVF,
 332                         .csicr1         = 0,
 333                 }
 334         },
 335         {
 336                 .in_fmt         = V4L2_MBUS_FMT_UYVY8_2X8,
 337                 .out_fmt        = V4L2_PIX_FMT_YUYV,
 338                 .cfg            = {
 339                         .channel        = 1,
 340                         .in_fmt         = PRP_CNTL_DATA_IN_YUV422,
 341                         .out_fmt        = PRP_CNTL_CH1_OUT_YUV422,
 342                         .src_pixel      = 0x22000888, /* YUV422 (YUYV) */
 343                         .ch1_pixel      = 0x62000888, /* YUV422 (YUYV) */
 344                         .irq_flags      = PRP_INTR_RDERR | PRP_INTR_CH1WERR |
 345                                                 PRP_INTR_CH1FC | PRP_INTR_LBOVF,
 346                         .csicr1         = CSICR1_SWAP16_EN,
 347                 }
 348         },
 349         {
 350                 .in_fmt         = V4L2_MBUS_FMT_YUYV8_2X8,
 351                 .out_fmt        = V4L2_PIX_FMT_YUYV,
 352                 .cfg            = {
 353                         .channel        = 1,
 354                         .in_fmt         = PRP_CNTL_DATA_IN_YUV422,
 355                         .out_fmt        = PRP_CNTL_CH1_OUT_YUV422,
 356                         .src_pixel      = 0x22000888, /* YUV422 (YUYV) */
 357                         .ch1_pixel      = 0x62000888, /* YUV422 (YUYV) */
 358                         .irq_flags      = PRP_INTR_RDERR | PRP_INTR_CH1WERR |
 359                                                 PRP_INTR_CH1FC | PRP_INTR_LBOVF,
 360                         .csicr1         = CSICR1_PACK_DIR,
 361                 }
 362         },
 363         {
 364                 .in_fmt         = V4L2_MBUS_FMT_YUYV8_2X8,
 365                 .out_fmt        = V4L2_PIX_FMT_YUV420,
 366                 .cfg            = {
 367                         .channel        = 2,
 368                         .in_fmt         = PRP_CNTL_DATA_IN_YUV422,
 369                         .out_fmt        = PRP_CNTL_CH2_OUT_YUV420,
 370                         .src_pixel      = 0x22000888, /* YUV422 (YUYV) */
 371                         .irq_flags      = PRP_INTR_RDERR | PRP_INTR_CH2WERR |
 372                                         PRP_INTR_CH2FC | PRP_INTR_LBOVF |
 373                                         PRP_INTR_CH2OVF,
 374                         .csicr1         = CSICR1_PACK_DIR,
 375                 }
 376         },
 377         {
 378                 .in_fmt         = V4L2_MBUS_FMT_UYVY8_2X8,
 379                 .out_fmt        = V4L2_PIX_FMT_YUV420,
 380                 .cfg            = {
 381                         .channel        = 2,
 382                         .in_fmt         = PRP_CNTL_DATA_IN_YUV422,
 383                         .out_fmt        = PRP_CNTL_CH2_OUT_YUV420,
 384                         .src_pixel      = 0x22000888, /* YUV422 (YUYV) */
 385                         .irq_flags      = PRP_INTR_RDERR | PRP_INTR_CH2WERR |
 386                                         PRP_INTR_CH2FC | PRP_INTR_LBOVF |
 387                                         PRP_INTR_CH2OVF,
 388                         .csicr1         = CSICR1_SWAP16_EN,
 389                 }
 390         },
 391 };
 392
 393 static struct mx2_fmt_cfg *mx27_emma_prp_get_format(
 394                                         enum v4l2_mbus_pixelcode in_fmt,
 395                                         u32 out_fmt)
 396 {
 397         int i;
 398
 399         for (i = 1; i < ARRAY_SIZE(mx27_emma_prp_table); i++)
 400                 if ((mx27_emma_prp_table[i].in_fmt == in_fmt) &&
 401                                 (mx27_emma_prp_table[i].out_fmt == out_fmt)) {
 402                         return &mx27_emma_prp_table[i];
 403                 }
 404         /* If no match return the most generic configuration */
 405         return &mx27_emma_prp_table[0];
 406 };
 407
 408 static void mx27_update_emma_buf(struct mx2_camera_dev *pcdev,
 409                                  unsigned long phys, int bufnum)
 410 {
 411         struct mx2_fmt_cfg *prp = pcdev->emma_prp;
 412
 413         if (prp->cfg.channel == 1) {
 414                 writel(phys, pcdev->base_emma +
 415                                 PRP_DEST_RGB1_PTR + 4 * bufnum);
 416         } else {
 417                 writel(phys, pcdev->base_emma +
 418                         PRP_DEST_Y_PTR - 0x14 * bufnum);
 419                 if (prp->out_fmt == V4L2_PIX_FMT_YUV420) {
 420                         u32 imgsize = pcdev->icd->user_height *
 421                                         pcdev->icd->user_width;
 422
 423                         writel(phys + imgsize, pcdev->base_emma +
 424                                 PRP_DEST_CB_PTR - 0x14 * bufnum);
 425                         writel(phys + ((5 * imgsize) / 4), pcdev->base_emma +
 426                                 PRP_DEST_CR_PTR - 0x14 * bufnum);
 427                 }
 428         }
 429 }
 430
 431 static void mx2_camera_deactivate(struct mx2_camera_dev *pcdev)
 432 {
 433         unsigned long flags;
 434
 435         clk_disable_unprepare(pcdev->clk_csi);
 436         writel(0, pcdev->base_csi + CSICR1);
 437         if (cpu_is_mx27()) {
 438                 writel(0, pcdev->base_emma + PRP_CNTL);
 439         } else if (cpu_is_mx25()) {
 440                 spin_lock_irqsave(&pcdev->lock, flags);
 441                 pcdev->fb1_active = NULL;
 442                 pcdev->fb2_active = NULL;
 443                 writel(0, pcdev->base_csi + CSIDMASA_FB1);
 444                 writel(0, pcdev->base_csi + CSIDMASA_FB2);
 445                 spin_unlock_irqrestore(&pcdev->lock, flags);
 446         }
 447 }
 448
 449 /*
 450  * The following two functions absolutely depend on the fact, that
 451  * there can be only one camera on mx2 camera sensor interface
 452  */
 453 static int mx2_camera_add_device(struct soc_camera_device *icd)
 454 {
 455         struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
 456         struct mx2_camera_dev *pcdev = ici->priv;
 457         int ret;
 458         u32 csicr1;
 459
 460         if (pcdev->icd)
 461                 return -EBUSY;
 462
 463         ret = clk_prepare_enable(pcdev->clk_csi);
 464         if (ret < 0)
 465                 return ret;
 466
 467         csicr1 = CSICR1_MCLKEN;
 468
 469         if (cpu_is_mx27())
 470                 csicr1 |= CSICR1_PRP_IF_EN | CSICR1_FCC |
 471                         CSICR1_RXFF_LEVEL(0);
 472
 473         pcdev->csicr1 = csicr1;
 474         writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
 475
 476         pcdev->icd = icd;
 477         pcdev->frame_count = 0;
 478
 479         dev_info(icd->parent, "Camera driver attached to camera %d\n",
 480                  icd->devnum);
 481
 482         return 0;
 483 }
 484
 485 static void mx2_camera_remove_device(struct soc_camera_device *icd)
 486 {
 487         struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
 488         struct mx2_camera_dev *pcdev = ici->priv;
 489
 490         BUG_ON(icd != pcdev->icd);
 491
 492         dev_info(icd->parent, "Camera driver detached from camera %d\n",
 493                  icd->devnum);
 494
 495         mx2_camera_deactivate(pcdev);
 496
 497         pcdev->icd = NULL;
 498 }
 499
 500 static void mx25_camera_frame_done(struct mx2_camera_dev *pcdev, int fb,
 501                 int state)
 502 {
 503         struct vb2_buffer *vb;
 504         struct mx2_buffer *buf;
 505         struct mx2_buffer **fb_active = fb == 1 ? &pcdev->fb1_active :
 506                 &pcdev->fb2_active;
 507         u32 fb_reg = fb == 1 ? CSIDMASA_FB1 : CSIDMASA_FB2;
 508         unsigned long flags;
 509
 510         spin_lock_irqsave(&pcdev->lock, flags);
 511
 512         if (*fb_active == NULL)
 513                 goto out;
 514
 515         vb = &(*fb_active)->vb;
 516         dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%p %lu\n", __func__,
 517                 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
 518
 519         do_gettimeofday(&vb->v4l2_buf.timestamp);
 520         vb->v4l2_buf.sequence++;
 521         vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
 522
 523         if (list_empty(&pcdev->capture)) {
 524                 buf = NULL;
 525                 writel(0, pcdev->base_csi + fb_reg);
 526         } else {
 527                 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
 528                                 internal.queue);
 529                 vb = &buf->vb;
 530                 list_del(&buf->internal.queue);
 531                 buf->state = MX2_STATE_ACTIVE;
 532                 writel(vb2_dma_contig_plane_dma_addr(vb, 0),
 533                        pcdev->base_csi + fb_reg);
 534         }
 535
 536         *fb_active = buf;
 537
 538 out:
 539         spin_unlock_irqrestore(&pcdev->lock, flags);
 540 }
 541
 542 static irqreturn_t mx25_camera_irq(int irq_csi, void *data)
 543 {
 544         struct mx2_camera_dev *pcdev = data;
 545         u32 status = readl(pcdev->base_csi + CSISR);
 546
 547         if (status & CSISR_DMA_TSF_FB1_INT)
 548                 mx25_camera_frame_done(pcdev, 1, MX2_STATE_DONE);
 549         else if (status & CSISR_DMA_TSF_FB2_INT)
 550                 mx25_camera_frame_done(pcdev, 2, MX2_STATE_DONE);
 551
 552         /* FIXME: handle CSISR_RFF_OR_INT */
 553
 554         writel(status, pcdev->base_csi + CSISR);
 555
 556         return IRQ_HANDLED;
 557 }
 558
 559 /*
 560  *  Videobuf operations
 561  */
 562 static int mx2_videobuf_setup(struct vb2_queue *vq,
 563                         const struct v4l2_format *fmt,
 564                         unsigned int *count, unsigned int *num_planes,
 565                         unsigned int sizes[], void *alloc_ctxs[])
 566 {
 567         struct soc_camera_device *icd = soc_camera_from_vb2q(vq);
 568         struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
 569         struct mx2_camera_dev *pcdev = ici->priv;
 570
 571         dev_dbg(icd->parent, "count=%d, size=%d\n", *count, sizes[0]);
 572
 573         /* TODO: support for VIDIOC_CREATE_BUFS not ready */
 574         if (fmt != NULL)
 575                 return -ENOTTY;
 576
 577         alloc_ctxs[0] = pcdev->alloc_ctx;
 578
 579         sizes[0] = icd->sizeimage;
 580
 581         if (0 == *count)
 582                 *count = 32;
 583         if (!*num_planes &&
 584             sizes[0] * *count > MAX_VIDEO_MEM * 1024 * 1024)
 585                 *count = (MAX_VIDEO_MEM * 1024 * 1024) / sizes[0];
 586
 587         *num_planes = 1;
 588
 589         return 0;
 590 }
 591
 592 static int mx2_videobuf_prepare(struct vb2_buffer *vb)
 593 {
 594         struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
 595         int ret = 0;
 596
 597         dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__,
 598                 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
 599
 600 #ifdef DEBUG
 601         /*
 602          * This can be useful if you want to see if we actually fill
 603          * the buffer with something
 604          */
 605         memset((void *)vb2_plane_vaddr(vb, 0),
 606                0xaa, vb2_get_plane_payload(vb, 0));
 607 #endif
 608
 609         vb2_set_plane_payload(vb, 0, icd->sizeimage);
 610         if (vb2_plane_vaddr(vb, 0) &&
 611             vb2_get_plane_payload(vb, 0) > vb2_plane_size(vb, 0)) {
 612                 ret = -EINVAL;
 613                 goto out;
 614         }
 615
 616         return 0;
 617
 618 out:
 619         return ret;
 620 }
 621
 622 static void mx2_videobuf_queue(struct vb2_buffer *vb)
 623 {
 624         struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
 625         struct soc_camera_host *ici =
 626                 to_soc_camera_host(icd->parent);
 627         struct mx2_camera_dev *pcdev = ici->priv;
 628         struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
 629         unsigned long flags;
 630
 631         dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__,
 632                 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
 633
 634         spin_lock_irqsave(&pcdev->lock, flags);
 635
 636         buf->state = MX2_STATE_QUEUED;
 637         list_add_tail(&buf->internal.queue, &pcdev->capture);
 638
 639         if (cpu_is_mx25()) {
 640                 u32 csicr3, dma_inten = 0;
 641
 642                 if (pcdev->fb1_active == NULL) {
 643                         writel(vb2_dma_contig_plane_dma_addr(vb, 0),
 644                                         pcdev->base_csi + CSIDMASA_FB1);
 645                         pcdev->fb1_active = buf;
 646                         dma_inten = CSICR1_FB1_DMA_INTEN;
 647                 } else if (pcdev->fb2_active == NULL) {
 648                         writel(vb2_dma_contig_plane_dma_addr(vb, 0),
 649                                         pcdev->base_csi + CSIDMASA_FB2);
 650                         pcdev->fb2_active = buf;
 651                         dma_inten = CSICR1_FB2_DMA_INTEN;
 652                 }
 653
 654                 if (dma_inten) {
 655                         list_del(&buf->internal.queue);
 656                         buf->state = MX2_STATE_ACTIVE;
 657
 658                         csicr3 = readl(pcdev->base_csi + CSICR3);
 659
 660                         /* Reflash DMA */
 661                         writel(csicr3 | CSICR3_DMA_REFLASH_RFF,
 662                                         pcdev->base_csi + CSICR3);
 663
 664                         /* clear & enable interrupts */
 665                         writel(dma_inten, pcdev->base_csi + CSISR);
 666                         pcdev->csicr1 |= dma_inten;
 667                         writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
 668
 669                         /* enable DMA */
 670                         csicr3 |= CSICR3_DMA_REQ_EN_RFF | CSICR3_RXFF_LEVEL(1);
 671                         writel(csicr3, pcdev->base_csi + CSICR3);
 672                 }
 673         }
 674
 675         spin_unlock_irqrestore(&pcdev->lock, flags);
 676 }
 677
 678 static void mx2_videobuf_release(struct vb2_buffer *vb)
 679 {
 680         struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
 681         struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
 682         struct mx2_camera_dev *pcdev = ici->priv;
 683         struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
 684         unsigned long flags;
 685
 686 #ifdef DEBUG
 687         dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__,
 688                 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
 689
 690         switch (buf->state) {
 691         case MX2_STATE_ACTIVE:
 692                 dev_info(icd->parent, "%s (active)\n", __func__);
 693                 break;
 694         case MX2_STATE_QUEUED:
 695                 dev_info(icd->parent, "%s (queued)\n", __func__);
 696                 break;
 697         default:
 698                 dev_info(icd->parent, "%s (unknown) %d\n", __func__,
 699                                 buf->state);
 700                 break;
 701         }
 702 #endif
 703
 704         /*
 705          * Terminate only queued but inactive buffers. Active buffers are
 706          * released when they become inactive after videobuf_waiton().
 707          *
 708          * FIXME: implement forced termination of active buffers for mx27 and
 709          * mx27 eMMA, so that the user won't get stuck in an uninterruptible
 710          * state. This requires a specific handling for each of the these DMA
 711          * types.
 712          */
 713
 714         spin_lock_irqsave(&pcdev->lock, flags);
 715         if (cpu_is_mx25() && buf->state == MX2_STATE_ACTIVE) {
 716                 if (pcdev->fb1_active == buf) {
 717                         pcdev->csicr1 &= ~CSICR1_FB1_DMA_INTEN;
 718                         writel(0, pcdev->base_csi + CSIDMASA_FB1);
 719                         pcdev->fb1_active = NULL;
 720                 } else if (pcdev->fb2_active == buf) {
 721                         pcdev->csicr1 &= ~CSICR1_FB2_DMA_INTEN;
 722                         writel(0, pcdev->base_csi + CSIDMASA_FB2);
 723                         pcdev->fb2_active = NULL;
 724                 }
 725                 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
 726         }
 727         spin_unlock_irqrestore(&pcdev->lock, flags);
 728 }
 729
 730 static void mx27_camera_emma_buf_init(struct soc_camera_device *icd,
 731                 int bytesperline)
 732 {
 733         struct soc_camera_host *ici =
 734                 to_soc_camera_host(icd->parent);
 735         struct mx2_camera_dev *pcdev = ici->priv;
 736         struct mx2_fmt_cfg *prp = pcdev->emma_prp;
 737
 738         writel((pcdev->s_width << 16) | pcdev->s_height,
 739                pcdev->base_emma + PRP_SRC_FRAME_SIZE);
 740         writel(prp->cfg.src_pixel,
 741                pcdev->base_emma + PRP_SRC_PIXEL_FORMAT_CNTL);
 742         if (prp->cfg.channel == 1) {
 743                 writel((icd->user_width << 16) | icd->user_height,
 744                         pcdev->base_emma + PRP_CH1_OUT_IMAGE_SIZE);
 745                 writel(bytesperline,
 746                         pcdev->base_emma + PRP_DEST_CH1_LINE_STRIDE);
 747                 writel(prp->cfg.ch1_pixel,
 748                         pcdev->base_emma + PRP_CH1_PIXEL_FORMAT_CNTL);
 749         } else { /* channel 2 */
 750                 writel((icd->user_width << 16) | icd->user_height,
 751                         pcdev->base_emma + PRP_CH2_OUT_IMAGE_SIZE);
 752         }
 753
 754         /* Enable interrupts */
 755         writel(prp->cfg.irq_flags, pcdev->base_emma + PRP_INTR_CNTL);
 756 }
 757
 758 static void mx2_prp_resize_commit(struct mx2_camera_dev *pcdev)
 759 {
 760         int dir;
 761
 762         for (dir = RESIZE_DIR_H; dir <= RESIZE_DIR_V; dir++) {
 763                 unsigned char *s = pcdev->resizing[dir].s;
 764                 int len = pcdev->resizing[dir].len;
 765                 unsigned int coeff[2] = {0, 0};
 766                 unsigned int valid  = 0;
 767                 int i;
 768
 769                 if (len == 0)
 770                         continue;
 771
 772                 for (i = RESIZE_NUM_MAX - 1; i >= 0; i--) {
 773                         int j;
 774
 775                         j = i > 9 ? 1 : 0;
 776                         coeff[j] = (coeff[j] << BC_COEF) |
 777                                         (s[i] & (SZ_COEF - 1));
 778
 779                         if (i == 5 || i == 15)
 780                                 coeff[j] <<= 1;
 781
 782                         valid = (valid << 1) | (s[i] >> BC_COEF);
 783                 }
 784
 785                 valid |= PRP_RZ_VALID_TBL_LEN(len);
 786
 787                 if (pcdev->resizing[dir].algo == RESIZE_ALGO_BILINEAR)
 788                         valid |= PRP_RZ_VALID_BILINEAR;
 789
 790                 if (pcdev->emma_prp->cfg.channel == 1) {
 791                         if (dir == RESIZE_DIR_H) {
 792                                 writel(coeff[0], pcdev->base_emma +
 793                                                         PRP_CH1_RZ_HORI_COEF1);
 794                                 writel(coeff[1], pcdev->base_emma +
 795                                                         PRP_CH1_RZ_HORI_COEF2);
 796                                 writel(valid, pcdev->base_emma +
 797                                                         PRP_CH1_RZ_HORI_VALID);
 798                         } else {
 799                                 writel(coeff[0], pcdev->base_emma +
 800                                                         PRP_CH1_RZ_VERT_COEF1);
 801                                 writel(coeff[1], pcdev->base_emma +
 802                                                         PRP_CH1_RZ_VERT_COEF2);
 803                                 writel(valid, pcdev->base_emma +
 804                                                         PRP_CH1_RZ_VERT_VALID);
 805                         }
 806                 } else {
 807                         if (dir == RESIZE_DIR_H) {
 808                                 writel(coeff[0], pcdev->base_emma +
 809                                                         PRP_CH2_RZ_HORI_COEF1);
 810                                 writel(coeff[1], pcdev->base_emma +
 811                                                         PRP_CH2_RZ_HORI_COEF2);
 812                                 writel(valid, pcdev->base_emma +
 813                                                         PRP_CH2_RZ_HORI_VALID);
 814                         } else {
 815                                 writel(coeff[0], pcdev->base_emma +
 816                                                         PRP_CH2_RZ_VERT_COEF1);
 817                                 writel(coeff[1], pcdev->base_emma +
 818                                                         PRP_CH2_RZ_VERT_COEF2);
 819                                 writel(valid, pcdev->base_emma +
 820                                                         PRP_CH2_RZ_VERT_VALID);
 821                         }
 822                 }
 823         }
 824 }
 825
 826 static int mx2_start_streaming(struct vb2_queue *q, unsigned int count)
 827 {
 828         struct soc_camera_device *icd = soc_camera_from_vb2q(q);
 829         struct soc_camera_host *ici =
 830                 to_soc_camera_host(icd->parent);
 831         struct mx2_camera_dev *pcdev = ici->priv;
 832         struct mx2_fmt_cfg *prp = pcdev->emma_prp;
 833         struct vb2_buffer *vb;
 834         struct mx2_buffer *buf;
 835         unsigned long phys;
 836         int bytesperline;
 837
 838         if (cpu_is_mx27()) {
 839                 unsigned long flags;
 840                 if (count < 2)
 841                         return -EINVAL;
 842
 843                 spin_lock_irqsave(&pcdev->lock, flags);
 844
 845                 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
 846                                        internal.queue);
 847                 buf->internal.bufnum = 0;
 848                 vb = &buf->vb;
 849                 buf->state = MX2_STATE_ACTIVE;
 850
 851                 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
 852                 mx27_update_emma_buf(pcdev, phys, buf->internal.bufnum);
 853                 list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
 854
 855                 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
 856                                        internal.queue);
 857                 buf->internal.bufnum = 1;
 858                 vb = &buf->vb;
 859                 buf->state = MX2_STATE_ACTIVE;
 860
 861                 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
 862                 mx27_update_emma_buf(pcdev, phys, buf->internal.bufnum);
 863                 list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
 864
 865                 bytesperline = soc_mbus_bytes_per_line(icd->user_width,
 866                                 icd->current_fmt->host_fmt);
 867                 if (bytesperline < 0)
 868                         return bytesperline;
 869
 870                 /*
 871                  * I didn't manage to properly enable/disable the prp
 872                  * on a per frame basis during running transfers,
 873                  * thus we allocate a buffer here and use it to
 874                  * discard frames when no buffer is available.
 875                  * Feel free to work on this ;)
 876                  */
 877                 pcdev->discard_size = icd->user_height * bytesperline;
 878                 pcdev->discard_buffer = dma_alloc_coherent(ici->v4l2_dev.dev,
 879                                 pcdev->discard_size, &pcdev->discard_buffer_dma,
 880                                 GFP_KERNEL);
 881                 if (!pcdev->discard_buffer)
 882                         return -ENOMEM;
 883
 884                 pcdev->buf_discard[0].discard = true;
 885                 list_add_tail(&pcdev->buf_discard[0].queue,
 886                                       &pcdev->discard);
 887
 888                 pcdev->buf_discard[1].discard = true;
 889                 list_add_tail(&pcdev->buf_discard[1].queue,
 890                                       &pcdev->discard);
 891
 892                 mx2_prp_resize_commit(pcdev);
 893
 894                 mx27_camera_emma_buf_init(icd, bytesperline);
 895
 896                 if (prp->cfg.channel == 1) {
 897                         writel(PRP_CNTL_CH1EN |
 898                                 PRP_CNTL_CSIEN |
 899                                 prp->cfg.in_fmt |
 900                                 prp->cfg.out_fmt |
 901                                 PRP_CNTL_CH1_LEN |
 902                                 PRP_CNTL_CH1BYP |
 903                                 PRP_CNTL_CH1_TSKIP(0) |
 904                                 PRP_CNTL_IN_TSKIP(0),
 905                                 pcdev->base_emma + PRP_CNTL);
 906                 } else {
 907                         writel(PRP_CNTL_CH2EN |
 908                                 PRP_CNTL_CSIEN |
 909                                 prp->cfg.in_fmt |
 910                                 prp->cfg.out_fmt |
 911                                 PRP_CNTL_CH2_LEN |
 912                                 PRP_CNTL_CH2_TSKIP(0) |
 913                                 PRP_CNTL_IN_TSKIP(0),
 914                                 pcdev->base_emma + PRP_CNTL);
 915                 }
 916                 spin_unlock_irqrestore(&pcdev->lock, flags);
 917         }
 918
 919         return 0;
 920 }
 921
 922 static int mx2_stop_streaming(struct vb2_queue *q)
 923 {
 924         struct soc_camera_device *icd = soc_camera_from_vb2q(q);
 925         struct soc_camera_host *ici =
 926                 to_soc_camera_host(icd->parent);
 927         struct mx2_camera_dev *pcdev = ici->priv;
 928         struct mx2_fmt_cfg *prp = pcdev->emma_prp;
 929         unsigned long flags;
 930         void *b;
 931         u32 cntl;
 932
 933         if (cpu_is_mx27()) {
 934                 spin_lock_irqsave(&pcdev->lock, flags);
 935
 936                 cntl = readl(pcdev->base_emma + PRP_CNTL);
 937                 if (prp->cfg.channel == 1) {
 938                         writel(cntl & ~PRP_CNTL_CH1EN,
 939                                pcdev->base_emma + PRP_CNTL);
 940                 } else {
 941                         writel(cntl & ~PRP_CNTL_CH2EN,
 942                                pcdev->base_emma + PRP_CNTL);
 943                 }
 944                 INIT_LIST_HEAD(&pcdev->capture);
 945                 INIT_LIST_HEAD(&pcdev->active_bufs);
 946                 INIT_LIST_HEAD(&pcdev->discard);
 947
 948                 b = pcdev->discard_buffer;
 949                 pcdev->discard_buffer = NULL;
 950
 951                 spin_unlock_irqrestore(&pcdev->lock, flags);
 952
 953                 dma_free_coherent(ici->v4l2_dev.dev,
 954                         pcdev->discard_size, b, pcdev->discard_buffer_dma);
 955         }
 956
 957         return 0;
 958 }
 959
 960 static struct vb2_ops mx2_videobuf_ops = {
 961         .queue_setup     = mx2_videobuf_setup,
 962         .buf_prepare     = mx2_videobuf_prepare,
 963         .buf_queue       = mx2_videobuf_queue,
 964         .buf_cleanup     = mx2_videobuf_release,
 965         .start_streaming = mx2_start_streaming,
 966         .stop_streaming  = mx2_stop_streaming,
 967 };
 968
 969 static int mx2_camera_init_videobuf(struct vb2_queue *q,
 970                               struct soc_camera_device *icd)
 971 {
 972         q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
 973         q->io_modes = VB2_MMAP | VB2_USERPTR;
 974         q->drv_priv = icd;
 975         q->ops = &mx2_videobuf_ops;
 976         q->mem_ops = &vb2_dma_contig_memops;
 977         q->buf_struct_size = sizeof(struct mx2_buffer);
 978
 979         return vb2_queue_init(q);
 980 }
 981
 982 #define MX2_BUS_FLAGS   (V4L2_MBUS_MASTER | \
 983                         V4L2_MBUS_VSYNC_ACTIVE_HIGH | \
 984                         V4L2_MBUS_VSYNC_ACTIVE_LOW | \
 985                         V4L2_MBUS_HSYNC_ACTIVE_HIGH | \
 986                         V4L2_MBUS_HSYNC_ACTIVE_LOW | \
 987                         V4L2_MBUS_PCLK_SAMPLE_RISING | \
 988                         V4L2_MBUS_PCLK_SAMPLE_FALLING | \
 989                         V4L2_MBUS_DATA_ACTIVE_HIGH | \
 990                         V4L2_MBUS_DATA_ACTIVE_LOW)
 991
 992 static int mx27_camera_emma_prp_reset(struct mx2_camera_dev *pcdev)
 993 {
 994         u32 cntl;
 995         int count = 0;
 996
 997         cntl = readl(pcdev->base_emma + PRP_CNTL);
 998         writel(PRP_CNTL_SWRST, pcdev->base_emma + PRP_CNTL);
 999         while (count++ < 100) {
1000                 if (!(readl(pcdev->base_emma + PRP_CNTL) & PRP_CNTL_SWRST))
1001                         return 0;
1002                 barrier();
1003                 udelay(1);
1004         }
1005
1006         return -ETIMEDOUT;
1007 }
1008
1009 static int mx2_camera_set_bus_param(struct soc_camera_device *icd)
1010 {
1011         struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1012         struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1013         struct mx2_camera_dev *pcdev = ici->priv;
1014         struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
1015         unsigned long common_flags;
1016         int ret;
1017         int bytesperline;
1018         u32 csicr1 = pcdev->csicr1;
1019
1020         ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg);
1021         if (!ret) {
1022                 common_flags = soc_mbus_config_compatible(&cfg, MX2_BUS_FLAGS);
1023                 if (!common_flags) {
1024                         dev_warn(icd->parent,
1025                                  "Flags incompatible: camera 0x%x, host 0x%x\n",
1026                                  cfg.flags, MX2_BUS_FLAGS);
1027                         return -EINVAL;
1028                 }
1029         } else if (ret != -ENOIOCTLCMD) {
1030                 return ret;
1031         } else {
1032                 common_flags = MX2_BUS_FLAGS;
1033         }
1034
1035         if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) &&
1036             (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) {
1037                 if (pcdev->platform_flags & MX2_CAMERA_HSYNC_HIGH)
1038                         common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW;
1039                 else
1040                         common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH;
1041         }
1042
1043         if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) &&
1044             (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) {
1045                 if (pcdev->platform_flags & MX2_CAMERA_PCLK_SAMPLE_RISING)
1046                         common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING;
1047                 else
1048                         common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING;
1049         }
1050
1051         cfg.flags = common_flags;
1052         ret = v4l2_subdev_call(sd, video, s_mbus_config, &cfg);
1053         if (ret < 0 && ret != -ENOIOCTLCMD) {
1054                 dev_dbg(icd->parent, "camera s_mbus_config(0x%lx) returned %d\n",
1055                         common_flags, ret);
1056                 return ret;
1057         }
1058
1059         csicr1 = (csicr1 & ~CSICR1_FMT_MASK) | pcdev->emma_prp->cfg.csicr1;
1060
1061         if (common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
1062                 csicr1 |= CSICR1_REDGE;
1063         if (common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
1064                 csicr1 |= CSICR1_SOF_POL;
1065         if (common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
1066                 csicr1 |= CSICR1_HSYNC_POL;
1067         if (pcdev->platform_flags & MX2_CAMERA_EXT_VSYNC)
1068                 csicr1 |= CSICR1_EXT_VSYNC;
1069         if (pcdev->platform_flags & MX2_CAMERA_CCIR)
1070                 csicr1 |= CSICR1_CCIR_EN;
1071         if (pcdev->platform_flags & MX2_CAMERA_CCIR_INTERLACE)
1072                 csicr1 |= CSICR1_CCIR_MODE;
1073         if (pcdev->platform_flags & MX2_CAMERA_GATED_CLOCK)
1074                 csicr1 |= CSICR1_GCLK_MODE;
1075         if (pcdev->platform_flags & MX2_CAMERA_INV_DATA)
1076                 csicr1 |= CSICR1_INV_DATA;
1077
1078         pcdev->csicr1 = csicr1;
1079
1080         bytesperline = soc_mbus_bytes_per_line(icd->user_width,
1081                         icd->current_fmt->host_fmt);
1082         if (bytesperline < 0)
1083                 return bytesperline;
1084
1085         if (cpu_is_mx27()) {
1086                 ret = mx27_camera_emma_prp_reset(pcdev);
1087                 if (ret)
1088                         return ret;
1089         } else if (cpu_is_mx25()) {
1090                 writel((bytesperline * icd->user_height) >> 2,
1091                                 pcdev->base_csi + CSIRXCNT);
1092                 writel((bytesperline << 16) | icd->user_height,
1093                                 pcdev->base_csi + CSIIMAG_PARA);
1094         }
1095
1096         writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
1097
1098         return 0;
1099 }
1100
1101 static int mx2_camera_set_crop(struct soc_camera_device *icd,
1102                                 const struct v4l2_crop *a)
1103 {
1104         struct v4l2_crop a_writable = *a;
1105         struct v4l2_rect *rect = &a_writable.c;
1106         struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1107         struct v4l2_mbus_framefmt mf;
1108         int ret;
1109
1110         soc_camera_limit_side(&rect->left, &rect->width, 0, 2, 4096);
1111         soc_camera_limit_side(&rect->top, &rect->height, 0, 2, 4096);
1112
1113         ret = v4l2_subdev_call(sd, video, s_crop, a);
1114         if (ret < 0)
1115                 return ret;
1116
1117         /* The capture device might have changed its output  */
1118         ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf);
1119         if (ret < 0)
1120                 return ret;
1121
1122         dev_dbg(icd->parent, "Sensor cropped %dx%d\n",
1123                 mf.width, mf.height);
1124
1125         icd->user_width         = mf.width;
1126         icd->user_height        = mf.height;
1127
1128         return ret;
1129 }
1130
1131 static int mx2_camera_get_formats(struct soc_camera_device *icd,
1132                                   unsigned int idx,
1133                                   struct soc_camera_format_xlate *xlate)
1134 {
1135         struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1136         const struct soc_mbus_pixelfmt *fmt;
1137         struct device *dev = icd->parent;
1138         enum v4l2_mbus_pixelcode code;
1139         int ret, formats = 0;
1140
1141         ret = v4l2_subdev_call(sd, video, enum_mbus_fmt, idx, &code);
1142         if (ret < 0)
1143                 /* no more formats */
1144                 return 0;
1145
1146         fmt = soc_mbus_get_fmtdesc(code);
1147         if (!fmt) {
1148                 dev_err(dev, "Invalid format code #%u: %d\n", idx, code);
1149                 return 0;
1150         }
1151
1152         if (code == V4L2_MBUS_FMT_YUYV8_2X8 ||
1153             code == V4L2_MBUS_FMT_UYVY8_2X8) {
1154                 formats++;
1155                 if (xlate) {
1156                         /*
1157                          * CH2 can output YUV420 which is a standard format in
1158                          * soc_mediabus.c
1159                          */
1160                         xlate->host_fmt =
1161                                 soc_mbus_get_fmtdesc(V4L2_MBUS_FMT_YUYV8_1_5X8);
1162                         xlate->code     = code;
1163                         dev_dbg(dev, "Providing host format %s for sensor code %d\n",
1164                                xlate->host_fmt->name, code);
1165                         xlate++;
1166                 }
1167         }
1168
1169         if (code == V4L2_MBUS_FMT_UYVY8_2X8) {
1170                 formats++;
1171                 if (xlate) {
1172                         xlate->host_fmt =
1173                                 soc_mbus_get_fmtdesc(V4L2_MBUS_FMT_YUYV8_2X8);
1174                         xlate->code     = code;
1175                         dev_dbg(dev, "Providing host format %s for sensor code %d\n",
1176                                 xlate->host_fmt->name, code);
1177                         xlate++;
1178                 }
1179         }
1180
1181         /* Generic pass-trough */
1182         formats++;
1183         if (xlate) {
1184                 xlate->host_fmt = fmt;
1185                 xlate->code     = code;
1186                 xlate++;
1187         }
1188         return formats;
1189 }
1190
1191 static int mx2_emmaprp_resize(struct mx2_camera_dev *pcdev,
1192                               struct v4l2_mbus_framefmt *mf_in,
1193                               struct v4l2_pix_format *pix_out, bool apply)
1194 {
1195         int num, den;
1196         unsigned long m;
1197         int i, dir;
1198
1199         for (dir = RESIZE_DIR_H; dir <= RESIZE_DIR_V; dir++) {
1200                 struct emma_prp_resize tmprsz;
1201                 unsigned char *s = tmprsz.s;
1202                 int len = 0;
1203                 int in, out;
1204
1205                 if (dir == RESIZE_DIR_H) {
1206                         in = mf_in->width;
1207                         out = pix_out->width;
1208                 } else {
1209                         in = mf_in->height;
1210                         out = pix_out->height;
1211                 }
1212
1213                 if (in < out)
1214                         return -EINVAL;
1215                 else if (in == out)
1216                         continue;
1217
1218                 /* Calculate ratio */
1219                 m = gcd(in, out);
1220                 num = in / m;
1221                 den = out / m;
1222                 if (num > RESIZE_NUM_MAX)
1223                         return -EINVAL;
1224
1225                 if ((num >= 2 * den) && (den == 1) &&
1226                     (num < 9) && (!(num & 0x01))) {
1227                         int sum = 0;
1228                         int j;
1229
1230                         /* Average scaling for >= 2:1 ratios */
1231                         /* Support can be added for num >=9 and odd values */
1232
1233                         tmprsz.algo = RESIZE_ALGO_AVERAGING;
1234                         len = num;
1235
1236                         for (i = 0; i < (len / 2); i++)
1237                                 s[i] = 8;
1238
1239                         do {
1240                                 for (i = 0; i < (len / 2); i++) {
1241                                         s[i] = s[i] >> 1;
1242                                         sum = 0;
1243                                         for (j = 0; j < (len / 2); j++)
1244                                                 sum += s[j];
1245                                         if (sum == 4)
1246                                                 break;
1247                                 }
1248                         } while (sum != 4);
1249
1250                         for (i = (len / 2); i < len; i++)
1251                                 s[i] = s[len - i - 1];
1252
1253                         s[len - 1] |= SZ_COEF;
1254                 } else {
1255                         /* bilinear scaling for < 2:1 ratios */
1256                         int v; /* overflow counter */
1257                         int coeff, nxt; /* table output */
1258                         int in_pos_inc = 2 * den;
1259                         int out_pos = num;
1260                         int out_pos_inc = 2 * num;
1261                         int init_carry = num - den;
1262                         int carry = init_carry;
1263
1264                         tmprsz.algo = RESIZE_ALGO_BILINEAR;
1265                         v = den + in_pos_inc;
1266                         do {
1267                                 coeff = v - out_pos;
1268                                 out_pos += out_pos_inc;
1269                                 carry += out_pos_inc;
1270                                 for (nxt = 0; v < out_pos; nxt++) {
1271                                         v += in_pos_inc;
1272                                         carry -= in_pos_inc;
1273                                 }
1274
1275                                 if (len > RESIZE_NUM_MAX)
1276                                         return -EINVAL;
1277
1278                                 coeff = ((coeff << BC_COEF) +
1279                                         (in_pos_inc >> 1)) / in_pos_inc;
1280
1281                                 if (coeff >= (SZ_COEF - 1))
1282                                         coeff--;
1283
1284                                 coeff |= SZ_COEF;
1285                                 s[len] = (unsigned char)coeff;
1286                                 len++;
1287
1288                                 for (i = 1; i < nxt; i++) {
1289                                         if (len >= RESIZE_NUM_MAX)
1290                                                 return -EINVAL;
1291                                         s[len] = 0;
1292                                         len++;
1293                                 }
1294                         } while (carry != init_carry);
1295                 }
1296                 tmprsz.len = len;
1297                 if (dir == RESIZE_DIR_H)
1298                         mf_in->width = pix_out->width;
1299                 else
1300                         mf_in->height = pix_out->height;
1301
1302                 if (apply)
1303                         memcpy(&pcdev->resizing[dir], &tmprsz, sizeof(tmprsz));
1304         }
1305         return 0;
1306 }
1307
1308 static int mx2_camera_set_fmt(struct soc_camera_device *icd,
1309                                struct v4l2_format *f)
1310 {
1311         struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1312         struct mx2_camera_dev *pcdev = ici->priv;
1313         struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1314         const struct soc_camera_format_xlate *xlate;
1315         struct v4l2_pix_format *pix = &f->fmt.pix;
1316         struct v4l2_mbus_framefmt mf;
1317         int ret;
1318
1319         dev_dbg(icd->parent, "%s: requested params: width = %d, height = %d\n",
1320                 __func__, pix->width, pix->height);
1321
1322         xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
1323         if (!xlate) {
1324                 dev_warn(icd->parent, "Format %x not found\n",
1325                                 pix->pixelformat);
1326                 return -EINVAL;
1327         }
1328
1329         mf.width        = pix->width;
1330         mf.height       = pix->height;
1331         mf.field        = pix->field;
1332         mf.colorspace   = pix->colorspace;
1333         mf.code         = xlate->code;
1334
1335         ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
1336         if (ret < 0 && ret != -ENOIOCTLCMD)
1337                 return ret;
1338
1339         /* Store width and height returned by the sensor for resizing */
1340         pcdev->s_width = mf.width;
1341         pcdev->s_height = mf.height;
1342         dev_dbg(icd->parent, "%s: sensor params: width = %d, height = %d\n",
1343                 __func__, pcdev->s_width, pcdev->s_height);
1344
1345         pcdev->emma_prp = mx27_emma_prp_get_format(xlate->code,
1346                                                    xlate->host_fmt->fourcc);
1347
1348         memset(pcdev->resizing, 0, sizeof(pcdev->resizing));
1349         if ((mf.width != pix->width || mf.height != pix->height) &&
1350                 pcdev->emma_prp->cfg.in_fmt == PRP_CNTL_DATA_IN_YUV422) {
1351                 if (mx2_emmaprp_resize(pcdev, &mf, pix, true) < 0)
1352                         dev_dbg(icd->parent, "%s: can't resize\n", __func__);
1353         }
1354
1355         if (mf.code != xlate->code)
1356                 return -EINVAL;
1357
1358         pix->width              = mf.width;
1359         pix->height             = mf.height;
1360         pix->field              = mf.field;
1361         pix->colorspace         = mf.colorspace;
1362         icd->current_fmt        = xlate;
1363
1364         dev_dbg(icd->parent, "%s: returned params: width = %d, height = %d\n",
1365                 __func__, pix->width, pix->height);
1366
1367         return 0;
1368 }
1369
1370 static int mx2_camera_try_fmt(struct soc_camera_device *icd,
1371                                   struct v4l2_format *f)
1372 {
1373         struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1374         const struct soc_camera_format_xlate *xlate;
1375         struct v4l2_pix_format *pix = &f->fmt.pix;
1376         struct v4l2_mbus_framefmt mf;
1377         __u32 pixfmt = pix->pixelformat;
1378         struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1379         struct mx2_camera_dev *pcdev = ici->priv;
1380         struct mx2_fmt_cfg *emma_prp;
1381         unsigned int width_limit;
1382         int ret;
1383
1384         dev_dbg(icd->parent, "%s: requested params: width = %d, height = %d\n",
1385                 __func__, pix->width, pix->height);
1386
1387         xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1388         if (pixfmt && !xlate) {
1389                 dev_warn(icd->parent, "Format %x not found\n", pixfmt);
1390                 return -EINVAL;
1391         }
1392
1393         /* FIXME: implement MX27 limits */
1394
1395         /* limit to MX25 hardware capabilities */
1396         if (cpu_is_mx25()) {
1397                 if (xlate->host_fmt->bits_per_sample <= 8)
1398                         width_limit = 0xffff * 4;
1399                 else
1400                         width_limit = 0xffff * 2;
1401                 /* CSIIMAG_PARA limit */
1402                 if (pix->width > width_limit)
1403                         pix->width = width_limit;
1404                 if (pix->height > 0xffff)
1405                         pix->height = 0xffff;
1406
1407                 pix->bytesperline = soc_mbus_bytes_per_line(pix->width,
1408                                 xlate->host_fmt);
1409                 if (pix->bytesperline < 0)
1410                         return pix->bytesperline;
1411                 pix->sizeimage = soc_mbus_image_size(xlate->host_fmt,
1412                                                 pix->bytesperline, pix->height);
1413                 /* Check against the CSIRXCNT limit */
1414                 if (pix->sizeimage > 4 * 0x3ffff) {
1415                         /* Adjust geometry, preserve aspect ratio */
1416                         unsigned int new_height = int_sqrt(div_u64(0x3ffffULL *
1417                                         4 * pix->height, pix->bytesperline));
1418                         pix->width = new_height * pix->width / pix->height;
1419                         pix->height = new_height;
1420                         pix->bytesperline = soc_mbus_bytes_per_line(pix->width,
1421                                                         xlate->host_fmt);
1422                         BUG_ON(pix->bytesperline < 0);
1423                         pix->sizeimage = soc_mbus_image_size(xlate->host_fmt,
1424                                                 pix->bytesperline, pix->height);
1425                 }
1426         }
1427
1428         /* limit to sensor capabilities */
1429         mf.width        = pix->width;
1430         mf.height       = pix->height;
1431         mf.field        = pix->field;
1432         mf.colorspace   = pix->colorspace;
1433         mf.code         = xlate->code;
1434
1435         ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf);
1436         if (ret < 0)
1437                 return ret;
1438
1439         dev_dbg(icd->parent, "%s: sensor params: width = %d, height = %d\n",
1440                 __func__, pcdev->s_width, pcdev->s_height);
1441
1442         /* If the sensor does not support image size try PrP resizing */
1443         emma_prp = mx27_emma_prp_get_format(xlate->code,
1444                                                    xlate->host_fmt->fourcc);
1445
1446         if ((mf.width != pix->width || mf.height != pix->height) &&
1447                 emma_prp->cfg.in_fmt == PRP_CNTL_DATA_IN_YUV422) {
1448                 if (mx2_emmaprp_resize(pcdev, &mf, pix, false) < 0)
1449                         dev_dbg(icd->parent, "%s: can't resize\n", __func__);
1450         }
1451
1452         if (mf.field == V4L2_FIELD_ANY)
1453                 mf.field = V4L2_FIELD_NONE;
1454         /*
1455          * Driver supports interlaced images provided they have
1456          * both fields so that they can be processed as if they
1457          * were progressive.
1458          */
1459         if (mf.field != V4L2_FIELD_NONE && !V4L2_FIELD_HAS_BOTH(mf.field)) {
1460                 dev_err(icd->parent, "Field type %d unsupported.\n",
1461                                 mf.field);
1462                 return -EINVAL;
1463         }
1464
1465         pix->width      = mf.width;
1466         pix->height     = mf.height;
1467         pix->field      = mf.field;
1468         pix->colorspace = mf.colorspace;
1469
1470         dev_dbg(icd->parent, "%s: returned params: width = %d, height = %d\n",
1471                 __func__, pix->width, pix->height);
1472
1473         return 0;
1474 }
1475
1476 static int mx2_camera_querycap(struct soc_camera_host *ici,
1477                                struct v4l2_capability *cap)
1478 {
1479         /* cap->name is set by the friendly caller:-> */
1480         strlcpy(cap->card, MX2_CAM_DRIVER_DESCRIPTION, sizeof(cap->card));
1481         cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1482
1483         return 0;
1484 }
1485
1486 static unsigned int mx2_camera_poll(struct file *file, poll_table *pt)
1487 {
1488         struct soc_camera_device *icd = file->private_data;
1489
1490         return vb2_poll(&icd->vb2_vidq, file, pt);
1491 }
1492
1493 static struct soc_camera_host_ops mx2_soc_camera_host_ops = {
1494         .owner          = THIS_MODULE,
1495         .add            = mx2_camera_add_device,
1496         .remove         = mx2_camera_remove_device,
1497         .set_fmt        = mx2_camera_set_fmt,
1498         .set_crop       = mx2_camera_set_crop,
1499         .get_formats    = mx2_camera_get_formats,
1500         .try_fmt        = mx2_camera_try_fmt,
1501         .init_videobuf2 = mx2_camera_init_videobuf,
1502         .poll           = mx2_camera_poll,
1503         .querycap       = mx2_camera_querycap,
1504         .set_bus_param  = mx2_camera_set_bus_param,
1505 };
1506
1507 static void mx27_camera_frame_done_emma(struct mx2_camera_dev *pcdev,
1508                 int bufnum, bool err)
1509 {
1510 #ifdef DEBUG
1511         struct mx2_fmt_cfg *prp = pcdev->emma_prp;
1512 #endif
1513         struct mx2_buf_internal *ibuf;
1514         struct mx2_buffer *buf;
1515         struct vb2_buffer *vb;
1516         unsigned long phys;
1517
1518         ibuf = list_first_entry(&pcdev->active_bufs, struct mx2_buf_internal,
1519                                queue);
1520
1521         BUG_ON(ibuf->bufnum != bufnum);
1522
1523         if (ibuf->discard) {
1524                 /*
1525                  * Discard buffer must not be returned to user space.
1526                  * Just return it to the discard queue.
1527                  */
1528                 list_move_tail(pcdev->active_bufs.next, &pcdev->discard);
1529         } else {
1530                 buf = mx2_ibuf_to_buf(ibuf);
1531
1532                 vb = &buf->vb;
1533 #ifdef DEBUG
1534                 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
1535                 if (prp->cfg.channel == 1) {
1536                         if (readl(pcdev->base_emma + PRP_DEST_RGB1_PTR +
1537                                 4 * bufnum) != phys) {
1538                                 dev_err(pcdev->dev, "%lx != %x\n", phys,
1539                                         readl(pcdev->base_emma +
1540                                         PRP_DEST_RGB1_PTR + 4 * bufnum));
1541                         }
1542                 } else {
1543                         if (readl(pcdev->base_emma + PRP_DEST_Y_PTR -
1544                                 0x14 * bufnum) != phys) {
1545                                 dev_err(pcdev->dev, "%lx != %x\n", phys,
1546                                         readl(pcdev->base_emma +
1547                                         PRP_DEST_Y_PTR - 0x14 * bufnum));
1548                         }
1549                 }
1550 #endif
1551                 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%p %lu\n", __func__, vb,
1552                                 vb2_plane_vaddr(vb, 0),
1553                                 vb2_get_plane_payload(vb, 0));
1554
1555                 list_del_init(&buf->internal.queue);
1556                 do_gettimeofday(&vb->v4l2_buf.timestamp);
1557                 vb->v4l2_buf.sequence = pcdev->frame_count;
1558                 if (err)
1559                         vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
1560                 else
1561                         vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
1562         }
1563
1564         pcdev->frame_count++;
1565
1566         if (list_empty(&pcdev->capture)) {
1567                 if (list_empty(&pcdev->discard)) {
1568                         dev_warn(pcdev->dev, "%s: trying to access empty discard list\n",
1569                                  __func__);
1570                         return;
1571                 }
1572
1573                 ibuf = list_first_entry(&pcdev->discard,
1574                                         struct mx2_buf_internal, queue);
1575                 ibuf->bufnum = bufnum;
1576
1577                 list_move_tail(pcdev->discard.next, &pcdev->active_bufs);
1578                 mx27_update_emma_buf(pcdev, pcdev->discard_buffer_dma, bufnum);
1579                 return;
1580         }
1581
1582         buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
1583                                internal.queue);
1584
1585         buf->internal.bufnum = bufnum;
1586
1587         list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
1588
1589         vb = &buf->vb;
1590         buf->state = MX2_STATE_ACTIVE;
1591
1592         phys = vb2_dma_contig_plane_dma_addr(vb, 0);
1593         mx27_update_emma_buf(pcdev, phys, bufnum);
1594 }
1595
1596 static irqreturn_t mx27_camera_emma_irq(int irq_emma, void *data)
1597 {
1598         struct mx2_camera_dev *pcdev = data;
1599         unsigned int status = readl(pcdev->base_emma + PRP_INTRSTATUS);
1600         struct mx2_buf_internal *ibuf;
1601
1602         spin_lock(&pcdev->lock);
1603
1604         if (list_empty(&pcdev->active_bufs)) {
1605                 dev_warn(pcdev->dev, "%s: called while active list is empty\n",
1606                         __func__);
1607
1608                 if (!status) {
1609                         spin_unlock(&pcdev->lock);
1610                         return IRQ_NONE;
1611                 }
1612         }
1613
1614         if (status & (1 << 7)) { /* overflow */
1615                 u32 cntl = readl(pcdev->base_emma + PRP_CNTL);
1616                 writel(cntl & ~(PRP_CNTL_CH1EN | PRP_CNTL_CH2EN),
1617                        pcdev->base_emma + PRP_CNTL);
1618                 writel(cntl, pcdev->base_emma + PRP_CNTL);
1619
1620                 ibuf = list_first_entry(&pcdev->active_bufs,
1621                                         struct mx2_buf_internal, queue);
1622                 mx27_camera_frame_done_emma(pcdev,
1623                                         ibuf->bufnum, true);
1624
1625                 status &= ~(1 << 7);
1626         } else if (((status & (3 << 5)) == (3 << 5)) ||
1627                 ((status & (3 << 3)) == (3 << 3))) {
1628                 /*
1629                  * Both buffers have triggered, process the one we're expecting
1630                  * to first
1631                  */
1632                 ibuf = list_first_entry(&pcdev->active_bufs,
1633                                         struct mx2_buf_internal, queue);
1634                 mx27_camera_frame_done_emma(pcdev, ibuf->bufnum, false);
1635                 status &= ~(1 << (6 - ibuf->bufnum)); /* mark processed */
1636         } else if ((status & (1 << 6)) || (status & (1 << 4))) {
1637                 mx27_camera_frame_done_emma(pcdev, 0, false);
1638         } else if ((status & (1 << 5)) || (status & (1 << 3))) {
1639                 mx27_camera_frame_done_emma(pcdev, 1, false);
1640         }
1641
1642         spin_unlock(&pcdev->lock);
1643         writel(status, pcdev->base_emma + PRP_INTRSTATUS);
1644
1645         return IRQ_HANDLED;
1646 }
1647
1648 static int __devinit mx27_camera_emma_init(struct platform_device *pdev)
1649 {
1650         struct mx2_camera_dev *pcdev = platform_get_drvdata(pdev);
1651         struct resource *res_emma;
1652         int irq_emma;
1653         int err = 0;
1654
1655         res_emma = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1656         irq_emma = platform_get_irq(pdev, 1);
1657         if (!res_emma || !irq_emma) {
1658                 dev_err(pcdev->dev, "no EMMA resources\n");
1659                 err = -ENODEV;
1660                 goto out;
1661         }
1662
1663         pcdev->base_emma = devm_request_and_ioremap(pcdev->dev, res_emma);
1664         if (!pcdev->base_emma) {
1665                 err = -EADDRNOTAVAIL;
1666                 goto out;
1667         }
1668
1669         err = devm_request_irq(pcdev->dev, irq_emma, mx27_camera_emma_irq, 0,
1670                                MX2_CAM_DRV_NAME, pcdev);
1671         if (err) {
1672                 dev_err(pcdev->dev, "Camera EMMA interrupt register failed \n");
1673                 goto out;
1674         }
1675
1676         pcdev->clk_emma_ipg = devm_clk_get(pcdev->dev, "emma-ipg");
1677         if (IS_ERR(pcdev->clk_emma_ipg)) {
1678                 err = PTR_ERR(pcdev->clk_emma_ipg);
1679                 goto out;
1680         }
1681
1682         clk_prepare_enable(pcdev->clk_emma_ipg);
1683
1684         pcdev->clk_emma_ahb = devm_clk_get(pcdev->dev, "emma-ahb");
1685         if (IS_ERR(pcdev->clk_emma_ahb)) {
1686                 err = PTR_ERR(pcdev->clk_emma_ahb);
1687                 goto exit_clk_emma_ipg;
1688         }
1689
1690         clk_prepare_enable(pcdev->clk_emma_ahb);
1691
1692         err = mx27_camera_emma_prp_reset(pcdev);
1693         if (err)
1694                 goto exit_clk_emma_ahb;
1695
1696         return err;
1697
1698 exit_clk_emma_ahb:
1699         clk_disable_unprepare(pcdev->clk_emma_ahb);
1700 exit_clk_emma_ipg:
1701         clk_disable_unprepare(pcdev->clk_emma_ipg);
1702 out:
1703         return err;
1704 }
1705
1706 static int __devinit mx2_camera_probe(struct platform_device *pdev)
1707 {
1708         struct mx2_camera_dev *pcdev;
1709         struct resource *res_csi;
1710         int irq_csi;
1711         int err = 0;
1712
1713         dev_dbg(&pdev->dev, "initialising\n");
1714
1715         res_csi = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1716         irq_csi = platform_get_irq(pdev, 0);
1717         if (res_csi == NULL || irq_csi < 0) {
1718                 dev_err(&pdev->dev, "Missing platform resources data\n");
1719                 err = -ENODEV;
1720                 goto exit;
1721         }
1722
1723         pcdev = devm_kzalloc(&pdev->dev, sizeof(*pcdev), GFP_KERNEL);
1724         if (!pcdev) {
1725                 dev_err(&pdev->dev, "Could not allocate pcdev\n");
1726                 err = -ENOMEM;
1727                 goto exit;
1728         }
1729
1730         pcdev->clk_csi = devm_clk_get(&pdev->dev, "ahb");
1731         if (IS_ERR(pcdev->clk_csi)) {
1732                 dev_err(&pdev->dev, "Could not get csi clock\n");
1733                 err = PTR_ERR(pcdev->clk_csi);
1734                 goto exit;
1735         }
1736
1737         pcdev->pdata = pdev->dev.platform_data;
1738         if (pcdev->pdata) {
1739                 long rate;
1740
1741                 pcdev->platform_flags = pcdev->pdata->flags;
1742
1743                 rate = clk_round_rate(pcdev->clk_csi, pcdev->pdata->clk * 2);
1744                 if (rate <= 0) {
1745                         err = -ENODEV;
1746                         goto exit;
1747                 }
1748                 err = clk_set_rate(pcdev->clk_csi, rate);
1749                 if (err < 0)
1750                         goto exit;
1751         }
1752
1753         INIT_LIST_HEAD(&pcdev->capture);
1754         INIT_LIST_HEAD(&pcdev->active_bufs);
1755         INIT_LIST_HEAD(&pcdev->discard);
1756         spin_lock_init(&pcdev->lock);
1757
1758         pcdev->base_csi = devm_request_and_ioremap(&pdev->dev, res_csi);
1759         if (!pcdev->base_csi) {
1760                 err = -EADDRNOTAVAIL;
1761                 goto exit;
1762         }
1763
1764         pcdev->dev = &pdev->dev;
1765         platform_set_drvdata(pdev, pcdev);
1766
1767         if (cpu_is_mx25()) {
1768                 err = devm_request_irq(&pdev->dev, irq_csi, mx25_camera_irq, 0,
1769                                        MX2_CAM_DRV_NAME, pcdev);
1770                 if (err) {
1771                         dev_err(pcdev->dev, "Camera interrupt register failed \n");
1772                         goto exit;
1773                 }
1774         }
1775
1776         if (cpu_is_mx27()) {
1777                 err = mx27_camera_emma_init(pdev);
1778                 if (err)
1779                         goto exit;
1780         }
1781
1782         /*
1783          * We're done with drvdata here.  Clear the pointer so that
1784          * v4l2 core can start using drvdata on its purpose.
1785          */
1786         platform_set_drvdata(pdev, NULL);
1787
1788         pcdev->soc_host.drv_name        = MX2_CAM_DRV_NAME,
1789         pcdev->soc_host.ops             = &mx2_soc_camera_host_ops,
1790         pcdev->soc_host.priv            = pcdev;
1791         pcdev->soc_host.v4l2_dev.dev    = &pdev->dev;
1792         pcdev->soc_host.nr              = pdev->id;
1793         if (cpu_is_mx25())
1794                 pcdev->soc_host.capabilities = SOCAM_HOST_CAP_STRIDE;
1795
1796         pcdev->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
1797         if (IS_ERR(pcdev->alloc_ctx)) {
1798                 err = PTR_ERR(pcdev->alloc_ctx);
1799                 goto eallocctx;
1800         }
1801         err = soc_camera_host_register(&pcdev->soc_host);
1802         if (err)
1803                 goto exit_free_emma;
1804
1805         dev_info(&pdev->dev, "MX2 Camera (CSI) driver probed, clock frequency: %ld\n",
1806                         clk_get_rate(pcdev->clk_csi));
1807
1808         return 0;
1809
1810 exit_free_emma:
1811         vb2_dma_contig_cleanup_ctx(pcdev->alloc_ctx);
1812 eallocctx:
1813         if (cpu_is_mx27()) {
1814                 clk_disable_unprepare(pcdev->clk_emma_ipg);
1815                 clk_disable_unprepare(pcdev->clk_emma_ahb);
1816         }
1817 exit:
1818         return err;
1819 }
1820
1821 static int __devexit mx2_camera_remove(struct platform_device *pdev)
1822 {
1823         struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
1824         struct mx2_camera_dev *pcdev = container_of(soc_host,
1825                         struct mx2_camera_dev, soc_host);
1826
1827         soc_camera_host_unregister(&pcdev->soc_host);
1828
1829         vb2_dma_contig_cleanup_ctx(pcdev->alloc_ctx);
1830
1831         if (cpu_is_mx27()) {
1832                 clk_disable_unprepare(pcdev->clk_emma_ipg);
1833                 clk_disable_unprepare(pcdev->clk_emma_ahb);
1834         }
1835
1836         dev_info(&pdev->dev, "MX2 Camera driver unloaded\n");
1837
1838         return 0;
1839 }
1840
1841 static struct platform_driver mx2_camera_driver = {
1842         .driver         = {
1843                 .name   = MX2_CAM_DRV_NAME,
1844         },
1845         .remove         = __devexit_p(mx2_camera_remove),
1846 };
1847
1848
1849 static int __init mx2_camera_init(void)
1850 {
1851         return platform_driver_probe(&mx2_camera_driver, &mx2_camera_probe);
1852 }
1853
1854 static void __exit mx2_camera_exit(void)
1855 {
1856         return platform_driver_unregister(&mx2_camera_driver);
1857 }
1858
1859 module_init(mx2_camera_init);
1860 module_exit(mx2_camera_exit);
1861
1862 MODULE_DESCRIPTION("i.MX27/i.MX25 SoC Camera Host driver");
1863 MODULE_AUTHOR("Sascha Hauer <sha@pengutronix.de>");
1864 MODULE_LICENSE("GPL");
1865 MODULE_VERSION(MX2_CAM_VERSION);