drivers/media/i2c/ths8200.c

   1 /*
   2  * ths8200 - Texas Instruments THS8200 video encoder driver
   3  *
   4  * Copyright 2013 Cisco Systems, Inc. and/or its affiliates.
   5  *
   6  * This program is free software; you may redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation version 2.
  13  *
  14  * This program is distributed .as is. WITHOUT ANY WARRANTY of any
  15  * kind, whether express or implied; without even the implied warranty
  16  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  */
  19
  20 #include <linux/i2c.h>
  21 #include <linux/module.h>
  22 #include <linux/v4l2-dv-timings.h>
  23
  24 #include <media/v4l2-dv-timings.h>
  25 #include <media/v4l2-async.h>
  26 #include <media/v4l2-device.h>
  27
  28 #include "ths8200_regs.h"
  29
  30 static int debug;
  31 module_param(debug, int, 0644);
  32 MODULE_PARM_DESC(debug, "debug level (0-2)");
  33
  34 MODULE_DESCRIPTION("Texas Instruments THS8200 video encoder driver");
  35 MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
  36 MODULE_AUTHOR("Martin Bugge <martin.bugge@cisco.com>");
  37 MODULE_LICENSE("GPL v2");
  38
  39 struct ths8200_state {
  40         struct v4l2_subdev sd;
  41         uint8_t chip_version;
  42         /* Is the ths8200 powered on? */
  43         bool power_on;
  44         struct v4l2_dv_timings dv_timings;
  45 };
  46
  47 static const struct v4l2_dv_timings ths8200_timings[] = {
  48         V4L2_DV_BT_CEA_720X480P59_94,
  49         V4L2_DV_BT_CEA_1280X720P24,
  50         V4L2_DV_BT_CEA_1280X720P25,
  51         V4L2_DV_BT_CEA_1280X720P30,
  52         V4L2_DV_BT_CEA_1280X720P50,
  53         V4L2_DV_BT_CEA_1280X720P60,
  54         V4L2_DV_BT_CEA_1920X1080P24,
  55         V4L2_DV_BT_CEA_1920X1080P25,
  56         V4L2_DV_BT_CEA_1920X1080P30,
  57         V4L2_DV_BT_CEA_1920X1080P50,
  58         V4L2_DV_BT_CEA_1920X1080P60,
  59 };
  60
  61 static inline struct ths8200_state *to_state(struct v4l2_subdev *sd)
  62 {
  63         return container_of(sd, struct ths8200_state, sd);
  64 }
  65
  66 static inline unsigned hblanking(const struct v4l2_bt_timings *t)
  67 {
  68         return V4L2_DV_BT_BLANKING_WIDTH(t);
  69 }
  70
  71 static inline unsigned htotal(const struct v4l2_bt_timings *t)
  72 {
  73         return V4L2_DV_BT_FRAME_WIDTH(t);
  74 }
  75
  76 static inline unsigned vblanking(const struct v4l2_bt_timings *t)
  77 {
  78         return V4L2_DV_BT_BLANKING_HEIGHT(t);
  79 }
  80
  81 static inline unsigned vtotal(const struct v4l2_bt_timings *t)
  82 {
  83         return V4L2_DV_BT_FRAME_HEIGHT(t);
  84 }
  85
  86 static int ths8200_read(struct v4l2_subdev *sd, u8 reg)
  87 {
  88         struct i2c_client *client = v4l2_get_subdevdata(sd);
  89
  90         return i2c_smbus_read_byte_data(client, reg);
  91 }
  92
  93 static int ths8200_write(struct v4l2_subdev *sd, u8 reg, u8 val)
  94 {
  95         struct i2c_client *client = v4l2_get_subdevdata(sd);
  96         int ret;
  97         int i;
  98
  99         for (i = 0; i < 3; i++) {
 100                 ret = i2c_smbus_write_byte_data(client, reg, val);
 101                 if (ret == 0)
 102                         return 0;
 103         }
 104         v4l2_err(sd, "I2C Write Problem\n");
 105         return ret;
 106 }
 107
 108 /* To set specific bits in the register, a clear-mask is given (to be AND-ed),
 109  * and then the value-mask (to be OR-ed).
 110  */
 111 static inline void
 112 ths8200_write_and_or(struct v4l2_subdev *sd, u8 reg,
 113                      uint8_t clr_mask, uint8_t val_mask)
 114 {
 115         ths8200_write(sd, reg, (ths8200_read(sd, reg) & clr_mask) | val_mask);
 116 }
 117
 118 #ifdef CONFIG_VIDEO_ADV_DEBUG
 119
 120 static int ths8200_g_register(struct v4l2_subdev *sd,
 121                               struct v4l2_dbg_register *reg)
 122 {
 123         reg->val = ths8200_read(sd, reg->reg & 0xff);
 124         reg->size = 1;
 125
 126         return 0;
 127 }
 128
 129 static int ths8200_s_register(struct v4l2_subdev *sd,
 130                               const struct v4l2_dbg_register *reg)
 131 {
 132         ths8200_write(sd, reg->reg & 0xff, reg->val & 0xff);
 133
 134         return 0;
 135 }
 136 #endif
 137
 138 static void ths8200_print_timings(struct v4l2_subdev *sd,
 139                                   struct v4l2_dv_timings *timings,
 140                                   const char *txt, bool detailed)
 141 {
 142         struct v4l2_bt_timings *bt = &timings->bt;
 143         u32 htot, vtot;
 144
 145         if (timings->type != V4L2_DV_BT_656_1120)
 146                 return;
 147
 148         htot = htotal(bt);
 149         vtot = vtotal(bt);
 150
 151         v4l2_info(sd, "%s %dx%d%s%d (%dx%d)",
 152                   txt, bt->width, bt->height, bt->interlaced ? "i" : "p",
 153                   (htot * vtot) > 0 ? ((u32)bt->pixelclock / (htot * vtot)) : 0,
 154                   htot, vtot);
 155
 156         if (detailed) {
 157                 v4l2_info(sd, "    horizontal: fp = %d, %ssync = %d, bp = %d\n",
 158                           bt->hfrontporch,
 159                           (bt->polarities & V4L2_DV_HSYNC_POS_POL) ? "+" : "-",
 160                           bt->hsync, bt->hbackporch);
 161                 v4l2_info(sd, "    vertical: fp = %d, %ssync = %d, bp = %d\n",
 162                           bt->vfrontporch,
 163                           (bt->polarities & V4L2_DV_VSYNC_POS_POL) ? "+" : "-",
 164                           bt->vsync, bt->vbackporch);
 165                 v4l2_info(sd,
 166                           "    pixelclock: %lld, flags: 0x%x, standards: 0x%x\n",
 167                           bt->pixelclock, bt->flags, bt->standards);
 168         }
 169 }
 170
 171 static int ths8200_log_status(struct v4l2_subdev *sd)
 172 {
 173         struct ths8200_state *state = to_state(sd);
 174         uint8_t reg_03 = ths8200_read(sd, THS8200_CHIP_CTL);
 175
 176         v4l2_info(sd, "----- Chip status -----\n");
 177         v4l2_info(sd, "version: %u\n", state->chip_version);
 178         v4l2_info(sd, "power: %s\n", (reg_03 & 0x0c) ? "off" : "on");
 179         v4l2_info(sd, "reset: %s\n", (reg_03 & 0x01) ? "off" : "on");
 180         v4l2_info(sd, "test pattern: %s\n",
 181                   (reg_03 & 0x20) ? "enabled" : "disabled");
 182         v4l2_info(sd, "format: %ux%u\n",
 183                   ths8200_read(sd, THS8200_DTG2_PIXEL_CNT_MSB) * 256 +
 184                   ths8200_read(sd, THS8200_DTG2_PIXEL_CNT_LSB),
 185                   (ths8200_read(sd, THS8200_DTG2_LINE_CNT_MSB) & 0x07) * 256 +
 186                   ths8200_read(sd, THS8200_DTG2_LINE_CNT_LSB));
 187         ths8200_print_timings(sd, &state->dv_timings,
 188                               "Configured format:", true);
 189
 190         return 0;
 191 }
 192
 193 /* Power up/down ths8200 */
 194 static int ths8200_s_power(struct v4l2_subdev *sd, int on)
 195 {
 196         struct ths8200_state *state = to_state(sd);
 197
 198         v4l2_dbg(1, debug, sd, "%s: power %s\n", __func__, on ? "on" : "off");
 199
 200         state->power_on = on;
 201
 202         /* Power up/down - leave in reset state until input video is present */
 203         ths8200_write_and_or(sd, THS8200_CHIP_CTL, 0xf2, (on ? 0x00 : 0x0c));
 204
 205         return 0;
 206 }
 207
 208 static const struct v4l2_subdev_core_ops ths8200_core_ops = {
 209         .log_status = ths8200_log_status,
 210         .s_power = ths8200_s_power,
 211 #ifdef CONFIG_VIDEO_ADV_DEBUG
 212         .g_register = ths8200_g_register,
 213         .s_register = ths8200_s_register,
 214 #endif
 215 };
 216
 217 /* -----------------------------------------------------------------------------
 218  * V4L2 subdev video operations
 219  */
 220
 221 static int ths8200_s_stream(struct v4l2_subdev *sd, int enable)
 222 {
 223         struct ths8200_state *state = to_state(sd);
 224
 225         if (enable && !state->power_on)
 226                 ths8200_s_power(sd, true);
 227
 228         ths8200_write_and_or(sd, THS8200_CHIP_CTL, 0xfe,
 229                              (enable ? 0x01 : 0x00));
 230
 231         v4l2_dbg(1, debug, sd, "%s: %sable\n",
 232                  __func__, (enable ? "en" : "dis"));
 233
 234         return 0;
 235 }
 236
 237 static void ths8200_core_init(struct v4l2_subdev *sd)
 238 {
 239         /* setup clocks */
 240         ths8200_write_and_or(sd, THS8200_CHIP_CTL, 0x3f, 0xc0);
 241
 242         /**** Data path control (DATA) ****/
 243         /* Set FSADJ 700 mV,
 244          * bypass 422-444 interpolation,
 245          * input format 30 bit RGB444
 246          */
 247         ths8200_write(sd, THS8200_DATA_CNTL, 0x70);
 248
 249         /* DTG Mode (Video blocked during blanking
 250          * VESA slave
 251          */
 252         ths8200_write(sd, THS8200_DTG1_MODE, 0x87);
 253
 254         /**** Display Timing Generator Control, Part 1 (DTG1). ****/
 255
 256         /* Disable embedded syncs on the output by setting
 257          * the amplitude to zero for all channels.
 258          */
 259         ths8200_write(sd, THS8200_DTG1_Y_SYNC_MSB, 0x2a);
 260         ths8200_write(sd, THS8200_DTG1_CBCR_SYNC_MSB, 0x2a);
 261 }
 262
 263 static void ths8200_setup(struct v4l2_subdev *sd, struct v4l2_bt_timings *bt)
 264 {
 265         uint8_t polarity = 0;
 266         uint16_t line_start_active_video = (bt->vsync + bt->vbackporch);
 267         uint16_t line_start_front_porch  = (vtotal(bt) - bt->vfrontporch);
 268
 269         /*** System ****/
 270         /* Set chip in reset while it is configured */
 271         ths8200_s_stream(sd, false);
 272
 273         /* configure video output timings */
 274         ths8200_write(sd, THS8200_DTG1_SPEC_A, bt->hsync);
 275         ths8200_write(sd, THS8200_DTG1_SPEC_B, bt->hfrontporch);
 276
 277         /* Zero for progressive scan formats.*/
 278         if (!bt->interlaced)
 279                 ths8200_write(sd, THS8200_DTG1_SPEC_C, 0x00);
 280
 281         /* Distance from leading edge of h sync to start of active video.
 282          * MSB in 0x2b
 283          */
 284         ths8200_write(sd, THS8200_DTG1_SPEC_D_LSB,
 285                       (bt->hbackporch + bt->hsync) & 0xff);
 286         /* Zero for SDTV-mode. MSB in 0x2b */
 287         ths8200_write(sd, THS8200_DTG1_SPEC_E_LSB, 0x00);
 288         /*
 289          * MSB for dtg1_spec(d/e/h). See comment for
 290          * corresponding LSB registers.
 291          */
 292         ths8200_write(sd, THS8200_DTG1_SPEC_DEH_MSB,
 293                       ((bt->hbackporch + bt->hsync) & 0x100) >> 1);
 294
 295         /* h front porch */
 296         ths8200_write(sd, THS8200_DTG1_SPEC_K_LSB, (bt->hfrontporch) & 0xff);
 297         ths8200_write(sd, THS8200_DTG1_SPEC_K_MSB,
 298                       ((bt->hfrontporch) & 0x700) >> 8);
 299
 300         /* Half the line length. Used to calculate SDTV line types. */
 301         ths8200_write(sd, THS8200_DTG1_SPEC_G_LSB, (htotal(bt)/2) & 0xff);
 302         ths8200_write(sd, THS8200_DTG1_SPEC_G_MSB,
 303                       ((htotal(bt)/2) >> 8) & 0x0f);
 304
 305         /* Total pixels per line (ex. 720p: 1650) */
 306         ths8200_write(sd, THS8200_DTG1_TOT_PIXELS_MSB, htotal(bt) >> 8);
 307         ths8200_write(sd, THS8200_DTG1_TOT_PIXELS_LSB, htotal(bt) & 0xff);
 308
 309         /* Frame height and field height */
 310         /* Field height should be programmed higher than frame_size for
 311          * progressive scan formats
 312          */
 313         ths8200_write(sd, THS8200_DTG1_FRAME_FIELD_SZ_MSB,
 314                       ((vtotal(bt) >> 4) & 0xf0) + 0x7);
 315         ths8200_write(sd, THS8200_DTG1_FRAME_SZ_LSB, vtotal(bt) & 0xff);
 316
 317         /* Should be programmed higher than frame_size
 318          * for progressive formats
 319          */
 320         if (!bt->interlaced)
 321                 ths8200_write(sd, THS8200_DTG1_FIELD_SZ_LSB, 0xff);
 322
 323         /**** Display Timing Generator Control, Part 2 (DTG2). ****/
 324         /* Set breakpoint line numbers and types
 325          * THS8200 generates line types with different properties. A line type
 326          * that sets all the RGB-outputs to zero is used in the blanking areas,
 327          * while a line type that enable the RGB-outputs is used in active video
 328          * area. The line numbers for start of active video, start of front
 329          * porch and after the last line in the frame must be set with the
 330          * corresponding line types.
 331          *
 332          * Line types:
 333          * 0x9 - Full normal sync pulse: Blocks data when dtg1_pass is off.
 334          *       Used in blanking area.
 335          * 0x0 - Active video: Video data is always passed. Used in active
 336          *       video area.
 337          */
 338         ths8200_write_and_or(sd, THS8200_DTG2_BP1_2_MSB, 0x88,
 339                              ((line_start_active_video >> 4) & 0x70) +
 340                              ((line_start_front_porch >> 8) & 0x07));
 341         ths8200_write(sd, THS8200_DTG2_BP3_4_MSB, ((vtotal(bt)) >> 4) & 0x70);
 342         ths8200_write(sd, THS8200_DTG2_BP1_LSB, line_start_active_video & 0xff);
 343         ths8200_write(sd, THS8200_DTG2_BP2_LSB, line_start_front_porch & 0xff);
 344         ths8200_write(sd, THS8200_DTG2_BP3_LSB, (vtotal(bt)) & 0xff);
 345
 346         /* line types */
 347         ths8200_write(sd, THS8200_DTG2_LINETYPE1, 0x90);
 348         ths8200_write(sd, THS8200_DTG2_LINETYPE2, 0x90);
 349
 350         /* h sync width transmitted */
 351         ths8200_write(sd, THS8200_DTG2_HLENGTH_LSB, bt->hsync & 0xff);
 352         ths8200_write_and_or(sd, THS8200_DTG2_HLENGTH_LSB_HDLY_MSB, 0x3f,
 353                              (bt->hsync >> 2) & 0xc0);
 354
 355         /* The pixel value h sync is asserted on */
 356         ths8200_write_and_or(sd, THS8200_DTG2_HLENGTH_LSB_HDLY_MSB, 0xe0,
 357                              (htotal(bt) >> 8) & 0x1f);
 358         ths8200_write(sd, THS8200_DTG2_HLENGTH_HDLY_LSB, htotal(bt));
 359
 360         /* v sync width transmitted */
 361         ths8200_write(sd, THS8200_DTG2_VLENGTH1_LSB, (bt->vsync) & 0xff);
 362         ths8200_write_and_or(sd, THS8200_DTG2_VLENGTH1_MSB_VDLY1_MSB, 0x3f,
 363                              ((bt->vsync) >> 2) & 0xc0);
 364
 365         /* The pixel value v sync is asserted on */
 366         ths8200_write_and_or(sd, THS8200_DTG2_VLENGTH1_MSB_VDLY1_MSB, 0xf8,
 367                              (vtotal(bt)>>8) & 0x7);
 368         ths8200_write(sd, THS8200_DTG2_VDLY1_LSB, vtotal(bt));
 369
 370         /* For progressive video vlength2 must be set to all 0 and vdly2 must
 371          * be set to all 1.
 372          */
 373         ths8200_write(sd, THS8200_DTG2_VLENGTH2_LSB, 0x00);
 374         ths8200_write(sd, THS8200_DTG2_VLENGTH2_MSB_VDLY2_MSB, 0x07);
 375         ths8200_write(sd, THS8200_DTG2_VDLY2_LSB, 0xff);
 376
 377         /* Internal delay factors to synchronize the sync pulses and the data */
 378         /* Experimental values delays (hor 4, ver 1) */
 379         ths8200_write(sd, THS8200_DTG2_HS_IN_DLY_MSB, (htotal(bt)>>8) & 0x1f);
 380         ths8200_write(sd, THS8200_DTG2_HS_IN_DLY_LSB, (htotal(bt) - 4) & 0xff);
 381         ths8200_write(sd, THS8200_DTG2_VS_IN_DLY_MSB, 0);
 382         ths8200_write(sd, THS8200_DTG2_VS_IN_DLY_LSB, 1);
 383
 384         /* Polarity of received and transmitted sync signals */
 385         if (bt->polarities & V4L2_DV_HSYNC_POS_POL) {
 386                 polarity |= 0x01; /* HS_IN */
 387                 polarity |= 0x08; /* HS_OUT */
 388         }
 389         if (bt->polarities & V4L2_DV_VSYNC_POS_POL) {
 390                 polarity |= 0x02; /* VS_IN */
 391                 polarity |= 0x10; /* VS_OUT */
 392         }
 393
 394         /* RGB mode, no embedded timings */
 395         /* Timing of video input bus is derived from HS, VS, and FID dedicated
 396          * inputs
 397          */
 398         ths8200_write(sd, THS8200_DTG2_CNTL, 0x47 | polarity);
 399
 400         /* leave reset */
 401         ths8200_s_stream(sd, true);
 402
 403         v4l2_dbg(1, debug, sd, "%s: frame %dx%d, polarity %d\n"
 404                  "horizontal: front porch %d, back porch %d, sync %d\n"
 405                  "vertical: sync %d\n", __func__, htotal(bt), vtotal(bt),
 406                  polarity, bt->hfrontporch, bt->hbackporch,
 407                  bt->hsync, bt->vsync);
 408 }
 409
 410 static int ths8200_s_dv_timings(struct v4l2_subdev *sd,
 411                                 struct v4l2_dv_timings *timings)
 412 {
 413         struct ths8200_state *state = to_state(sd);
 414         int i;
 415
 416         v4l2_dbg(1, debug, sd, "%s:\n", __func__);
 417
 418         if (timings->type != V4L2_DV_BT_656_1120)
 419                 return -EINVAL;
 420
 421         /* TODO Support interlaced formats */
 422         if (timings->bt.interlaced) {
 423                 v4l2_dbg(1, debug, sd, "TODO Support interlaced formats\n");
 424                 return -EINVAL;
 425         }
 426
 427         for (i = 0; i < ARRAY_SIZE(ths8200_timings); i++) {
 428                 if (v4l_match_dv_timings(&ths8200_timings[i], timings, 10))
 429                         break;
 430         }
 431
 432         if (i == ARRAY_SIZE(ths8200_timings)) {
 433                 v4l2_dbg(1, debug, sd, "Unsupported format\n");
 434                 return -EINVAL;
 435         }
 436
 437         timings->bt.flags &= ~V4L2_DV_FL_REDUCED_FPS;
 438
 439         /* save timings */
 440         state->dv_timings = *timings;
 441
 442         ths8200_setup(sd, &timings->bt);
 443
 444         return 0;
 445 }
 446
 447 static int ths8200_g_dv_timings(struct v4l2_subdev *sd,
 448                                 struct v4l2_dv_timings *timings)
 449 {
 450         struct ths8200_state *state = to_state(sd);
 451
 452         v4l2_dbg(1, debug, sd, "%s:\n", __func__);
 453
 454         *timings = state->dv_timings;
 455
 456         return 0;
 457 }
 458
 459 static int ths8200_enum_dv_timings(struct v4l2_subdev *sd,
 460                                    struct v4l2_enum_dv_timings *timings)
 461 {
 462         /* Check requested format index is within range */
 463         if (timings->index >= ARRAY_SIZE(ths8200_timings))
 464                 return -EINVAL;
 465
 466         timings->timings = ths8200_timings[timings->index];
 467
 468         return 0;
 469 }
 470
 471 static int ths8200_dv_timings_cap(struct v4l2_subdev *sd,
 472                                   struct v4l2_dv_timings_cap *cap)
 473 {
 474         cap->type = V4L2_DV_BT_656_1120;
 475         cap->bt.max_width = 1920;
 476         cap->bt.max_height = 1080;
 477         cap->bt.min_pixelclock = 27000000;
 478         cap->bt.max_pixelclock = 148500000;
 479         cap->bt.standards = V4L2_DV_BT_STD_CEA861;
 480         cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE;
 481
 482         return 0;
 483 }
 484
 485 /* Specific video subsystem operation handlers */
 486 static const struct v4l2_subdev_video_ops ths8200_video_ops = {
 487         .s_stream = ths8200_s_stream,
 488         .s_dv_timings = ths8200_s_dv_timings,
 489         .g_dv_timings = ths8200_g_dv_timings,
 490         .enum_dv_timings = ths8200_enum_dv_timings,
 491         .dv_timings_cap = ths8200_dv_timings_cap,
 492 };
 493
 494 /* V4L2 top level operation handlers */
 495 static const struct v4l2_subdev_ops ths8200_ops = {
 496         .core  = &ths8200_core_ops,
 497         .video = &ths8200_video_ops,
 498 };
 499
 500 static int ths8200_probe(struct i2c_client *client,
 501                          const struct i2c_device_id *id)
 502 {
 503         struct ths8200_state *state;
 504         struct v4l2_subdev *sd;
 505         int error;
 506
 507         /* Check if the adapter supports the needed features */
 508         if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
 509                 return -EIO;
 510
 511         state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
 512         if (!state)
 513                 return -ENOMEM;
 514
 515         sd = &state->sd;
 516         v4l2_i2c_subdev_init(sd, client, &ths8200_ops);
 517
 518         state->chip_version = ths8200_read(sd, THS8200_VERSION);
 519         v4l2_dbg(1, debug, sd, "chip version 0x%x\n", state->chip_version);
 520
 521         ths8200_core_init(sd);
 522
 523         error = v4l2_async_register_subdev(&state->sd);
 524         if (error)
 525                 return error;
 526
 527         v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
 528                   client->addr << 1, client->adapter->name);
 529
 530         return 0;
 531 }
 532
 533 static int ths8200_remove(struct i2c_client *client)
 534 {
 535         struct v4l2_subdev *sd = i2c_get_clientdata(client);
 536         struct ths8200_state *decoder = to_state(sd);
 537
 538         v4l2_dbg(1, debug, sd, "%s removed @ 0x%x (%s)\n", client->name,
 539                  client->addr << 1, client->adapter->name);
 540
 541         ths8200_s_power(sd, false);
 542         v4l2_async_unregister_subdev(&decoder->sd);
 543         v4l2_device_unregister_subdev(sd);
 544
 545         return 0;
 546 }
 547
 548 static struct i2c_device_id ths8200_id[] = {
 549         { "ths8200", 0 },
 550         {},
 551 };
 552 MODULE_DEVICE_TABLE(i2c, ths8200_id);
 553
 554 #if IS_ENABLED(CONFIG_OF)
 555 static const struct of_device_id ths8200_of_match[] = {
 556         { .compatible = "ti,ths8200", },
 557         { /* sentinel */ },
 558 };
 559 MODULE_DEVICE_TABLE(of, ths8200_of_match);
 560 #endif
 561
 562 static struct i2c_driver ths8200_driver = {
 563         .driver = {
 564                 .owner = THIS_MODULE,
 565                 .name = "ths8200",
 566                 .of_match_table = of_match_ptr(ths8200_of_match),
 567         },
 568         .probe = ths8200_probe,
 569         .remove = ths8200_remove,
 570         .id_table = ths8200_id,
 571 };
 572
 573 module_i2c_driver(ths8200_driver);