2 * budget-ci.c: driver for the SAA7146 based Budget DVB cards
4 * Compiled from various sources by Michael Hunold <michael@mihu.de>
6 * msp430 IR support contributed by Jack Thomasson <jkt@Helius.COM>
7 * partially based on the Siemens DVB driver by Ralph+Marcus Metzler
9 * CI interface support (c) 2004 Andrew de Quincey <adq_dvb@lidskialf.net>
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version 2
14 * of the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
29 * the project's page is at http://www.linuxtv.org/
32 #include <linux/module.h>
33 #include <linux/errno.h>
34 #include <linux/slab.h>
35 #include <linux/interrupt.h>
36 #include <linux/spinlock.h>
37 #include <media/rc-core.h>
41 #include "dvb_ca_en50221.h"
45 #include "stb0899_drv.h"
46 #include "stb0899_reg.h"
47 #include "stb0899_cfg.h"
49 #include "stb6100_cfg.h"
56 #define MODULE_NAME "budget_ci"
59 * Regarding DEBIADDR_IR:
60 * Some CI modules hang if random addresses are read.
61 * Using address 0x4000 for the IR read means that we
62 * use the same address as for CI version, which should
65 #define DEBIADDR_IR 0x4000
66 #define DEBIADDR_CICONTROL 0x0000
67 #define DEBIADDR_CIVERSION 0x4000
68 #define DEBIADDR_IO 0x1000
69 #define DEBIADDR_ATTR 0x3000
71 #define CICONTROL_RESET 0x01
72 #define CICONTROL_ENABLETS 0x02
73 #define CICONTROL_CAMDETECT 0x08
75 #define DEBICICTL 0x00420000
76 #define DEBICICAM 0x02420000
78 #define SLOTSTATUS_NONE 1
79 #define SLOTSTATUS_PRESENT 2
80 #define SLOTSTATUS_RESET 4
81 #define SLOTSTATUS_READY 8
82 #define SLOTSTATUS_OCCUPIED (SLOTSTATUS_PRESENT|SLOTSTATUS_RESET|SLOTSTATUS_READY)
84 /* RC5 device wildcard */
85 #define IR_DEVICE_ANY 255
87 static int rc5_device = -1;
88 module_param(rc5_device, int, 0644);
89 MODULE_PARM_DESC(rc5_device, "only IR commands to given RC5 device (device = 0 - 31, any device = 255, default: autodetect)");
92 module_param(ir_debug, int, 0644);
93 MODULE_PARM_DESC(ir_debug, "enable debugging information for IR decoding");
95 DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
99 struct tasklet_struct msp430_irq_tasklet;
100 char name[72]; /* 40 + 32 for (struct saa7146_dev).name */
105 bool full_rc5; /* Outputs a full RC5 code */
109 struct budget budget;
110 struct tasklet_struct ciintf_irq_tasklet;
113 struct dvb_ca_en50221 ca;
114 struct budget_ci_ir ir;
115 u8 tuner_pll_address; /* used for philips_tdm1316l configs */
118 static void msp430_ir_interrupt(unsigned long data)
120 struct budget_ci *budget_ci = (struct budget_ci *) data;
121 struct rc_dev *dev = budget_ci->ir.dev;
122 u32 command = ttpci_budget_debiread(&budget_ci->budget, DEBINOSWAP, DEBIADDR_IR, 2, 1, 0) >> 8;
125 * The msp430 chip can generate two different bytes, command and device
127 * type1: X1CCCCCC, C = command bits (0 - 63)
128 * type2: X0TDDDDD, D = device bits (0 - 31), T = RC5 toggle bit
130 * Each signal from the remote control can generate one or more command
131 * bytes and one or more device bytes. For the repeated bytes, the
132 * highest bit (X) is set. The first command byte is always generated
133 * before the first device byte. Other than that, no specific order
134 * seems to apply. To make life interesting, bytes can also be lost.
136 * Only when we have a command and device byte, a keypress is
141 printk("budget_ci: received byte 0x%02x\n", command);
143 /* Remove repeat bit, we use every command */
144 command = command & 0x7f;
146 /* Is this a RC5 command byte? */
147 if (command & 0x40) {
148 budget_ci->ir.have_command = true;
149 budget_ci->ir.ir_key = command & 0x3f;
153 /* It's a RC5 device byte */
154 if (!budget_ci->ir.have_command)
156 budget_ci->ir.have_command = false;
158 if (budget_ci->ir.rc5_device != IR_DEVICE_ANY &&
159 budget_ci->ir.rc5_device != (command & 0x1f))
162 if (budget_ci->ir.full_rc5) {
164 budget_ci->ir.rc5_device <<8 | budget_ci->ir.ir_key,
165 (command & 0x20) ? 1 : 0);
169 /* FIXME: We should generate complete scancodes for all devices */
170 rc_keydown(dev, budget_ci->ir.ir_key, (command & 0x20) ? 1 : 0);
173 static int msp430_ir_init(struct budget_ci *budget_ci)
175 struct saa7146_dev *saa = budget_ci->budget.dev;
179 dev = rc_allocate_device();
181 printk(KERN_ERR "budget_ci: IR interface initialisation failed\n");
185 snprintf(budget_ci->ir.name, sizeof(budget_ci->ir.name),
186 "Budget-CI dvb ir receiver %s", saa->name);
187 snprintf(budget_ci->ir.phys, sizeof(budget_ci->ir.phys),
188 "pci-%s/ir0", pci_name(saa->pci));
190 dev->driver_name = MODULE_NAME;
191 dev->input_name = budget_ci->ir.name;
192 dev->input_phys = budget_ci->ir.phys;
193 dev->input_id.bustype = BUS_PCI;
194 dev->input_id.version = 1;
195 dev->scanmask = 0xff;
196 if (saa->pci->subsystem_vendor) {
197 dev->input_id.vendor = saa->pci->subsystem_vendor;
198 dev->input_id.product = saa->pci->subsystem_device;
200 dev->input_id.vendor = saa->pci->vendor;
201 dev->input_id.product = saa->pci->device;
203 dev->dev.parent = &saa->pci->dev;
206 budget_ci->ir.rc5_device = IR_DEVICE_ANY;
208 budget_ci->ir.rc5_device = rc5_device;
210 /* Select keymap and address */
211 switch (budget_ci->budget.dev->pci->subsystem_device) {
216 /* The hauppauge keymap is a superset of these remotes */
217 dev->map_name = RC_MAP_HAUPPAUGE;
218 budget_ci->ir.full_rc5 = true;
221 budget_ci->ir.rc5_device = 0x1f;
227 /* for the Technotrend 1500 bundled remote */
228 dev->map_name = RC_MAP_TT_1500;
232 dev->map_name = RC_MAP_BUDGET_CI_OLD;
236 error = rc_register_device(dev);
238 printk(KERN_ERR "budget_ci: could not init driver for IR device (code %d)\n", error);
243 budget_ci->ir.dev = dev;
245 tasklet_init(&budget_ci->ir.msp430_irq_tasklet, msp430_ir_interrupt,
246 (unsigned long) budget_ci);
248 SAA7146_IER_ENABLE(saa, MASK_06);
249 saa7146_setgpio(saa, 3, SAA7146_GPIO_IRQHI);
254 static void msp430_ir_deinit(struct budget_ci *budget_ci)
256 struct saa7146_dev *saa = budget_ci->budget.dev;
258 SAA7146_IER_DISABLE(saa, MASK_06);
259 saa7146_setgpio(saa, 3, SAA7146_GPIO_INPUT);
260 tasklet_kill(&budget_ci->ir.msp430_irq_tasklet);
262 rc_unregister_device(budget_ci->ir.dev);
265 static int ciintf_read_attribute_mem(struct dvb_ca_en50221 *ca, int slot, int address)
267 struct budget_ci *budget_ci = (struct budget_ci *) ca->data;
272 return ttpci_budget_debiread(&budget_ci->budget, DEBICICAM,
273 DEBIADDR_ATTR | (address & 0xfff), 1, 1, 0);
276 static int ciintf_write_attribute_mem(struct dvb_ca_en50221 *ca, int slot, int address, u8 value)
278 struct budget_ci *budget_ci = (struct budget_ci *) ca->data;
283 return ttpci_budget_debiwrite(&budget_ci->budget, DEBICICAM,
284 DEBIADDR_ATTR | (address & 0xfff), 1, value, 1, 0);
287 static int ciintf_read_cam_control(struct dvb_ca_en50221 *ca, int slot, u8 address)
289 struct budget_ci *budget_ci = (struct budget_ci *) ca->data;
294 return ttpci_budget_debiread(&budget_ci->budget, DEBICICAM,
295 DEBIADDR_IO | (address & 3), 1, 1, 0);
298 static int ciintf_write_cam_control(struct dvb_ca_en50221 *ca, int slot, u8 address, u8 value)
300 struct budget_ci *budget_ci = (struct budget_ci *) ca->data;
305 return ttpci_budget_debiwrite(&budget_ci->budget, DEBICICAM,
306 DEBIADDR_IO | (address & 3), 1, value, 1, 0);
309 static int ciintf_slot_reset(struct dvb_ca_en50221 *ca, int slot)
311 struct budget_ci *budget_ci = (struct budget_ci *) ca->data;
312 struct saa7146_dev *saa = budget_ci->budget.dev;
317 if (budget_ci->ci_irq) {
318 // trigger on RISING edge during reset so we know when READY is re-asserted
319 saa7146_setgpio(saa, 0, SAA7146_GPIO_IRQHI);
321 budget_ci->slot_status = SLOTSTATUS_RESET;
322 ttpci_budget_debiwrite(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1, 0, 1, 0);
324 ttpci_budget_debiwrite(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1,
325 CICONTROL_RESET, 1, 0);
327 saa7146_setgpio(saa, 1, SAA7146_GPIO_OUTHI);
328 ttpci_budget_set_video_port(saa, BUDGET_VIDEO_PORTB);
332 static int ciintf_slot_shutdown(struct dvb_ca_en50221 *ca, int slot)
334 struct budget_ci *budget_ci = (struct budget_ci *) ca->data;
335 struct saa7146_dev *saa = budget_ci->budget.dev;
340 saa7146_setgpio(saa, 1, SAA7146_GPIO_OUTHI);
341 ttpci_budget_set_video_port(saa, BUDGET_VIDEO_PORTB);
345 static int ciintf_slot_ts_enable(struct dvb_ca_en50221 *ca, int slot)
347 struct budget_ci *budget_ci = (struct budget_ci *) ca->data;
348 struct saa7146_dev *saa = budget_ci->budget.dev;
354 saa7146_setgpio(saa, 1, SAA7146_GPIO_OUTLO);
356 tmp = ttpci_budget_debiread(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1, 1, 0);
357 ttpci_budget_debiwrite(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1,
358 tmp | CICONTROL_ENABLETS, 1, 0);
360 ttpci_budget_set_video_port(saa, BUDGET_VIDEO_PORTA);
364 static void ciintf_interrupt(unsigned long data)
366 struct budget_ci *budget_ci = (struct budget_ci *) data;
367 struct saa7146_dev *saa = budget_ci->budget.dev;
370 // ensure we don't get spurious IRQs during initialisation
371 if (!budget_ci->budget.ci_present)
374 // read the CAM status
375 flags = ttpci_budget_debiread(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1, 1, 0);
376 if (flags & CICONTROL_CAMDETECT) {
378 // GPIO should be set to trigger on falling edge if a CAM is present
379 saa7146_setgpio(saa, 0, SAA7146_GPIO_IRQLO);
381 if (budget_ci->slot_status & SLOTSTATUS_NONE) {
383 budget_ci->slot_status = SLOTSTATUS_PRESENT;
384 dvb_ca_en50221_camchange_irq(&budget_ci->ca, 0,
385 DVB_CA_EN50221_CAMCHANGE_INSERTED);
387 } else if (budget_ci->slot_status & SLOTSTATUS_RESET) {
388 // CAM ready (reset completed)
389 budget_ci->slot_status = SLOTSTATUS_READY;
390 dvb_ca_en50221_camready_irq(&budget_ci->ca, 0);
392 } else if (budget_ci->slot_status & SLOTSTATUS_READY) {
394 dvb_ca_en50221_frda_irq(&budget_ci->ca, 0);
398 // trigger on rising edge if a CAM is not present - when a CAM is inserted, we
399 // only want to get the IRQ when it sets READY. If we trigger on the falling edge,
400 // the CAM might not actually be ready yet.
401 saa7146_setgpio(saa, 0, SAA7146_GPIO_IRQHI);
403 // generate a CAM removal IRQ if we haven't already
404 if (budget_ci->slot_status & SLOTSTATUS_OCCUPIED) {
406 budget_ci->slot_status = SLOTSTATUS_NONE;
407 dvb_ca_en50221_camchange_irq(&budget_ci->ca, 0,
408 DVB_CA_EN50221_CAMCHANGE_REMOVED);
413 static int ciintf_poll_slot_status(struct dvb_ca_en50221 *ca, int slot, int open)
415 struct budget_ci *budget_ci = (struct budget_ci *) ca->data;
418 // ensure we don't get spurious IRQs during initialisation
419 if (!budget_ci->budget.ci_present)
422 // read the CAM status
423 flags = ttpci_budget_debiread(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1, 1, 0);
424 if (flags & CICONTROL_CAMDETECT) {
425 // mark it as present if it wasn't before
426 if (budget_ci->slot_status & SLOTSTATUS_NONE) {
427 budget_ci->slot_status = SLOTSTATUS_PRESENT;
430 // during a RESET, we check if we can read from IO memory to see when CAM is ready
431 if (budget_ci->slot_status & SLOTSTATUS_RESET) {
432 if (ciintf_read_attribute_mem(ca, slot, 0) == 0x1d) {
433 budget_ci->slot_status = SLOTSTATUS_READY;
437 budget_ci->slot_status = SLOTSTATUS_NONE;
440 if (budget_ci->slot_status != SLOTSTATUS_NONE) {
441 if (budget_ci->slot_status & SLOTSTATUS_READY) {
442 return DVB_CA_EN50221_POLL_CAM_PRESENT | DVB_CA_EN50221_POLL_CAM_READY;
444 return DVB_CA_EN50221_POLL_CAM_PRESENT;
450 static int ciintf_init(struct budget_ci *budget_ci)
452 struct saa7146_dev *saa = budget_ci->budget.dev;
458 memset(&budget_ci->ca, 0, sizeof(struct dvb_ca_en50221));
461 saa7146_write(saa, MC1, MASK_27 | MASK_11);
463 // test if it is there
464 ci_version = ttpci_budget_debiread(&budget_ci->budget, DEBICICTL, DEBIADDR_CIVERSION, 1, 1, 0);
465 if ((ci_version & 0xa0) != 0xa0) {
470 // determine whether a CAM is present or not
471 flags = ttpci_budget_debiread(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1, 1, 0);
472 budget_ci->slot_status = SLOTSTATUS_NONE;
473 if (flags & CICONTROL_CAMDETECT)
474 budget_ci->slot_status = SLOTSTATUS_PRESENT;
476 // version 0xa2 of the CI firmware doesn't generate interrupts
477 if (ci_version == 0xa2) {
479 budget_ci->ci_irq = 0;
481 ca_flags = DVB_CA_EN50221_FLAG_IRQ_CAMCHANGE |
482 DVB_CA_EN50221_FLAG_IRQ_FR |
483 DVB_CA_EN50221_FLAG_IRQ_DA;
484 budget_ci->ci_irq = 1;
487 // register CI interface
488 budget_ci->ca.owner = THIS_MODULE;
489 budget_ci->ca.read_attribute_mem = ciintf_read_attribute_mem;
490 budget_ci->ca.write_attribute_mem = ciintf_write_attribute_mem;
491 budget_ci->ca.read_cam_control = ciintf_read_cam_control;
492 budget_ci->ca.write_cam_control = ciintf_write_cam_control;
493 budget_ci->ca.slot_reset = ciintf_slot_reset;
494 budget_ci->ca.slot_shutdown = ciintf_slot_shutdown;
495 budget_ci->ca.slot_ts_enable = ciintf_slot_ts_enable;
496 budget_ci->ca.poll_slot_status = ciintf_poll_slot_status;
497 budget_ci->ca.data = budget_ci;
498 if ((result = dvb_ca_en50221_init(&budget_ci->budget.dvb_adapter,
500 ca_flags, 1)) != 0) {
501 printk("budget_ci: CI interface detected, but initialisation failed.\n");
506 if (budget_ci->ci_irq) {
507 tasklet_init(&budget_ci->ciintf_irq_tasklet, ciintf_interrupt, (unsigned long) budget_ci);
508 if (budget_ci->slot_status != SLOTSTATUS_NONE) {
509 saa7146_setgpio(saa, 0, SAA7146_GPIO_IRQLO);
511 saa7146_setgpio(saa, 0, SAA7146_GPIO_IRQHI);
513 SAA7146_IER_ENABLE(saa, MASK_03);
517 ttpci_budget_debiwrite(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1,
518 CICONTROL_RESET, 1, 0);
521 printk("budget_ci: CI interface initialised\n");
522 budget_ci->budget.ci_present = 1;
524 // forge a fake CI IRQ so the CAM state is setup correctly
525 if (budget_ci->ci_irq) {
526 flags = DVB_CA_EN50221_CAMCHANGE_REMOVED;
527 if (budget_ci->slot_status != SLOTSTATUS_NONE)
528 flags = DVB_CA_EN50221_CAMCHANGE_INSERTED;
529 dvb_ca_en50221_camchange_irq(&budget_ci->ca, 0, flags);
535 saa7146_write(saa, MC1, MASK_27);
539 static void ciintf_deinit(struct budget_ci *budget_ci)
541 struct saa7146_dev *saa = budget_ci->budget.dev;
543 // disable CI interrupts
544 if (budget_ci->ci_irq) {
545 SAA7146_IER_DISABLE(saa, MASK_03);
546 saa7146_setgpio(saa, 0, SAA7146_GPIO_INPUT);
547 tasklet_kill(&budget_ci->ciintf_irq_tasklet);
551 ttpci_budget_debiwrite(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1, 0, 1, 0);
553 ttpci_budget_debiwrite(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1,
554 CICONTROL_RESET, 1, 0);
556 // disable TS data stream to CI interface
557 saa7146_setgpio(saa, 1, SAA7146_GPIO_INPUT);
559 // release the CA device
560 dvb_ca_en50221_release(&budget_ci->ca);
563 saa7146_write(saa, MC1, MASK_27);
566 static void budget_ci_irq(struct saa7146_dev *dev, u32 * isr)
568 struct budget_ci *budget_ci = (struct budget_ci *) dev->ext_priv;
570 dprintk(8, "dev: %p, budget_ci: %p\n", dev, budget_ci);
573 tasklet_schedule(&budget_ci->ir.msp430_irq_tasklet);
576 ttpci_budget_irq10_handler(dev, isr);
578 if ((*isr & MASK_03) && (budget_ci->budget.ci_present) && (budget_ci->ci_irq))
579 tasklet_schedule(&budget_ci->ciintf_irq_tasklet);
582 static u8 philips_su1278_tt_inittab[] = {
628 static int philips_su1278_tt_set_symbol_rate(struct dvb_frontend *fe, u32 srate, u32 ratio)
630 stv0299_writereg(fe, 0x0e, 0x44);
631 if (srate >= 10000000) {
632 stv0299_writereg(fe, 0x13, 0x97);
633 stv0299_writereg(fe, 0x14, 0x95);
634 stv0299_writereg(fe, 0x15, 0xc9);
635 stv0299_writereg(fe, 0x17, 0x8c);
636 stv0299_writereg(fe, 0x1a, 0xfe);
637 stv0299_writereg(fe, 0x1c, 0x7f);
638 stv0299_writereg(fe, 0x2d, 0x09);
640 stv0299_writereg(fe, 0x13, 0x99);
641 stv0299_writereg(fe, 0x14, 0x8d);
642 stv0299_writereg(fe, 0x15, 0xce);
643 stv0299_writereg(fe, 0x17, 0x43);
644 stv0299_writereg(fe, 0x1a, 0x1d);
645 stv0299_writereg(fe, 0x1c, 0x12);
646 stv0299_writereg(fe, 0x2d, 0x05);
648 stv0299_writereg(fe, 0x0e, 0x23);
649 stv0299_writereg(fe, 0x0f, 0x94);
650 stv0299_writereg(fe, 0x10, 0x39);
651 stv0299_writereg(fe, 0x15, 0xc9);
653 stv0299_writereg(fe, 0x1f, (ratio >> 16) & 0xff);
654 stv0299_writereg(fe, 0x20, (ratio >> 8) & 0xff);
655 stv0299_writereg(fe, 0x21, (ratio) & 0xf0);
660 static int philips_su1278_tt_tuner_set_params(struct dvb_frontend *fe,
661 struct dvb_frontend_parameters *params)
663 struct budget_ci *budget_ci = (struct budget_ci *) fe->dvb->priv;
666 struct i2c_msg msg = {.addr = 0x60,.flags = 0,.buf = buf,.len = sizeof(buf) };
668 if ((params->frequency < 950000) || (params->frequency > 2150000))
671 div = (params->frequency + (500 - 1)) / 500; // round correctly
672 buf[0] = (div >> 8) & 0x7f;
674 buf[2] = 0x80 | ((div & 0x18000) >> 10) | 2;
677 if (params->u.qpsk.symbol_rate < 4000000)
680 if (params->frequency < 1250000)
682 else if (params->frequency < 1550000)
684 else if (params->frequency < 2050000)
686 else if (params->frequency < 2150000)
689 if (fe->ops.i2c_gate_ctrl)
690 fe->ops.i2c_gate_ctrl(fe, 1);
691 if (i2c_transfer(&budget_ci->budget.i2c_adap, &msg, 1) != 1)
696 static struct stv0299_config philips_su1278_tt_config = {
698 .demod_address = 0x68,
699 .inittab = philips_su1278_tt_inittab,
703 .lock_output = STV0299_LOCKOUTPUT_1,
704 .volt13_op0_op1 = STV0299_VOLT13_OP1,
706 .set_symbol_rate = philips_su1278_tt_set_symbol_rate,
711 static int philips_tdm1316l_tuner_init(struct dvb_frontend *fe)
713 struct budget_ci *budget_ci = (struct budget_ci *) fe->dvb->priv;
714 static u8 td1316_init[] = { 0x0b, 0xf5, 0x85, 0xab };
715 static u8 disable_mc44BC374c[] = { 0x1d, 0x74, 0xa0, 0x68 };
716 struct i2c_msg tuner_msg = {.addr = budget_ci->tuner_pll_address,.flags = 0,.buf = td1316_init,.len =
717 sizeof(td1316_init) };
719 // setup PLL configuration
720 if (fe->ops.i2c_gate_ctrl)
721 fe->ops.i2c_gate_ctrl(fe, 1);
722 if (i2c_transfer(&budget_ci->budget.i2c_adap, &tuner_msg, 1) != 1)
726 // disable the mc44BC374c (do not check for errors)
727 tuner_msg.addr = 0x65;
728 tuner_msg.buf = disable_mc44BC374c;
729 tuner_msg.len = sizeof(disable_mc44BC374c);
730 if (fe->ops.i2c_gate_ctrl)
731 fe->ops.i2c_gate_ctrl(fe, 1);
732 if (i2c_transfer(&budget_ci->budget.i2c_adap, &tuner_msg, 1) != 1) {
733 if (fe->ops.i2c_gate_ctrl)
734 fe->ops.i2c_gate_ctrl(fe, 1);
735 i2c_transfer(&budget_ci->budget.i2c_adap, &tuner_msg, 1);
741 static int philips_tdm1316l_tuner_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params)
743 struct budget_ci *budget_ci = (struct budget_ci *) fe->dvb->priv;
745 struct i2c_msg tuner_msg = {.addr = budget_ci->tuner_pll_address,.flags = 0,.buf = tuner_buf,.len = sizeof(tuner_buf) };
746 int tuner_frequency = 0;
749 // determine charge pump
750 tuner_frequency = params->frequency + 36130000;
751 if (tuner_frequency < 87000000)
753 else if (tuner_frequency < 130000000)
755 else if (tuner_frequency < 160000000)
757 else if (tuner_frequency < 200000000)
759 else if (tuner_frequency < 290000000)
761 else if (tuner_frequency < 420000000)
763 else if (tuner_frequency < 480000000)
765 else if (tuner_frequency < 620000000)
767 else if (tuner_frequency < 830000000)
769 else if (tuner_frequency < 895000000)
775 if (params->frequency < 49000000)
777 else if (params->frequency < 159000000)
779 else if (params->frequency < 444000000)
781 else if (params->frequency < 861000000)
786 // setup PLL filter and TDA9889
787 switch (params->u.ofdm.bandwidth) {
788 case BANDWIDTH_6_MHZ:
789 tda1004x_writereg(fe, 0x0C, 0x14);
793 case BANDWIDTH_7_MHZ:
794 tda1004x_writereg(fe, 0x0C, 0x80);
798 case BANDWIDTH_8_MHZ:
799 tda1004x_writereg(fe, 0x0C, 0x14);
808 // ((36130000+((1000000/6)/2)) + Finput)/(1000000/6)
809 tuner_frequency = (((params->frequency / 1000) * 6) + 217280) / 1000;
811 // setup tuner buffer
812 tuner_buf[0] = tuner_frequency >> 8;
813 tuner_buf[1] = tuner_frequency & 0xff;
815 tuner_buf[3] = (cp << 5) | (filter << 3) | band;
817 if (fe->ops.i2c_gate_ctrl)
818 fe->ops.i2c_gate_ctrl(fe, 1);
819 if (i2c_transfer(&budget_ci->budget.i2c_adap, &tuner_msg, 1) != 1)
826 static int philips_tdm1316l_request_firmware(struct dvb_frontend *fe,
827 const struct firmware **fw, char *name)
829 struct budget_ci *budget_ci = (struct budget_ci *) fe->dvb->priv;
831 return request_firmware(fw, name, &budget_ci->budget.dev->pci->dev);
834 static struct tda1004x_config philips_tdm1316l_config = {
836 .demod_address = 0x8,
839 .xtal_freq = TDA10046_XTAL_4M,
840 .agc_config = TDA10046_AGC_DEFAULT,
841 .if_freq = TDA10046_FREQ_3617,
842 .request_firmware = philips_tdm1316l_request_firmware,
845 static struct tda1004x_config philips_tdm1316l_config_invert = {
847 .demod_address = 0x8,
850 .xtal_freq = TDA10046_XTAL_4M,
851 .agc_config = TDA10046_AGC_DEFAULT,
852 .if_freq = TDA10046_FREQ_3617,
853 .request_firmware = philips_tdm1316l_request_firmware,
856 static int dvbc_philips_tdm1316l_tuner_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params)
858 struct budget_ci *budget_ci = (struct budget_ci *) fe->dvb->priv;
860 struct i2c_msg tuner_msg = {.addr = budget_ci->tuner_pll_address,
863 .len = sizeof(tuner_buf) };
864 int tuner_frequency = 0;
867 // determine charge pump
868 tuner_frequency = params->frequency + 36125000;
869 if (tuner_frequency < 87000000)
871 else if (tuner_frequency < 130000000) {
874 } else if (tuner_frequency < 160000000) {
877 } else if (tuner_frequency < 200000000) {
880 } else if (tuner_frequency < 290000000) {
883 } else if (tuner_frequency < 420000000) {
886 } else if (tuner_frequency < 480000000) {
889 } else if (tuner_frequency < 620000000) {
892 } else if (tuner_frequency < 830000000) {
895 } else if (tuner_frequency < 895000000) {
901 // assume PLL filter should always be 8MHz for the moment.
905 tuner_frequency = (params->frequency + 36125000 + (62500/2)) / 62500;
907 // setup tuner buffer
908 tuner_buf[0] = tuner_frequency >> 8;
909 tuner_buf[1] = tuner_frequency & 0xff;
911 tuner_buf[3] = (cp << 5) | (filter << 3) | band;
914 if (fe->ops.i2c_gate_ctrl)
915 fe->ops.i2c_gate_ctrl(fe, 1);
916 if (i2c_transfer(&budget_ci->budget.i2c_adap, &tuner_msg, 1) != 1)
921 if (fe->ops.i2c_gate_ctrl)
922 fe->ops.i2c_gate_ctrl(fe, 1);
923 if (i2c_transfer(&budget_ci->budget.i2c_adap, &tuner_msg, 1) != 1)
931 static u8 dvbc_philips_tdm1316l_inittab[] = {
1024 static struct stv0297_config dvbc_philips_tdm1316l_config = {
1025 .demod_address = 0x1c,
1026 .inittab = dvbc_philips_tdm1316l_inittab,
1028 .stop_during_read = 1,
1031 static struct tda10023_config tda10023_config = {
1032 .demod_address = 0xc,
1041 static struct tda827x_config tda827x_config = {
1045 /* TT S2-3200 DVB-S (STB0899) Inittab */
1046 static const struct stb0899_s1_reg tt3200_stb0899_s1_init_1[] = {
1048 { STB0899_DEV_ID , 0x81 },
1049 { STB0899_DISCNTRL1 , 0x32 },
1050 { STB0899_DISCNTRL2 , 0x80 },
1051 { STB0899_DISRX_ST0 , 0x04 },
1052 { STB0899_DISRX_ST1 , 0x00 },
1053 { STB0899_DISPARITY , 0x00 },
1054 { STB0899_DISFIFO , 0x00 },
1055 { STB0899_DISSTATUS , 0x20 },
1056 { STB0899_DISF22 , 0x8c },
1057 { STB0899_DISF22RX , 0x9a },
1058 { STB0899_SYSREG , 0x0b },
1059 { STB0899_ACRPRESC , 0x11 },
1060 { STB0899_ACRDIV1 , 0x0a },
1061 { STB0899_ACRDIV2 , 0x05 },
1062 { STB0899_DACR1 , 0x00 },
1063 { STB0899_DACR2 , 0x00 },
1064 { STB0899_OUTCFG , 0x00 },
1065 { STB0899_MODECFG , 0x00 },
1066 { STB0899_IRQSTATUS_3 , 0x30 },
1067 { STB0899_IRQSTATUS_2 , 0x00 },
1068 { STB0899_IRQSTATUS_1 , 0x00 },
1069 { STB0899_IRQSTATUS_0 , 0x00 },
1070 { STB0899_IRQMSK_3 , 0xf3 },
1071 { STB0899_IRQMSK_2 , 0xfc },
1072 { STB0899_IRQMSK_1 , 0xff },
1073 { STB0899_IRQMSK_0 , 0xff },
1074 { STB0899_IRQCFG , 0x00 },
1075 { STB0899_I2CCFG , 0x88 },
1076 { STB0899_I2CRPT , 0x48 }, /* 12k Pullup, Repeater=16, Stop=disabled */
1077 { STB0899_IOPVALUE5 , 0x00 },
1078 { STB0899_IOPVALUE4 , 0x20 },
1079 { STB0899_IOPVALUE3 , 0xc9 },
1080 { STB0899_IOPVALUE2 , 0x90 },
1081 { STB0899_IOPVALUE1 , 0x40 },
1082 { STB0899_IOPVALUE0 , 0x00 },
1083 { STB0899_GPIO00CFG , 0x82 },
1084 { STB0899_GPIO01CFG , 0x82 },
1085 { STB0899_GPIO02CFG , 0x82 },
1086 { STB0899_GPIO03CFG , 0x82 },
1087 { STB0899_GPIO04CFG , 0x82 },
1088 { STB0899_GPIO05CFG , 0x82 },
1089 { STB0899_GPIO06CFG , 0x82 },
1090 { STB0899_GPIO07CFG , 0x82 },
1091 { STB0899_GPIO08CFG , 0x82 },
1092 { STB0899_GPIO09CFG , 0x82 },
1093 { STB0899_GPIO10CFG , 0x82 },
1094 { STB0899_GPIO11CFG , 0x82 },
1095 { STB0899_GPIO12CFG , 0x82 },
1096 { STB0899_GPIO13CFG , 0x82 },
1097 { STB0899_GPIO14CFG , 0x82 },
1098 { STB0899_GPIO15CFG , 0x82 },
1099 { STB0899_GPIO16CFG , 0x82 },
1100 { STB0899_GPIO17CFG , 0x82 },
1101 { STB0899_GPIO18CFG , 0x82 },
1102 { STB0899_GPIO19CFG , 0x82 },
1103 { STB0899_GPIO20CFG , 0x82 },
1104 { STB0899_SDATCFG , 0xb8 },
1105 { STB0899_SCLTCFG , 0xba },
1106 { STB0899_AGCRFCFG , 0x1c }, /* 0x11 */
1107 { STB0899_GPIO22 , 0x82 }, /* AGCBB2CFG */
1108 { STB0899_GPIO21 , 0x91 }, /* AGCBB1CFG */
1109 { STB0899_DIRCLKCFG , 0x82 },
1110 { STB0899_CLKOUT27CFG , 0x7e },
1111 { STB0899_STDBYCFG , 0x82 },
1112 { STB0899_CS0CFG , 0x82 },
1113 { STB0899_CS1CFG , 0x82 },
1114 { STB0899_DISEQCOCFG , 0x20 },
1115 { STB0899_GPIO32CFG , 0x82 },
1116 { STB0899_GPIO33CFG , 0x82 },
1117 { STB0899_GPIO34CFG , 0x82 },
1118 { STB0899_GPIO35CFG , 0x82 },
1119 { STB0899_GPIO36CFG , 0x82 },
1120 { STB0899_GPIO37CFG , 0x82 },
1121 { STB0899_GPIO38CFG , 0x82 },
1122 { STB0899_GPIO39CFG , 0x82 },
1123 { STB0899_NCOARSE , 0x15 }, /* 0x15 = 27 Mhz Clock, F/3 = 198MHz, F/6 = 99MHz */
1124 { STB0899_SYNTCTRL , 0x02 }, /* 0x00 = CLK from CLKI, 0x02 = CLK from XTALI */
1125 { STB0899_FILTCTRL , 0x00 },
1126 { STB0899_SYSCTRL , 0x00 },
1127 { STB0899_STOPCLK1 , 0x20 },
1128 { STB0899_STOPCLK2 , 0x00 },
1129 { STB0899_INTBUFSTATUS , 0x00 },
1130 { STB0899_INTBUFCTRL , 0x0a },
1134 static const struct stb0899_s1_reg tt3200_stb0899_s1_init_3[] = {
1135 { STB0899_DEMOD , 0x00 },
1136 { STB0899_RCOMPC , 0xc9 },
1137 { STB0899_AGC1CN , 0x41 },
1138 { STB0899_AGC1REF , 0x10 },
1139 { STB0899_RTC , 0x7a },
1140 { STB0899_TMGCFG , 0x4e },
1141 { STB0899_AGC2REF , 0x34 },
1142 { STB0899_TLSR , 0x84 },
1143 { STB0899_CFD , 0xc7 },
1144 { STB0899_ACLC , 0x87 },
1145 { STB0899_BCLC , 0x94 },
1146 { STB0899_EQON , 0x41 },
1147 { STB0899_LDT , 0xdd },
1148 { STB0899_LDT2 , 0xc9 },
1149 { STB0899_EQUALREF , 0xb4 },
1150 { STB0899_TMGRAMP , 0x10 },
1151 { STB0899_TMGTHD , 0x30 },
1152 { STB0899_IDCCOMP , 0xfb },
1153 { STB0899_QDCCOMP , 0x03 },
1154 { STB0899_POWERI , 0x3b },
1155 { STB0899_POWERQ , 0x3d },
1156 { STB0899_RCOMP , 0x81 },
1157 { STB0899_AGCIQIN , 0x80 },
1158 { STB0899_AGC2I1 , 0x04 },
1159 { STB0899_AGC2I2 , 0xf5 },
1160 { STB0899_TLIR , 0x25 },
1161 { STB0899_RTF , 0x80 },
1162 { STB0899_DSTATUS , 0x00 },
1163 { STB0899_LDI , 0xca },
1164 { STB0899_CFRM , 0xf1 },
1165 { STB0899_CFRL , 0xf3 },
1166 { STB0899_NIRM , 0x2a },
1167 { STB0899_NIRL , 0x05 },
1168 { STB0899_ISYMB , 0x17 },
1169 { STB0899_QSYMB , 0xfa },
1170 { STB0899_SFRH , 0x2f },
1171 { STB0899_SFRM , 0x68 },
1172 { STB0899_SFRL , 0x40 },
1173 { STB0899_SFRUPH , 0x2f },
1174 { STB0899_SFRUPM , 0x68 },
1175 { STB0899_SFRUPL , 0x40 },
1176 { STB0899_EQUAI1 , 0xfd },
1177 { STB0899_EQUAQ1 , 0x04 },
1178 { STB0899_EQUAI2 , 0x0f },
1179 { STB0899_EQUAQ2 , 0xff },
1180 { STB0899_EQUAI3 , 0xdf },
1181 { STB0899_EQUAQ3 , 0xfa },
1182 { STB0899_EQUAI4 , 0x37 },
1183 { STB0899_EQUAQ4 , 0x0d },
1184 { STB0899_EQUAI5 , 0xbd },
1185 { STB0899_EQUAQ5 , 0xf7 },
1186 { STB0899_DSTATUS2 , 0x00 },
1187 { STB0899_VSTATUS , 0x00 },
1188 { STB0899_VERROR , 0xff },
1189 { STB0899_IQSWAP , 0x2a },
1190 { STB0899_ECNT1M , 0x00 },
1191 { STB0899_ECNT1L , 0x00 },
1192 { STB0899_ECNT2M , 0x00 },
1193 { STB0899_ECNT2L , 0x00 },
1194 { STB0899_ECNT3M , 0x00 },
1195 { STB0899_ECNT3L , 0x00 },
1196 { STB0899_FECAUTO1 , 0x06 },
1197 { STB0899_FECM , 0x01 },
1198 { STB0899_VTH12 , 0xf0 },
1199 { STB0899_VTH23 , 0xa0 },
1200 { STB0899_VTH34 , 0x78 },
1201 { STB0899_VTH56 , 0x4e },
1202 { STB0899_VTH67 , 0x48 },
1203 { STB0899_VTH78 , 0x38 },
1204 { STB0899_PRVIT , 0xff },
1205 { STB0899_VITSYNC , 0x19 },
1206 { STB0899_RSULC , 0xb1 }, /* DVB = 0xb1, DSS = 0xa1 */
1207 { STB0899_TSULC , 0x42 },
1208 { STB0899_RSLLC , 0x40 },
1209 { STB0899_TSLPL , 0x12 },
1210 { STB0899_TSCFGH , 0x0c },
1211 { STB0899_TSCFGM , 0x00 },
1212 { STB0899_TSCFGL , 0x0c },
1213 { STB0899_TSOUT , 0x4d }, /* 0x0d for CAM */
1214 { STB0899_RSSYNCDEL , 0x00 },
1215 { STB0899_TSINHDELH , 0x02 },
1216 { STB0899_TSINHDELM , 0x00 },
1217 { STB0899_TSINHDELL , 0x00 },
1218 { STB0899_TSLLSTKM , 0x00 },
1219 { STB0899_TSLLSTKL , 0x00 },
1220 { STB0899_TSULSTKM , 0x00 },
1221 { STB0899_TSULSTKL , 0xab },
1222 { STB0899_PCKLENUL , 0x00 },
1223 { STB0899_PCKLENLL , 0xcc },
1224 { STB0899_RSPCKLEN , 0xcc },
1225 { STB0899_TSSTATUS , 0x80 },
1226 { STB0899_ERRCTRL1 , 0xb6 },
1227 { STB0899_ERRCTRL2 , 0x96 },
1228 { STB0899_ERRCTRL3 , 0x89 },
1229 { STB0899_DMONMSK1 , 0x27 },
1230 { STB0899_DMONMSK0 , 0x03 },
1231 { STB0899_DEMAPVIT , 0x5c },
1232 { STB0899_PLPARM , 0x1f },
1233 { STB0899_PDELCTRL , 0x48 },
1234 { STB0899_PDELCTRL2 , 0x00 },
1235 { STB0899_BBHCTRL1 , 0x00 },
1236 { STB0899_BBHCTRL2 , 0x00 },
1237 { STB0899_HYSTTHRESH , 0x77 },
1238 { STB0899_MATCSTM , 0x00 },
1239 { STB0899_MATCSTL , 0x00 },
1240 { STB0899_UPLCSTM , 0x00 },
1241 { STB0899_UPLCSTL , 0x00 },
1242 { STB0899_DFLCSTM , 0x00 },
1243 { STB0899_DFLCSTL , 0x00 },
1244 { STB0899_SYNCCST , 0x00 },
1245 { STB0899_SYNCDCSTM , 0x00 },
1246 { STB0899_SYNCDCSTL , 0x00 },
1247 { STB0899_ISI_ENTRY , 0x00 },
1248 { STB0899_ISI_BIT_EN , 0x00 },
1249 { STB0899_MATSTRM , 0x00 },
1250 { STB0899_MATSTRL , 0x00 },
1251 { STB0899_UPLSTRM , 0x00 },
1252 { STB0899_UPLSTRL , 0x00 },
1253 { STB0899_DFLSTRM , 0x00 },
1254 { STB0899_DFLSTRL , 0x00 },
1255 { STB0899_SYNCSTR , 0x00 },
1256 { STB0899_SYNCDSTRM , 0x00 },
1257 { STB0899_SYNCDSTRL , 0x00 },
1258 { STB0899_CFGPDELSTATUS1 , 0x10 },
1259 { STB0899_CFGPDELSTATUS2 , 0x00 },
1260 { STB0899_BBFERRORM , 0x00 },
1261 { STB0899_BBFERRORL , 0x00 },
1262 { STB0899_UPKTERRORM , 0x00 },
1263 { STB0899_UPKTERRORL , 0x00 },
1267 static struct stb0899_config tt3200_config = {
1268 .init_dev = tt3200_stb0899_s1_init_1,
1269 .init_s2_demod = stb0899_s2_init_2,
1270 .init_s1_demod = tt3200_stb0899_s1_init_3,
1271 .init_s2_fec = stb0899_s2_init_4,
1272 .init_tst = stb0899_s1_init_5,
1276 .demod_address = 0x68,
1278 .xtal_freq = 27000000,
1279 .inversion = IQ_SWAP_ON, /* 1 */
1284 .esno_ave = STB0899_DVBS2_ESNO_AVE,
1285 .esno_quant = STB0899_DVBS2_ESNO_QUANT,
1286 .avframes_coarse = STB0899_DVBS2_AVFRAMES_COARSE,
1287 .avframes_fine = STB0899_DVBS2_AVFRAMES_FINE,
1288 .miss_threshold = STB0899_DVBS2_MISS_THRESHOLD,
1289 .uwp_threshold_acq = STB0899_DVBS2_UWP_THRESHOLD_ACQ,
1290 .uwp_threshold_track = STB0899_DVBS2_UWP_THRESHOLD_TRACK,
1291 .uwp_threshold_sof = STB0899_DVBS2_UWP_THRESHOLD_SOF,
1292 .sof_search_timeout = STB0899_DVBS2_SOF_SEARCH_TIMEOUT,
1294 .btr_nco_bits = STB0899_DVBS2_BTR_NCO_BITS,
1295 .btr_gain_shift_offset = STB0899_DVBS2_BTR_GAIN_SHIFT_OFFSET,
1296 .crl_nco_bits = STB0899_DVBS2_CRL_NCO_BITS,
1297 .ldpc_max_iter = STB0899_DVBS2_LDPC_MAX_ITER,
1299 .tuner_get_frequency = stb6100_get_frequency,
1300 .tuner_set_frequency = stb6100_set_frequency,
1301 .tuner_set_bandwidth = stb6100_set_bandwidth,
1302 .tuner_get_bandwidth = stb6100_get_bandwidth,
1303 .tuner_set_rfsiggain = NULL
1306 static struct stb6100_config tt3200_stb6100_config = {
1307 .tuner_address = 0x60,
1308 .refclock = 27000000,
1311 static void frontend_init(struct budget_ci *budget_ci)
1313 switch (budget_ci->budget.dev->pci->subsystem_device) {
1314 case 0x100c: // Hauppauge/TT Nova-CI budget (stv0299/ALPS BSRU6(tsa5059))
1315 budget_ci->budget.dvb_frontend =
1316 dvb_attach(stv0299_attach, &alps_bsru6_config, &budget_ci->budget.i2c_adap);
1317 if (budget_ci->budget.dvb_frontend) {
1318 budget_ci->budget.dvb_frontend->ops.tuner_ops.set_params = alps_bsru6_tuner_set_params;
1319 budget_ci->budget.dvb_frontend->tuner_priv = &budget_ci->budget.i2c_adap;
1324 case 0x100f: // Hauppauge/TT Nova-CI budget (stv0299b/Philips su1278(tsa5059))
1325 budget_ci->budget.dvb_frontend =
1326 dvb_attach(stv0299_attach, &philips_su1278_tt_config, &budget_ci->budget.i2c_adap);
1327 if (budget_ci->budget.dvb_frontend) {
1328 budget_ci->budget.dvb_frontend->ops.tuner_ops.set_params = philips_su1278_tt_tuner_set_params;
1333 case 0x1010: // TT DVB-C CI budget (stv0297/Philips tdm1316l(tda6651tt))
1334 budget_ci->tuner_pll_address = 0x61;
1335 budget_ci->budget.dvb_frontend =
1336 dvb_attach(stv0297_attach, &dvbc_philips_tdm1316l_config, &budget_ci->budget.i2c_adap);
1337 if (budget_ci->budget.dvb_frontend) {
1338 budget_ci->budget.dvb_frontend->ops.tuner_ops.set_params = dvbc_philips_tdm1316l_tuner_set_params;
1343 case 0x1011: // Hauppauge/TT Nova-T budget (tda10045/Philips tdm1316l(tda6651tt) + TDA9889)
1344 budget_ci->tuner_pll_address = 0x63;
1345 budget_ci->budget.dvb_frontend =
1346 dvb_attach(tda10045_attach, &philips_tdm1316l_config, &budget_ci->budget.i2c_adap);
1347 if (budget_ci->budget.dvb_frontend) {
1348 budget_ci->budget.dvb_frontend->ops.tuner_ops.init = philips_tdm1316l_tuner_init;
1349 budget_ci->budget.dvb_frontend->ops.tuner_ops.set_params = philips_tdm1316l_tuner_set_params;
1354 case 0x1012: // TT DVB-T CI budget (tda10046/Philips tdm1316l(tda6651tt))
1355 budget_ci->tuner_pll_address = 0x60;
1356 budget_ci->budget.dvb_frontend =
1357 dvb_attach(tda10046_attach, &philips_tdm1316l_config_invert, &budget_ci->budget.i2c_adap);
1358 if (budget_ci->budget.dvb_frontend) {
1359 budget_ci->budget.dvb_frontend->ops.tuner_ops.init = philips_tdm1316l_tuner_init;
1360 budget_ci->budget.dvb_frontend->ops.tuner_ops.set_params = philips_tdm1316l_tuner_set_params;
1365 case 0x1017: // TT S-1500 PCI
1366 budget_ci->budget.dvb_frontend = dvb_attach(stv0299_attach, &alps_bsbe1_config, &budget_ci->budget.i2c_adap);
1367 if (budget_ci->budget.dvb_frontend) {
1368 budget_ci->budget.dvb_frontend->ops.tuner_ops.set_params = alps_bsbe1_tuner_set_params;
1369 budget_ci->budget.dvb_frontend->tuner_priv = &budget_ci->budget.i2c_adap;
1371 budget_ci->budget.dvb_frontend->ops.dishnetwork_send_legacy_command = NULL;
1372 if (dvb_attach(lnbp21_attach, budget_ci->budget.dvb_frontend, &budget_ci->budget.i2c_adap, LNBP21_LLC, 0) == NULL) {
1373 printk("%s: No LNBP21 found!\n", __func__);
1374 dvb_frontend_detach(budget_ci->budget.dvb_frontend);
1375 budget_ci->budget.dvb_frontend = NULL;
1380 case 0x101a: /* TT Budget-C-1501 (philips tda10023/philips tda8274A) */
1381 budget_ci->budget.dvb_frontend = dvb_attach(tda10023_attach, &tda10023_config, &budget_ci->budget.i2c_adap, 0x48);
1382 if (budget_ci->budget.dvb_frontend) {
1383 if (dvb_attach(tda827x_attach, budget_ci->budget.dvb_frontend, 0x61, &budget_ci->budget.i2c_adap, &tda827x_config) == NULL) {
1384 printk(KERN_ERR "%s: No tda827x found!\n", __func__);
1385 dvb_frontend_detach(budget_ci->budget.dvb_frontend);
1386 budget_ci->budget.dvb_frontend = NULL;
1391 case 0x1019: // TT S2-3200 PCI
1393 * NOTE! on some STB0899 versions, the internal PLL takes a longer time
1394 * to settle, aka LOCK. On the older revisions of the chip, we don't see
1395 * this, as a result on the newer chips the entire clock tree, will not
1396 * be stable after a freshly POWER 'ed up situation.
1397 * In this case, we should RESET the STB0899 (Active LOW) and wait for
1398 * PLL stabilization.
1400 * On the TT S2 3200 and clones, the STB0899 demodulator's RESETB is
1401 * connected to the SAA7146 GPIO, GPIO2, Pin 142
1403 /* Reset Demodulator */
1404 saa7146_setgpio(budget_ci->budget.dev, 2, SAA7146_GPIO_OUTLO);
1405 /* Wait for everything to die */
1407 /* Pull it up out of Reset state */
1408 saa7146_setgpio(budget_ci->budget.dev, 2, SAA7146_GPIO_OUTHI);
1409 /* Wait for PLL to stabilize */
1412 * PLL state should be stable now. Ideally, we should check
1413 * for PLL LOCK status. But well, never mind!
1415 budget_ci->budget.dvb_frontend = dvb_attach(stb0899_attach, &tt3200_config, &budget_ci->budget.i2c_adap);
1416 if (budget_ci->budget.dvb_frontend) {
1417 if (dvb_attach(stb6100_attach, budget_ci->budget.dvb_frontend, &tt3200_stb6100_config, &budget_ci->budget.i2c_adap)) {
1418 if (!dvb_attach(lnbp21_attach, budget_ci->budget.dvb_frontend, &budget_ci->budget.i2c_adap, 0, 0)) {
1419 printk("%s: No LNBP21 found!\n", __func__);
1420 dvb_frontend_detach(budget_ci->budget.dvb_frontend);
1421 budget_ci->budget.dvb_frontend = NULL;
1424 dvb_frontend_detach(budget_ci->budget.dvb_frontend);
1425 budget_ci->budget.dvb_frontend = NULL;
1432 if (budget_ci->budget.dvb_frontend == NULL) {
1433 printk("budget-ci: A frontend driver was not found for device [%04x:%04x] subsystem [%04x:%04x]\n",
1434 budget_ci->budget.dev->pci->vendor,
1435 budget_ci->budget.dev->pci->device,
1436 budget_ci->budget.dev->pci->subsystem_vendor,
1437 budget_ci->budget.dev->pci->subsystem_device);
1439 if (dvb_register_frontend
1440 (&budget_ci->budget.dvb_adapter, budget_ci->budget.dvb_frontend)) {
1441 printk("budget-ci: Frontend registration failed!\n");
1442 dvb_frontend_detach(budget_ci->budget.dvb_frontend);
1443 budget_ci->budget.dvb_frontend = NULL;
1448 static int budget_ci_attach(struct saa7146_dev *dev, struct saa7146_pci_extension_data *info)
1450 struct budget_ci *budget_ci;
1453 budget_ci = kzalloc(sizeof(struct budget_ci), GFP_KERNEL);
1459 dprintk(2, "budget_ci: %p\n", budget_ci);
1461 dev->ext_priv = budget_ci;
1463 err = ttpci_budget_init(&budget_ci->budget, dev, info, THIS_MODULE,
1468 err = msp430_ir_init(budget_ci);
1472 ciintf_init(budget_ci);
1474 budget_ci->budget.dvb_adapter.priv = budget_ci;
1475 frontend_init(budget_ci);
1477 ttpci_budget_init_hooks(&budget_ci->budget);
1482 ttpci_budget_deinit(&budget_ci->budget);
1489 static int budget_ci_detach(struct saa7146_dev *dev)
1491 struct budget_ci *budget_ci = (struct budget_ci *) dev->ext_priv;
1492 struct saa7146_dev *saa = budget_ci->budget.dev;
1495 if (budget_ci->budget.ci_present)
1496 ciintf_deinit(budget_ci);
1497 msp430_ir_deinit(budget_ci);
1498 if (budget_ci->budget.dvb_frontend) {
1499 dvb_unregister_frontend(budget_ci->budget.dvb_frontend);
1500 dvb_frontend_detach(budget_ci->budget.dvb_frontend);
1502 err = ttpci_budget_deinit(&budget_ci->budget);
1504 // disable frontend and CI interface
1505 saa7146_setgpio(saa, 2, SAA7146_GPIO_INPUT);
1512 static struct saa7146_extension budget_extension;
1514 MAKE_BUDGET_INFO(ttbs2, "TT-Budget/S-1500 PCI", BUDGET_TT);
1515 MAKE_BUDGET_INFO(ttbci, "TT-Budget/WinTV-NOVA-CI PCI", BUDGET_TT_HW_DISEQC);
1516 MAKE_BUDGET_INFO(ttbt2, "TT-Budget/WinTV-NOVA-T PCI", BUDGET_TT);
1517 MAKE_BUDGET_INFO(ttbtci, "TT-Budget-T-CI PCI", BUDGET_TT);
1518 MAKE_BUDGET_INFO(ttbcci, "TT-Budget-C-CI PCI", BUDGET_TT);
1519 MAKE_BUDGET_INFO(ttc1501, "TT-Budget C-1501 PCI", BUDGET_TT);
1520 MAKE_BUDGET_INFO(tt3200, "TT-Budget S2-3200 PCI", BUDGET_TT);
1522 static struct pci_device_id pci_tbl[] = {
1523 MAKE_EXTENSION_PCI(ttbci, 0x13c2, 0x100c),
1524 MAKE_EXTENSION_PCI(ttbci, 0x13c2, 0x100f),
1525 MAKE_EXTENSION_PCI(ttbcci, 0x13c2, 0x1010),
1526 MAKE_EXTENSION_PCI(ttbt2, 0x13c2, 0x1011),
1527 MAKE_EXTENSION_PCI(ttbtci, 0x13c2, 0x1012),
1528 MAKE_EXTENSION_PCI(ttbs2, 0x13c2, 0x1017),
1529 MAKE_EXTENSION_PCI(ttc1501, 0x13c2, 0x101a),
1530 MAKE_EXTENSION_PCI(tt3200, 0x13c2, 0x1019),
1536 MODULE_DEVICE_TABLE(pci, pci_tbl);
1538 static struct saa7146_extension budget_extension = {
1539 .name = "budget_ci dvb",
1540 .flags = SAA7146_USE_I2C_IRQ,
1542 .module = THIS_MODULE,
1543 .pci_tbl = &pci_tbl[0],
1544 .attach = budget_ci_attach,
1545 .detach = budget_ci_detach,
1547 .irq_mask = MASK_03 | MASK_06 | MASK_10,
1548 .irq_func = budget_ci_irq,
1551 static int __init budget_ci_init(void)
1553 return saa7146_register_extension(&budget_extension);
1556 static void __exit budget_ci_exit(void)
1558 saa7146_unregister_extension(&budget_extension);
1561 module_init(budget_ci_init);
1562 module_exit(budget_ci_exit);
1564 MODULE_LICENSE("GPL");
1565 MODULE_AUTHOR("Michael Hunold, Jack Thomasson, Andrew de Quincey, others");
1566 MODULE_DESCRIPTION("driver for the SAA7146 based so-called "
1567 "budget PCI DVB cards w/ CI-module produced by "
1568 "Siemens, Technotrend, Hauppauge");