drivers/media/dvb/ngene/ngene-core.c

   1 /*
   2  * ngene.c: nGene PCIe bridge driver
   3  *
   4  * Copyright (C) 2005-2007 Micronas
   5  *
   6  * Copyright (C) 2008-2009 Ralph Metzler <rjkm@metzlerbros.de>
   7  *                         Modifications for new nGene firmware,
   8  *                         support for EEPROM-copying,
   9  *                         support for new dual DVB-S2 card prototype
  10  *
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * version 2 only, as published by the Free Software Foundation.
  15  *
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  26  * 02110-1301, USA
  27  * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
  28  */
  29
  30 #include <linux/module.h>
  31 #include <linux/init.h>
  32 #include <linux/delay.h>
  33 #include <linux/poll.h>
  34 #include <linux/io.h>
  35 #include <asm/div64.h>
  36 #include <linux/pci.h>
  37 #include <linux/pci_ids.h>
  38 #include <linux/smp_lock.h>
  39 #include <linux/timer.h>
  40 #include <linux/byteorder/generic.h>
  41 #include <linux/firmware.h>
  42 #include <linux/vmalloc.h>
  43
  44 #include "ngene.h"
  45
  46 #include "stv6110x.h"
  47 #include "stv090x.h"
  48 #include "lnbh24.h"
  49 #include "lgdt330x.h"
  50 #include "mt2131.h"
  51
  52 static int one_adapter = 1;
  53 module_param(one_adapter, int, 0444);
  54 MODULE_PARM_DESC(one_adapter, "Use only one adapter.");
  55
  56
  57 static int debug;
  58 module_param(debug, int, 0444);
  59 MODULE_PARM_DESC(debug, "Print debugging information.");
  60
  61 DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  62
  63 #define COMMAND_TIMEOUT_WORKAROUND
  64
  65 #define dprintk if (debug) printk
  66
  67 #define DEVICE_NAME "ngene"
  68
  69 #define ngwriteb(dat, adr)         writeb((dat), (char *)(dev->iomem + (adr)))
  70 #define ngwritel(dat, adr)         writel((dat), (char *)(dev->iomem + (adr)))
  71 #define ngwriteb(dat, adr)         writeb((dat), (char *)(dev->iomem + (adr)))
  72 #define ngreadl(adr)               readl(dev->iomem + (adr))
  73 #define ngreadb(adr)               readb(dev->iomem + (adr))
  74 #define ngcpyto(adr, src, count)   memcpy_toio((char *) \
  75                                    (dev->iomem + (adr)), (src), (count))
  76 #define ngcpyfrom(dst, adr, count) memcpy_fromio((dst), (char *) \
  77                                    (dev->iomem + (adr)), (count))
  78
  79 /****************************************************************************/
  80 /* nGene interrupt handler **************************************************/
  81 /****************************************************************************/
  82
  83 static void event_tasklet(unsigned long data)
  84 {
  85         struct ngene *dev = (struct ngene *)data;
  86
  87         while (dev->EventQueueReadIndex != dev->EventQueueWriteIndex) {
  88                 struct EVENT_BUFFER Event =
  89                         dev->EventQueue[dev->EventQueueReadIndex];
  90                 dev->EventQueueReadIndex =
  91                         (dev->EventQueueReadIndex + 1) & (EVENT_QUEUE_SIZE - 1);
  92
  93                 if ((Event.UARTStatus & 0x01) && (dev->TxEventNotify))
  94                         dev->TxEventNotify(dev, Event.TimeStamp);
  95                 if ((Event.UARTStatus & 0x02) && (dev->RxEventNotify))
  96                         dev->RxEventNotify(dev, Event.TimeStamp,
  97                                            Event.RXCharacter);
  98         }
  99 }
 100
 101 static void demux_tasklet(unsigned long data)
 102 {
 103         struct ngene_channel *chan = (struct ngene_channel *)data;
 104         struct SBufferHeader *Cur = chan->nextBuffer;
 105
 106         spin_lock_irq(&chan->state_lock);
 107
 108         while (Cur->ngeneBuffer.SR.Flags & 0x80) {
 109                 if (chan->mode & NGENE_IO_TSOUT) {
 110                         u32 Flags = chan->DataFormatFlags;
 111                         if (Cur->ngeneBuffer.SR.Flags & 0x20)
 112                                 Flags |= BEF_OVERFLOW;
 113                         if (chan->pBufferExchange) {
 114                                 if (!chan->pBufferExchange(chan,
 115                                                            Cur->Buffer1,
 116                                                            chan->Capture1Length,
 117                                                            Cur->ngeneBuffer.SR.
 118                                                            Clock, Flags)) {
 119                                         /*
 120                                            We didn't get data
 121                                            Clear in service flag to make sure we
 122                                            get called on next interrupt again.
 123                                            leave fill/empty (0x80) flag alone
 124                                            to avoid hardware running out of
 125                                            buffers during startup, we hold only
 126                                            in run state ( the source may be late
 127                                            delivering data )
 128                                         */
 129
 130                                         if (chan->HWState == HWSTATE_RUN) {
 131                                                 Cur->ngeneBuffer.SR.Flags &=
 132                                                         ~0x40;
 133                                                 break;
 134                                                 /* Stop proccessing stream */
 135                                         }
 136                                 } else {
 137                                         /* We got a valid buffer,
 138                                            so switch to run state */
 139                                         chan->HWState = HWSTATE_RUN;
 140                                 }
 141                         } else {
 142                                 printk(KERN_ERR DEVICE_NAME ": OOPS\n");
 143                                 if (chan->HWState == HWSTATE_RUN) {
 144                                         Cur->ngeneBuffer.SR.Flags &= ~0x40;
 145                                         break;  /* Stop proccessing stream */
 146                                 }
 147                         }
 148                         if (chan->AudioDTOUpdated) {
 149                                 printk(KERN_INFO DEVICE_NAME
 150                                        ": Update AudioDTO = %d\n",
 151                                        chan->AudioDTOValue);
 152                                 Cur->ngeneBuffer.SR.DTOUpdate =
 153                                         chan->AudioDTOValue;
 154                                 chan->AudioDTOUpdated = 0;
 155                         }
 156                 } else {
 157                         if (chan->HWState == HWSTATE_RUN) {
 158                                 u32 Flags = 0;
 159                                 if (Cur->ngeneBuffer.SR.Flags & 0x01)
 160                                         Flags |= BEF_EVEN_FIELD;
 161                                 if (Cur->ngeneBuffer.SR.Flags & 0x20)
 162                                         Flags |= BEF_OVERFLOW;
 163                                 if (chan->pBufferExchange)
 164                                         chan->pBufferExchange(chan,
 165                                                               Cur->Buffer1,
 166                                                               chan->
 167                                                               Capture1Length,
 168                                                               Cur->ngeneBuffer.
 169                                                               SR.Clock, Flags);
 170                                 if (chan->pBufferExchange2)
 171                                         chan->pBufferExchange2(chan,
 172                                                                Cur->Buffer2,
 173                                                                chan->
 174                                                                Capture2Length,
 175                                                                Cur->ngeneBuffer.
 176                                                                SR.Clock, Flags);
 177                         } else if (chan->HWState != HWSTATE_STOP)
 178                                 chan->HWState = HWSTATE_RUN;
 179                 }
 180                 Cur->ngeneBuffer.SR.Flags = 0x00;
 181                 Cur = Cur->Next;
 182         }
 183         chan->nextBuffer = Cur;
 184
 185         spin_unlock_irq(&chan->state_lock);
 186 }
 187
 188 static irqreturn_t irq_handler(int irq, void *dev_id)
 189 {
 190         struct ngene *dev = (struct ngene *)dev_id;
 191         u32 icounts = 0;
 192         irqreturn_t rc = IRQ_NONE;
 193         u32 i = MAX_STREAM;
 194         u8 *tmpCmdDoneByte;
 195
 196         if (dev->BootFirmware) {
 197                 icounts = ngreadl(NGENE_INT_COUNTS);
 198                 if (icounts != dev->icounts) {
 199                         ngwritel(0, FORCE_NMI);
 200                         dev->cmd_done = 1;
 201                         wake_up(&dev->cmd_wq);
 202                         dev->icounts = icounts;
 203                         rc = IRQ_HANDLED;
 204                 }
 205                 return rc;
 206         }
 207
 208         ngwritel(0, FORCE_NMI);
 209
 210         spin_lock(&dev->cmd_lock);
 211         tmpCmdDoneByte = dev->CmdDoneByte;
 212         if (tmpCmdDoneByte &&
 213             (*tmpCmdDoneByte ||
 214             (dev->ngenetohost[0] == 1 && dev->ngenetohost[1] != 0))) {
 215                 dev->CmdDoneByte = NULL;
 216                 dev->cmd_done = 1;
 217                 wake_up(&dev->cmd_wq);
 218                 rc = IRQ_HANDLED;
 219         }
 220         spin_unlock(&dev->cmd_lock);
 221
 222         if (dev->EventBuffer->EventStatus & 0x80) {
 223                 u8 nextWriteIndex =
 224                         (dev->EventQueueWriteIndex + 1) &
 225                         (EVENT_QUEUE_SIZE - 1);
 226                 if (nextWriteIndex != dev->EventQueueReadIndex) {
 227                         dev->EventQueue[dev->EventQueueWriteIndex] =
 228                                 *(dev->EventBuffer);
 229                         dev->EventQueueWriteIndex = nextWriteIndex;
 230                 } else {
 231                         printk(KERN_ERR DEVICE_NAME ": event overflow\n");
 232                         dev->EventQueueOverflowCount += 1;
 233                         dev->EventQueueOverflowFlag = 1;
 234                 }
 235                 dev->EventBuffer->EventStatus &= ~0x80;
 236                 tasklet_schedule(&dev->event_tasklet);
 237                 rc = IRQ_HANDLED;
 238         }
 239
 240         while (i > 0) {
 241                 i--;
 242                 spin_lock(&dev->channel[i].state_lock);
 243                 /* if (dev->channel[i].State>=KSSTATE_RUN) { */
 244                 if (dev->channel[i].nextBuffer) {
 245                         if ((dev->channel[i].nextBuffer->
 246                              ngeneBuffer.SR.Flags & 0xC0) == 0x80) {
 247                                 dev->channel[i].nextBuffer->
 248                                         ngeneBuffer.SR.Flags |= 0x40;
 249                                 tasklet_schedule(
 250                                         &dev->channel[i].demux_tasklet);
 251                                 rc = IRQ_HANDLED;
 252                         }
 253                 }
 254                 spin_unlock(&dev->channel[i].state_lock);
 255         }
 256
 257         /* Request might have been processed by a previous call. */
 258         return IRQ_HANDLED;
 259 }
 260
 261 /****************************************************************************/
 262 /* nGene command interface **************************************************/
 263 /****************************************************************************/
 264
 265 static void dump_command_io(struct ngene *dev)
 266 {
 267         u8 buf[8], *b;
 268
 269         ngcpyfrom(buf, HOST_TO_NGENE, 8);
 270         printk(KERN_ERR "host_to_ngene (%04x): %02x %02x %02x %02x %02x %02x %02x %02x\n",
 271                 HOST_TO_NGENE, buf[0], buf[1], buf[2], buf[3],
 272                 buf[4], buf[5], buf[6], buf[7]);
 273
 274         ngcpyfrom(buf, NGENE_TO_HOST, 8);
 275         printk(KERN_ERR "ngene_to_host (%04x): %02x %02x %02x %02x %02x %02x %02x %02x\n",
 276                 NGENE_TO_HOST, buf[0], buf[1], buf[2], buf[3],
 277                 buf[4], buf[5], buf[6], buf[7]);
 278
 279         b = dev->hosttongene;
 280         printk(KERN_ERR "dev->hosttongene (%p): %02x %02x %02x %02x %02x %02x %02x %02x\n",
 281                 b, b[0], b[1], b[2], b[3], b[4], b[5], b[6], b[7]);
 282
 283         b = dev->ngenetohost;
 284         printk(KERN_ERR "dev->ngenetohost (%p): %02x %02x %02x %02x %02x %02x %02x %02x\n",
 285                 b, b[0], b[1], b[2], b[3], b[4], b[5], b[6], b[7]);
 286 }
 287
 288 static int ngene_command_mutex(struct ngene *dev, struct ngene_command *com)
 289 {
 290         int ret;
 291         u8 *tmpCmdDoneByte;
 292
 293         dev->cmd_done = 0;
 294
 295         if (com->cmd.hdr.Opcode == CMD_FWLOAD_PREPARE) {
 296                 dev->BootFirmware = 1;
 297                 dev->icounts = ngreadl(NGENE_INT_COUNTS);
 298                 ngwritel(0, NGENE_COMMAND);
 299                 ngwritel(0, NGENE_COMMAND_HI);
 300                 ngwritel(0, NGENE_STATUS);
 301                 ngwritel(0, NGENE_STATUS_HI);
 302                 ngwritel(0, NGENE_EVENT);
 303                 ngwritel(0, NGENE_EVENT_HI);
 304         } else if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH) {
 305                 u64 fwio = dev->PAFWInterfaceBuffer;
 306
 307                 ngwritel(fwio & 0xffffffff, NGENE_COMMAND);
 308                 ngwritel(fwio >> 32, NGENE_COMMAND_HI);
 309                 ngwritel((fwio + 256) & 0xffffffff, NGENE_STATUS);
 310                 ngwritel((fwio + 256) >> 32, NGENE_STATUS_HI);
 311                 ngwritel((fwio + 512) & 0xffffffff, NGENE_EVENT);
 312                 ngwritel((fwio + 512) >> 32, NGENE_EVENT_HI);
 313         }
 314
 315         memcpy(dev->FWInterfaceBuffer, com->cmd.raw8, com->in_len + 2);
 316
 317         if (dev->BootFirmware)
 318                 ngcpyto(HOST_TO_NGENE, com->cmd.raw8, com->in_len + 2);
 319
 320         spin_lock_irq(&dev->cmd_lock);
 321         tmpCmdDoneByte = dev->ngenetohost + com->out_len;
 322         if (!com->out_len)
 323                 tmpCmdDoneByte++;
 324         *tmpCmdDoneByte = 0;
 325         dev->ngenetohost[0] = 0;
 326         dev->ngenetohost[1] = 0;
 327         dev->CmdDoneByte = tmpCmdDoneByte;
 328         spin_unlock_irq(&dev->cmd_lock);
 329
 330         /* Notify 8051. */
 331         ngwritel(1, FORCE_INT);
 332
 333         ret = wait_event_timeout(dev->cmd_wq, dev->cmd_done == 1, 2 * HZ);
 334         if (!ret) {
 335                 /*ngwritel(0, FORCE_NMI);*/
 336
 337                 printk(KERN_ERR DEVICE_NAME
 338                        ": Command timeout cmd=%02x prev=%02x\n",
 339                        com->cmd.hdr.Opcode, dev->prev_cmd);
 340                 dump_command_io(dev);
 341                 return -1;
 342         }
 343         if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH)
 344                 dev->BootFirmware = 0;
 345
 346         dev->prev_cmd = com->cmd.hdr.Opcode;
 347
 348         if (!com->out_len)
 349                 return 0;
 350
 351         memcpy(com->cmd.raw8, dev->ngenetohost, com->out_len);
 352
 353         return 0;
 354 }
 355
 356 int ngene_command(struct ngene *dev, struct ngene_command *com)
 357 {
 358         int result;
 359
 360         down(&dev->cmd_mutex);
 361         result = ngene_command_mutex(dev, com);
 362         up(&dev->cmd_mutex);
 363         return result;
 364 }
 365
 366
 367 static int ngene_command_load_firmware(struct ngene *dev,
 368                                        u8 *ngene_fw, u32 size)
 369 {
 370 #define FIRSTCHUNK (1024)
 371         u32 cleft;
 372         struct ngene_command com;
 373
 374         com.cmd.hdr.Opcode = CMD_FWLOAD_PREPARE;
 375         com.cmd.hdr.Length = 0;
 376         com.in_len = 0;
 377         com.out_len = 0;
 378
 379         ngene_command(dev, &com);
 380
 381         cleft = (size + 3) & ~3;
 382         if (cleft > FIRSTCHUNK) {
 383                 ngcpyto(PROGRAM_SRAM + FIRSTCHUNK, ngene_fw + FIRSTCHUNK,
 384                         cleft - FIRSTCHUNK);
 385                 cleft = FIRSTCHUNK;
 386         }
 387         ngcpyto(DATA_FIFO_AREA, ngene_fw, cleft);
 388
 389         memset(&com, 0, sizeof(struct ngene_command));
 390         com.cmd.hdr.Opcode = CMD_FWLOAD_FINISH;
 391         com.cmd.hdr.Length = 4;
 392         com.cmd.FWLoadFinish.Address = DATA_FIFO_AREA;
 393         com.cmd.FWLoadFinish.Length = (unsigned short)cleft;
 394         com.in_len = 4;
 395         com.out_len = 0;
 396
 397         return ngene_command(dev, &com);
 398 }
 399
 400
 401 static int ngene_command_config_buf(struct ngene *dev, u8 config)
 402 {
 403         struct ngene_command com;
 404
 405         com.cmd.hdr.Opcode = CMD_CONFIGURE_BUFFER;
 406         com.cmd.hdr.Length = 1;
 407         com.cmd.ConfigureBuffers.config = config;
 408         com.in_len = 1;
 409         com.out_len = 0;
 410
 411         if (ngene_command(dev, &com) < 0)
 412                 return -EIO;
 413         return 0;
 414 }
 415
 416 static int ngene_command_config_free_buf(struct ngene *dev, u8 *config)
 417 {
 418         struct ngene_command com;
 419
 420         com.cmd.hdr.Opcode = CMD_CONFIGURE_FREE_BUFFER;
 421         com.cmd.hdr.Length = 6;
 422         memcpy(&com.cmd.ConfigureBuffers.config, config, 6);
 423         com.in_len = 6;
 424         com.out_len = 0;
 425
 426         if (ngene_command(dev, &com) < 0)
 427                 return -EIO;
 428
 429         return 0;
 430 }
 431
 432 int ngene_command_gpio_set(struct ngene *dev, u8 select, u8 level)
 433 {
 434         struct ngene_command com;
 435
 436         com.cmd.hdr.Opcode = CMD_SET_GPIO_PIN;
 437         com.cmd.hdr.Length = 1;
 438         com.cmd.SetGpioPin.select = select | (level << 7);
 439         com.in_len = 1;
 440         com.out_len = 0;
 441
 442         return ngene_command(dev, &com);
 443 }
 444
 445
 446 /*
 447  02000640 is sample on rising edge.
 448  02000740 is sample on falling edge.
 449  02000040 is ignore "valid" signal
 450
 451  0: FD_CTL1 Bit 7,6 must be 0,1
 452     7   disable(fw controlled)
 453     6   0-AUX,1-TS
 454     5   0-par,1-ser
 455     4   0-lsb/1-msb
 456     3,2 reserved
 457     1,0 0-no sync, 1-use ext. start, 2-use 0x47, 3-both
 458  1: FD_CTL2 has 3-valid must be hi, 2-use valid, 1-edge
 459  2: FD_STA is read-only. 0-sync
 460  3: FD_INSYNC is number of 47s to trigger "in sync".
 461  4: FD_OUTSYNC is number of 47s to trigger "out of sync".
 462  5: FD_MAXBYTE1 is low-order of bytes per packet.
 463  6: FD_MAXBYTE2 is high-order of bytes per packet.
 464  7: Top byte is unused.
 465 */
 466
 467 /****************************************************************************/
 468
 469 static u8 TSFeatureDecoderSetup[8 * 5] = {
 470         0x42, 0x00, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00,
 471         0x40, 0x06, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXH */
 472         0x71, 0x07, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXHser */
 473         0x72, 0x06, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* S2ser */
 474         0x40, 0x07, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* LGDT3303 */
 475 };
 476
 477 /* Set NGENE I2S Config to 16 bit packed */
 478 static u8 I2SConfiguration[] = {
 479         0x00, 0x10, 0x00, 0x00,
 480         0x80, 0x10, 0x00, 0x00,
 481 };
 482
 483 static u8 SPDIFConfiguration[10] = {
 484         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
 485 };
 486
 487 /* Set NGENE I2S Config to transport stream compatible mode */
 488
 489 static u8 TS_I2SConfiguration[4] = { 0x3E, 0x1A, 0x00, 0x00 }; /*3e 18 00 00 ?*/
 490
 491 static u8 TS_I2SOutConfiguration[4] = { 0x80, 0x20, 0x00, 0x00 };
 492
 493 static u8 ITUDecoderSetup[4][16] = {
 494         {0x1c, 0x13, 0x01, 0x68, 0x3d, 0x90, 0x14, 0x20,  /* SDTV */
 495          0x00, 0x00, 0x01, 0xb0, 0x9c, 0x00, 0x00, 0x00},
 496         {0x9c, 0x03, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00,
 497          0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
 498         {0x9f, 0x00, 0x23, 0xC0, 0x60, 0x0F, 0x13, 0x00,  /* HDTV 1080i50 */
 499          0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
 500         {0x9c, 0x01, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00,  /* HDTV 1080i60 */
 501          0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
 502 };
 503
 504 /*
 505  * 50 48 60 gleich
 506  * 27p50 9f 00 22 80 42 69 18 ...
 507  * 27p60 93 00 22 80 82 69 1c ...
 508  */
 509
 510 /* Maxbyte to 1144 (for raw data) */
 511 static u8 ITUFeatureDecoderSetup[8] = {
 512         0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x04, 0x00
 513 };
 514
 515 static void FillTSBuffer(void *Buffer, int Length, u32 Flags)
 516 {
 517         u32 *ptr = Buffer;
 518
 519         memset(Buffer, 0xff, Length);
 520         while (Length > 0) {
 521                 if (Flags & DF_SWAP32)
 522                         *ptr = 0x471FFF10;
 523                 else
 524                         *ptr = 0x10FF1F47;
 525                 ptr += (188 / 4);
 526                 Length -= 188;
 527         }
 528 }
 529
 530
 531 static void flush_buffers(struct ngene_channel *chan)
 532 {
 533         u8 val;
 534
 535         do {
 536                 msleep(1);
 537                 spin_lock_irq(&chan->state_lock);
 538                 val = chan->nextBuffer->ngeneBuffer.SR.Flags & 0x80;
 539                 spin_unlock_irq(&chan->state_lock);
 540         } while (val);
 541 }
 542
 543 static void clear_buffers(struct ngene_channel *chan)
 544 {
 545         struct SBufferHeader *Cur = chan->nextBuffer;
 546
 547         do {
 548                 memset(&Cur->ngeneBuffer.SR, 0, sizeof(Cur->ngeneBuffer.SR));
 549                 if (chan->mode & NGENE_IO_TSOUT)
 550                         FillTSBuffer(Cur->Buffer1,
 551                                      chan->Capture1Length,
 552                                      chan->DataFormatFlags);
 553                 Cur = Cur->Next;
 554         } while (Cur != chan->nextBuffer);
 555
 556         if (chan->mode & NGENE_IO_TSOUT) {
 557                 chan->nextBuffer->ngeneBuffer.SR.DTOUpdate =
 558                         chan->AudioDTOValue;
 559                 chan->AudioDTOUpdated = 0;
 560
 561                 Cur = chan->TSIdleBuffer.Head;
 562
 563                 do {
 564                         memset(&Cur->ngeneBuffer.SR, 0,
 565                                sizeof(Cur->ngeneBuffer.SR));
 566                         FillTSBuffer(Cur->Buffer1,
 567                                      chan->Capture1Length,
 568                                      chan->DataFormatFlags);
 569                         Cur = Cur->Next;
 570                 } while (Cur != chan->TSIdleBuffer.Head);
 571         }
 572 }
 573
 574 static int ngene_command_stream_control(struct ngene *dev, u8 stream,
 575                                         u8 control, u8 mode, u8 flags)
 576 {
 577         struct ngene_channel *chan = &dev->channel[stream];
 578         struct ngene_command com;
 579         u16 BsUVI = ((stream & 1) ? 0x9400 : 0x9300);
 580         u16 BsSDI = ((stream & 1) ? 0x9600 : 0x9500);
 581         u16 BsSPI = ((stream & 1) ? 0x9800 : 0x9700);
 582         u16 BsSDO = 0x9B00;
 583
 584         /* down(&dev->stream_mutex); */
 585         while (down_trylock(&dev->stream_mutex)) {
 586                 printk(KERN_INFO DEVICE_NAME ": SC locked\n");
 587                 msleep(1);
 588         }
 589         memset(&com, 0, sizeof(com));
 590         com.cmd.hdr.Opcode = CMD_CONTROL;
 591         com.cmd.hdr.Length = sizeof(struct FW_STREAM_CONTROL) - 2;
 592         com.cmd.StreamControl.Stream = stream | (control ? 8 : 0);
 593         if (chan->mode & NGENE_IO_TSOUT)
 594                 com.cmd.StreamControl.Stream |= 0x07;
 595         com.cmd.StreamControl.Control = control |
 596                 (flags & SFLAG_ORDER_LUMA_CHROMA);
 597         com.cmd.StreamControl.Mode = mode;
 598         com.in_len = sizeof(struct FW_STREAM_CONTROL);
 599         com.out_len = 0;
 600
 601         dprintk(KERN_INFO DEVICE_NAME
 602                 ": Stream=%02x, Control=%02x, Mode=%02x\n",
 603                 com.cmd.StreamControl.Stream, com.cmd.StreamControl.Control,
 604                 com.cmd.StreamControl.Mode);
 605
 606         chan->Mode = mode;
 607
 608         if (!(control & 0x80)) {
 609                 spin_lock_irq(&chan->state_lock);
 610                 if (chan->State == KSSTATE_RUN) {
 611                         chan->State = KSSTATE_ACQUIRE;
 612                         chan->HWState = HWSTATE_STOP;
 613                         spin_unlock_irq(&chan->state_lock);
 614                         if (ngene_command(dev, &com) < 0) {
 615                                 up(&dev->stream_mutex);
 616                                 return -1;
 617                         }
 618                         /* clear_buffers(chan); */
 619                         flush_buffers(chan);
 620                         up(&dev->stream_mutex);
 621                         return 0;
 622                 }
 623                 spin_unlock_irq(&chan->state_lock);
 624                 up(&dev->stream_mutex);
 625                 return 0;
 626         }
 627
 628         if (mode & SMODE_AUDIO_CAPTURE) {
 629                 com.cmd.StreamControl.CaptureBlockCount =
 630                         chan->Capture1Length / AUDIO_BLOCK_SIZE;
 631                 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead;
 632         } else if (mode & SMODE_TRANSPORT_STREAM) {
 633                 com.cmd.StreamControl.CaptureBlockCount =
 634                         chan->Capture1Length / TS_BLOCK_SIZE;
 635                 com.cmd.StreamControl.MaxLinesPerField =
 636                         chan->Capture1Length / TS_BLOCK_SIZE;
 637                 com.cmd.StreamControl.Buffer_Address =
 638                         chan->TSRingBuffer.PAHead;
 639                 if (chan->mode & NGENE_IO_TSOUT) {
 640                         com.cmd.StreamControl.BytesPerVBILine =
 641                                 chan->Capture1Length / TS_BLOCK_SIZE;
 642                         com.cmd.StreamControl.Stream |= 0x07;
 643                 }
 644         } else {
 645                 com.cmd.StreamControl.BytesPerVideoLine = chan->nBytesPerLine;
 646                 com.cmd.StreamControl.MaxLinesPerField = chan->nLines;
 647                 com.cmd.StreamControl.MinLinesPerField = 100;
 648                 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead;
 649
 650                 if (mode & SMODE_VBI_CAPTURE) {
 651                         com.cmd.StreamControl.MaxVBILinesPerField =
 652                                 chan->nVBILines;
 653                         com.cmd.StreamControl.MinVBILinesPerField = 0;
 654                         com.cmd.StreamControl.BytesPerVBILine =
 655                                 chan->nBytesPerVBILine;
 656                 }
 657                 if (flags & SFLAG_COLORBAR)
 658                         com.cmd.StreamControl.Stream |= 0x04;
 659         }
 660
 661         spin_lock_irq(&chan->state_lock);
 662         if (mode & SMODE_AUDIO_CAPTURE) {
 663                 chan->nextBuffer = chan->RingBuffer.Head;
 664                 if (mode & SMODE_AUDIO_SPDIF) {
 665                         com.cmd.StreamControl.SetupDataLen =
 666                                 sizeof(SPDIFConfiguration);
 667                         com.cmd.StreamControl.SetupDataAddr = BsSPI;
 668                         memcpy(com.cmd.StreamControl.SetupData,
 669                                SPDIFConfiguration, sizeof(SPDIFConfiguration));
 670                 } else {
 671                         com.cmd.StreamControl.SetupDataLen = 4;
 672                         com.cmd.StreamControl.SetupDataAddr = BsSDI;
 673                         memcpy(com.cmd.StreamControl.SetupData,
 674                                I2SConfiguration +
 675                                4 * dev->card_info->i2s[stream], 4);
 676                 }
 677         } else if (mode & SMODE_TRANSPORT_STREAM) {
 678                 chan->nextBuffer = chan->TSRingBuffer.Head;
 679                 if (stream >= STREAM_AUDIOIN1) {
 680                         if (chan->mode & NGENE_IO_TSOUT) {
 681                                 com.cmd.StreamControl.SetupDataLen =
 682                                         sizeof(TS_I2SOutConfiguration);
 683                                 com.cmd.StreamControl.SetupDataAddr = BsSDO;
 684                                 memcpy(com.cmd.StreamControl.SetupData,
 685                                        TS_I2SOutConfiguration,
 686                                        sizeof(TS_I2SOutConfiguration));
 687                         } else {
 688                                 com.cmd.StreamControl.SetupDataLen =
 689                                         sizeof(TS_I2SConfiguration);
 690                                 com.cmd.StreamControl.SetupDataAddr = BsSDI;
 691                                 memcpy(com.cmd.StreamControl.SetupData,
 692                                        TS_I2SConfiguration,
 693                                        sizeof(TS_I2SConfiguration));
 694                         }
 695                 } else {
 696                         com.cmd.StreamControl.SetupDataLen = 8;
 697                         com.cmd.StreamControl.SetupDataAddr = BsUVI + 0x10;
 698                         memcpy(com.cmd.StreamControl.SetupData,
 699                                TSFeatureDecoderSetup +
 700                                8 * dev->card_info->tsf[stream], 8);
 701                 }
 702         } else {
 703                 chan->nextBuffer = chan->RingBuffer.Head;
 704                 com.cmd.StreamControl.SetupDataLen =
 705                         16 + sizeof(ITUFeatureDecoderSetup);
 706                 com.cmd.StreamControl.SetupDataAddr = BsUVI;
 707                 memcpy(com.cmd.StreamControl.SetupData,
 708                        ITUDecoderSetup[chan->itumode], 16);
 709                 memcpy(com.cmd.StreamControl.SetupData + 16,
 710                        ITUFeatureDecoderSetup, sizeof(ITUFeatureDecoderSetup));
 711         }
 712         clear_buffers(chan);
 713         chan->State = KSSTATE_RUN;
 714         if (mode & SMODE_TRANSPORT_STREAM)
 715                 chan->HWState = HWSTATE_RUN;
 716         else
 717                 chan->HWState = HWSTATE_STARTUP;
 718         spin_unlock_irq(&chan->state_lock);
 719
 720         if (ngene_command(dev, &com) < 0) {
 721                 up(&dev->stream_mutex);
 722                 return -1;
 723         }
 724         up(&dev->stream_mutex);
 725         return 0;
 726 }
 727
 728
 729 /****************************************************************************/
 730 /* EEPROM TAGS **************************************************************/
 731 /****************************************************************************/
 732
 733 /****************************************************************************/
 734 /* DVB functions and API interface ******************************************/
 735 /****************************************************************************/
 736
 737 static void swap_buffer(u32 *p, u32 len)
 738 {
 739         while (len) {
 740                 *p = swab32(*p);
 741                 p++;
 742                 len -= 4;
 743         }
 744 }
 745
 746
 747 static void *tsin_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags)
 748 {
 749         struct ngene_channel *chan = priv;
 750
 751
 752 #ifdef COMMAND_TIMEOUT_WORKAROUND
 753         if (chan->users > 0)
 754 #endif
 755                 dvb_dmx_swfilter(&chan->demux, buf, len);
 756         return NULL;
 757 }
 758
 759 u8 fill_ts[188] = { 0x47, 0x1f, 0xff, 0x10 };
 760
 761 static void *tsout_exchange(void *priv, void *buf, u32 len,
 762                             u32 clock, u32 flags)
 763 {
 764         struct ngene_channel *chan = priv;
 765         struct ngene *dev = chan->dev;
 766         u32 alen;
 767
 768         alen = dvb_ringbuffer_avail(&dev->tsout_rbuf);
 769         alen -= alen % 188;
 770
 771         if (alen < len)
 772                 FillTSBuffer(buf + alen, len - alen, flags);
 773         else
 774                 alen = len;
 775         dvb_ringbuffer_read(&dev->tsout_rbuf, buf, alen);
 776         if (flags & DF_SWAP32)
 777                 swap_buffer((u32 *)buf, alen);
 778         wake_up_interruptible(&dev->tsout_rbuf.queue);
 779         return buf;
 780 }
 781
 782
 783 static void set_transfer(struct ngene_channel *chan, int state)
 784 {
 785         u8 control = 0, mode = 0, flags = 0;
 786         struct ngene *dev = chan->dev;
 787         int ret;
 788
 789         /*
 790         printk(KERN_INFO DEVICE_NAME ": st %d\n", state);
 791         msleep(100);
 792         */
 793
 794         if (state) {
 795                 if (chan->running) {
 796                         printk(KERN_INFO DEVICE_NAME ": already running\n");
 797                         return;
 798                 }
 799         } else {
 800                 if (!chan->running) {
 801                         printk(KERN_INFO DEVICE_NAME ": already stopped\n");
 802                         return;
 803                 }
 804         }
 805
 806         if (dev->card_info->switch_ctrl)
 807                 dev->card_info->switch_ctrl(chan, 1, state ^ 1);
 808
 809         if (state) {
 810                 spin_lock_irq(&chan->state_lock);
 811
 812                 /* printk(KERN_INFO DEVICE_NAME ": lock=%08x\n",
 813                           ngreadl(0x9310)); */
 814                 dvb_ringbuffer_flush(&dev->tsout_rbuf);
 815                 control = 0x80;
 816                 if (chan->mode & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
 817                         chan->Capture1Length = 512 * 188;
 818                         mode = SMODE_TRANSPORT_STREAM;
 819                 }
 820                 if (chan->mode & NGENE_IO_TSOUT) {
 821                         chan->pBufferExchange = tsout_exchange;
 822                         /* 0x66666666 = 50MHz *2^33 /250MHz */
 823                         chan->AudioDTOValue = 0x66666666;
 824                         /* set_dto(chan, 38810700+1000); */
 825                         /* set_dto(chan, 19392658); */
 826                 }
 827                 if (chan->mode & NGENE_IO_TSIN)
 828                         chan->pBufferExchange = tsin_exchange;
 829                 /* ngwritel(0, 0x9310); */
 830                 spin_unlock_irq(&chan->state_lock);
 831         } else
 832                 ;/* printk(KERN_INFO DEVICE_NAME ": lock=%08x\n",
 833                            ngreadl(0x9310)); */
 834
 835         ret = ngene_command_stream_control(dev, chan->number,
 836                                            control, mode, flags);
 837         if (!ret)
 838                 chan->running = state;
 839         else
 840                 printk(KERN_ERR DEVICE_NAME ": set_transfer %d failed\n",
 841                        state);
 842         if (!state) {
 843                 spin_lock_irq(&chan->state_lock);
 844                 chan->pBufferExchange = NULL;
 845                 dvb_ringbuffer_flush(&dev->tsout_rbuf);
 846                 spin_unlock_irq(&chan->state_lock);
 847         }
 848 }
 849
 850 static int ngene_start_feed(struct dvb_demux_feed *dvbdmxfeed)
 851 {
 852         struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
 853         struct ngene_channel *chan = dvbdmx->priv;
 854
 855         if (chan->users == 0) {
 856 #ifdef COMMAND_TIMEOUT_WORKAROUND
 857                 if (!chan->running)
 858 #endif
 859                         set_transfer(chan, 1);
 860                 /* msleep(10); */
 861         }
 862
 863         return ++chan->users;
 864 }
 865
 866 static int ngene_stop_feed(struct dvb_demux_feed *dvbdmxfeed)
 867 {
 868         struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
 869         struct ngene_channel *chan = dvbdmx->priv;
 870
 871         if (--chan->users)
 872                 return chan->users;
 873
 874 #ifndef COMMAND_TIMEOUT_WORKAROUND
 875         set_transfer(chan, 0);
 876 #endif
 877
 878         return 0;
 879 }
 880
 881
 882
 883 static int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id,
 884                                    int (*start_feed)(struct dvb_demux_feed *),
 885                                    int (*stop_feed)(struct dvb_demux_feed *),
 886                                    void *priv)
 887 {
 888         dvbdemux->priv = priv;
 889
 890         dvbdemux->filternum = 256;
 891         dvbdemux->feednum = 256;
 892         dvbdemux->start_feed = start_feed;
 893         dvbdemux->stop_feed = stop_feed;
 894         dvbdemux->write_to_decoder = NULL;
 895         dvbdemux->dmx.capabilities = (DMX_TS_FILTERING |
 896                                       DMX_SECTION_FILTERING |
 897                                       DMX_MEMORY_BASED_FILTERING);
 898         return dvb_dmx_init(dvbdemux);
 899 }
 900
 901 static int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev,
 902                                       struct dvb_demux *dvbdemux,
 903                                       struct dmx_frontend *hw_frontend,
 904                                       struct dmx_frontend *mem_frontend,
 905                                       struct dvb_adapter *dvb_adapter)
 906 {
 907         int ret;
 908
 909         dmxdev->filternum = 256;
 910         dmxdev->demux = &dvbdemux->dmx;
 911         dmxdev->capabilities = 0;
 912         ret = dvb_dmxdev_init(dmxdev, dvb_adapter);
 913         if (ret < 0)
 914                 return ret;
 915
 916         hw_frontend->source = DMX_FRONTEND_0;
 917         dvbdemux->dmx.add_frontend(&dvbdemux->dmx, hw_frontend);
 918         mem_frontend->source = DMX_MEMORY_FE;
 919         dvbdemux->dmx.add_frontend(&dvbdemux->dmx, mem_frontend);
 920         return dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, hw_frontend);
 921 }
 922
 923
 924 /****************************************************************************/
 925 /* nGene hardware init and release functions ********************************/
 926 /****************************************************************************/
 927
 928 static void free_ringbuffer(struct ngene *dev, struct SRingBufferDescriptor *rb)
 929 {
 930         struct SBufferHeader *Cur = rb->Head;
 931         u32 j;
 932
 933         if (!Cur)
 934                 return;
 935
 936         for (j = 0; j < rb->NumBuffers; j++, Cur = Cur->Next) {
 937                 if (Cur->Buffer1)
 938                         pci_free_consistent(dev->pci_dev,
 939                                             rb->Buffer1Length,
 940                                             Cur->Buffer1,
 941                                             Cur->scList1->Address);
 942
 943                 if (Cur->Buffer2)
 944                         pci_free_consistent(dev->pci_dev,
 945                                             rb->Buffer2Length,
 946                                             Cur->Buffer2,
 947                                             Cur->scList2->Address);
 948         }
 949
 950         if (rb->SCListMem)
 951                 pci_free_consistent(dev->pci_dev, rb->SCListMemSize,
 952                                     rb->SCListMem, rb->PASCListMem);
 953
 954         pci_free_consistent(dev->pci_dev, rb->MemSize, rb->Head, rb->PAHead);
 955 }
 956
 957 static void free_idlebuffer(struct ngene *dev,
 958                      struct SRingBufferDescriptor *rb,
 959                      struct SRingBufferDescriptor *tb)
 960 {
 961         int j;
 962         struct SBufferHeader *Cur = tb->Head;
 963
 964         if (!rb->Head)
 965                 return;
 966         free_ringbuffer(dev, rb);
 967         for (j = 0; j < tb->NumBuffers; j++, Cur = Cur->Next) {
 968                 Cur->Buffer2 = NULL;
 969                 Cur->scList2 = NULL;
 970                 Cur->ngeneBuffer.Address_of_first_entry_2 = 0;
 971                 Cur->ngeneBuffer.Number_of_entries_2 = 0;
 972         }
 973 }
 974
 975 static void free_common_buffers(struct ngene *dev)
 976 {
 977         u32 i;
 978         struct ngene_channel *chan;
 979
 980         for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) {
 981                 chan = &dev->channel[i];
 982                 free_idlebuffer(dev, &chan->TSIdleBuffer, &chan->TSRingBuffer);
 983                 free_ringbuffer(dev, &chan->RingBuffer);
 984                 free_ringbuffer(dev, &chan->TSRingBuffer);
 985         }
 986
 987         if (dev->OverflowBuffer)
 988                 pci_free_consistent(dev->pci_dev,
 989                                     OVERFLOW_BUFFER_SIZE,
 990                                     dev->OverflowBuffer, dev->PAOverflowBuffer);
 991
 992         if (dev->FWInterfaceBuffer)
 993                 pci_free_consistent(dev->pci_dev,
 994                                     4096,
 995                                     dev->FWInterfaceBuffer,
 996                                     dev->PAFWInterfaceBuffer);
 997 }
 998
 999 /****************************************************************************/
1000 /* Ring buffer handling *****************************************************/
1001 /****************************************************************************/
1002
1003 static int create_ring_buffer(struct pci_dev *pci_dev,
1004                        struct SRingBufferDescriptor *descr, u32 NumBuffers)
1005 {
1006         dma_addr_t tmp;
1007         struct SBufferHeader *Head;
1008         u32 i;
1009         u32 MemSize = SIZEOF_SBufferHeader * NumBuffers;
1010         u64 PARingBufferHead;
1011         u64 PARingBufferCur;
1012         u64 PARingBufferNext;
1013         struct SBufferHeader *Cur, *Next;
1014
1015         descr->Head = NULL;
1016         descr->MemSize = 0;
1017         descr->PAHead = 0;
1018         descr->NumBuffers = 0;
1019
1020         if (MemSize < 4096)
1021                 MemSize = 4096;
1022
1023         Head = pci_alloc_consistent(pci_dev, MemSize, &tmp);
1024         PARingBufferHead = tmp;
1025
1026         if (!Head)
1027                 return -ENOMEM;
1028
1029         memset(Head, 0, MemSize);
1030
1031         PARingBufferCur = PARingBufferHead;
1032         Cur = Head;
1033
1034         for (i = 0; i < NumBuffers - 1; i++) {
1035                 Next = (struct SBufferHeader *)
1036                         (((u8 *) Cur) + SIZEOF_SBufferHeader);
1037                 PARingBufferNext = PARingBufferCur + SIZEOF_SBufferHeader;
1038                 Cur->Next = Next;
1039                 Cur->ngeneBuffer.Next = PARingBufferNext;
1040                 Cur = Next;
1041                 PARingBufferCur = PARingBufferNext;
1042         }
1043         /* Last Buffer points back to first one */
1044         Cur->Next = Head;
1045         Cur->ngeneBuffer.Next = PARingBufferHead;
1046
1047         descr->Head       = Head;
1048         descr->MemSize    = MemSize;
1049         descr->PAHead     = PARingBufferHead;
1050         descr->NumBuffers = NumBuffers;
1051
1052         return 0;
1053 }
1054
1055 static int AllocateRingBuffers(struct pci_dev *pci_dev,
1056                                dma_addr_t of,
1057                                struct SRingBufferDescriptor *pRingBuffer,
1058                                u32 Buffer1Length, u32 Buffer2Length)
1059 {
1060         dma_addr_t tmp;
1061         u32 i, j;
1062         int status = 0;
1063         u32 SCListMemSize = pRingBuffer->NumBuffers
1064                 * ((Buffer2Length != 0) ? (NUM_SCATTER_GATHER_ENTRIES * 2) :
1065                     NUM_SCATTER_GATHER_ENTRIES)
1066                 * sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1067
1068         u64 PASCListMem;
1069         struct HW_SCATTER_GATHER_ELEMENT *SCListEntry;
1070         u64 PASCListEntry;
1071         struct SBufferHeader *Cur;
1072         void *SCListMem;
1073
1074         if (SCListMemSize < 4096)
1075                 SCListMemSize = 4096;
1076
1077         SCListMem = pci_alloc_consistent(pci_dev, SCListMemSize, &tmp);
1078
1079         PASCListMem = tmp;
1080         if (SCListMem == NULL)
1081                 return -ENOMEM;
1082
1083         memset(SCListMem, 0, SCListMemSize);
1084
1085         pRingBuffer->SCListMem = SCListMem;
1086         pRingBuffer->PASCListMem = PASCListMem;
1087         pRingBuffer->SCListMemSize = SCListMemSize;
1088         pRingBuffer->Buffer1Length = Buffer1Length;
1089         pRingBuffer->Buffer2Length = Buffer2Length;
1090
1091         SCListEntry = SCListMem;
1092         PASCListEntry = PASCListMem;
1093         Cur = pRingBuffer->Head;
1094
1095         for (i = 0; i < pRingBuffer->NumBuffers; i += 1, Cur = Cur->Next) {
1096                 u64 PABuffer;
1097
1098                 void *Buffer = pci_alloc_consistent(pci_dev, Buffer1Length,
1099                                                     &tmp);
1100                 PABuffer = tmp;
1101
1102                 if (Buffer == NULL)
1103                         return -ENOMEM;
1104
1105                 Cur->Buffer1 = Buffer;
1106
1107                 SCListEntry->Address = PABuffer;
1108                 SCListEntry->Length  = Buffer1Length;
1109
1110                 Cur->scList1 = SCListEntry;
1111                 Cur->ngeneBuffer.Address_of_first_entry_1 = PASCListEntry;
1112                 Cur->ngeneBuffer.Number_of_entries_1 =
1113                         NUM_SCATTER_GATHER_ENTRIES;
1114
1115                 SCListEntry += 1;
1116                 PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1117
1118 #if NUM_SCATTER_GATHER_ENTRIES > 1
1119                 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j += 1) {
1120                         SCListEntry->Address = of;
1121                         SCListEntry->Length = OVERFLOW_BUFFER_SIZE;
1122                         SCListEntry += 1;
1123                         PASCListEntry +=
1124                                 sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1125                 }
1126 #endif
1127
1128                 if (!Buffer2Length)
1129                         continue;
1130
1131                 Buffer = pci_alloc_consistent(pci_dev, Buffer2Length, &tmp);
1132                 PABuffer = tmp;
1133
1134                 if (Buffer == NULL)
1135                         return -ENOMEM;
1136
1137                 Cur->Buffer2 = Buffer;
1138
1139                 SCListEntry->Address = PABuffer;
1140                 SCListEntry->Length  = Buffer2Length;
1141
1142                 Cur->scList2 = SCListEntry;
1143                 Cur->ngeneBuffer.Address_of_first_entry_2 = PASCListEntry;
1144                 Cur->ngeneBuffer.Number_of_entries_2 =
1145                         NUM_SCATTER_GATHER_ENTRIES;
1146
1147                 SCListEntry   += 1;
1148                 PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1149
1150 #if NUM_SCATTER_GATHER_ENTRIES > 1
1151                 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j++) {
1152                         SCListEntry->Address = of;
1153                         SCListEntry->Length = OVERFLOW_BUFFER_SIZE;
1154                         SCListEntry += 1;
1155                         PASCListEntry +=
1156                                 sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1157                 }
1158 #endif
1159
1160         }
1161
1162         return status;
1163 }
1164
1165 static int FillTSIdleBuffer(struct SRingBufferDescriptor *pIdleBuffer,
1166                             struct SRingBufferDescriptor *pRingBuffer)
1167 {
1168         int status = 0;
1169
1170         /* Copy pointer to scatter gather list in TSRingbuffer
1171            structure for buffer 2
1172            Load number of buffer
1173         */
1174         u32 n = pRingBuffer->NumBuffers;
1175
1176         /* Point to first buffer entry */
1177         struct SBufferHeader *Cur = pRingBuffer->Head;
1178         int i;
1179         /* Loop thru all buffer and set Buffer 2 pointers to TSIdlebuffer */
1180         for (i = 0; i < n; i++) {
1181                 Cur->Buffer2 = pIdleBuffer->Head->Buffer1;
1182                 Cur->scList2 = pIdleBuffer->Head->scList1;
1183                 Cur->ngeneBuffer.Address_of_first_entry_2 =
1184                         pIdleBuffer->Head->ngeneBuffer.
1185                         Address_of_first_entry_1;
1186                 Cur->ngeneBuffer.Number_of_entries_2 =
1187                         pIdleBuffer->Head->ngeneBuffer.Number_of_entries_1;
1188                 Cur = Cur->Next;
1189         }
1190         return status;
1191 }
1192
1193 static u32 RingBufferSizes[MAX_STREAM] = {
1194         RING_SIZE_VIDEO,
1195         RING_SIZE_VIDEO,
1196         RING_SIZE_AUDIO,
1197         RING_SIZE_AUDIO,
1198         RING_SIZE_AUDIO,
1199 };
1200
1201 static u32 Buffer1Sizes[MAX_STREAM] = {
1202         MAX_VIDEO_BUFFER_SIZE,
1203         MAX_VIDEO_BUFFER_SIZE,
1204         MAX_AUDIO_BUFFER_SIZE,
1205         MAX_AUDIO_BUFFER_SIZE,
1206         MAX_AUDIO_BUFFER_SIZE
1207 };
1208
1209 static u32 Buffer2Sizes[MAX_STREAM] = {
1210         MAX_VBI_BUFFER_SIZE,
1211         MAX_VBI_BUFFER_SIZE,
1212         0,
1213         0,
1214         0
1215 };
1216
1217
1218 static int AllocCommonBuffers(struct ngene *dev)
1219 {
1220         int status = 0, i;
1221
1222         dev->FWInterfaceBuffer = pci_alloc_consistent(dev->pci_dev, 4096,
1223                                                      &dev->PAFWInterfaceBuffer);
1224         if (!dev->FWInterfaceBuffer)
1225                 return -ENOMEM;
1226         dev->hosttongene = dev->FWInterfaceBuffer;
1227         dev->ngenetohost = dev->FWInterfaceBuffer + 256;
1228         dev->EventBuffer = dev->FWInterfaceBuffer + 512;
1229
1230         dev->OverflowBuffer = pci_alloc_consistent(dev->pci_dev,
1231                                                    OVERFLOW_BUFFER_SIZE,
1232                                                    &dev->PAOverflowBuffer);
1233         if (!dev->OverflowBuffer)
1234                 return -ENOMEM;
1235         memset(dev->OverflowBuffer, 0, OVERFLOW_BUFFER_SIZE);
1236
1237         for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) {
1238                 int type = dev->card_info->io_type[i];
1239
1240                 dev->channel[i].State = KSSTATE_STOP;
1241
1242                 if (type & (NGENE_IO_TV | NGENE_IO_HDTV | NGENE_IO_AIN)) {
1243                         status = create_ring_buffer(dev->pci_dev,
1244                                                     &dev->channel[i].RingBuffer,
1245                                                     RingBufferSizes[i]);
1246                         if (status < 0)
1247                                 break;
1248
1249                         if (type & (NGENE_IO_TV | NGENE_IO_AIN)) {
1250                                 status = AllocateRingBuffers(dev->pci_dev,
1251                                                              dev->
1252                                                              PAOverflowBuffer,
1253                                                              &dev->channel[i].
1254                                                              RingBuffer,
1255                                                              Buffer1Sizes[i],
1256                                                              Buffer2Sizes[i]);
1257                                 if (status < 0)
1258                                         break;
1259                         } else if (type & NGENE_IO_HDTV) {
1260                                 status = AllocateRingBuffers(dev->pci_dev,
1261                                                              dev->
1262                                                              PAOverflowBuffer,
1263                                                              &dev->channel[i].
1264                                                              RingBuffer,
1265                                                            MAX_HDTV_BUFFER_SIZE,
1266                                                              0);
1267                                 if (status < 0)
1268                                         break;
1269                         }
1270                 }
1271
1272                 if (type & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
1273
1274                         status = create_ring_buffer(dev->pci_dev,
1275                                                     &dev->channel[i].
1276                                                     TSRingBuffer, RING_SIZE_TS);
1277                         if (status < 0)
1278                                 break;
1279
1280                         status = AllocateRingBuffers(dev->pci_dev,
1281                                                      dev->PAOverflowBuffer,
1282                                                      &dev->channel[i].
1283                                                      TSRingBuffer,
1284                                                      MAX_TS_BUFFER_SIZE, 0);
1285                         if (status)
1286                                 break;
1287                 }
1288
1289                 if (type & NGENE_IO_TSOUT) {
1290                         status = create_ring_buffer(dev->pci_dev,
1291                                                     &dev->channel[i].
1292                                                     TSIdleBuffer, 1);
1293                         if (status < 0)
1294                                 break;
1295                         status = AllocateRingBuffers(dev->pci_dev,
1296                                                      dev->PAOverflowBuffer,
1297                                                      &dev->channel[i].
1298                                                      TSIdleBuffer,
1299                                                      MAX_TS_BUFFER_SIZE, 0);
1300                         if (status)
1301                                 break;
1302                         FillTSIdleBuffer(&dev->channel[i].TSIdleBuffer,
1303                                          &dev->channel[i].TSRingBuffer);
1304                 }
1305         }
1306         return status;
1307 }
1308
1309 static void ngene_release_buffers(struct ngene *dev)
1310 {
1311         if (dev->iomem)
1312                 iounmap(dev->iomem);
1313         free_common_buffers(dev);
1314         vfree(dev->tsout_buf);
1315         vfree(dev->ain_buf);
1316         vfree(dev->vin_buf);
1317         vfree(dev);
1318 }
1319
1320 static int ngene_get_buffers(struct ngene *dev)
1321 {
1322         if (AllocCommonBuffers(dev))
1323                 return -ENOMEM;
1324         if (dev->card_info->io_type[4] & NGENE_IO_TSOUT) {
1325                 dev->tsout_buf = vmalloc(TSOUT_BUF_SIZE);
1326                 if (!dev->tsout_buf)
1327                         return -ENOMEM;
1328                 dvb_ringbuffer_init(&dev->tsout_rbuf,
1329                                     dev->tsout_buf, TSOUT_BUF_SIZE);
1330         }
1331         if (dev->card_info->io_type[2] & NGENE_IO_AIN) {
1332                 dev->ain_buf = vmalloc(AIN_BUF_SIZE);
1333                 if (!dev->ain_buf)
1334                         return -ENOMEM;
1335                 dvb_ringbuffer_init(&dev->ain_rbuf, dev->ain_buf, AIN_BUF_SIZE);
1336         }
1337         if (dev->card_info->io_type[0] & NGENE_IO_HDTV) {
1338                 dev->vin_buf = vmalloc(VIN_BUF_SIZE);
1339                 if (!dev->vin_buf)
1340                         return -ENOMEM;
1341                 dvb_ringbuffer_init(&dev->vin_rbuf, dev->vin_buf, VIN_BUF_SIZE);
1342         }
1343         dev->iomem = ioremap(pci_resource_start(dev->pci_dev, 0),
1344                              pci_resource_len(dev->pci_dev, 0));
1345         if (!dev->iomem)
1346                 return -ENOMEM;
1347
1348         return 0;
1349 }
1350
1351 static void ngene_init(struct ngene *dev)
1352 {
1353         int i;
1354
1355         tasklet_init(&dev->event_tasklet, event_tasklet, (unsigned long)dev);
1356
1357         memset_io(dev->iomem + 0xc000, 0x00, 0x220);
1358         memset_io(dev->iomem + 0xc400, 0x00, 0x100);
1359
1360         for (i = 0; i < MAX_STREAM; i++) {
1361                 dev->channel[i].dev = dev;
1362                 dev->channel[i].number = i;
1363         }
1364
1365         dev->fw_interface_version = 0;
1366
1367         ngwritel(0, NGENE_INT_ENABLE);
1368
1369         dev->icounts = ngreadl(NGENE_INT_COUNTS);
1370
1371         dev->device_version = ngreadl(DEV_VER) & 0x0f;
1372         printk(KERN_INFO DEVICE_NAME ": Device version %d\n",
1373                dev->device_version);
1374 }
1375
1376 static int ngene_load_firm(struct ngene *dev)
1377 {
1378         u32 size;
1379         const struct firmware *fw = NULL;
1380         u8 *ngene_fw;
1381         char *fw_name;
1382         int err, version;
1383
1384         version = dev->card_info->fw_version;
1385
1386         switch (version) {
1387         default:
1388         case 15:
1389                 version = 15;
1390                 size = 23466;
1391                 fw_name = "ngene_15.fw";
1392                 break;
1393         case 16:
1394                 size = 23498;
1395                 fw_name = "ngene_16.fw";
1396                 break;
1397         case 17:
1398                 size = 24446;
1399                 fw_name = "ngene_17.fw";
1400                 break;
1401         }
1402
1403         if (request_firmware(&fw, fw_name, &dev->pci_dev->dev) < 0) {
1404                 printk(KERN_ERR DEVICE_NAME
1405                         ": Could not load firmware file %s.\n", fw_name);
1406                 printk(KERN_INFO DEVICE_NAME
1407                         ": Copy %s to your hotplug directory!\n", fw_name);
1408                 return -1;
1409         }
1410         if (size != fw->size) {
1411                 printk(KERN_ERR DEVICE_NAME
1412                         ": Firmware %s has invalid size!", fw_name);
1413                 err = -1;
1414         } else {
1415                 printk(KERN_INFO DEVICE_NAME
1416                         ": Loading firmware file %s.\n", fw_name);
1417                 ngene_fw = (u8 *) fw->data;
1418                 err = ngene_command_load_firmware(dev, ngene_fw, size);
1419         }
1420
1421         release_firmware(fw);
1422
1423         return err;
1424 }
1425
1426 static void ngene_stop(struct ngene *dev)
1427 {
1428         down(&dev->cmd_mutex);
1429         i2c_del_adapter(&(dev->channel[0].i2c_adapter));
1430         i2c_del_adapter(&(dev->channel[1].i2c_adapter));
1431         ngwritel(0, NGENE_INT_ENABLE);
1432         ngwritel(0, NGENE_COMMAND);
1433         ngwritel(0, NGENE_COMMAND_HI);
1434         ngwritel(0, NGENE_STATUS);
1435         ngwritel(0, NGENE_STATUS_HI);
1436         ngwritel(0, NGENE_EVENT);
1437         ngwritel(0, NGENE_EVENT_HI);
1438         free_irq(dev->pci_dev->irq, dev);
1439 }
1440
1441 static int ngene_start(struct ngene *dev)
1442 {
1443         int stat;
1444         int i;
1445
1446         pci_set_master(dev->pci_dev);
1447         ngene_init(dev);
1448
1449         stat = request_irq(dev->pci_dev->irq, irq_handler,
1450                            IRQF_SHARED, "nGene",
1451                            (void *)dev);
1452         if (stat < 0)
1453                 return stat;
1454
1455         init_waitqueue_head(&dev->cmd_wq);
1456         init_waitqueue_head(&dev->tx_wq);
1457         init_waitqueue_head(&dev->rx_wq);
1458         sema_init(&dev->cmd_mutex, 1);
1459         sema_init(&dev->stream_mutex, 1);
1460         sema_init(&dev->pll_mutex, 1);
1461         sema_init(&dev->i2c_switch_mutex, 1);
1462         spin_lock_init(&dev->cmd_lock);
1463         for (i = 0; i < MAX_STREAM; i++)
1464                 spin_lock_init(&dev->channel[i].state_lock);
1465         ngwritel(1, TIMESTAMPS);
1466
1467         ngwritel(1, NGENE_INT_ENABLE);
1468
1469         stat = ngene_load_firm(dev);
1470         if (stat < 0)
1471                 goto fail;
1472
1473         stat = ngene_i2c_init(dev, 0);
1474         if (stat < 0)
1475                 goto fail;
1476
1477         stat = ngene_i2c_init(dev, 1);
1478         if (stat < 0)
1479                 goto fail;
1480
1481         if (dev->card_info->fw_version == 17) {
1482                 u8 tsin4_config[6] = {
1483                         3072 / 64, 3072 / 64, 0, 3072 / 64, 3072 / 64, 0};
1484                 u8 default_config[6] = {
1485                         4096 / 64, 4096 / 64, 0, 2048 / 64, 2048 / 64, 0};
1486                 u8 *bconf = default_config;
1487
1488                 if (dev->card_info->io_type[3] == NGENE_IO_TSIN)
1489                         bconf = tsin4_config;
1490                 dprintk(KERN_DEBUG DEVICE_NAME ": FW 17 buffer config\n");
1491                 stat = ngene_command_config_free_buf(dev, bconf);
1492         } else {
1493                 int bconf = BUFFER_CONFIG_4422;
1494                 if (dev->card_info->io_type[3] == NGENE_IO_TSIN)
1495                         bconf = BUFFER_CONFIG_3333;
1496                 stat = ngene_command_config_buf(dev, bconf);
1497         }
1498         return stat;
1499 fail:
1500         ngwritel(0, NGENE_INT_ENABLE);
1501         free_irq(dev->pci_dev->irq, dev);
1502         return stat;
1503 }
1504
1505
1506
1507 /****************************************************************************/
1508 /* Switch control (I2C gates, etc.) *****************************************/
1509 /****************************************************************************/
1510
1511
1512 /****************************************************************************/
1513 /* Demod/tuner attachment ***************************************************/
1514 /****************************************************************************/
1515
1516 static int tuner_attach_stv6110(struct ngene_channel *chan)
1517 {
1518         struct stv090x_config *feconf = (struct stv090x_config *)
1519                 chan->dev->card_info->fe_config[chan->number];
1520         struct stv6110x_config *tunerconf = (struct stv6110x_config *)
1521                 chan->dev->card_info->tuner_config[chan->number];
1522         struct stv6110x_devctl *ctl;
1523
1524         ctl = dvb_attach(stv6110x_attach, chan->fe, tunerconf,
1525                          &chan->i2c_adapter);
1526         if (ctl == NULL) {
1527                 printk(KERN_ERR DEVICE_NAME ": No STV6110X found!\n");
1528                 return -ENODEV;
1529         }
1530
1531         feconf->tuner_init          = ctl->tuner_init;
1532         feconf->tuner_set_mode      = ctl->tuner_set_mode;
1533         feconf->tuner_set_frequency = ctl->tuner_set_frequency;
1534         feconf->tuner_get_frequency = ctl->tuner_get_frequency;
1535         feconf->tuner_set_bandwidth = ctl->tuner_set_bandwidth;
1536         feconf->tuner_get_bandwidth = ctl->tuner_get_bandwidth;
1537         feconf->tuner_set_bbgain    = ctl->tuner_set_bbgain;
1538         feconf->tuner_get_bbgain    = ctl->tuner_get_bbgain;
1539         feconf->tuner_set_refclk    = ctl->tuner_set_refclk;
1540         feconf->tuner_get_status    = ctl->tuner_get_status;
1541
1542         return 0;
1543 }
1544
1545
1546 static int demod_attach_stv0900(struct ngene_channel *chan)
1547 {
1548         struct stv090x_config *feconf = (struct stv090x_config *)
1549                 chan->dev->card_info->fe_config[chan->number];
1550
1551         chan->fe = dvb_attach(stv090x_attach,
1552                         feconf,
1553                         &chan->i2c_adapter,
1554                         chan->number == 0 ? STV090x_DEMODULATOR_0 :
1555                                             STV090x_DEMODULATOR_1);
1556         if (chan->fe == NULL) {
1557                 printk(KERN_ERR DEVICE_NAME ": No STV0900 found!\n");
1558                 return -ENODEV;
1559         }
1560
1561         if (!dvb_attach(lnbh24_attach, chan->fe, &chan->i2c_adapter, 0,
1562                         0, chan->dev->card_info->lnb[chan->number])) {
1563                 printk(KERN_ERR DEVICE_NAME ": No LNBH24 found!\n");
1564                 dvb_frontend_detach(chan->fe);
1565                 return -ENODEV;
1566         }
1567
1568         return 0;
1569 }
1570
1571 static struct lgdt330x_config aver_m780 = {
1572         .demod_address = 0xb2 >> 1,
1573         .demod_chip    = LGDT3303,
1574         .serial_mpeg   = 0x00, /* PARALLEL */
1575         .clock_polarity_flip = 1,
1576 };
1577
1578 static struct mt2131_config m780_tunerconfig = {
1579         0xc0 >> 1
1580 };
1581
1582 /* A single func to attach the demo and tuner, rather than
1583  * use two sep funcs like the current design mandates.
1584  */
1585 static int demod_attach_lg330x(struct ngene_channel *chan)
1586 {
1587         chan->fe = dvb_attach(lgdt330x_attach, &aver_m780, &chan->i2c_adapter);
1588         if (chan->fe == NULL) {
1589                 printk(KERN_ERR DEVICE_NAME ": No LGDT330x found!\n");
1590                 return -ENODEV;
1591         }
1592
1593         dvb_attach(mt2131_attach, chan->fe, &chan->i2c_adapter,
1594                    &m780_tunerconfig, 0);
1595
1596         return (chan->fe) ? 0 : -ENODEV;
1597 }
1598
1599 /****************************************************************************/
1600 /****************************************************************************/
1601 /****************************************************************************/
1602
1603 static void release_channel(struct ngene_channel *chan)
1604 {
1605         struct dvb_demux *dvbdemux = &chan->demux;
1606         struct ngene *dev = chan->dev;
1607         struct ngene_info *ni = dev->card_info;
1608         int io = ni->io_type[chan->number];
1609
1610 #ifdef COMMAND_TIMEOUT_WORKAROUND
1611         if (chan->running)
1612                 set_transfer(chan, 0);
1613 #endif
1614
1615         tasklet_kill(&chan->demux_tasklet);
1616
1617         if (io & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
1618                 if (chan->fe) {
1619                         dvb_unregister_frontend(chan->fe);
1620                         dvb_frontend_detach(chan->fe);
1621                         chan->fe = NULL;
1622                 }
1623                 dvbdemux->dmx.close(&dvbdemux->dmx);
1624                 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
1625                                               &chan->hw_frontend);
1626                 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
1627                                               &chan->mem_frontend);
1628                 dvb_dmxdev_release(&chan->dmxdev);
1629                 dvb_dmx_release(&chan->demux);
1630
1631                 if (chan->number == 0 || !one_adapter)
1632                         dvb_unregister_adapter(&dev->adapter[chan->number]);
1633         }
1634 }
1635
1636 static int init_channel(struct ngene_channel *chan)
1637 {
1638         int ret = 0, nr = chan->number;
1639         struct dvb_adapter *adapter = NULL;
1640         struct dvb_demux *dvbdemux = &chan->demux;
1641         struct ngene *dev = chan->dev;
1642         struct ngene_info *ni = dev->card_info;
1643         int io = ni->io_type[nr];
1644
1645         tasklet_init(&chan->demux_tasklet, demux_tasklet, (unsigned long)chan);
1646         chan->users = 0;
1647         chan->type = io;
1648         chan->mode = chan->type;        /* for now only one mode */
1649
1650         if (io & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
1651                 if (nr >= STREAM_AUDIOIN1)
1652                         chan->DataFormatFlags = DF_SWAP32;
1653                 if (nr == 0 || !one_adapter || dev->first_adapter == NULL) {
1654                         adapter = &dev->adapter[nr];
1655                         ret = dvb_register_adapter(adapter, "nGene",
1656                                                    THIS_MODULE,
1657                                                    &chan->dev->pci_dev->dev,
1658                                                    adapter_nr);
1659                         if (ret < 0)
1660                                 return ret;
1661                         if (dev->first_adapter == NULL)
1662                                 dev->first_adapter = adapter;
1663                 } else {
1664                         adapter = dev->first_adapter;
1665                 }
1666
1667                 ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux",
1668                                               ngene_start_feed,
1669                                               ngene_stop_feed, chan);
1670                 ret = my_dvb_dmxdev_ts_card_init(&chan->dmxdev, &chan->demux,
1671                                                  &chan->hw_frontend,
1672                                                  &chan->mem_frontend, adapter);
1673         }
1674
1675         if (io & NGENE_IO_TSIN) {
1676                 chan->fe = NULL;
1677                 if (ni->demod_attach[nr])
1678                         ni->demod_attach[nr](chan);
1679                 if (chan->fe) {
1680                         if (dvb_register_frontend(adapter, chan->fe) < 0) {
1681                                 if (chan->fe->ops.release)
1682                                         chan->fe->ops.release(chan->fe);
1683                                 chan->fe = NULL;
1684                         }
1685                 }
1686                 if (chan->fe && ni->tuner_attach[nr])
1687                         if (ni->tuner_attach[nr] (chan) < 0) {
1688                                 printk(KERN_ERR DEVICE_NAME
1689                                        ": Tuner attach failed on channel %d!\n",
1690                                        nr);
1691                         }
1692         }
1693         return ret;
1694 }
1695
1696 static int init_channels(struct ngene *dev)
1697 {
1698         int i, j;
1699
1700         for (i = 0; i < MAX_STREAM; i++) {
1701                 dev->channel[i].number = i;
1702                 if (init_channel(&dev->channel[i]) < 0) {
1703                         for (j = i - 1; j >= 0; j--)
1704                                 release_channel(&dev->channel[j]);
1705                         return -1;
1706                 }
1707         }
1708         return 0;
1709 }
1710
1711 /****************************************************************************/
1712 /* device probe/remove calls ************************************************/
1713 /****************************************************************************/
1714
1715 static void __devexit ngene_remove(struct pci_dev *pdev)
1716 {
1717         struct ngene *dev = (struct ngene *)pci_get_drvdata(pdev);
1718         int i;
1719
1720         tasklet_kill(&dev->event_tasklet);
1721         for (i = MAX_STREAM - 1; i >= 0; i--)
1722                 release_channel(&dev->channel[i]);
1723         ngene_stop(dev);
1724         ngene_release_buffers(dev);
1725         pci_set_drvdata(pdev, NULL);
1726         pci_disable_device(pdev);
1727 }
1728
1729 static int __devinit ngene_probe(struct pci_dev *pci_dev,
1730                                  const struct pci_device_id *id)
1731 {
1732         struct ngene *dev;
1733         int stat = 0;
1734
1735         if (pci_enable_device(pci_dev) < 0)
1736                 return -ENODEV;
1737
1738         dev = vmalloc(sizeof(struct ngene));
1739         if (dev == NULL) {
1740                 stat = -ENOMEM;
1741                 goto fail0;
1742         }
1743         memset(dev, 0, sizeof(struct ngene));
1744
1745         dev->pci_dev = pci_dev;
1746         dev->card_info = (struct ngene_info *)id->driver_data;
1747         printk(KERN_INFO DEVICE_NAME ": Found %s\n", dev->card_info->name);
1748
1749         pci_set_drvdata(pci_dev, dev);
1750
1751         /* Alloc buffers and start nGene */
1752         stat = ngene_get_buffers(dev);
1753         if (stat < 0)
1754                 goto fail1;
1755         stat = ngene_start(dev);
1756         if (stat < 0)
1757                 goto fail1;
1758
1759         dev->i2c_current_bus = -1;
1760
1761         /* Register DVB adapters and devices for both channels */
1762         if (init_channels(dev) < 0)
1763                 goto fail2;
1764
1765         return 0;
1766
1767 fail2:
1768         ngene_stop(dev);
1769 fail1:
1770         ngene_release_buffers(dev);
1771 fail0:
1772         pci_disable_device(pci_dev);
1773         pci_set_drvdata(pci_dev, NULL);
1774         return stat;
1775 }
1776
1777 /****************************************************************************/
1778 /* Card configs *************************************************************/
1779 /****************************************************************************/
1780
1781 static struct stv090x_config fe_cineS2 = {
1782         .device         = STV0900,
1783         .demod_mode     = STV090x_DUAL,
1784         .clk_mode       = STV090x_CLK_EXT,
1785
1786         .xtal           = 27000000,
1787         .address        = 0x68,
1788
1789         .ts1_mode       = STV090x_TSMODE_SERIAL_PUNCTURED,
1790         .ts2_mode       = STV090x_TSMODE_SERIAL_PUNCTURED,
1791
1792         .repeater_level = STV090x_RPTLEVEL_16,
1793
1794         .adc1_range     = STV090x_ADC_1Vpp,
1795         .adc2_range     = STV090x_ADC_1Vpp,
1796
1797         .diseqc_envelope_mode = true,
1798 };
1799
1800 static struct stv6110x_config tuner_cineS2_0 = {
1801         .addr   = 0x60,
1802         .refclk = 27000000,
1803         .clk_div = 1,
1804 };
1805
1806 static struct stv6110x_config tuner_cineS2_1 = {
1807         .addr   = 0x63,
1808         .refclk = 27000000,
1809         .clk_div = 1,
1810 };
1811
1812 static struct ngene_info ngene_info_cineS2 = {
1813         .type           = NGENE_SIDEWINDER,
1814         .name           = "Linux4Media cineS2 DVB-S2 Twin Tuner",
1815         .io_type        = {NGENE_IO_TSIN, NGENE_IO_TSIN},
1816         .demod_attach   = {demod_attach_stv0900, demod_attach_stv0900},
1817         .tuner_attach   = {tuner_attach_stv6110, tuner_attach_stv6110},
1818         .fe_config      = {&fe_cineS2, &fe_cineS2},
1819         .tuner_config   = {&tuner_cineS2_0, &tuner_cineS2_1},
1820         .lnb            = {0x0b, 0x08},
1821         .tsf            = {3, 3},
1822         .fw_version     = 15,
1823 };
1824
1825 static struct ngene_info ngene_info_satixS2 = {
1826         .type           = NGENE_SIDEWINDER,
1827         .name           = "Mystique SaTiX-S2 Dual",
1828         .io_type        = {NGENE_IO_TSIN, NGENE_IO_TSIN},
1829         .demod_attach   = {demod_attach_stv0900, demod_attach_stv0900},
1830         .tuner_attach   = {tuner_attach_stv6110, tuner_attach_stv6110},
1831         .fe_config      = {&fe_cineS2, &fe_cineS2},
1832         .tuner_config   = {&tuner_cineS2_0, &tuner_cineS2_1},
1833         .lnb            = {0x0b, 0x08},
1834         .tsf            = {3, 3},
1835         .fw_version     = 15,
1836 };
1837
1838 static struct ngene_info ngene_info_satixS2v2 = {
1839         .type           = NGENE_SIDEWINDER,
1840         .name           = "Mystique SaTiX-S2 Dual (v2)",
1841         .io_type        = {NGENE_IO_TSIN, NGENE_IO_TSIN},
1842         .demod_attach   = {demod_attach_stv0900, demod_attach_stv0900},
1843         .tuner_attach   = {tuner_attach_stv6110, tuner_attach_stv6110},
1844         .fe_config      = {&fe_cineS2, &fe_cineS2},
1845         .tuner_config   = {&tuner_cineS2_0, &tuner_cineS2_1},
1846         .lnb            = {0x0a, 0x08},
1847         .tsf            = {3, 3},
1848         .fw_version     = 15,
1849 };
1850
1851 static struct ngene_info ngene_info_cineS2v5 = {
1852         .type           = NGENE_SIDEWINDER,
1853         .name           = "Linux4Media cineS2 DVB-S2 Twin Tuner (v5)",
1854         .io_type        = {NGENE_IO_TSIN, NGENE_IO_TSIN},
1855         .demod_attach   = {demod_attach_stv0900, demod_attach_stv0900},
1856         .tuner_attach   = {tuner_attach_stv6110, tuner_attach_stv6110},
1857         .fe_config      = {&fe_cineS2, &fe_cineS2},
1858         .tuner_config   = {&tuner_cineS2_0, &tuner_cineS2_1},
1859         .lnb            = {0x0a, 0x08},
1860         .tsf            = {3, 3},
1861         .fw_version     = 15,
1862 };
1863
1864 static struct ngene_info ngene_info_m780 = {
1865         .type           = NGENE_APP,
1866         .name           = "Aver M780 ATSC/QAM-B",
1867
1868         /* Channel 0 is analog, which is currently unsupported */
1869         .io_type        = { NGENE_IO_NONE, NGENE_IO_TSIN },
1870         .demod_attach   = { NULL, demod_attach_lg330x },
1871
1872         /* Ensure these are NULL else the frame will call them (as funcs) */
1873         .tuner_attach   = { 0, 0, 0, 0 },
1874         .fe_config      = { NULL, &aver_m780 },
1875         .avf            = { 0 },
1876
1877         /* A custom electrical interface config for the demod to bridge */
1878         .tsf            = { 4, 4 },
1879         .fw_version     = 15,
1880 };
1881
1882 /****************************************************************************/
1883
1884
1885
1886 /****************************************************************************/
1887 /* PCI Subsystem ID *********************************************************/
1888 /****************************************************************************/
1889
1890 #define NGENE_ID(_subvend, _subdev, _driverdata) { \
1891         .vendor = NGENE_VID, .device = NGENE_PID, \
1892         .subvendor = _subvend, .subdevice = _subdev, \
1893         .driver_data = (unsigned long) &_driverdata }
1894
1895 /****************************************************************************/
1896
1897 static const struct pci_device_id ngene_id_tbl[] __devinitdata = {
1898         NGENE_ID(0x18c3, 0xabc3, ngene_info_cineS2),
1899         NGENE_ID(0x18c3, 0xabc4, ngene_info_cineS2),
1900         NGENE_ID(0x18c3, 0xdb01, ngene_info_satixS2),
1901         NGENE_ID(0x18c3, 0xdb02, ngene_info_satixS2v2),
1902         NGENE_ID(0x18c3, 0xdd00, ngene_info_cineS2v5),
1903         NGENE_ID(0x1461, 0x062e, ngene_info_m780),
1904         {0}
1905 };
1906 MODULE_DEVICE_TABLE(pci, ngene_id_tbl);
1907
1908 /****************************************************************************/
1909 /* Init/Exit ****************************************************************/
1910 /****************************************************************************/
1911
1912 static pci_ers_result_t ngene_error_detected(struct pci_dev *dev,
1913                                              enum pci_channel_state state)
1914 {
1915         printk(KERN_ERR DEVICE_NAME ": PCI error\n");
1916         if (state == pci_channel_io_perm_failure)
1917                 return PCI_ERS_RESULT_DISCONNECT;
1918         if (state == pci_channel_io_frozen)
1919                 return PCI_ERS_RESULT_NEED_RESET;
1920         return PCI_ERS_RESULT_CAN_RECOVER;
1921 }
1922
1923 static pci_ers_result_t ngene_link_reset(struct pci_dev *dev)
1924 {
1925         printk(KERN_INFO DEVICE_NAME ": link reset\n");
1926         return 0;
1927 }
1928
1929 static pci_ers_result_t ngene_slot_reset(struct pci_dev *dev)
1930 {
1931         printk(KERN_INFO DEVICE_NAME ": slot reset\n");
1932         return 0;
1933 }
1934
1935 static void ngene_resume(struct pci_dev *dev)
1936 {
1937         printk(KERN_INFO DEVICE_NAME ": resume\n");
1938 }
1939
1940 static struct pci_error_handlers ngene_errors = {
1941         .error_detected = ngene_error_detected,
1942         .link_reset = ngene_link_reset,
1943         .slot_reset = ngene_slot_reset,
1944         .resume = ngene_resume,
1945 };
1946
1947 static struct pci_driver ngene_pci_driver = {
1948         .name        = "ngene",
1949         .id_table    = ngene_id_tbl,
1950         .probe       = ngene_probe,
1951         .remove      = __devexit_p(ngene_remove),
1952         .err_handler = &ngene_errors,
1953 };
1954
1955 static __init int module_init_ngene(void)
1956 {
1957         printk(KERN_INFO
1958                "nGene PCIE bridge driver, Copyright (C) 2005-2007 Micronas\n");
1959         return pci_register_driver(&ngene_pci_driver);
1960 }
1961
1962 static __exit void module_exit_ngene(void)
1963 {
1964         pci_unregister_driver(&ngene_pci_driver);
1965 }
1966
1967 module_init(module_init_ngene);
1968 module_exit(module_exit_ngene);
1969
1970 MODULE_DESCRIPTION("nGene");
1971 MODULE_AUTHOR("Micronas, Ralph Metzler, Manfred Voelkel");
1972 MODULE_LICENSE("GPL");