drivers/media/dvb/frontends/tda10048.c

   1 /*
   2     NXP TDA10048HN DVB OFDM demodulator driver
   3
   4     Copyright (C) 2009 Steven Toth <stoth@kernellabs.com>
   5
   6     This program is free software; you can redistribute it and/or modify
   7     it under the terms of the GNU General Public License as published by
   8     the Free Software Foundation; either version 2 of the License, or
   9     (at your option) any later version.
  10
  11     This program is distributed in the hope that it will be useful,
  12     but WITHOUT ANY WARRANTY; without even the implied warranty of
  13     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14     GNU General Public License for more details.
  15
  16     You should have received a copy of the GNU General Public License
  17     along with this program; if not, write to the Free Software
  18     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19
  20 */
  21
  22 #include <linux/kernel.h>
  23 #include <linux/init.h>
  24 #include <linux/module.h>
  25 #include <linux/string.h>
  26 #include <linux/slab.h>
  27 #include <linux/delay.h>
  28 #include <asm/div64.h>
  29 #include "dvb_frontend.h"
  30 #include "dvb_math.h"
  31 #include "tda10048.h"
  32
  33 #define TDA10048_DEFAULT_FIRMWARE "dvb-fe-tda10048-1.0.fw"
  34 #define TDA10048_DEFAULT_FIRMWARE_SIZE 24878
  35
  36 /* Register name definitions */
  37 #define TDA10048_IDENTITY          0x00
  38 #define TDA10048_VERSION           0x01
  39 #define TDA10048_DSP_CODE_CPT      0x0C
  40 #define TDA10048_DSP_CODE_IN       0x0E
  41 #define TDA10048_IN_CONF1          0x10
  42 #define TDA10048_IN_CONF2          0x11
  43 #define TDA10048_IN_CONF3          0x12
  44 #define TDA10048_OUT_CONF1         0x14
  45 #define TDA10048_OUT_CONF2         0x15
  46 #define TDA10048_OUT_CONF3         0x16
  47 #define TDA10048_AUTO              0x18
  48 #define TDA10048_SYNC_STATUS       0x1A
  49 #define TDA10048_CONF_C4_1         0x1E
  50 #define TDA10048_CONF_C4_2         0x1F
  51 #define TDA10048_CODE_IN_RAM       0x20
  52 #define TDA10048_CHANNEL_INFO_1_R  0x22
  53 #define TDA10048_CHANNEL_INFO_2_R  0x23
  54 #define TDA10048_CHANNEL_INFO1     0x24
  55 #define TDA10048_CHANNEL_INFO2     0x25
  56 #define TDA10048_TIME_ERROR_R      0x26
  57 #define TDA10048_TIME_ERROR        0x27
  58 #define TDA10048_FREQ_ERROR_LSB_R  0x28
  59 #define TDA10048_FREQ_ERROR_MSB_R  0x29
  60 #define TDA10048_FREQ_ERROR_LSB    0x2A
  61 #define TDA10048_FREQ_ERROR_MSB    0x2B
  62 #define TDA10048_IT_SEL            0x30
  63 #define TDA10048_IT_STAT           0x32
  64 #define TDA10048_DSP_AD_LSB        0x3C
  65 #define TDA10048_DSP_AD_MSB        0x3D
  66 #define TDA10048_DSP_REF_LSB       0x3E
  67 #define TDA10048_DSP_REF_MSB       0x3F
  68 #define TDA10048_CONF_TRISTATE1    0x44
  69 #define TDA10048_CONF_TRISTATE2    0x45
  70 #define TDA10048_CONF_POLARITY     0x46
  71 #define TDA10048_GPIO_SP_DS0       0x48
  72 #define TDA10048_GPIO_SP_DS1       0x49
  73 #define TDA10048_GPIO_SP_DS2       0x4A
  74 #define TDA10048_GPIO_SP_DS3       0x4B
  75 #define TDA10048_GPIO_OUT_SEL      0x4C
  76 #define TDA10048_GPIO_SELECT       0x4D
  77 #define TDA10048_IC_MODE           0x4E
  78 #define TDA10048_CONF_XO           0x50
  79 #define TDA10048_CONF_PLL1         0x51
  80 #define TDA10048_CONF_PLL2         0x52
  81 #define TDA10048_CONF_PLL3         0x53
  82 #define TDA10048_CONF_ADC          0x54
  83 #define TDA10048_CONF_ADC_2        0x55
  84 #define TDA10048_CONF_C1_1         0x60
  85 #define TDA10048_CONF_C1_3         0x62
  86 #define TDA10048_AGC_CONF          0x70
  87 #define TDA10048_AGC_THRESHOLD_LSB 0x72
  88 #define TDA10048_AGC_THRESHOLD_MSB 0x73
  89 #define TDA10048_AGC_RENORM        0x74
  90 #define TDA10048_AGC_GAINS         0x76
  91 #define TDA10048_AGC_TUN_MIN       0x78
  92 #define TDA10048_AGC_TUN_MAX       0x79
  93 #define TDA10048_AGC_IF_MIN        0x7A
  94 #define TDA10048_AGC_IF_MAX        0x7B
  95 #define TDA10048_AGC_TUN_LEVEL     0x7E
  96 #define TDA10048_AGC_IF_LEVEL      0x7F
  97 #define TDA10048_DIG_AGC_LEVEL     0x81
  98 #define TDA10048_FREQ_PHY2_LSB     0x86
  99 #define TDA10048_FREQ_PHY2_MSB     0x87
 100 #define TDA10048_TIME_INVWREF_LSB  0x88
 101 #define TDA10048_TIME_INVWREF_MSB  0x89
 102 #define TDA10048_TIME_WREF_LSB     0x8A
 103 #define TDA10048_TIME_WREF_MID1    0x8B
 104 #define TDA10048_TIME_WREF_MID2    0x8C
 105 #define TDA10048_TIME_WREF_MSB     0x8D
 106 #define TDA10048_NP_OUT            0xA2
 107 #define TDA10048_CELL_ID_LSB       0xA4
 108 #define TDA10048_CELL_ID_MSB       0xA5
 109 #define TDA10048_EXTTPS_ODD        0xAA
 110 #define TDA10048_EXTTPS_EVEN       0xAB
 111 #define TDA10048_TPS_LENGTH        0xAC
 112 #define TDA10048_FREE_REG_1        0xB2
 113 #define TDA10048_FREE_REG_2        0xB3
 114 #define TDA10048_CONF_C3_1         0xC0
 115 #define TDA10048_CYBER_CTRL        0xC2
 116 #define TDA10048_CBER_NMAX_LSB     0xC4
 117 #define TDA10048_CBER_NMAX_MSB     0xC5
 118 #define TDA10048_CBER_LSB          0xC6
 119 #define TDA10048_CBER_MSB          0xC7
 120 #define TDA10048_VBER_LSB          0xC8
 121 #define TDA10048_VBER_MID          0xC9
 122 #define TDA10048_VBER_MSB          0xCA
 123 #define TDA10048_CYBER_LUT         0xCC
 124 #define TDA10048_UNCOR_CTRL        0xCD
 125 #define TDA10048_UNCOR_CPT_LSB     0xCE
 126 #define TDA10048_UNCOR_CPT_MSB     0xCF
 127 #define TDA10048_SOFT_IT_C3        0xD6
 128 #define TDA10048_CONF_TS2          0xE0
 129 #define TDA10048_CONF_TS1          0xE1
 130
 131 static unsigned int debug;
 132
 133 #define dprintk(level, fmt, arg...)\
 134         do { if (debug >= level)\
 135                 printk(KERN_DEBUG "tda10048: " fmt, ## arg);\
 136         } while (0)
 137
 138 struct tda10048_state {
 139
 140         struct i2c_adapter *i2c;
 141
 142         /* We'll cache and update the attach config settings */
 143         struct tda10048_config config;
 144         struct dvb_frontend frontend;
 145
 146         int fwloaded;
 147
 148         u32 freq_if_hz;
 149         u32 xtal_hz;
 150         u32 pll_mfactor;
 151         u32 pll_nfactor;
 152         u32 pll_pfactor;
 153         u32 sample_freq;
 154
 155         enum fe_bandwidth bandwidth;
 156 };
 157
 158 static struct init_tab {
 159         u8      reg;
 160         u16     data;
 161 } init_tab[] = {
 162         { TDA10048_CONF_PLL1, 0x08 },
 163         { TDA10048_CONF_ADC_2, 0x00 },
 164         { TDA10048_CONF_C4_1, 0x00 },
 165         { TDA10048_CONF_PLL1, 0x0f },
 166         { TDA10048_CONF_PLL2, 0x0a },
 167         { TDA10048_CONF_PLL3, 0x43 },
 168         { TDA10048_FREQ_PHY2_LSB, 0x02 },
 169         { TDA10048_FREQ_PHY2_MSB, 0x0a },
 170         { TDA10048_TIME_WREF_LSB, 0xbd },
 171         { TDA10048_TIME_WREF_MID1, 0xe4 },
 172         { TDA10048_TIME_WREF_MID2, 0xa8 },
 173         { TDA10048_TIME_WREF_MSB, 0x02 },
 174         { TDA10048_TIME_INVWREF_LSB, 0x04 },
 175         { TDA10048_TIME_INVWREF_MSB, 0x06 },
 176         { TDA10048_CONF_C4_1, 0x00 },
 177         { TDA10048_CONF_C1_1, 0xa8 },
 178         { TDA10048_AGC_CONF, 0x16 },
 179         { TDA10048_CONF_C1_3, 0x0b },
 180         { TDA10048_AGC_TUN_MIN, 0x00 },
 181         { TDA10048_AGC_TUN_MAX, 0xff },
 182         { TDA10048_AGC_IF_MIN, 0x00 },
 183         { TDA10048_AGC_IF_MAX, 0xff },
 184         { TDA10048_AGC_THRESHOLD_MSB, 0x00 },
 185         { TDA10048_AGC_THRESHOLD_LSB, 0x70 },
 186         { TDA10048_CYBER_CTRL, 0x38 },
 187         { TDA10048_AGC_GAINS, 0x12 },
 188         { TDA10048_CONF_XO, 0x00 },
 189         { TDA10048_CONF_TS1, 0x07 },
 190         { TDA10048_IC_MODE, 0x00 },
 191         { TDA10048_CONF_TS2, 0xc0 },
 192         { TDA10048_CONF_TRISTATE1, 0x21 },
 193         { TDA10048_CONF_TRISTATE2, 0x00 },
 194         { TDA10048_CONF_POLARITY, 0x00 },
 195         { TDA10048_CONF_C4_2, 0x04 },
 196         { TDA10048_CONF_ADC, 0x60 },
 197         { TDA10048_CONF_ADC_2, 0x10 },
 198         { TDA10048_CONF_ADC, 0x60 },
 199         { TDA10048_CONF_ADC_2, 0x00 },
 200         { TDA10048_CONF_C1_1, 0xa8 },
 201         { TDA10048_UNCOR_CTRL, 0x00 },
 202         { TDA10048_CONF_C4_2, 0x04 },
 203 };
 204
 205 static struct pll_tab {
 206         u32     clk_freq_khz;
 207         u32     if_freq_khz;
 208         u8      m, n, p;
 209 } pll_tab[] = {
 210         { TDA10048_CLK_4000,  TDA10048_IF_36130, 10, 0, 0 },
 211         { TDA10048_CLK_16000, TDA10048_IF_3300,  10, 3, 0 },
 212         { TDA10048_CLK_16000, TDA10048_IF_3500,  10, 3, 0 },
 213         { TDA10048_CLK_16000, TDA10048_IF_4000,  10, 3, 0 },
 214         { TDA10048_CLK_16000, TDA10048_IF_4300,  10, 3, 0 },
 215         { TDA10048_CLK_16000, TDA10048_IF_36130, 10, 3, 0 },
 216 };
 217
 218 static int tda10048_writereg(struct tda10048_state *state, u8 reg, u8 data)
 219 {
 220         struct tda10048_config *config = &state->config;
 221         int ret;
 222         u8 buf[] = { reg, data };
 223         struct i2c_msg msg = {
 224                 .addr = config->demod_address,
 225                 .flags = 0, .buf = buf, .len = 2 };
 226
 227         dprintk(2, "%s(reg = 0x%02x, data = 0x%02x)\n", __func__, reg, data);
 228
 229         ret = i2c_transfer(state->i2c, &msg, 1);
 230
 231         if (ret != 1)
 232                 printk("%s: writereg error (ret == %i)\n", __func__, ret);
 233
 234         return (ret != 1) ? -1 : 0;
 235 }
 236
 237 static u8 tda10048_readreg(struct tda10048_state *state, u8 reg)
 238 {
 239         struct tda10048_config *config = &state->config;
 240         int ret;
 241         u8 b0[] = { reg };
 242         u8 b1[] = { 0 };
 243         struct i2c_msg msg[] = {
 244                 { .addr = config->demod_address,
 245                         .flags = 0, .buf = b0, .len = 1 },
 246                 { .addr = config->demod_address,
 247                         .flags = I2C_M_RD, .buf = b1, .len = 1 } };
 248
 249         dprintk(2, "%s(reg = 0x%02x)\n", __func__, reg);
 250
 251         ret = i2c_transfer(state->i2c, msg, 2);
 252
 253         if (ret != 2)
 254                 printk(KERN_ERR "%s: readreg error (ret == %i)\n",
 255                         __func__, ret);
 256
 257         return b1[0];
 258 }
 259
 260 static int tda10048_writeregbulk(struct tda10048_state *state, u8 reg,
 261                                  const u8 *data, u16 len)
 262 {
 263         struct tda10048_config *config = &state->config;
 264         int ret = -EREMOTEIO;
 265         struct i2c_msg msg;
 266         u8 *buf;
 267
 268         dprintk(2, "%s(%d, ?, len = %d)\n", __func__, reg, len);
 269
 270         buf = kmalloc(len + 1, GFP_KERNEL);
 271         if (buf == NULL) {
 272                 ret = -ENOMEM;
 273                 goto error;
 274         }
 275
 276         *buf = reg;
 277         memcpy(buf + 1, data, len);
 278
 279         msg.addr = config->demod_address;
 280         msg.flags = 0;
 281         msg.buf = buf;
 282         msg.len = len + 1;
 283
 284         dprintk(2, "%s():  write len = %d\n",
 285                 __func__, msg.len);
 286
 287         ret = i2c_transfer(state->i2c, &msg, 1);
 288         if (ret != 1) {
 289                 printk(KERN_ERR "%s(): writereg error err %i\n",
 290                          __func__, ret);
 291                 ret = -EREMOTEIO;
 292         }
 293
 294 error:
 295         kfree(buf);
 296
 297         return ret;
 298 }
 299
 300 static int tda10048_set_phy2(struct dvb_frontend *fe, u32 sample_freq_hz,
 301                              u32 if_hz)
 302 {
 303         struct tda10048_state *state = fe->demodulator_priv;
 304         u64 t;
 305
 306         dprintk(1, "%s()\n", __func__);
 307
 308         if (sample_freq_hz == 0)
 309                 return -EINVAL;
 310
 311         if (if_hz < (sample_freq_hz / 2)) {
 312                 /* PHY2 = (if2/fs) * 2^15 */
 313                 t = if_hz;
 314                 t *= 10;
 315                 t *= 32768;
 316                 do_div(t, sample_freq_hz);
 317                 t += 5;
 318                 do_div(t, 10);
 319         } else {
 320                 /* PHY2 = ((IF1-fs)/fs) * 2^15 */
 321                 t = sample_freq_hz - if_hz;
 322                 t *= 10;
 323                 t *= 32768;
 324                 do_div(t, sample_freq_hz);
 325                 t += 5;
 326                 do_div(t, 10);
 327                 t = ~t + 1;
 328         }
 329
 330         tda10048_writereg(state, TDA10048_FREQ_PHY2_LSB, (u8)t);
 331         tda10048_writereg(state, TDA10048_FREQ_PHY2_MSB, (u8)(t >> 8));
 332
 333         return 0;
 334 }
 335
 336 static int tda10048_set_wref(struct dvb_frontend *fe, u32 sample_freq_hz,
 337                              u32 bw)
 338 {
 339         struct tda10048_state *state = fe->demodulator_priv;
 340         u64 t, z;
 341         u32 b = 8000000;
 342
 343         dprintk(1, "%s()\n", __func__);
 344
 345         if (sample_freq_hz == 0)
 346                 return -EINVAL;
 347
 348         if (bw == BANDWIDTH_6_MHZ)
 349                 b = 6000000;
 350         else
 351         if (bw == BANDWIDTH_7_MHZ)
 352                 b = 7000000;
 353
 354         /* WREF = (B / (7 * fs)) * 2^31 */
 355         t = b * 10;
 356         /* avoid warning: this decimal constant is unsigned only in ISO C90 */
 357         /* t *= 2147483648 on 32bit platforms */
 358         t *= (2048 * 1024);
 359         t *= 1024;
 360         z = 7 * sample_freq_hz;
 361         do_div(t, z);
 362         t += 5;
 363         do_div(t, 10);
 364
 365         tda10048_writereg(state, TDA10048_TIME_WREF_LSB, (u8)t);
 366         tda10048_writereg(state, TDA10048_TIME_WREF_MID1, (u8)(t >> 8));
 367         tda10048_writereg(state, TDA10048_TIME_WREF_MID2, (u8)(t >> 16));
 368         tda10048_writereg(state, TDA10048_TIME_WREF_MSB, (u8)(t >> 24));
 369
 370         return 0;
 371 }
 372
 373 static int tda10048_set_invwref(struct dvb_frontend *fe, u32 sample_freq_hz,
 374                                 u32 bw)
 375 {
 376         struct tda10048_state *state = fe->demodulator_priv;
 377         u64 t;
 378         u32 b = 8000000;
 379
 380         dprintk(1, "%s()\n", __func__);
 381
 382         if (sample_freq_hz == 0)
 383                 return -EINVAL;
 384
 385         if (bw == BANDWIDTH_6_MHZ)
 386                 b = 6000000;
 387         else
 388         if (bw == BANDWIDTH_7_MHZ)
 389                 b = 7000000;
 390
 391         /* INVWREF = ((7 * fs) / B) * 2^5 */
 392         t = sample_freq_hz;
 393         t *= 7;
 394         t *= 32;
 395         t *= 10;
 396         do_div(t, b);
 397         t += 5;
 398         do_div(t, 10);
 399
 400         tda10048_writereg(state, TDA10048_TIME_INVWREF_LSB, (u8)t);
 401         tda10048_writereg(state, TDA10048_TIME_INVWREF_MSB, (u8)(t >> 8));
 402
 403         return 0;
 404 }
 405
 406 static int tda10048_set_bandwidth(struct dvb_frontend *fe,
 407         enum fe_bandwidth bw)
 408 {
 409         struct tda10048_state *state = fe->demodulator_priv;
 410         dprintk(1, "%s(bw=%d)\n", __func__, bw);
 411
 412         /* Bandwidth setting may need to be adjusted */
 413         switch (bw) {
 414         case BANDWIDTH_6_MHZ:
 415         case BANDWIDTH_7_MHZ:
 416         case BANDWIDTH_8_MHZ:
 417                 tda10048_set_wref(fe, state->sample_freq, bw);
 418                 tda10048_set_invwref(fe, state->sample_freq, bw);
 419                 break;
 420         default:
 421                 printk(KERN_ERR "%s() invalid bandwidth\n", __func__);
 422                 return -EINVAL;
 423         }
 424
 425         state->bandwidth = bw;
 426
 427         return 0;
 428 }
 429
 430 static int tda10048_set_if(struct dvb_frontend *fe, enum fe_bandwidth bw)
 431 {
 432         struct tda10048_state *state = fe->demodulator_priv;
 433         struct tda10048_config *config = &state->config;
 434         int i;
 435         u32 if_freq_khz;
 436
 437         dprintk(1, "%s(bw = %d)\n", __func__, bw);
 438
 439         /* based on target bandwidth and clk we calculate pll factors */
 440         switch (bw) {
 441         case BANDWIDTH_6_MHZ:
 442                 if_freq_khz = config->dtv6_if_freq_khz;
 443                 break;
 444         case BANDWIDTH_7_MHZ:
 445                 if_freq_khz = config->dtv7_if_freq_khz;
 446                 break;
 447         case BANDWIDTH_8_MHZ:
 448                 if_freq_khz = config->dtv8_if_freq_khz;
 449                 break;
 450         default:
 451                 printk(KERN_ERR "%s() no default\n", __func__);
 452                 return -EINVAL;
 453         }
 454
 455         for (i = 0; i < ARRAY_SIZE(pll_tab); i++) {
 456                 if ((pll_tab[i].clk_freq_khz == config->clk_freq_khz) &&
 457                         (pll_tab[i].if_freq_khz == if_freq_khz)) {
 458
 459                         state->freq_if_hz = pll_tab[i].if_freq_khz * 1000;
 460                         state->xtal_hz = pll_tab[i].clk_freq_khz * 1000;
 461                         state->pll_mfactor = pll_tab[i].m;
 462                         state->pll_nfactor = pll_tab[i].n;
 463                         state->pll_pfactor = pll_tab[i].p;
 464                         break;
 465                 }
 466         }
 467         if (i == ARRAY_SIZE(pll_tab)) {
 468                 printk(KERN_ERR "%s() Incorrect attach settings\n",
 469                         __func__);
 470                 return -EINVAL;
 471         }
 472
 473         dprintk(1, "- freq_if_hz = %d\n", state->freq_if_hz);
 474         dprintk(1, "- xtal_hz = %d\n", state->xtal_hz);
 475         dprintk(1, "- pll_mfactor = %d\n", state->pll_mfactor);
 476         dprintk(1, "- pll_nfactor = %d\n", state->pll_nfactor);
 477         dprintk(1, "- pll_pfactor = %d\n", state->pll_pfactor);
 478
 479         /* Calculate the sample frequency */
 480         state->sample_freq = state->xtal_hz * (state->pll_mfactor + 45);
 481         state->sample_freq /= (state->pll_nfactor + 1);
 482         state->sample_freq /= (state->pll_pfactor + 4);
 483         dprintk(1, "- sample_freq = %d\n", state->sample_freq);
 484
 485         /* Update the I/F */
 486         tda10048_set_phy2(fe, state->sample_freq, state->freq_if_hz);
 487
 488         return 0;
 489 }
 490
 491 static int tda10048_firmware_upload(struct dvb_frontend *fe)
 492 {
 493         struct tda10048_state *state = fe->demodulator_priv;
 494         struct tda10048_config *config = &state->config;
 495         const struct firmware *fw;
 496         int ret;
 497         int pos = 0;
 498         int cnt;
 499         u8 wlen = config->fwbulkwritelen;
 500
 501         if ((wlen != TDA10048_BULKWRITE_200) && (wlen != TDA10048_BULKWRITE_50))
 502                 wlen = TDA10048_BULKWRITE_200;
 503
 504         /* request the firmware, this will block and timeout */
 505         printk(KERN_INFO "%s: waiting for firmware upload (%s)...\n",
 506                 __func__,
 507                 TDA10048_DEFAULT_FIRMWARE);
 508
 509         ret = request_firmware(&fw, TDA10048_DEFAULT_FIRMWARE,
 510                 state->i2c->dev.parent);
 511         if (ret) {
 512                 printk(KERN_ERR "%s: Upload failed. (file not found?)\n",
 513                         __func__);
 514                 return -EIO;
 515         } else {
 516                 printk(KERN_INFO "%s: firmware read %Zu bytes.\n",
 517                         __func__,
 518                         fw->size);
 519                 ret = 0;
 520         }
 521
 522         if (fw->size != TDA10048_DEFAULT_FIRMWARE_SIZE) {
 523                 printk(KERN_ERR "%s: firmware incorrect size\n", __func__);
 524                 ret = -EIO;
 525         } else {
 526                 printk(KERN_INFO "%s: firmware uploading\n", __func__);
 527
 528                 /* Soft reset */
 529                 tda10048_writereg(state, TDA10048_CONF_TRISTATE1,
 530                         tda10048_readreg(state, TDA10048_CONF_TRISTATE1)
 531                                 & 0xfe);
 532                 tda10048_writereg(state, TDA10048_CONF_TRISTATE1,
 533                         tda10048_readreg(state, TDA10048_CONF_TRISTATE1)
 534                                 | 0x01);
 535
 536                 /* Put the demod into host download mode */
 537                 tda10048_writereg(state, TDA10048_CONF_C4_1,
 538                         tda10048_readreg(state, TDA10048_CONF_C4_1) & 0xf9);
 539
 540                 /* Boot the DSP */
 541                 tda10048_writereg(state, TDA10048_CONF_C4_1,
 542                         tda10048_readreg(state, TDA10048_CONF_C4_1) | 0x08);
 543
 544                 /* Prepare for download */
 545                 tda10048_writereg(state, TDA10048_DSP_CODE_CPT, 0);
 546
 547                 /* Download the firmware payload */
 548                 while (pos < fw->size) {
 549
 550                         if ((fw->size - pos) > wlen)
 551                                 cnt = wlen;
 552                         else
 553                                 cnt = fw->size - pos;
 554
 555                         tda10048_writeregbulk(state, TDA10048_DSP_CODE_IN,
 556                                 &fw->data[pos], cnt);
 557
 558                         pos += cnt;
 559                 }
 560
 561                 ret = -EIO;
 562                 /* Wait up to 250ms for the DSP to boot */
 563                 for (cnt = 0; cnt < 250 ; cnt += 10) {
 564
 565                         msleep(10);
 566
 567                         if (tda10048_readreg(state, TDA10048_SYNC_STATUS)
 568                                 & 0x40) {
 569                                 ret = 0;
 570                                 break;
 571                         }
 572                 }
 573         }
 574
 575         release_firmware(fw);
 576
 577         if (ret == 0) {
 578                 printk(KERN_INFO "%s: firmware uploaded\n", __func__);
 579                 state->fwloaded = 1;
 580         } else
 581                 printk(KERN_ERR "%s: firmware upload failed\n", __func__);
 582
 583         return ret;
 584 }
 585
 586 static int tda10048_set_inversion(struct dvb_frontend *fe, int inversion)
 587 {
 588         struct tda10048_state *state = fe->demodulator_priv;
 589
 590         dprintk(1, "%s(%d)\n", __func__, inversion);
 591
 592         if (inversion == TDA10048_INVERSION_ON)
 593                 tda10048_writereg(state, TDA10048_CONF_C1_1,
 594                         tda10048_readreg(state, TDA10048_CONF_C1_1) | 0x20);
 595         else
 596                 tda10048_writereg(state, TDA10048_CONF_C1_1,
 597                         tda10048_readreg(state, TDA10048_CONF_C1_1) & 0xdf);
 598
 599         return 0;
 600 }
 601
 602 /* Retrieve the demod settings */
 603 static int tda10048_get_tps(struct tda10048_state *state,
 604         struct dvb_ofdm_parameters *p)
 605 {
 606         u8 val;
 607
 608         /* Make sure the TPS regs are valid */
 609         if (!(tda10048_readreg(state, TDA10048_AUTO) & 0x01))
 610                 return -EAGAIN;
 611
 612         val = tda10048_readreg(state, TDA10048_OUT_CONF2);
 613         switch ((val & 0x60) >> 5) {
 614         case 0:
 615                 p->constellation = QPSK;
 616                 break;
 617         case 1:
 618                 p->constellation = QAM_16;
 619                 break;
 620         case 2:
 621                 p->constellation = QAM_64;
 622                 break;
 623         }
 624         switch ((val & 0x18) >> 3) {
 625         case 0:
 626                 p->hierarchy_information = HIERARCHY_NONE;
 627                 break;
 628         case 1:
 629                 p->hierarchy_information = HIERARCHY_1;
 630                 break;
 631         case 2:
 632                 p->hierarchy_information = HIERARCHY_2;
 633                 break;
 634         case 3:
 635                 p->hierarchy_information = HIERARCHY_4;
 636                 break;
 637         }
 638         switch (val & 0x07) {
 639         case 0:
 640                 p->code_rate_HP = FEC_1_2;
 641                 break;
 642         case 1:
 643                 p->code_rate_HP = FEC_2_3;
 644                 break;
 645         case 2:
 646                 p->code_rate_HP = FEC_3_4;
 647                 break;
 648         case 3:
 649                 p->code_rate_HP = FEC_5_6;
 650                 break;
 651         case 4:
 652                 p->code_rate_HP = FEC_7_8;
 653                 break;
 654         }
 655
 656         val = tda10048_readreg(state, TDA10048_OUT_CONF3);
 657         switch (val & 0x07) {
 658         case 0:
 659                 p->code_rate_LP = FEC_1_2;
 660                 break;
 661         case 1:
 662                 p->code_rate_LP = FEC_2_3;
 663                 break;
 664         case 2:
 665                 p->code_rate_LP = FEC_3_4;
 666                 break;
 667         case 3:
 668                 p->code_rate_LP = FEC_5_6;
 669                 break;
 670         case 4:
 671                 p->code_rate_LP = FEC_7_8;
 672                 break;
 673         }
 674
 675         val = tda10048_readreg(state, TDA10048_OUT_CONF1);
 676         switch ((val & 0x0c) >> 2) {
 677         case 0:
 678                 p->guard_interval = GUARD_INTERVAL_1_32;
 679                 break;
 680         case 1:
 681                 p->guard_interval = GUARD_INTERVAL_1_16;
 682                 break;
 683         case 2:
 684                 p->guard_interval =  GUARD_INTERVAL_1_8;
 685                 break;
 686         case 3:
 687                 p->guard_interval =  GUARD_INTERVAL_1_4;
 688                 break;
 689         }
 690         switch (val & 0x02) {
 691         case 0:
 692                 p->transmission_mode = TRANSMISSION_MODE_2K;
 693                 break;
 694         case 1:
 695                 p->transmission_mode = TRANSMISSION_MODE_8K;
 696                 break;
 697         }
 698
 699         return 0;
 700 }
 701
 702 static int tda10048_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
 703 {
 704         struct tda10048_state *state = fe->demodulator_priv;
 705         struct tda10048_config *config = &state->config;
 706         dprintk(1, "%s(%d)\n", __func__, enable);
 707
 708         if (config->disable_gate_access)
 709                 return 0;
 710
 711         if (enable)
 712                 return tda10048_writereg(state, TDA10048_CONF_C4_1,
 713                         tda10048_readreg(state, TDA10048_CONF_C4_1) | 0x02);
 714         else
 715                 return tda10048_writereg(state, TDA10048_CONF_C4_1,
 716                         tda10048_readreg(state, TDA10048_CONF_C4_1) & 0xfd);
 717 }
 718
 719 static int tda10048_output_mode(struct dvb_frontend *fe, int serial)
 720 {
 721         struct tda10048_state *state = fe->demodulator_priv;
 722         dprintk(1, "%s(%d)\n", __func__, serial);
 723
 724         /* Ensure pins are out of tri-state */
 725         tda10048_writereg(state, TDA10048_CONF_TRISTATE1, 0x21);
 726         tda10048_writereg(state, TDA10048_CONF_TRISTATE2, 0x00);
 727
 728         if (serial) {
 729                 tda10048_writereg(state, TDA10048_IC_MODE, 0x80 | 0x20);
 730                 tda10048_writereg(state, TDA10048_CONF_TS2, 0xc0);
 731         } else {
 732                 tda10048_writereg(state, TDA10048_IC_MODE, 0x00);
 733                 tda10048_writereg(state, TDA10048_CONF_TS2, 0x01);
 734         }
 735
 736         return 0;
 737 }
 738
 739 /* Talk to the demod, set the FEC, GUARD, QAM settings etc */
 740 /* TODO: Support manual tuning with specific params */
 741 static int tda10048_set_frontend(struct dvb_frontend *fe,
 742         struct dvb_frontend_parameters *p)
 743 {
 744         struct tda10048_state *state = fe->demodulator_priv;
 745
 746         dprintk(1, "%s(frequency=%d)\n", __func__, p->frequency);
 747
 748         /* Update the I/F pll's if the bandwidth changes */
 749         if (p->u.ofdm.bandwidth != state->bandwidth) {
 750                 tda10048_set_if(fe, p->u.ofdm.bandwidth);
 751                 tda10048_set_bandwidth(fe, p->u.ofdm.bandwidth);
 752         }
 753
 754         if (fe->ops.tuner_ops.set_params) {
 755
 756                 if (fe->ops.i2c_gate_ctrl)
 757                         fe->ops.i2c_gate_ctrl(fe, 1);
 758
 759                 fe->ops.tuner_ops.set_params(fe, p);
 760
 761                 if (fe->ops.i2c_gate_ctrl)
 762                         fe->ops.i2c_gate_ctrl(fe, 0);
 763         }
 764
 765         /* Enable demod TPS auto detection and begin acquisition */
 766         tda10048_writereg(state, TDA10048_AUTO, 0x57);
 767
 768         return 0;
 769 }
 770
 771 /* Establish sane defaults and load firmware. */
 772 static int tda10048_init(struct dvb_frontend *fe)
 773 {
 774         struct tda10048_state *state = fe->demodulator_priv;
 775         struct tda10048_config *config = &state->config;
 776         int ret = 0, i;
 777
 778         dprintk(1, "%s()\n", __func__);
 779
 780         /* Apply register defaults */
 781         for (i = 0; i < ARRAY_SIZE(init_tab); i++)
 782                 tda10048_writereg(state, init_tab[i].reg, init_tab[i].data);
 783
 784         if (state->fwloaded == 0)
 785                 ret = tda10048_firmware_upload(fe);
 786
 787         /* Set either serial or parallel */
 788         tda10048_output_mode(fe, config->output_mode);
 789
 790         /* Set inversion */
 791         tda10048_set_inversion(fe, config->inversion);
 792
 793         /* Establish default RF values */
 794         tda10048_set_if(fe, BANDWIDTH_8_MHZ);
 795         tda10048_set_bandwidth(fe, BANDWIDTH_8_MHZ);
 796
 797         /* Ensure we leave the gate closed */
 798         tda10048_i2c_gate_ctrl(fe, 0);
 799
 800         return ret;
 801 }
 802
 803 static int tda10048_read_status(struct dvb_frontend *fe, fe_status_t *status)
 804 {
 805         struct tda10048_state *state = fe->demodulator_priv;
 806         u8 reg;
 807
 808         *status = 0;
 809
 810         reg = tda10048_readreg(state, TDA10048_SYNC_STATUS);
 811
 812         dprintk(1, "%s() status =0x%02x\n", __func__, reg);
 813
 814         if (reg & 0x02)
 815                 *status |= FE_HAS_CARRIER;
 816
 817         if (reg & 0x04)
 818                 *status |= FE_HAS_SIGNAL;
 819
 820         if (reg & 0x08) {
 821                 *status |= FE_HAS_LOCK;
 822                 *status |= FE_HAS_VITERBI;
 823                 *status |= FE_HAS_SYNC;
 824         }
 825
 826         return 0;
 827 }
 828
 829 static int tda10048_read_ber(struct dvb_frontend *fe, u32 *ber)
 830 {
 831         struct tda10048_state *state = fe->demodulator_priv;
 832
 833         dprintk(1, "%s()\n", __func__);
 834
 835         /* TODO: A reset may be required here */
 836         *ber = tda10048_readreg(state, TDA10048_CBER_MSB) << 8 |
 837                 tda10048_readreg(state, TDA10048_CBER_LSB);
 838
 839         return 0;
 840 }
 841
 842 static int tda10048_read_signal_strength(struct dvb_frontend *fe,
 843         u16 *signal_strength)
 844 {
 845         struct tda10048_state *state = fe->demodulator_priv;
 846         u8 v;
 847
 848         dprintk(1, "%s()\n", __func__);
 849
 850         *signal_strength = 65535;
 851
 852         v = tda10048_readreg(state, TDA10048_NP_OUT);
 853         if (v > 0)
 854                 *signal_strength -= (v << 8) | v;
 855
 856         return 0;
 857 }
 858
 859 /* SNR lookup table */
 860 static struct snr_tab {
 861         u8 val;
 862         u8 data;
 863 } snr_tab[] = {
 864         {   0,   0 },
 865         {   1, 246 },
 866         {   2, 215 },
 867         {   3, 198 },
 868         {   4, 185 },
 869         {   5, 176 },
 870         {   6, 168 },
 871         {   7, 161 },
 872         {   8, 155 },
 873         {   9, 150 },
 874         {  10, 146 },
 875         {  11, 141 },
 876         {  12, 138 },
 877         {  13, 134 },
 878         {  14, 131 },
 879         {  15, 128 },
 880         {  16, 125 },
 881         {  17, 122 },
 882         {  18, 120 },
 883         {  19, 118 },
 884         {  20, 115 },
 885         {  21, 113 },
 886         {  22, 111 },
 887         {  23, 109 },
 888         {  24, 107 },
 889         {  25, 106 },
 890         {  26, 104 },
 891         {  27, 102 },
 892         {  28, 101 },
 893         {  29,  99 },
 894         {  30,  98 },
 895         {  31,  96 },
 896         {  32,  95 },
 897         {  33,  94 },
 898         {  34,  92 },
 899         {  35,  91 },
 900         {  36,  90 },
 901         {  37,  89 },
 902         {  38,  88 },
 903         {  39,  86 },
 904         {  40,  85 },
 905         {  41,  84 },
 906         {  42,  83 },
 907         {  43,  82 },
 908         {  44,  81 },
 909         {  45,  80 },
 910         {  46,  79 },
 911         {  47,  78 },
 912         {  48,  77 },
 913         {  49,  76 },
 914         {  50,  76 },
 915         {  51,  75 },
 916         {  52,  74 },
 917         {  53,  73 },
 918         {  54,  72 },
 919         {  56,  71 },
 920         {  57,  70 },
 921         {  58,  69 },
 922         {  60,  68 },
 923         {  61,  67 },
 924         {  63,  66 },
 925         {  64,  65 },
 926         {  66,  64 },
 927         {  67,  63 },
 928         {  68,  62 },
 929         {  69,  62 },
 930         {  70,  61 },
 931         {  72,  60 },
 932         {  74,  59 },
 933         {  75,  58 },
 934         {  77,  57 },
 935         {  79,  56 },
 936         {  81,  55 },
 937         {  83,  54 },
 938         {  85,  53 },
 939         {  87,  52 },
 940         {  89,  51 },
 941         {  91,  50 },
 942         {  93,  49 },
 943         {  95,  48 },
 944         {  97,  47 },
 945         { 100,  46 },
 946         { 102,  45 },
 947         { 104,  44 },
 948         { 107,  43 },
 949         { 109,  42 },
 950         { 112,  41 },
 951         { 114,  40 },
 952         { 117,  39 },
 953         { 120,  38 },
 954         { 123,  37 },
 955         { 125,  36 },
 956         { 128,  35 },
 957         { 131,  34 },
 958         { 134,  33 },
 959         { 138,  32 },
 960         { 141,  31 },
 961         { 144,  30 },
 962         { 147,  29 },
 963         { 151,  28 },
 964         { 154,  27 },
 965         { 158,  26 },
 966         { 162,  25 },
 967         { 165,  24 },
 968         { 169,  23 },
 969         { 173,  22 },
 970         { 177,  21 },
 971         { 181,  20 },
 972         { 186,  19 },
 973         { 190,  18 },
 974         { 194,  17 },
 975         { 199,  16 },
 976         { 204,  15 },
 977         { 208,  14 },
 978         { 213,  13 },
 979         { 218,  12 },
 980         { 223,  11 },
 981         { 229,  10 },
 982         { 234,   9 },
 983         { 239,   8 },
 984         { 245,   7 },
 985         { 251,   6 },
 986         { 255,   5 },
 987 };
 988
 989 static int tda10048_read_snr(struct dvb_frontend *fe, u16 *snr)
 990 {
 991         struct tda10048_state *state = fe->demodulator_priv;
 992         u8 v;
 993         int i, ret = -EINVAL;
 994
 995         dprintk(1, "%s()\n", __func__);
 996
 997         v = tda10048_readreg(state, TDA10048_NP_OUT);
 998         for (i = 0; i < ARRAY_SIZE(snr_tab); i++) {
 999                 if (v <= snr_tab[i].val) {
1000                         *snr = snr_tab[i].data;
1001                         ret = 0;
1002                         break;
1003                 }
1004         }
1005
1006         return ret;
1007 }
1008
1009 static int tda10048_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1010 {
1011         struct tda10048_state *state = fe->demodulator_priv;
1012
1013         dprintk(1, "%s()\n", __func__);
1014
1015         *ucblocks = tda10048_readreg(state, TDA10048_UNCOR_CPT_MSB) << 8 |
1016                 tda10048_readreg(state, TDA10048_UNCOR_CPT_LSB);
1017
1018         return 0;
1019 }
1020
1021 static int tda10048_get_frontend(struct dvb_frontend *fe,
1022         struct dvb_frontend_parameters *p)
1023 {
1024         struct tda10048_state *state = fe->demodulator_priv;
1025
1026         dprintk(1, "%s()\n", __func__);
1027
1028         p->inversion = tda10048_readreg(state, TDA10048_CONF_C1_1)
1029                 & 0x20 ? INVERSION_ON : INVERSION_OFF;
1030
1031         return tda10048_get_tps(state, &p->u.ofdm);
1032 }
1033
1034 static int tda10048_get_tune_settings(struct dvb_frontend *fe,
1035         struct dvb_frontend_tune_settings *tune)
1036 {
1037         tune->min_delay_ms = 1000;
1038         return 0;
1039 }
1040
1041 static void tda10048_release(struct dvb_frontend *fe)
1042 {
1043         struct tda10048_state *state = fe->demodulator_priv;
1044         dprintk(1, "%s()\n", __func__);
1045         kfree(state);
1046 }
1047
1048 static void tda10048_establish_defaults(struct dvb_frontend *fe)
1049 {
1050         struct tda10048_state *state = fe->demodulator_priv;
1051         struct tda10048_config *config = &state->config;
1052
1053         /* Validate/default the config */
1054         if (config->dtv6_if_freq_khz == 0) {
1055                 config->dtv6_if_freq_khz = TDA10048_IF_4300;
1056                 printk(KERN_WARNING "%s() tda10048_config.dtv6_if_freq_khz "
1057                         "is not set (defaulting to %d)\n",
1058                         __func__,
1059                         config->dtv6_if_freq_khz);
1060         }
1061
1062         if (config->dtv7_if_freq_khz == 0) {
1063                 config->dtv7_if_freq_khz = TDA10048_IF_4300;
1064                 printk(KERN_WARNING "%s() tda10048_config.dtv7_if_freq_khz "
1065                         "is not set (defaulting to %d)\n",
1066                         __func__,
1067                         config->dtv7_if_freq_khz);
1068         }
1069
1070         if (config->dtv8_if_freq_khz == 0) {
1071                 config->dtv8_if_freq_khz = TDA10048_IF_4300;
1072                 printk(KERN_WARNING "%s() tda10048_config.dtv8_if_freq_khz "
1073                         "is not set (defaulting to %d)\n",
1074                         __func__,
1075                         config->dtv8_if_freq_khz);
1076         }
1077
1078         if (config->clk_freq_khz == 0) {
1079                 config->clk_freq_khz = TDA10048_CLK_16000;
1080                 printk(KERN_WARNING "%s() tda10048_config.clk_freq_khz "
1081                         "is not set (defaulting to %d)\n",
1082                         __func__,
1083                         config->clk_freq_khz);
1084         }
1085 }
1086
1087 static struct dvb_frontend_ops tda10048_ops;
1088
1089 struct dvb_frontend *tda10048_attach(const struct tda10048_config *config,
1090         struct i2c_adapter *i2c)
1091 {
1092         struct tda10048_state *state = NULL;
1093
1094         dprintk(1, "%s()\n", __func__);
1095
1096         /* allocate memory for the internal state */
1097         state = kmalloc(sizeof(struct tda10048_state), GFP_KERNEL);
1098         if (state == NULL)
1099                 goto error;
1100
1101         /* setup the state and clone the config */
1102         memcpy(&state->config, config, sizeof(*config));
1103         state->i2c = i2c;
1104         state->fwloaded = 0;
1105         state->bandwidth = BANDWIDTH_8_MHZ;
1106
1107         /* check if the demod is present */
1108         if (tda10048_readreg(state, TDA10048_IDENTITY) != 0x048)
1109                 goto error;
1110
1111         /* create dvb_frontend */
1112         memcpy(&state->frontend.ops, &tda10048_ops,
1113                 sizeof(struct dvb_frontend_ops));
1114         state->frontend.demodulator_priv = state;
1115
1116         /* Establish any defaults the the user didn't pass */
1117         tda10048_establish_defaults(&state->frontend);
1118
1119         /* Set the xtal and freq defaults */
1120         if (tda10048_set_if(&state->frontend, BANDWIDTH_8_MHZ) != 0)
1121                 goto error;
1122
1123         /* Default bandwidth */
1124         if (tda10048_set_bandwidth(&state->frontend, BANDWIDTH_8_MHZ) != 0)
1125                 goto error;
1126
1127         /* Leave the gate closed */
1128         tda10048_i2c_gate_ctrl(&state->frontend, 0);
1129
1130         return &state->frontend;
1131
1132 error:
1133         kfree(state);
1134         return NULL;
1135 }
1136 EXPORT_SYMBOL(tda10048_attach);
1137
1138 static struct dvb_frontend_ops tda10048_ops = {
1139
1140         .info = {
1141                 .name                   = "NXP TDA10048HN DVB-T",
1142                 .type                   = FE_OFDM,
1143                 .frequency_min          = 177000000,
1144                 .frequency_max          = 858000000,
1145                 .frequency_stepsize     = 166666,
1146                 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1147                 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1148                 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1149                 FE_CAN_HIERARCHY_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
1150                 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER
1151         },
1152
1153         .release = tda10048_release,
1154         .init = tda10048_init,
1155         .i2c_gate_ctrl = tda10048_i2c_gate_ctrl,
1156         .set_frontend = tda10048_set_frontend,
1157         .get_frontend = tda10048_get_frontend,
1158         .get_tune_settings = tda10048_get_tune_settings,
1159         .read_status = tda10048_read_status,
1160         .read_ber = tda10048_read_ber,
1161         .read_signal_strength = tda10048_read_signal_strength,
1162         .read_snr = tda10048_read_snr,
1163         .read_ucblocks = tda10048_read_ucblocks,
1164 };
1165
1166 module_param(debug, int, 0644);
1167 MODULE_PARM_DESC(debug, "Enable verbose debug messages");
1168
1169 MODULE_DESCRIPTION("NXP TDA10048HN DVB-T Demodulator driver");
1170 MODULE_AUTHOR("Steven Toth");
1171 MODULE_LICENSE("GPL");