2 STV0900/0903 Multistandard Broadcast Frontend driver
3 Copyright (C) Manu Abraham <abraham.manu@gmail.com>
5 Copyright (C) ST Microelectronics
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #include <linux/init.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/string.h>
26 #include <linux/slab.h>
27 #include <linux/mutex.h>
29 #include <linux/dvb/frontend.h>
30 #include "dvb_frontend.h"
32 #include "stv6110x.h" /* for demodulator internal modes */
34 #include "stv090x_reg.h"
36 #include "stv090x_priv.h"
38 static unsigned int verbose;
39 module_param(verbose, int, 0644);
41 /* internal params node */
43 /* pointer for internal params, one for each pair of demods */
44 struct stv090x_internal *internal;
45 struct stv090x_dev *next_dev;
48 /* first internal params */
49 static struct stv090x_dev *stv090x_first_dev;
51 /* find chip by i2c adapter and i2c address */
52 static struct stv090x_dev *find_dev(struct i2c_adapter *i2c_adap,
55 struct stv090x_dev *temp_dev = stv090x_first_dev;
58 Search of the last stv0900 chip or
59 find it by i2c adapter and i2c address */
60 while ((temp_dev != NULL) &&
61 ((temp_dev->internal->i2c_adap != i2c_adap) ||
62 (temp_dev->internal->i2c_addr != i2c_addr))) {
64 temp_dev = temp_dev->next_dev;
70 /* deallocating chip */
71 static void remove_dev(struct stv090x_internal *internal)
73 struct stv090x_dev *prev_dev = stv090x_first_dev;
74 struct stv090x_dev *del_dev = find_dev(internal->i2c_adap,
77 if (del_dev != NULL) {
78 if (del_dev == stv090x_first_dev) {
79 stv090x_first_dev = del_dev->next_dev;
81 while (prev_dev->next_dev != del_dev)
82 prev_dev = prev_dev->next_dev;
84 prev_dev->next_dev = del_dev->next_dev;
91 /* allocating new chip */
92 static struct stv090x_dev *append_internal(struct stv090x_internal *internal)
94 struct stv090x_dev *new_dev;
95 struct stv090x_dev *temp_dev;
97 new_dev = kmalloc(sizeof(struct stv090x_dev), GFP_KERNEL);
98 if (new_dev != NULL) {
99 new_dev->internal = internal;
100 new_dev->next_dev = NULL;
103 if (stv090x_first_dev == NULL) {
104 stv090x_first_dev = new_dev;
106 temp_dev = stv090x_first_dev;
107 while (temp_dev->next_dev != NULL)
108 temp_dev = temp_dev->next_dev;
110 temp_dev->next_dev = new_dev;
118 /* DVBS1 and DSS C/N Lookup table */
119 static const struct stv090x_tab stv090x_s1cn_tab[] = {
120 { 0, 8917 }, /* 0.0dB */
121 { 5, 8801 }, /* 0.5dB */
122 { 10, 8667 }, /* 1.0dB */
123 { 15, 8522 }, /* 1.5dB */
124 { 20, 8355 }, /* 2.0dB */
125 { 25, 8175 }, /* 2.5dB */
126 { 30, 7979 }, /* 3.0dB */
127 { 35, 7763 }, /* 3.5dB */
128 { 40, 7530 }, /* 4.0dB */
129 { 45, 7282 }, /* 4.5dB */
130 { 50, 7026 }, /* 5.0dB */
131 { 55, 6781 }, /* 5.5dB */
132 { 60, 6514 }, /* 6.0dB */
133 { 65, 6241 }, /* 6.5dB */
134 { 70, 5965 }, /* 7.0dB */
135 { 75, 5690 }, /* 7.5dB */
136 { 80, 5424 }, /* 8.0dB */
137 { 85, 5161 }, /* 8.5dB */
138 { 90, 4902 }, /* 9.0dB */
139 { 95, 4654 }, /* 9.5dB */
140 { 100, 4417 }, /* 10.0dB */
141 { 105, 4186 }, /* 10.5dB */
142 { 110, 3968 }, /* 11.0dB */
143 { 115, 3757 }, /* 11.5dB */
144 { 120, 3558 }, /* 12.0dB */
145 { 125, 3366 }, /* 12.5dB */
146 { 130, 3185 }, /* 13.0dB */
147 { 135, 3012 }, /* 13.5dB */
148 { 140, 2850 }, /* 14.0dB */
149 { 145, 2698 }, /* 14.5dB */
150 { 150, 2550 }, /* 15.0dB */
151 { 160, 2283 }, /* 16.0dB */
152 { 170, 2042 }, /* 17.0dB */
153 { 180, 1827 }, /* 18.0dB */
154 { 190, 1636 }, /* 19.0dB */
155 { 200, 1466 }, /* 20.0dB */
156 { 210, 1315 }, /* 21.0dB */
157 { 220, 1181 }, /* 22.0dB */
158 { 230, 1064 }, /* 23.0dB */
159 { 240, 960 }, /* 24.0dB */
160 { 250, 869 }, /* 25.0dB */
161 { 260, 792 }, /* 26.0dB */
162 { 270, 724 }, /* 27.0dB */
163 { 280, 665 }, /* 28.0dB */
164 { 290, 616 }, /* 29.0dB */
165 { 300, 573 }, /* 30.0dB */
166 { 310, 537 }, /* 31.0dB */
167 { 320, 507 }, /* 32.0dB */
168 { 330, 483 }, /* 33.0dB */
169 { 400, 398 }, /* 40.0dB */
170 { 450, 381 }, /* 45.0dB */
171 { 500, 377 } /* 50.0dB */
174 /* DVBS2 C/N Lookup table */
175 static const struct stv090x_tab stv090x_s2cn_tab[] = {
176 { -30, 13348 }, /* -3.0dB */
177 { -20, 12640 }, /* -2d.0B */
178 { -10, 11883 }, /* -1.0dB */
179 { 0, 11101 }, /* -0.0dB */
180 { 5, 10718 }, /* 0.5dB */
181 { 10, 10339 }, /* 1.0dB */
182 { 15, 9947 }, /* 1.5dB */
183 { 20, 9552 }, /* 2.0dB */
184 { 25, 9183 }, /* 2.5dB */
185 { 30, 8799 }, /* 3.0dB */
186 { 35, 8422 }, /* 3.5dB */
187 { 40, 8062 }, /* 4.0dB */
188 { 45, 7707 }, /* 4.5dB */
189 { 50, 7353 }, /* 5.0dB */
190 { 55, 7025 }, /* 5.5dB */
191 { 60, 6684 }, /* 6.0dB */
192 { 65, 6331 }, /* 6.5dB */
193 { 70, 6036 }, /* 7.0dB */
194 { 75, 5727 }, /* 7.5dB */
195 { 80, 5437 }, /* 8.0dB */
196 { 85, 5164 }, /* 8.5dB */
197 { 90, 4902 }, /* 9.0dB */
198 { 95, 4653 }, /* 9.5dB */
199 { 100, 4408 }, /* 10.0dB */
200 { 105, 4187 }, /* 10.5dB */
201 { 110, 3961 }, /* 11.0dB */
202 { 115, 3751 }, /* 11.5dB */
203 { 120, 3558 }, /* 12.0dB */
204 { 125, 3368 }, /* 12.5dB */
205 { 130, 3191 }, /* 13.0dB */
206 { 135, 3017 }, /* 13.5dB */
207 { 140, 2862 }, /* 14.0dB */
208 { 145, 2710 }, /* 14.5dB */
209 { 150, 2565 }, /* 15.0dB */
210 { 160, 2300 }, /* 16.0dB */
211 { 170, 2058 }, /* 17.0dB */
212 { 180, 1849 }, /* 18.0dB */
213 { 190, 1663 }, /* 19.0dB */
214 { 200, 1495 }, /* 20.0dB */
215 { 210, 1349 }, /* 21.0dB */
216 { 220, 1222 }, /* 22.0dB */
217 { 230, 1110 }, /* 23.0dB */
218 { 240, 1011 }, /* 24.0dB */
219 { 250, 925 }, /* 25.0dB */
220 { 260, 853 }, /* 26.0dB */
221 { 270, 789 }, /* 27.0dB */
222 { 280, 734 }, /* 28.0dB */
223 { 290, 690 }, /* 29.0dB */
224 { 300, 650 }, /* 30.0dB */
225 { 310, 619 }, /* 31.0dB */
226 { 320, 593 }, /* 32.0dB */
227 { 330, 571 }, /* 33.0dB */
228 { 400, 498 }, /* 40.0dB */
229 { 450, 484 }, /* 45.0dB */
230 { 500, 481 } /* 50.0dB */
233 /* RF level C/N lookup table */
234 static const struct stv090x_tab stv090x_rf_tab[] = {
235 { -5, 0xcaa1 }, /* -5dBm */
236 { -10, 0xc229 }, /* -10dBm */
237 { -15, 0xbb08 }, /* -15dBm */
238 { -20, 0xb4bc }, /* -20dBm */
239 { -25, 0xad5a }, /* -25dBm */
240 { -30, 0xa298 }, /* -30dBm */
241 { -35, 0x98a8 }, /* -35dBm */
242 { -40, 0x8389 }, /* -40dBm */
243 { -45, 0x59be }, /* -45dBm */
244 { -50, 0x3a14 }, /* -50dBm */
245 { -55, 0x2d11 }, /* -55dBm */
246 { -60, 0x210d }, /* -60dBm */
247 { -65, 0xa14f }, /* -65dBm */
248 { -70, 0x07aa } /* -70dBm */
252 static struct stv090x_reg stv0900_initval[] = {
254 { STV090x_OUTCFG, 0x00 },
255 { STV090x_MODECFG, 0xff },
256 { STV090x_AGCRF1CFG, 0x11 },
257 { STV090x_AGCRF2CFG, 0x13 },
258 { STV090x_TSGENERAL1X, 0x14 },
259 { STV090x_TSTTNR2, 0x21 },
260 { STV090x_TSTTNR4, 0x21 },
261 { STV090x_P2_DISTXCTL, 0x22 },
262 { STV090x_P2_F22TX, 0xc0 },
263 { STV090x_P2_F22RX, 0xc0 },
264 { STV090x_P2_DISRXCTL, 0x00 },
265 { STV090x_P2_DMDCFGMD, 0xF9 },
266 { STV090x_P2_DEMOD, 0x08 },
267 { STV090x_P2_DMDCFG3, 0xc4 },
268 { STV090x_P2_CARFREQ, 0xed },
269 { STV090x_P2_LDT, 0xd0 },
270 { STV090x_P2_LDT2, 0xb8 },
271 { STV090x_P2_TMGCFG, 0xd2 },
272 { STV090x_P2_TMGTHRISE, 0x20 },
273 { STV090x_P1_TMGCFG, 0xd2 },
275 { STV090x_P2_TMGTHFALL, 0x00 },
276 { STV090x_P2_FECSPY, 0x88 },
277 { STV090x_P2_FSPYDATA, 0x3a },
278 { STV090x_P2_FBERCPT4, 0x00 },
279 { STV090x_P2_FSPYBER, 0x10 },
280 { STV090x_P2_ERRCTRL1, 0x35 },
281 { STV090x_P2_ERRCTRL2, 0xc1 },
282 { STV090x_P2_CFRICFG, 0xf8 },
283 { STV090x_P2_NOSCFG, 0x1c },
284 { STV090x_P2_DMDTOM, 0x20 },
285 { STV090x_P2_CORRELMANT, 0x70 },
286 { STV090x_P2_CORRELABS, 0x88 },
287 { STV090x_P2_AGC2O, 0x5b },
288 { STV090x_P2_AGC2REF, 0x38 },
289 { STV090x_P2_CARCFG, 0xe4 },
290 { STV090x_P2_ACLC, 0x1A },
291 { STV090x_P2_BCLC, 0x09 },
292 { STV090x_P2_CARHDR, 0x08 },
293 { STV090x_P2_KREFTMG, 0xc1 },
294 { STV090x_P2_SFRUPRATIO, 0xf0 },
295 { STV090x_P2_SFRLOWRATIO, 0x70 },
296 { STV090x_P2_SFRSTEP, 0x58 },
297 { STV090x_P2_TMGCFG2, 0x01 },
298 { STV090x_P2_CAR2CFG, 0x26 },
299 { STV090x_P2_BCLC2S2Q, 0x86 },
300 { STV090x_P2_BCLC2S28, 0x86 },
301 { STV090x_P2_SMAPCOEF7, 0x77 },
302 { STV090x_P2_SMAPCOEF6, 0x85 },
303 { STV090x_P2_SMAPCOEF5, 0x77 },
304 { STV090x_P2_TSCFGL, 0x20 },
305 { STV090x_P2_DMDCFG2, 0x3b },
306 { STV090x_P2_MODCODLST0, 0xff },
307 { STV090x_P2_MODCODLST1, 0xff },
308 { STV090x_P2_MODCODLST2, 0xff },
309 { STV090x_P2_MODCODLST3, 0xff },
310 { STV090x_P2_MODCODLST4, 0xff },
311 { STV090x_P2_MODCODLST5, 0xff },
312 { STV090x_P2_MODCODLST6, 0xff },
313 { STV090x_P2_MODCODLST7, 0xcc },
314 { STV090x_P2_MODCODLST8, 0xcc },
315 { STV090x_P2_MODCODLST9, 0xcc },
316 { STV090x_P2_MODCODLSTA, 0xcc },
317 { STV090x_P2_MODCODLSTB, 0xcc },
318 { STV090x_P2_MODCODLSTC, 0xcc },
319 { STV090x_P2_MODCODLSTD, 0xcc },
320 { STV090x_P2_MODCODLSTE, 0xcc },
321 { STV090x_P2_MODCODLSTF, 0xcf },
322 { STV090x_P1_DISTXCTL, 0x22 },
323 { STV090x_P1_F22TX, 0xc0 },
324 { STV090x_P1_F22RX, 0xc0 },
325 { STV090x_P1_DISRXCTL, 0x00 },
326 { STV090x_P1_DMDCFGMD, 0xf9 },
327 { STV090x_P1_DEMOD, 0x08 },
328 { STV090x_P1_DMDCFG3, 0xc4 },
329 { STV090x_P1_DMDTOM, 0x20 },
330 { STV090x_P1_CARFREQ, 0xed },
331 { STV090x_P1_LDT, 0xd0 },
332 { STV090x_P1_LDT2, 0xb8 },
333 { STV090x_P1_TMGCFG, 0xd2 },
334 { STV090x_P1_TMGTHRISE, 0x20 },
335 { STV090x_P1_TMGTHFALL, 0x00 },
336 { STV090x_P1_SFRUPRATIO, 0xf0 },
337 { STV090x_P1_SFRLOWRATIO, 0x70 },
338 { STV090x_P1_TSCFGL, 0x20 },
339 { STV090x_P1_FECSPY, 0x88 },
340 { STV090x_P1_FSPYDATA, 0x3a },
341 { STV090x_P1_FBERCPT4, 0x00 },
342 { STV090x_P1_FSPYBER, 0x10 },
343 { STV090x_P1_ERRCTRL1, 0x35 },
344 { STV090x_P1_ERRCTRL2, 0xc1 },
345 { STV090x_P1_CFRICFG, 0xf8 },
346 { STV090x_P1_NOSCFG, 0x1c },
347 { STV090x_P1_CORRELMANT, 0x70 },
348 { STV090x_P1_CORRELABS, 0x88 },
349 { STV090x_P1_AGC2O, 0x5b },
350 { STV090x_P1_AGC2REF, 0x38 },
351 { STV090x_P1_CARCFG, 0xe4 },
352 { STV090x_P1_ACLC, 0x1A },
353 { STV090x_P1_BCLC, 0x09 },
354 { STV090x_P1_CARHDR, 0x08 },
355 { STV090x_P1_KREFTMG, 0xc1 },
356 { STV090x_P1_SFRSTEP, 0x58 },
357 { STV090x_P1_TMGCFG2, 0x01 },
358 { STV090x_P1_CAR2CFG, 0x26 },
359 { STV090x_P1_BCLC2S2Q, 0x86 },
360 { STV090x_P1_BCLC2S28, 0x86 },
361 { STV090x_P1_SMAPCOEF7, 0x77 },
362 { STV090x_P1_SMAPCOEF6, 0x85 },
363 { STV090x_P1_SMAPCOEF5, 0x77 },
364 { STV090x_P1_DMDCFG2, 0x3b },
365 { STV090x_P1_MODCODLST0, 0xff },
366 { STV090x_P1_MODCODLST1, 0xff },
367 { STV090x_P1_MODCODLST2, 0xff },
368 { STV090x_P1_MODCODLST3, 0xff },
369 { STV090x_P1_MODCODLST4, 0xff },
370 { STV090x_P1_MODCODLST5, 0xff },
371 { STV090x_P1_MODCODLST6, 0xff },
372 { STV090x_P1_MODCODLST7, 0xcc },
373 { STV090x_P1_MODCODLST8, 0xcc },
374 { STV090x_P1_MODCODLST9, 0xcc },
375 { STV090x_P1_MODCODLSTA, 0xcc },
376 { STV090x_P1_MODCODLSTB, 0xcc },
377 { STV090x_P1_MODCODLSTC, 0xcc },
378 { STV090x_P1_MODCODLSTD, 0xcc },
379 { STV090x_P1_MODCODLSTE, 0xcc },
380 { STV090x_P1_MODCODLSTF, 0xcf },
381 { STV090x_GENCFG, 0x1d },
382 { STV090x_NBITER_NF4, 0x37 },
383 { STV090x_NBITER_NF5, 0x29 },
384 { STV090x_NBITER_NF6, 0x37 },
385 { STV090x_NBITER_NF7, 0x33 },
386 { STV090x_NBITER_NF8, 0x31 },
387 { STV090x_NBITER_NF9, 0x2f },
388 { STV090x_NBITER_NF10, 0x39 },
389 { STV090x_NBITER_NF11, 0x3a },
390 { STV090x_NBITER_NF12, 0x29 },
391 { STV090x_NBITER_NF13, 0x37 },
392 { STV090x_NBITER_NF14, 0x33 },
393 { STV090x_NBITER_NF15, 0x2f },
394 { STV090x_NBITER_NF16, 0x39 },
395 { STV090x_NBITER_NF17, 0x3a },
396 { STV090x_NBITERNOERR, 0x04 },
397 { STV090x_GAINLLR_NF4, 0x0C },
398 { STV090x_GAINLLR_NF5, 0x0F },
399 { STV090x_GAINLLR_NF6, 0x11 },
400 { STV090x_GAINLLR_NF7, 0x14 },
401 { STV090x_GAINLLR_NF8, 0x17 },
402 { STV090x_GAINLLR_NF9, 0x19 },
403 { STV090x_GAINLLR_NF10, 0x20 },
404 { STV090x_GAINLLR_NF11, 0x21 },
405 { STV090x_GAINLLR_NF12, 0x0D },
406 { STV090x_GAINLLR_NF13, 0x0F },
407 { STV090x_GAINLLR_NF14, 0x13 },
408 { STV090x_GAINLLR_NF15, 0x1A },
409 { STV090x_GAINLLR_NF16, 0x1F },
410 { STV090x_GAINLLR_NF17, 0x21 },
411 { STV090x_RCCFGH, 0x20 },
412 { STV090x_P1_FECM, 0x01 }, /* disable DSS modes */
413 { STV090x_P2_FECM, 0x01 }, /* disable DSS modes */
414 { STV090x_P1_PRVIT, 0x2F }, /* disable PR 6/7 */
415 { STV090x_P2_PRVIT, 0x2F }, /* disable PR 6/7 */
418 static struct stv090x_reg stv0903_initval[] = {
419 { STV090x_OUTCFG, 0x00 },
420 { STV090x_AGCRF1CFG, 0x11 },
421 { STV090x_STOPCLK1, 0x48 },
422 { STV090x_STOPCLK2, 0x14 },
423 { STV090x_TSTTNR1, 0x27 },
424 { STV090x_TSTTNR2, 0x21 },
425 { STV090x_P1_DISTXCTL, 0x22 },
426 { STV090x_P1_F22TX, 0xc0 },
427 { STV090x_P1_F22RX, 0xc0 },
428 { STV090x_P1_DISRXCTL, 0x00 },
429 { STV090x_P1_DMDCFGMD, 0xF9 },
430 { STV090x_P1_DEMOD, 0x08 },
431 { STV090x_P1_DMDCFG3, 0xc4 },
432 { STV090x_P1_CARFREQ, 0xed },
433 { STV090x_P1_TNRCFG2, 0x82 },
434 { STV090x_P1_LDT, 0xd0 },
435 { STV090x_P1_LDT2, 0xb8 },
436 { STV090x_P1_TMGCFG, 0xd2 },
437 { STV090x_P1_TMGTHRISE, 0x20 },
438 { STV090x_P1_TMGTHFALL, 0x00 },
439 { STV090x_P1_SFRUPRATIO, 0xf0 },
440 { STV090x_P1_SFRLOWRATIO, 0x70 },
441 { STV090x_P1_TSCFGL, 0x20 },
442 { STV090x_P1_FECSPY, 0x88 },
443 { STV090x_P1_FSPYDATA, 0x3a },
444 { STV090x_P1_FBERCPT4, 0x00 },
445 { STV090x_P1_FSPYBER, 0x10 },
446 { STV090x_P1_ERRCTRL1, 0x35 },
447 { STV090x_P1_ERRCTRL2, 0xc1 },
448 { STV090x_P1_CFRICFG, 0xf8 },
449 { STV090x_P1_NOSCFG, 0x1c },
450 { STV090x_P1_DMDTOM, 0x20 },
451 { STV090x_P1_CORRELMANT, 0x70 },
452 { STV090x_P1_CORRELABS, 0x88 },
453 { STV090x_P1_AGC2O, 0x5b },
454 { STV090x_P1_AGC2REF, 0x38 },
455 { STV090x_P1_CARCFG, 0xe4 },
456 { STV090x_P1_ACLC, 0x1A },
457 { STV090x_P1_BCLC, 0x09 },
458 { STV090x_P1_CARHDR, 0x08 },
459 { STV090x_P1_KREFTMG, 0xc1 },
460 { STV090x_P1_SFRSTEP, 0x58 },
461 { STV090x_P1_TMGCFG2, 0x01 },
462 { STV090x_P1_CAR2CFG, 0x26 },
463 { STV090x_P1_BCLC2S2Q, 0x86 },
464 { STV090x_P1_BCLC2S28, 0x86 },
465 { STV090x_P1_SMAPCOEF7, 0x77 },
466 { STV090x_P1_SMAPCOEF6, 0x85 },
467 { STV090x_P1_SMAPCOEF5, 0x77 },
468 { STV090x_P1_DMDCFG2, 0x3b },
469 { STV090x_P1_MODCODLST0, 0xff },
470 { STV090x_P1_MODCODLST1, 0xff },
471 { STV090x_P1_MODCODLST2, 0xff },
472 { STV090x_P1_MODCODLST3, 0xff },
473 { STV090x_P1_MODCODLST4, 0xff },
474 { STV090x_P1_MODCODLST5, 0xff },
475 { STV090x_P1_MODCODLST6, 0xff },
476 { STV090x_P1_MODCODLST7, 0xcc },
477 { STV090x_P1_MODCODLST8, 0xcc },
478 { STV090x_P1_MODCODLST9, 0xcc },
479 { STV090x_P1_MODCODLSTA, 0xcc },
480 { STV090x_P1_MODCODLSTB, 0xcc },
481 { STV090x_P1_MODCODLSTC, 0xcc },
482 { STV090x_P1_MODCODLSTD, 0xcc },
483 { STV090x_P1_MODCODLSTE, 0xcc },
484 { STV090x_P1_MODCODLSTF, 0xcf },
485 { STV090x_GENCFG, 0x1c },
486 { STV090x_NBITER_NF4, 0x37 },
487 { STV090x_NBITER_NF5, 0x29 },
488 { STV090x_NBITER_NF6, 0x37 },
489 { STV090x_NBITER_NF7, 0x33 },
490 { STV090x_NBITER_NF8, 0x31 },
491 { STV090x_NBITER_NF9, 0x2f },
492 { STV090x_NBITER_NF10, 0x39 },
493 { STV090x_NBITER_NF11, 0x3a },
494 { STV090x_NBITER_NF12, 0x29 },
495 { STV090x_NBITER_NF13, 0x37 },
496 { STV090x_NBITER_NF14, 0x33 },
497 { STV090x_NBITER_NF15, 0x2f },
498 { STV090x_NBITER_NF16, 0x39 },
499 { STV090x_NBITER_NF17, 0x3a },
500 { STV090x_NBITERNOERR, 0x04 },
501 { STV090x_GAINLLR_NF4, 0x0C },
502 { STV090x_GAINLLR_NF5, 0x0F },
503 { STV090x_GAINLLR_NF6, 0x11 },
504 { STV090x_GAINLLR_NF7, 0x14 },
505 { STV090x_GAINLLR_NF8, 0x17 },
506 { STV090x_GAINLLR_NF9, 0x19 },
507 { STV090x_GAINLLR_NF10, 0x20 },
508 { STV090x_GAINLLR_NF11, 0x21 },
509 { STV090x_GAINLLR_NF12, 0x0D },
510 { STV090x_GAINLLR_NF13, 0x0F },
511 { STV090x_GAINLLR_NF14, 0x13 },
512 { STV090x_GAINLLR_NF15, 0x1A },
513 { STV090x_GAINLLR_NF16, 0x1F },
514 { STV090x_GAINLLR_NF17, 0x21 },
515 { STV090x_RCCFGH, 0x20 },
516 { STV090x_P1_FECM, 0x01 }, /*disable the DSS mode */
517 { STV090x_P1_PRVIT, 0x2f } /*disable puncture rate 6/7*/
520 static struct stv090x_reg stv0900_cut20_val[] = {
522 { STV090x_P2_DMDCFG3, 0xe8 },
523 { STV090x_P2_DMDCFG4, 0x10 },
524 { STV090x_P2_CARFREQ, 0x38 },
525 { STV090x_P2_CARHDR, 0x20 },
526 { STV090x_P2_KREFTMG, 0x5a },
527 { STV090x_P2_SMAPCOEF7, 0x06 },
528 { STV090x_P2_SMAPCOEF6, 0x00 },
529 { STV090x_P2_SMAPCOEF5, 0x04 },
530 { STV090x_P2_NOSCFG, 0x0c },
531 { STV090x_P1_DMDCFG3, 0xe8 },
532 { STV090x_P1_DMDCFG4, 0x10 },
533 { STV090x_P1_CARFREQ, 0x38 },
534 { STV090x_P1_CARHDR, 0x20 },
535 { STV090x_P1_KREFTMG, 0x5a },
536 { STV090x_P1_SMAPCOEF7, 0x06 },
537 { STV090x_P1_SMAPCOEF6, 0x00 },
538 { STV090x_P1_SMAPCOEF5, 0x04 },
539 { STV090x_P1_NOSCFG, 0x0c },
540 { STV090x_GAINLLR_NF4, 0x21 },
541 { STV090x_GAINLLR_NF5, 0x21 },
542 { STV090x_GAINLLR_NF6, 0x20 },
543 { STV090x_GAINLLR_NF7, 0x1F },
544 { STV090x_GAINLLR_NF8, 0x1E },
545 { STV090x_GAINLLR_NF9, 0x1E },
546 { STV090x_GAINLLR_NF10, 0x1D },
547 { STV090x_GAINLLR_NF11, 0x1B },
548 { STV090x_GAINLLR_NF12, 0x20 },
549 { STV090x_GAINLLR_NF13, 0x20 },
550 { STV090x_GAINLLR_NF14, 0x20 },
551 { STV090x_GAINLLR_NF15, 0x20 },
552 { STV090x_GAINLLR_NF16, 0x20 },
553 { STV090x_GAINLLR_NF17, 0x21 },
556 static struct stv090x_reg stv0903_cut20_val[] = {
557 { STV090x_P1_DMDCFG3, 0xe8 },
558 { STV090x_P1_DMDCFG4, 0x10 },
559 { STV090x_P1_CARFREQ, 0x38 },
560 { STV090x_P1_CARHDR, 0x20 },
561 { STV090x_P1_KREFTMG, 0x5a },
562 { STV090x_P1_SMAPCOEF7, 0x06 },
563 { STV090x_P1_SMAPCOEF6, 0x00 },
564 { STV090x_P1_SMAPCOEF5, 0x04 },
565 { STV090x_P1_NOSCFG, 0x0c },
566 { STV090x_GAINLLR_NF4, 0x21 },
567 { STV090x_GAINLLR_NF5, 0x21 },
568 { STV090x_GAINLLR_NF6, 0x20 },
569 { STV090x_GAINLLR_NF7, 0x1F },
570 { STV090x_GAINLLR_NF8, 0x1E },
571 { STV090x_GAINLLR_NF9, 0x1E },
572 { STV090x_GAINLLR_NF10, 0x1D },
573 { STV090x_GAINLLR_NF11, 0x1B },
574 { STV090x_GAINLLR_NF12, 0x20 },
575 { STV090x_GAINLLR_NF13, 0x20 },
576 { STV090x_GAINLLR_NF14, 0x20 },
577 { STV090x_GAINLLR_NF15, 0x20 },
578 { STV090x_GAINLLR_NF16, 0x20 },
579 { STV090x_GAINLLR_NF17, 0x21 }
582 /* Cut 2.0 Long Frame Tracking CR loop */
583 static struct stv090x_long_frame_crloop stv090x_s2_crl_cut20[] = {
584 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
585 { STV090x_QPSK_12, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x1e },
586 { STV090x_QPSK_35, 0x2f, 0x3f, 0x2e, 0x2f, 0x3d, 0x0f, 0x0e, 0x2e, 0x3d, 0x0e },
587 { STV090x_QPSK_23, 0x2f, 0x3f, 0x2e, 0x2f, 0x0e, 0x0f, 0x0e, 0x1e, 0x3d, 0x3d },
588 { STV090x_QPSK_34, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
589 { STV090x_QPSK_45, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
590 { STV090x_QPSK_56, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
591 { STV090x_QPSK_89, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
592 { STV090x_QPSK_910, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
593 { STV090x_8PSK_35, 0x3c, 0x3e, 0x1c, 0x2e, 0x0c, 0x1e, 0x2b, 0x2d, 0x1b, 0x1d },
594 { STV090x_8PSK_23, 0x1d, 0x3e, 0x3c, 0x2e, 0x2c, 0x1e, 0x0c, 0x2d, 0x2b, 0x1d },
595 { STV090x_8PSK_34, 0x0e, 0x3e, 0x3d, 0x2e, 0x0d, 0x1e, 0x2c, 0x2d, 0x0c, 0x1d },
596 { STV090x_8PSK_56, 0x2e, 0x3e, 0x1e, 0x2e, 0x2d, 0x1e, 0x3c, 0x2d, 0x2c, 0x1d },
597 { STV090x_8PSK_89, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x0d, 0x2d, 0x3c, 0x1d },
598 { STV090x_8PSK_910, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x1d, 0x2d, 0x0d, 0x1d }
601 /* Cut 3.0 Long Frame Tracking CR loop */
602 static struct stv090x_long_frame_crloop stv090x_s2_crl_cut30[] = {
603 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
604 { STV090x_QPSK_12, 0x3c, 0x2c, 0x0c, 0x2c, 0x1b, 0x2c, 0x1b, 0x1c, 0x0b, 0x3b },
605 { STV090x_QPSK_35, 0x0d, 0x0d, 0x0c, 0x0d, 0x1b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
606 { STV090x_QPSK_23, 0x1d, 0x0d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
607 { STV090x_QPSK_34, 0x1d, 0x1d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
608 { STV090x_QPSK_45, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
609 { STV090x_QPSK_56, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
610 { STV090x_QPSK_89, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
611 { STV090x_QPSK_910, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
612 { STV090x_8PSK_35, 0x39, 0x29, 0x39, 0x19, 0x19, 0x19, 0x19, 0x19, 0x09, 0x19 },
613 { STV090x_8PSK_23, 0x2a, 0x39, 0x1a, 0x0a, 0x39, 0x0a, 0x29, 0x39, 0x29, 0x0a },
614 { STV090x_8PSK_34, 0x2b, 0x3a, 0x1b, 0x1b, 0x3a, 0x1b, 0x1a, 0x0b, 0x1a, 0x3a },
615 { STV090x_8PSK_56, 0x0c, 0x1b, 0x3b, 0x3b, 0x1b, 0x3b, 0x3a, 0x3b, 0x3a, 0x1b },
616 { STV090x_8PSK_89, 0x0d, 0x3c, 0x2c, 0x2c, 0x2b, 0x0c, 0x0b, 0x3b, 0x0b, 0x1b },
617 { STV090x_8PSK_910, 0x0d, 0x0d, 0x2c, 0x3c, 0x3b, 0x1c, 0x0b, 0x3b, 0x0b, 0x1b }
620 /* Cut 2.0 Long Frame Tracking CR Loop */
621 static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut20[] = {
622 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
623 { STV090x_16APSK_23, 0x0c, 0x0c, 0x0c, 0x0c, 0x1d, 0x0c, 0x3c, 0x0c, 0x2c, 0x0c },
624 { STV090x_16APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0e, 0x0c, 0x2d, 0x0c, 0x1d, 0x0c },
625 { STV090x_16APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
626 { STV090x_16APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
627 { STV090x_16APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
628 { STV090x_16APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
629 { STV090x_32APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
630 { STV090x_32APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
631 { STV090x_32APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
632 { STV090x_32APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
633 { STV090x_32APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }
636 /* Cut 3.0 Long Frame Tracking CR Loop */
637 static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut30[] = {
638 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
639 { STV090x_16APSK_23, 0x0a, 0x0a, 0x0a, 0x0a, 0x1a, 0x0a, 0x3a, 0x0a, 0x2a, 0x0a },
640 { STV090x_16APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0b, 0x0a, 0x3b, 0x0a, 0x1b, 0x0a },
641 { STV090x_16APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a },
642 { STV090x_16APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a },
643 { STV090x_16APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a },
644 { STV090x_16APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a },
645 { STV090x_32APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
646 { STV090x_32APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
647 { STV090x_32APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
648 { STV090x_32APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
649 { STV090x_32APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a }
652 static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut20[] = {
653 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
654 { STV090x_QPSK_14, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x2d, 0x1f, 0x3d, 0x3e },
655 { STV090x_QPSK_13, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x3d, 0x0f, 0x3d, 0x2e },
656 { STV090x_QPSK_25, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x2e }
659 static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut30[] = {
660 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
661 { STV090x_QPSK_14, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x2a, 0x1c, 0x3a, 0x3b },
662 { STV090x_QPSK_13, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x3a, 0x0c, 0x3a, 0x2b },
663 { STV090x_QPSK_25, 0x1c, 0x3c, 0x1b, 0x3c, 0x3a, 0x1c, 0x3a, 0x3b, 0x3a, 0x2b }
666 /* Cut 2.0 Short Frame Tracking CR Loop */
667 static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut20[] = {
668 /* MODCOD 2M 5M 10M 20M 30M */
669 { STV090x_QPSK, 0x2f, 0x2e, 0x0e, 0x0e, 0x3d },
670 { STV090x_8PSK, 0x3e, 0x0e, 0x2d, 0x0d, 0x3c },
671 { STV090x_16APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d },
672 { STV090x_32APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d }
675 /* Cut 3.0 Short Frame Tracking CR Loop */
676 static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut30[] = {
677 /* MODCOD 2M 5M 10M 20M 30M */
678 { STV090x_QPSK, 0x2C, 0x2B, 0x0B, 0x0B, 0x3A },
679 { STV090x_8PSK, 0x3B, 0x0B, 0x2A, 0x0A, 0x39 },
680 { STV090x_16APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A },
681 { STV090x_32APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A }
684 static inline s32 comp2(s32 __x, s32 __width)
689 return (__x >= (1 << (__width - 1))) ? (__x - (1 << __width)) : __x;
692 static int stv090x_read_reg(struct stv090x_state *state, unsigned int reg)
694 const struct stv090x_config *config = state->config;
697 u8 b0[] = { reg >> 8, reg & 0xff };
700 struct i2c_msg msg[] = {
701 { .addr = config->address, .flags = 0, .buf = b0, .len = 2 },
702 { .addr = config->address, .flags = I2C_M_RD, .buf = &buf, .len = 1 }
705 ret = i2c_transfer(state->i2c, msg, 2);
707 if (ret != -ERESTARTSYS)
709 "Read error, Reg=[0x%02x], Status=%d",
712 return ret < 0 ? ret : -EREMOTEIO;
714 if (unlikely(*state->verbose >= FE_DEBUGREG))
715 dprintk(FE_ERROR, 1, "Reg=[0x%02x], data=%02x",
718 return (unsigned int) buf;
721 static int stv090x_write_regs(struct stv090x_state *state, unsigned int reg, u8 *data, u32 count)
723 const struct stv090x_config *config = state->config;
726 struct i2c_msg i2c_msg = { .addr = config->address, .flags = 0, .buf = buf, .len = 2 + count };
730 memcpy(&buf[2], data, count);
732 if (unlikely(*state->verbose >= FE_DEBUGREG)) {
735 printk(KERN_DEBUG "%s [0x%04x]:", __func__, reg);
736 for (i = 0; i < count; i++)
737 printk(" %02x", data[i]);
741 ret = i2c_transfer(state->i2c, &i2c_msg, 1);
743 if (ret != -ERESTARTSYS)
744 dprintk(FE_ERROR, 1, "Reg=[0x%04x], Data=[0x%02x ...], Count=%u, Status=%d",
745 reg, data[0], count, ret);
746 return ret < 0 ? ret : -EREMOTEIO;
752 static int stv090x_write_reg(struct stv090x_state *state, unsigned int reg, u8 data)
754 return stv090x_write_regs(state, reg, &data, 1);
757 static int stv090x_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
759 struct stv090x_state *state = fe->demodulator_priv;
763 mutex_lock(&state->internal->tuner_lock);
765 reg = STV090x_READ_DEMOD(state, I2CRPT);
767 dprintk(FE_DEBUG, 1, "Enable Gate");
768 STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 1);
769 if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0)
773 dprintk(FE_DEBUG, 1, "Disable Gate");
774 STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 0);
775 if ((STV090x_WRITE_DEMOD(state, I2CRPT, reg)) < 0)
780 mutex_unlock(&state->internal->tuner_lock);
784 dprintk(FE_ERROR, 1, "I/O error");
785 mutex_unlock(&state->internal->tuner_lock);
789 static void stv090x_get_lock_tmg(struct stv090x_state *state)
791 switch (state->algo) {
792 case STV090x_BLIND_SEARCH:
793 dprintk(FE_DEBUG, 1, "Blind Search");
794 if (state->srate <= 1500000) { /*10Msps< SR <=15Msps*/
795 state->DemodTimeout = 1500;
796 state->FecTimeout = 400;
797 } else if (state->srate <= 5000000) { /*10Msps< SR <=15Msps*/
798 state->DemodTimeout = 1000;
799 state->FecTimeout = 300;
800 } else { /*SR >20Msps*/
801 state->DemodTimeout = 700;
802 state->FecTimeout = 100;
806 case STV090x_COLD_SEARCH:
807 case STV090x_WARM_SEARCH:
809 dprintk(FE_DEBUG, 1, "Normal Search");
810 if (state->srate <= 1000000) { /*SR <=1Msps*/
811 state->DemodTimeout = 4500;
812 state->FecTimeout = 1700;
813 } else if (state->srate <= 2000000) { /*1Msps < SR <= 2Msps */
814 state->DemodTimeout = 2500;
815 state->FecTimeout = 1100;
816 } else if (state->srate <= 5000000) { /*2Msps < SR <= 5Msps */
817 state->DemodTimeout = 1000;
818 state->FecTimeout = 550;
819 } else if (state->srate <= 10000000) { /*5Msps < SR <= 10Msps */
820 state->DemodTimeout = 700;
821 state->FecTimeout = 250;
822 } else if (state->srate <= 20000000) { /*10Msps < SR <= 20Msps */
823 state->DemodTimeout = 400;
824 state->FecTimeout = 130;
825 } else { /*SR >20Msps*/
826 state->DemodTimeout = 300;
827 state->FecTimeout = 100;
832 if (state->algo == STV090x_WARM_SEARCH)
833 state->DemodTimeout /= 2;
836 static int stv090x_set_srate(struct stv090x_state *state, u32 srate)
840 if (srate > 60000000) {
841 sym = (srate << 4); /* SR * 2^16 / master_clk */
842 sym /= (state->internal->mclk >> 12);
843 } else if (srate > 6000000) {
845 sym /= (state->internal->mclk >> 10);
848 sym /= (state->internal->mclk >> 7);
851 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0x7f) < 0) /* MSB */
853 if (STV090x_WRITE_DEMOD(state, SFRINIT0, (sym & 0xff)) < 0) /* LSB */
858 dprintk(FE_ERROR, 1, "I/O error");
862 static int stv090x_set_max_srate(struct stv090x_state *state, u32 clk, u32 srate)
866 srate = 105 * (srate / 100);
867 if (srate > 60000000) {
868 sym = (srate << 4); /* SR * 2^16 / master_clk */
869 sym /= (state->internal->mclk >> 12);
870 } else if (srate > 6000000) {
872 sym /= (state->internal->mclk >> 10);
875 sym /= (state->internal->mclk >> 7);
879 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) /* MSB */
881 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) /* LSB */
884 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x7f) < 0) /* MSB */
886 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xff) < 0) /* LSB */
892 dprintk(FE_ERROR, 1, "I/O error");
896 static int stv090x_set_min_srate(struct stv090x_state *state, u32 clk, u32 srate)
900 srate = 95 * (srate / 100);
901 if (srate > 60000000) {
902 sym = (srate << 4); /* SR * 2^16 / master_clk */
903 sym /= (state->internal->mclk >> 12);
904 } else if (srate > 6000000) {
906 sym /= (state->internal->mclk >> 10);
909 sym /= (state->internal->mclk >> 7);
912 if (STV090x_WRITE_DEMOD(state, SFRLOW1, ((sym >> 8) & 0x7f)) < 0) /* MSB */
914 if (STV090x_WRITE_DEMOD(state, SFRLOW0, (sym & 0xff)) < 0) /* LSB */
918 dprintk(FE_ERROR, 1, "I/O error");
922 static u32 stv090x_car_width(u32 srate, enum stv090x_rolloff rolloff)
939 return srate + (srate * ro) / 100;
942 static int stv090x_set_vit_thacq(struct stv090x_state *state)
944 if (STV090x_WRITE_DEMOD(state, VTH12, 0x96) < 0)
946 if (STV090x_WRITE_DEMOD(state, VTH23, 0x64) < 0)
948 if (STV090x_WRITE_DEMOD(state, VTH34, 0x36) < 0)
950 if (STV090x_WRITE_DEMOD(state, VTH56, 0x23) < 0)
952 if (STV090x_WRITE_DEMOD(state, VTH67, 0x1e) < 0)
954 if (STV090x_WRITE_DEMOD(state, VTH78, 0x19) < 0)
958 dprintk(FE_ERROR, 1, "I/O error");
962 static int stv090x_set_vit_thtracq(struct stv090x_state *state)
964 if (STV090x_WRITE_DEMOD(state, VTH12, 0xd0) < 0)
966 if (STV090x_WRITE_DEMOD(state, VTH23, 0x7d) < 0)
968 if (STV090x_WRITE_DEMOD(state, VTH34, 0x53) < 0)
970 if (STV090x_WRITE_DEMOD(state, VTH56, 0x2f) < 0)
972 if (STV090x_WRITE_DEMOD(state, VTH67, 0x24) < 0)
974 if (STV090x_WRITE_DEMOD(state, VTH78, 0x1f) < 0)
978 dprintk(FE_ERROR, 1, "I/O error");
982 static int stv090x_set_viterbi(struct stv090x_state *state)
984 switch (state->search_mode) {
985 case STV090x_SEARCH_AUTO:
986 if (STV090x_WRITE_DEMOD(state, FECM, 0x10) < 0) /* DVB-S and DVB-S2 */
988 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x3f) < 0) /* all puncture rate */
991 case STV090x_SEARCH_DVBS1:
992 if (STV090x_WRITE_DEMOD(state, FECM, 0x00) < 0) /* disable DSS */
994 switch (state->fec) {
996 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
1001 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
1006 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x04) < 0)
1011 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x08) < 0)
1016 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x20) < 0)
1021 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x2f) < 0) /* all */
1026 case STV090x_SEARCH_DSS:
1027 if (STV090x_WRITE_DEMOD(state, FECM, 0x80) < 0)
1029 switch (state->fec) {
1031 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
1036 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
1041 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x10) < 0)
1046 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x13) < 0) /* 1/2, 2/3, 6/7 */
1056 dprintk(FE_ERROR, 1, "I/O error");
1060 static int stv090x_stop_modcod(struct stv090x_state *state)
1062 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
1064 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0)
1066 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0)
1068 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0)
1070 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0)
1072 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0)
1074 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0)
1076 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xff) < 0)
1078 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xff) < 0)
1080 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xff) < 0)
1082 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xff) < 0)
1084 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xff) < 0)
1086 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xff) < 0)
1088 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xff) < 0)
1090 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0)
1092 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xff) < 0)
1096 dprintk(FE_ERROR, 1, "I/O error");
1100 static int stv090x_activate_modcod(struct stv090x_state *state)
1102 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
1104 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xfc) < 0)
1106 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xcc) < 0)
1108 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xcc) < 0)
1110 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xcc) < 0)
1112 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xcc) < 0)
1114 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xcc) < 0)
1116 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0)
1118 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0)
1120 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0)
1122 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0)
1124 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0)
1126 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0)
1128 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0)
1130 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xcc) < 0)
1132 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0)
1137 dprintk(FE_ERROR, 1, "I/O error");
1141 static int stv090x_activate_modcod_single(struct stv090x_state *state)
1144 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
1146 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xf0) < 0)
1148 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0x00) < 0)
1150 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0x00) < 0)
1152 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0x00) < 0)
1154 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0x00) < 0)
1156 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0x00) < 0)
1158 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0x00) < 0)
1160 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0x00) < 0)
1162 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0x00) < 0)
1164 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0x00) < 0)
1166 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0x00) < 0)
1168 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0x00) < 0)
1170 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0x00) < 0)
1172 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0x00) < 0)
1174 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0x0f) < 0)
1180 dprintk(FE_ERROR, 1, "I/O error");
1184 static int stv090x_vitclk_ctl(struct stv090x_state *state, int enable)
1188 switch (state->demod) {
1189 case STV090x_DEMODULATOR_0:
1190 mutex_lock(&state->internal->demod_lock);
1191 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
1192 STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, enable);
1193 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
1195 mutex_unlock(&state->internal->demod_lock);
1198 case STV090x_DEMODULATOR_1:
1199 mutex_lock(&state->internal->demod_lock);
1200 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
1201 STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, enable);
1202 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
1204 mutex_unlock(&state->internal->demod_lock);
1208 dprintk(FE_ERROR, 1, "Wrong demodulator!");
1213 mutex_unlock(&state->internal->demod_lock);
1214 dprintk(FE_ERROR, 1, "I/O error");
1218 static int stv090x_dvbs_track_crl(struct stv090x_state *state)
1220 if (state->internal->dev_ver >= 0x30) {
1221 /* Set ACLC BCLC optimised value vs SR */
1222 if (state->srate >= 15000000) {
1223 if (STV090x_WRITE_DEMOD(state, ACLC, 0x2b) < 0)
1225 if (STV090x_WRITE_DEMOD(state, BCLC, 0x1a) < 0)
1227 } else if ((state->srate >= 7000000) && (15000000 > state->srate)) {
1228 if (STV090x_WRITE_DEMOD(state, ACLC, 0x0c) < 0)
1230 if (STV090x_WRITE_DEMOD(state, BCLC, 0x1b) < 0)
1232 } else if (state->srate < 7000000) {
1233 if (STV090x_WRITE_DEMOD(state, ACLC, 0x2c) < 0)
1235 if (STV090x_WRITE_DEMOD(state, BCLC, 0x1c) < 0)
1241 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0)
1243 if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
1248 dprintk(FE_ERROR, 1, "I/O error");
1252 static int stv090x_delivery_search(struct stv090x_state *state)
1256 switch (state->search_mode) {
1257 case STV090x_SEARCH_DVBS1:
1258 case STV090x_SEARCH_DSS:
1259 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1260 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1261 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1262 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1265 /* Activate Viterbi decoder in legacy search,
1266 * do not use FRESVIT1, might impact VITERBI2
1268 if (stv090x_vitclk_ctl(state, 0) < 0)
1271 if (stv090x_dvbs_track_crl(state) < 0)
1274 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x22) < 0) /* disable DVB-S2 */
1277 if (stv090x_set_vit_thacq(state) < 0)
1279 if (stv090x_set_viterbi(state) < 0)
1283 case STV090x_SEARCH_DVBS2:
1284 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1285 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
1286 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1287 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1289 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1290 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
1291 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1294 if (stv090x_vitclk_ctl(state, 1) < 0)
1297 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0) /* stop DVB-S CR loop */
1299 if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
1302 if (state->internal->dev_ver <= 0x20) {
1303 /* enable S2 carrier loop */
1304 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
1307 /* > Cut 3: Stop carrier 3 */
1308 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0)
1312 if (state->demod_mode != STV090x_SINGLE) {
1313 /* Cut 2: enable link during search */
1314 if (stv090x_activate_modcod(state) < 0)
1317 /* Single demodulator
1318 * Authorize SHORT and LONG frames,
1319 * QPSK, 8PSK, 16APSK and 32APSK
1321 if (stv090x_activate_modcod_single(state) < 0)
1325 if (stv090x_set_vit_thtracq(state) < 0)
1329 case STV090x_SEARCH_AUTO:
1331 /* enable DVB-S2 and DVB-S2 in Auto MODE */
1332 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1333 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
1334 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1335 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1337 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1338 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
1339 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1342 if (stv090x_vitclk_ctl(state, 0) < 0)
1345 if (stv090x_dvbs_track_crl(state) < 0)
1348 if (state->internal->dev_ver <= 0x20) {
1349 /* enable S2 carrier loop */
1350 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
1353 /* > Cut 3: Stop carrier 3 */
1354 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0)
1358 if (state->demod_mode != STV090x_SINGLE) {
1359 /* Cut 2: enable link during search */
1360 if (stv090x_activate_modcod(state) < 0)
1363 /* Single demodulator
1364 * Authorize SHORT and LONG frames,
1365 * QPSK, 8PSK, 16APSK and 32APSK
1367 if (stv090x_activate_modcod_single(state) < 0)
1371 if (stv090x_set_vit_thacq(state) < 0)
1374 if (stv090x_set_viterbi(state) < 0)
1380 dprintk(FE_ERROR, 1, "I/O error");
1384 static int stv090x_start_search(struct stv090x_state *state)
1389 /* Reset demodulator */
1390 reg = STV090x_READ_DEMOD(state, DMDISTATE);
1391 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f);
1392 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
1395 if (state->internal->dev_ver <= 0x20) {
1396 if (state->srate <= 5000000) {
1397 if (STV090x_WRITE_DEMOD(state, CARCFG, 0x44) < 0)
1399 if (STV090x_WRITE_DEMOD(state, CFRUP1, 0x0f) < 0)
1401 if (STV090x_WRITE_DEMOD(state, CFRUP0, 0xff) < 0)
1403 if (STV090x_WRITE_DEMOD(state, CFRLOW1, 0xf0) < 0)
1405 if (STV090x_WRITE_DEMOD(state, CFRLOW0, 0x00) < 0)
1408 /*enlarge the timing bandwith for Low SR*/
1409 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0)
1412 /* If the symbol rate is >5 Msps
1413 Set The carrier search up and low to auto mode */
1414 if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
1416 /*reduce the timing bandwith for high SR*/
1417 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
1422 if (state->srate <= 5000000) {
1423 /* enlarge the timing bandwith for Low SR */
1424 STV090x_WRITE_DEMOD(state, RTCS2, 0x68);
1426 /* reduce timing bandwith for high SR */
1427 STV090x_WRITE_DEMOD(state, RTCS2, 0x44);
1430 /* Set CFR min and max to manual mode */
1431 STV090x_WRITE_DEMOD(state, CARCFG, 0x46);
1433 if (state->algo == STV090x_WARM_SEARCH) {
1438 freq_abs = 1000 << 16;
1439 freq_abs /= (state->internal->mclk / 1000);
1440 freq = (s16) freq_abs;
1443 * CFR min =- (SearchRange / 2 + 600KHz)
1444 * CFR max = +(SearchRange / 2 + 600KHz)
1445 * (600KHz for the tuner step size)
1447 freq_abs = (state->search_range / 2000) + 600;
1448 freq_abs = freq_abs << 16;
1449 freq_abs /= (state->internal->mclk / 1000);
1450 freq = (s16) freq_abs;
1453 if (STV090x_WRITE_DEMOD(state, CFRUP1, MSB(freq)) < 0)
1455 if (STV090x_WRITE_DEMOD(state, CFRUP0, LSB(freq)) < 0)
1460 if (STV090x_WRITE_DEMOD(state, CFRLOW1, MSB(freq)) < 0)
1462 if (STV090x_WRITE_DEMOD(state, CFRLOW0, LSB(freq)) < 0)
1467 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0) < 0)
1469 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0) < 0)
1472 if (state->internal->dev_ver >= 0x20) {
1473 if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
1475 if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
1478 if ((state->search_mode == STV090x_DVBS1) ||
1479 (state->search_mode == STV090x_DSS) ||
1480 (state->search_mode == STV090x_SEARCH_AUTO)) {
1482 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
1484 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0)
1489 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00) < 0)
1491 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xe0) < 0)
1493 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xc0) < 0)
1496 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1497 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0);
1498 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
1499 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1501 reg = STV090x_READ_DEMOD(state, DMDCFG2);
1502 STV090x_SETFIELD_Px(reg, S1S2_SEQUENTIAL_FIELD, 0x0);
1503 if (STV090x_WRITE_DEMOD(state, DMDCFG2, reg) < 0)
1506 if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0)
1509 if (state->internal->dev_ver >= 0x20) {
1510 /*Frequency offset detector setting*/
1511 if (state->srate < 2000000) {
1512 if (state->internal->dev_ver <= 0x20) {
1514 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x39) < 0)
1518 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x89) < 0)
1521 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x40) < 0)
1523 } else if (state->srate < 10000000) {
1524 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4c) < 0)
1526 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0)
1529 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4b) < 0)
1531 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0)
1535 if (state->srate < 10000000) {
1536 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0)
1539 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
1544 switch (state->algo) {
1545 case STV090x_WARM_SEARCH:
1546 /* The symbol rate and the exact
1547 * carrier Frequency are known
1549 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1551 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
1555 case STV090x_COLD_SEARCH:
1556 /* The symbol rate is known */
1557 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1559 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
1568 dprintk(FE_ERROR, 1, "I/O error");
1572 static int stv090x_get_agc2_min_level(struct stv090x_state *state)
1574 u32 agc2_min = 0xffff, agc2 = 0, freq_init, freq_step, reg;
1575 s32 i, j, steps, dir;
1577 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
1579 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1580 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0);
1581 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
1582 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1585 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0) /* SR = 65 Msps Max */
1587 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
1589 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0) /* SR= 400 ksps Min */
1591 if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
1593 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0) /* stop acq @ coarse carrier state */
1595 if (stv090x_set_srate(state, 1000000) < 0)
1598 steps = state->search_range / 1000000;
1603 freq_step = (1000000 * 256) / (state->internal->mclk / 256);
1606 for (i = 0; i < steps; i++) {
1608 freq_init = freq_init + (freq_step * i);
1610 freq_init = freq_init - (freq_step * i);
1614 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod RESET */
1616 if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_init >> 8) & 0xff) < 0)
1618 if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_init & 0xff) < 0)
1620 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x58) < 0) /* Demod RESET */
1625 for (j = 0; j < 10; j++) {
1626 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
1627 STV090x_READ_DEMOD(state, AGC2I0);
1630 if (agc2 < agc2_min)
1636 dprintk(FE_ERROR, 1, "I/O error");
1640 static u32 stv090x_get_srate(struct stv090x_state *state, u32 clk)
1643 s32 srate, int_1, int_2, tmp_1, tmp_2;
1645 r3 = STV090x_READ_DEMOD(state, SFR3);
1646 r2 = STV090x_READ_DEMOD(state, SFR2);
1647 r1 = STV090x_READ_DEMOD(state, SFR1);
1648 r0 = STV090x_READ_DEMOD(state, SFR0);
1650 srate = ((r3 << 24) | (r2 << 16) | (r1 << 8) | r0);
1653 int_2 = srate >> 16;
1655 tmp_1 = clk % 0x10000;
1656 tmp_2 = srate % 0x10000;
1658 srate = (int_1 * int_2) +
1659 ((int_1 * tmp_2) >> 16) +
1660 ((int_2 * tmp_1) >> 16);
1665 static u32 stv090x_srate_srch_coarse(struct stv090x_state *state)
1667 struct dvb_frontend *fe = &state->frontend;
1669 int tmg_lock = 0, i;
1670 s32 tmg_cpt = 0, dir = 1, steps, cur_step = 0, freq;
1671 u32 srate_coarse = 0, agc2 = 0, car_step = 1200, reg;
1674 if (state->internal->dev_ver >= 0x30)
1679 reg = STV090x_READ_DEMOD(state, DMDISTATE);
1680 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); /* Demod RESET */
1681 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
1683 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0x12) < 0)
1685 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0)
1687 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xf0) < 0)
1689 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xe0) < 0)
1691 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1692 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1);
1693 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
1694 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1697 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0)
1699 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
1701 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0)
1703 if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
1705 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0)
1707 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x50) < 0)
1710 if (state->internal->dev_ver >= 0x30) {
1711 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x99) < 0)
1713 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x98) < 0)
1716 } else if (state->internal->dev_ver >= 0x20) {
1717 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x6a) < 0)
1719 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x95) < 0)
1723 if (state->srate <= 2000000)
1725 else if (state->srate <= 5000000)
1727 else if (state->srate <= 12000000)
1732 steps = -1 + ((state->search_range / 1000) / car_step);
1734 steps = (2 * steps) + 1;
1737 else if (steps > 10) {
1739 car_step = (state->search_range / 1000) / 10;
1743 freq = state->frequency;
1745 while ((!tmg_lock) && (cur_step < steps)) {
1746 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5f) < 0) /* Demod RESET */
1748 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
1750 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
1752 if (STV090x_WRITE_DEMOD(state, SFRINIT1, 0x00) < 0)
1754 if (STV090x_WRITE_DEMOD(state, SFRINIT0, 0x00) < 0)
1756 /* trigger acquisition */
1757 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x40) < 0)
1760 for (i = 0; i < 10; i++) {
1761 reg = STV090x_READ_DEMOD(state, DSTATUS);
1762 if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
1764 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
1765 STV090x_READ_DEMOD(state, AGC2I0);
1768 srate_coarse = stv090x_get_srate(state, state->internal->mclk);
1771 if ((tmg_cpt >= 5) && (agc2 < agc2th) &&
1772 (srate_coarse < 50000000) && (srate_coarse > 850000))
1774 else if (cur_step < steps) {
1776 freq += cur_step * car_step;
1778 freq -= cur_step * car_step;
1781 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
1784 if (state->config->tuner_set_frequency) {
1785 if (state->config->tuner_set_frequency(fe, freq) < 0)
1789 if (state->config->tuner_set_bandwidth) {
1790 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
1794 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
1799 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
1802 if (state->config->tuner_get_status) {
1803 if (state->config->tuner_get_status(fe, ®) < 0)
1808 dprintk(FE_DEBUG, 1, "Tuner phase locked");
1810 dprintk(FE_DEBUG, 1, "Tuner unlocked");
1812 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
1820 srate_coarse = stv090x_get_srate(state, state->internal->mclk);
1822 return srate_coarse;
1825 stv090x_i2c_gate_ctrl(fe, 0);
1827 dprintk(FE_ERROR, 1, "I/O error");
1831 static u32 stv090x_srate_srch_fine(struct stv090x_state *state)
1833 u32 srate_coarse, freq_coarse, sym, reg;
1835 srate_coarse = stv090x_get_srate(state, state->internal->mclk);
1836 freq_coarse = STV090x_READ_DEMOD(state, CFR2) << 8;
1837 freq_coarse |= STV090x_READ_DEMOD(state, CFR1);
1838 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1840 if (sym < state->srate)
1843 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) /* Demod RESET */
1845 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0)
1847 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
1849 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
1851 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
1853 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1854 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
1855 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1858 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
1861 if (state->internal->dev_ver >= 0x30) {
1862 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x79) < 0)
1864 } else if (state->internal->dev_ver >= 0x20) {
1865 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
1869 if (srate_coarse > 3000000) {
1870 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1871 sym = (sym / 1000) * 65536;
1872 sym /= (state->internal->mclk / 1000);
1873 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
1875 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
1877 sym = 10 * (srate_coarse / 13); /* SFRLOW = SFR - 30% */
1878 sym = (sym / 1000) * 65536;
1879 sym /= (state->internal->mclk / 1000);
1880 if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
1882 if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
1884 sym = (srate_coarse / 1000) * 65536;
1885 sym /= (state->internal->mclk / 1000);
1886 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
1888 if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
1891 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1892 sym = (sym / 100) * 65536;
1893 sym /= (state->internal->mclk / 100);
1894 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
1896 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
1898 sym = 10 * (srate_coarse / 14); /* SFRLOW = SFR - 30% */
1899 sym = (sym / 100) * 65536;
1900 sym /= (state->internal->mclk / 100);
1901 if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
1903 if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
1905 sym = (srate_coarse / 100) * 65536;
1906 sym /= (state->internal->mclk / 100);
1907 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
1909 if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
1912 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
1914 if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_coarse >> 8) & 0xff) < 0)
1916 if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_coarse & 0xff) < 0)
1918 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) /* trigger acquisition */
1922 return srate_coarse;
1925 dprintk(FE_ERROR, 1, "I/O error");
1929 static int stv090x_get_dmdlock(struct stv090x_state *state, s32 timeout)
1931 s32 timer = 0, lock = 0;
1935 while ((timer < timeout) && (!lock)) {
1936 reg = STV090x_READ_DEMOD(state, DMDSTATE);
1937 stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
1940 case 0: /* searching */
1941 case 1: /* first PLH detected */
1943 dprintk(FE_DEBUG, 1, "Demodulator searching ..");
1946 case 2: /* DVB-S2 mode */
1947 case 3: /* DVB-S1/legacy mode */
1948 reg = STV090x_READ_DEMOD(state, DSTATUS);
1949 lock = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
1956 dprintk(FE_DEBUG, 1, "Demodulator acquired LOCK");
1963 static int stv090x_blind_search(struct stv090x_state *state)
1965 u32 agc2, reg, srate_coarse;
1966 s32 cpt_fail, agc2_ovflw, i;
1967 u8 k_ref, k_max, k_min;
1968 int coarse_fail = 0;
1974 agc2 = stv090x_get_agc2_min_level(state);
1976 if (agc2 > STV090x_SEARCH_AGC2_TH(state->internal->dev_ver)) {
1980 if (state->internal->dev_ver <= 0x20) {
1981 if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
1985 if (STV090x_WRITE_DEMOD(state, CARCFG, 0x06) < 0)
1989 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
1992 if (state->internal->dev_ver >= 0x20) {
1993 if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
1995 if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
1997 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
1999 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0) /* set viterbi hysteresis */
2005 if (STV090x_WRITE_DEMOD(state, KREFTMG, k_ref) < 0)
2007 if (stv090x_srate_srch_coarse(state) != 0) {
2008 srate_coarse = stv090x_srate_srch_fine(state);
2009 if (srate_coarse != 0) {
2010 stv090x_get_lock_tmg(state);
2011 lock = stv090x_get_dmdlock(state,
2012 state->DemodTimeout);
2019 for (i = 0; i < 10; i++) {
2020 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
2021 STV090x_READ_DEMOD(state, AGC2I0);
2024 reg = STV090x_READ_DEMOD(state, DSTATUS2);
2025 if ((STV090x_GETFIELD_Px(reg, CFR_OVERFLOW_FIELD) == 0x01) &&
2026 (STV090x_GETFIELD_Px(reg, DEMOD_DELOCK_FIELD) == 0x01))
2030 if ((cpt_fail > 7) || (agc2_ovflw > 7))
2036 } while ((k_ref >= k_min) && (!lock) && (!coarse_fail));
2042 dprintk(FE_ERROR, 1, "I/O error");
2046 static int stv090x_chk_tmg(struct stv090x_state *state)
2050 u8 freq, tmg_thh, tmg_thl;
2053 freq = STV090x_READ_DEMOD(state, CARFREQ);
2054 tmg_thh = STV090x_READ_DEMOD(state, TMGTHRISE);
2055 tmg_thl = STV090x_READ_DEMOD(state, TMGTHFALL);
2056 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
2058 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
2061 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2062 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); /* stop carrier offset search */
2063 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2065 if (STV090x_WRITE_DEMOD(state, RTC, 0x80) < 0)
2068 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x40) < 0)
2070 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x00) < 0)
2073 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) /* set car ofset to 0 */
2075 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
2077 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x65) < 0)
2080 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* trigger acquisition */
2084 for (i = 0; i < 10; i++) {
2085 reg = STV090x_READ_DEMOD(state, DSTATUS);
2086 if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
2093 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
2095 if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0) /* DVB-S1 timing */
2097 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0) /* DVB-S2 timing */
2100 if (STV090x_WRITE_DEMOD(state, CARFREQ, freq) < 0)
2102 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, tmg_thh) < 0)
2104 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, tmg_thl) < 0)
2110 dprintk(FE_ERROR, 1, "I/O error");
2114 static int stv090x_get_coldlock(struct stv090x_state *state, s32 timeout_dmd)
2116 struct dvb_frontend *fe = &state->frontend;
2119 s32 car_step, steps, cur_step, dir, freq, timeout_lock;
2122 if (state->srate >= 10000000)
2123 timeout_lock = timeout_dmd / 3;
2125 timeout_lock = timeout_dmd / 2;
2127 lock = stv090x_get_dmdlock(state, timeout_lock); /* cold start wait */
2129 if (state->srate >= 10000000) {
2130 if (stv090x_chk_tmg(state)) {
2131 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
2133 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
2135 lock = stv090x_get_dmdlock(state, timeout_dmd);
2140 if (state->srate <= 4000000)
2142 else if (state->srate <= 7000000)
2144 else if (state->srate <= 10000000)
2149 steps = (state->search_range / 1000) / car_step;
2151 steps = 2 * (steps + 1);
2154 else if (steps > 12)
2161 freq = state->frequency;
2162 state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + state->srate;
2163 while ((cur_step <= steps) && (!lock)) {
2165 freq += cur_step * car_step;
2167 freq -= cur_step * car_step;
2170 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
2173 if (state->config->tuner_set_frequency) {
2174 if (state->config->tuner_set_frequency(fe, freq) < 0)
2178 if (state->config->tuner_set_bandwidth) {
2179 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
2183 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
2188 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
2191 if (state->config->tuner_get_status) {
2192 if (state->config->tuner_get_status(fe, ®) < 0)
2197 dprintk(FE_DEBUG, 1, "Tuner phase locked");
2199 dprintk(FE_DEBUG, 1, "Tuner unlocked");
2201 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
2204 STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c);
2205 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
2207 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
2209 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
2211 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
2213 lock = stv090x_get_dmdlock(state, (timeout_dmd / 3));
2225 stv090x_i2c_gate_ctrl(fe, 0);
2227 dprintk(FE_ERROR, 1, "I/O error");
2231 static int stv090x_get_loop_params(struct stv090x_state *state, s32 *freq_inc, s32 *timeout_sw, s32 *steps)
2233 s32 timeout, inc, steps_max, srate, car_max;
2235 srate = state->srate;
2236 car_max = state->search_range / 1000;
2237 car_max += car_max / 10;
2238 car_max = 65536 * (car_max / 2);
2239 car_max /= (state->internal->mclk / 1000);
2241 if (car_max > 0x4000)
2242 car_max = 0x4000 ; /* maxcarrier should be<= +-1/4 Mclk */
2245 inc /= state->internal->mclk / 1000;
2250 switch (state->search_mode) {
2251 case STV090x_SEARCH_DVBS1:
2252 case STV090x_SEARCH_DSS:
2253 inc *= 3; /* freq step = 3% of srate */
2257 case STV090x_SEARCH_DVBS2:
2262 case STV090x_SEARCH_AUTO:
2269 if ((inc > car_max) || (inc < 0))
2270 inc = car_max / 2; /* increment <= 1/8 Mclk */
2272 timeout *= 27500; /* 27.5 Msps reference */
2274 timeout /= (srate / 1000);
2276 if ((timeout > 100) || (timeout < 0))
2279 steps_max = (car_max / inc) + 1; /* min steps = 3 */
2280 if ((steps_max > 100) || (steps_max < 0)) {
2281 steps_max = 100; /* max steps <= 100 */
2282 inc = car_max / steps_max;
2285 *timeout_sw = timeout;
2291 static int stv090x_chk_signal(struct stv090x_state *state)
2293 s32 offst_car, agc2, car_max;
2296 offst_car = STV090x_READ_DEMOD(state, CFR2) << 8;
2297 offst_car |= STV090x_READ_DEMOD(state, CFR1);
2298 offst_car = comp2(offst_car, 16);
2300 agc2 = STV090x_READ_DEMOD(state, AGC2I1) << 8;
2301 agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
2302 car_max = state->search_range / 1000;
2304 car_max += (car_max / 10); /* 10% margin */
2305 car_max = (65536 * car_max / 2);
2306 car_max /= state->internal->mclk / 1000;
2308 if (car_max > 0x4000)
2311 if ((agc2 > 0x2000) || (offst_car > 2 * car_max) || (offst_car < -2 * car_max)) {
2313 dprintk(FE_DEBUG, 1, "No Signal");
2316 dprintk(FE_DEBUG, 1, "Found Signal");
2322 static int stv090x_search_car_loop(struct stv090x_state *state, s32 inc, s32 timeout, int zigzag, s32 steps_max)
2324 int no_signal, lock = 0;
2325 s32 cpt_step = 0, offst_freq, car_max;
2328 car_max = state->search_range / 1000;
2329 car_max += (car_max / 10);
2330 car_max = (65536 * car_max / 2);
2331 car_max /= (state->internal->mclk / 1000);
2332 if (car_max > 0x4000)
2338 offst_freq = -car_max + inc;
2341 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0)
2343 if (STV090x_WRITE_DEMOD(state, CFRINIT1, ((offst_freq / 256) & 0xff)) < 0)
2345 if (STV090x_WRITE_DEMOD(state, CFRINIT0, offst_freq & 0xff) < 0)
2347 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
2350 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
2351 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x1); /* stop DVB-S2 packet delin */
2352 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
2356 if (offst_freq >= 0)
2357 offst_freq = -offst_freq - 2 * inc;
2359 offst_freq = -offst_freq;
2361 offst_freq += 2 * inc;
2366 lock = stv090x_get_dmdlock(state, timeout);
2367 no_signal = stv090x_chk_signal(state);
2371 ((offst_freq - inc) < car_max) &&
2372 ((offst_freq + inc) > -car_max) &&
2373 (cpt_step < steps_max));
2375 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
2376 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0);
2377 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
2382 dprintk(FE_ERROR, 1, "I/O error");
2386 static int stv090x_sw_algo(struct stv090x_state *state)
2388 int no_signal, zigzag, lock = 0;
2391 s32 dvbs2_fly_wheel;
2392 s32 inc, timeout_step, trials, steps_max;
2395 stv090x_get_loop_params(state, &inc, &timeout_step, &steps_max);
2397 switch (state->search_mode) {
2398 case STV090x_SEARCH_DVBS1:
2399 case STV090x_SEARCH_DSS:
2400 /* accelerate the frequency detector */
2401 if (state->internal->dev_ver >= 0x20) {
2402 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3B) < 0)
2406 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x49) < 0)
2411 case STV090x_SEARCH_DVBS2:
2412 if (state->internal->dev_ver >= 0x20) {
2413 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2417 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
2422 case STV090x_SEARCH_AUTO:
2424 /* accelerate the frequency detector */
2425 if (state->internal->dev_ver >= 0x20) {
2426 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3b) < 0)
2428 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2432 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0xc9) < 0)
2440 lock = stv090x_search_car_loop(state, inc, timeout_step, zigzag, steps_max);
2441 no_signal = stv090x_chk_signal(state);
2444 /*run the SW search 2 times maximum*/
2445 if (lock || no_signal || (trials == 2)) {
2446 /*Check if the demod is not losing lock in DVBS2*/
2447 if (state->internal->dev_ver >= 0x20) {
2448 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
2450 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
2454 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2455 if ((lock) && (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == STV090x_DVBS2)) {
2456 /*Check if the demod is not losing lock in DVBS2*/
2457 msleep(timeout_step);
2458 reg = STV090x_READ_DEMOD(state, DMDFLYW);
2459 dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
2460 if (dvbs2_fly_wheel < 0xd) { /*if correct frames is decrementing */
2461 msleep(timeout_step);
2462 reg = STV090x_READ_DEMOD(state, DMDFLYW);
2463 dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
2465 if (dvbs2_fly_wheel < 0xd) {
2466 /*FALSE lock, The demod is loosing lock */
2469 if (state->internal->dev_ver >= 0x20) {
2470 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2474 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
2480 } while ((!lock) && (trials < 2) && (!no_signal));
2484 dprintk(FE_ERROR, 1, "I/O error");
2488 static enum stv090x_delsys stv090x_get_std(struct stv090x_state *state)
2491 enum stv090x_delsys delsys;
2493 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2494 if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 2)
2495 delsys = STV090x_DVBS2;
2496 else if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 3) {
2497 reg = STV090x_READ_DEMOD(state, FECM);
2498 if (STV090x_GETFIELD_Px(reg, DSS_DVB_FIELD) == 1)
2499 delsys = STV090x_DSS;
2501 delsys = STV090x_DVBS1;
2503 delsys = STV090x_ERROR;
2510 static s32 stv090x_get_car_freq(struct stv090x_state *state, u32 mclk)
2512 s32 derot, int_1, int_2, tmp_1, tmp_2;
2514 derot = STV090x_READ_DEMOD(state, CFR2) << 16;
2515 derot |= STV090x_READ_DEMOD(state, CFR1) << 8;
2516 derot |= STV090x_READ_DEMOD(state, CFR0);
2518 derot = comp2(derot, 24);
2520 int_2 = derot >> 12;
2522 /* carrier_frequency = MasterClock * Reg / 2^24 */
2523 tmp_1 = mclk % 0x1000;
2524 tmp_2 = derot % 0x1000;
2526 derot = (int_1 * int_2) +
2527 ((int_1 * tmp_2) >> 12) +
2528 ((int_2 * tmp_1) >> 12);
2533 static int stv090x_get_viterbi(struct stv090x_state *state)
2537 reg = STV090x_READ_DEMOD(state, VITCURPUN);
2538 rate = STV090x_GETFIELD_Px(reg, VIT_CURPUN_FIELD);
2542 state->fec = STV090x_PR12;
2546 state->fec = STV090x_PR23;
2550 state->fec = STV090x_PR34;
2554 state->fec = STV090x_PR56;
2558 state->fec = STV090x_PR67;
2562 state->fec = STV090x_PR78;
2566 state->fec = STV090x_PRERR;
2573 static enum stv090x_signal_state stv090x_get_sig_params(struct stv090x_state *state)
2575 struct dvb_frontend *fe = &state->frontend;
2579 s32 i = 0, offst_freq;
2583 if (state->algo == STV090x_BLIND_SEARCH) {
2584 tmg = STV090x_READ_DEMOD(state, TMGREG2);
2585 STV090x_WRITE_DEMOD(state, SFRSTEP, 0x5c);
2586 while ((i <= 50) && (tmg != 0) && (tmg != 0xff)) {
2587 tmg = STV090x_READ_DEMOD(state, TMGREG2);
2592 state->delsys = stv090x_get_std(state);
2594 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
2597 if (state->config->tuner_get_frequency) {
2598 if (state->config->tuner_get_frequency(fe, &state->frequency) < 0)
2602 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
2605 offst_freq = stv090x_get_car_freq(state, state->internal->mclk) / 1000;
2606 state->frequency += offst_freq;
2608 if (stv090x_get_viterbi(state) < 0)
2611 reg = STV090x_READ_DEMOD(state, DMDMODCOD);
2612 state->modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
2613 state->pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
2614 state->frame_len = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) >> 1;
2615 reg = STV090x_READ_DEMOD(state, TMGOBS);
2616 state->rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
2617 reg = STV090x_READ_DEMOD(state, FECM);
2618 state->inversion = STV090x_GETFIELD_Px(reg, IQINV_FIELD);
2620 if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000)) {
2622 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
2625 if (state->config->tuner_get_frequency) {
2626 if (state->config->tuner_get_frequency(fe, &state->frequency) < 0)
2630 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
2633 if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
2634 return STV090x_RANGEOK;
2635 else if (abs(offst_freq) <= (stv090x_car_width(state->srate, state->rolloff) / 2000))
2636 return STV090x_RANGEOK;
2638 return STV090x_OUTOFRANGE; /* Out of Range */
2640 if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
2641 return STV090x_RANGEOK;
2643 return STV090x_OUTOFRANGE;
2646 return STV090x_OUTOFRANGE;
2649 stv090x_i2c_gate_ctrl(fe, 0);
2651 dprintk(FE_ERROR, 1, "I/O error");
2655 static u32 stv090x_get_tmgoffst(struct stv090x_state *state, u32 srate)
2659 offst_tmg = STV090x_READ_DEMOD(state, TMGREG2) << 16;
2660 offst_tmg |= STV090x_READ_DEMOD(state, TMGREG1) << 8;
2661 offst_tmg |= STV090x_READ_DEMOD(state, TMGREG0);
2663 offst_tmg = comp2(offst_tmg, 24); /* 2's complement */
2667 offst_tmg = ((s32) srate * 10) / ((s32) 0x1000000 / offst_tmg);
2673 static u8 stv090x_optimize_carloop(struct stv090x_state *state, enum stv090x_modcod modcod, s32 pilots)
2677 struct stv090x_long_frame_crloop *car_loop, *car_loop_qpsk_low, *car_loop_apsk_low;
2679 if (state->internal->dev_ver == 0x20) {
2680 car_loop = stv090x_s2_crl_cut20;
2681 car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut20;
2682 car_loop_apsk_low = stv090x_s2_apsk_crl_cut20;
2685 car_loop = stv090x_s2_crl_cut30;
2686 car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut30;
2687 car_loop_apsk_low = stv090x_s2_apsk_crl_cut30;
2690 if (modcod < STV090x_QPSK_12) {
2692 while ((i < 3) && (modcod != car_loop_qpsk_low[i].modcod))
2700 while ((i < 14) && (modcod != car_loop[i].modcod))
2705 while ((i < 11) && (modcod != car_loop_apsk_low[i].modcod))
2713 if (modcod <= STV090x_QPSK_25) {
2715 if (state->srate <= 3000000)
2716 aclc = car_loop_qpsk_low[i].crl_pilots_on_2;
2717 else if (state->srate <= 7000000)
2718 aclc = car_loop_qpsk_low[i].crl_pilots_on_5;
2719 else if (state->srate <= 15000000)
2720 aclc = car_loop_qpsk_low[i].crl_pilots_on_10;
2721 else if (state->srate <= 25000000)
2722 aclc = car_loop_qpsk_low[i].crl_pilots_on_20;
2724 aclc = car_loop_qpsk_low[i].crl_pilots_on_30;
2726 if (state->srate <= 3000000)
2727 aclc = car_loop_qpsk_low[i].crl_pilots_off_2;
2728 else if (state->srate <= 7000000)
2729 aclc = car_loop_qpsk_low[i].crl_pilots_off_5;
2730 else if (state->srate <= 15000000)
2731 aclc = car_loop_qpsk_low[i].crl_pilots_off_10;
2732 else if (state->srate <= 25000000)
2733 aclc = car_loop_qpsk_low[i].crl_pilots_off_20;
2735 aclc = car_loop_qpsk_low[i].crl_pilots_off_30;
2738 } else if (modcod <= STV090x_8PSK_910) {
2740 if (state->srate <= 3000000)
2741 aclc = car_loop[i].crl_pilots_on_2;
2742 else if (state->srate <= 7000000)
2743 aclc = car_loop[i].crl_pilots_on_5;
2744 else if (state->srate <= 15000000)
2745 aclc = car_loop[i].crl_pilots_on_10;
2746 else if (state->srate <= 25000000)
2747 aclc = car_loop[i].crl_pilots_on_20;
2749 aclc = car_loop[i].crl_pilots_on_30;
2751 if (state->srate <= 3000000)
2752 aclc = car_loop[i].crl_pilots_off_2;
2753 else if (state->srate <= 7000000)
2754 aclc = car_loop[i].crl_pilots_off_5;
2755 else if (state->srate <= 15000000)
2756 aclc = car_loop[i].crl_pilots_off_10;
2757 else if (state->srate <= 25000000)
2758 aclc = car_loop[i].crl_pilots_off_20;
2760 aclc = car_loop[i].crl_pilots_off_30;
2762 } else { /* 16APSK and 32APSK */
2763 if (state->srate <= 3000000)
2764 aclc = car_loop_apsk_low[i].crl_pilots_on_2;
2765 else if (state->srate <= 7000000)
2766 aclc = car_loop_apsk_low[i].crl_pilots_on_5;
2767 else if (state->srate <= 15000000)
2768 aclc = car_loop_apsk_low[i].crl_pilots_on_10;
2769 else if (state->srate <= 25000000)
2770 aclc = car_loop_apsk_low[i].crl_pilots_on_20;
2772 aclc = car_loop_apsk_low[i].crl_pilots_on_30;
2778 static u8 stv090x_optimize_carloop_short(struct stv090x_state *state)
2780 struct stv090x_short_frame_crloop *short_crl = NULL;
2784 switch (state->modulation) {
2792 case STV090x_16APSK:
2795 case STV090x_32APSK:
2800 if (state->internal->dev_ver >= 0x30) {
2801 /* Cut 3.0 and up */
2802 short_crl = stv090x_s2_short_crl_cut30;
2804 /* Cut 2.0 and up: we don't support cuts older than 2.0 */
2805 short_crl = stv090x_s2_short_crl_cut20;
2808 if (state->srate <= 3000000)
2809 aclc = short_crl[index].crl_2;
2810 else if (state->srate <= 7000000)
2811 aclc = short_crl[index].crl_5;
2812 else if (state->srate <= 15000000)
2813 aclc = short_crl[index].crl_10;
2814 else if (state->srate <= 25000000)
2815 aclc = short_crl[index].crl_20;
2817 aclc = short_crl[index].crl_30;
2822 static int stv090x_optimize_track(struct stv090x_state *state)
2824 struct dvb_frontend *fe = &state->frontend;
2826 enum stv090x_rolloff rolloff;
2827 enum stv090x_modcod modcod;
2829 s32 srate, pilots, aclc, f_1, f_0, i = 0, blind_tune = 0;
2832 srate = stv090x_get_srate(state, state->internal->mclk);
2833 srate += stv090x_get_tmgoffst(state, srate);
2835 switch (state->delsys) {
2838 if (state->search_mode == STV090x_SEARCH_AUTO) {
2839 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2840 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
2841 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
2842 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2845 reg = STV090x_READ_DEMOD(state, DEMOD);
2846 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
2847 STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x01);
2848 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2851 if (state->internal->dev_ver >= 0x30) {
2852 if (stv090x_get_viterbi(state) < 0)
2855 if (state->fec == STV090x_PR12) {
2856 if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x98) < 0)
2858 if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0)
2861 if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x18) < 0)
2863 if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0)
2868 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
2873 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2874 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
2875 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
2876 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2878 if (STV090x_WRITE_DEMOD(state, ACLC, 0) < 0)
2880 if (STV090x_WRITE_DEMOD(state, BCLC, 0) < 0)
2882 if (state->frame_len == STV090x_LONG_FRAME) {
2883 reg = STV090x_READ_DEMOD(state, DMDMODCOD);
2884 modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
2885 pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
2886 aclc = stv090x_optimize_carloop(state, modcod, pilots);
2887 if (modcod <= STV090x_QPSK_910) {
2888 STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc);
2889 } else if (modcod <= STV090x_8PSK_910) {
2890 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2892 if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
2895 if ((state->demod_mode == STV090x_SINGLE) && (modcod > STV090x_8PSK_910)) {
2896 if (modcod <= STV090x_16APSK_910) {
2897 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2899 if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
2902 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2904 if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
2909 /*Carrier loop setting for short frame*/
2910 aclc = stv090x_optimize_carloop_short(state);
2911 if (state->modulation == STV090x_QPSK) {
2912 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc) < 0)
2914 } else if (state->modulation == STV090x_8PSK) {
2915 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2917 if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
2919 } else if (state->modulation == STV090x_16APSK) {
2920 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2922 if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
2924 } else if (state->modulation == STV090x_32APSK) {
2925 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2927 if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
2932 STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67); /* PER */
2935 case STV090x_UNKNOWN:
2937 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2938 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
2939 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
2940 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2945 f_1 = STV090x_READ_DEMOD(state, CFR2);
2946 f_0 = STV090x_READ_DEMOD(state, CFR1);
2947 reg = STV090x_READ_DEMOD(state, TMGOBS);
2948 rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
2950 if (state->algo == STV090x_BLIND_SEARCH) {
2951 STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00);
2952 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2953 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0x00);
2954 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
2955 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2957 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0)
2960 if (stv090x_set_srate(state, srate) < 0)
2964 if (stv090x_dvbs_track_crl(state) < 0)
2968 if (state->internal->dev_ver >= 0x20) {
2969 if ((state->search_mode == STV090x_SEARCH_DVBS1) ||
2970 (state->search_mode == STV090x_SEARCH_DSS) ||
2971 (state->search_mode == STV090x_SEARCH_AUTO)) {
2973 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x0a) < 0)
2975 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x00) < 0)
2980 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
2983 /* AUTO tracking MODE */
2984 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x80) < 0)
2986 /* AUTO tracking MODE */
2987 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x80) < 0)
2990 if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1) ||
2991 (state->srate < 10000000)) {
2992 /* update initial carrier freq with the found freq offset */
2993 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
2995 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
2997 state->tuner_bw = stv090x_car_width(srate, state->rolloff) + 10000000;
2999 if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1)) {
3001 if (state->algo != STV090x_WARM_SEARCH) {
3003 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
3006 if (state->config->tuner_set_bandwidth) {
3007 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
3011 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
3016 if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000))
3017 msleep(50); /* blind search: wait 50ms for SR stabilization */
3021 stv090x_get_lock_tmg(state);
3023 if (!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) {
3024 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
3026 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
3028 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
3030 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
3035 while ((!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) && (i <= 2)) {
3037 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
3039 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
3041 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
3043 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
3051 if (state->internal->dev_ver >= 0x20) {
3052 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
3056 if ((state->delsys == STV090x_DVBS1) || (state->delsys == STV090x_DSS))
3057 stv090x_set_vit_thtracq(state);
3062 stv090x_i2c_gate_ctrl(fe, 0);
3064 dprintk(FE_ERROR, 1, "I/O error");
3068 static int stv090x_get_feclock(struct stv090x_state *state, s32 timeout)
3070 s32 timer = 0, lock = 0, stat;
3073 while ((timer < timeout) && (!lock)) {
3074 reg = STV090x_READ_DEMOD(state, DMDSTATE);
3075 stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
3078 case 0: /* searching */
3079 case 1: /* first PLH detected */
3084 case 2: /* DVB-S2 mode */
3085 reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
3086 lock = STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD);
3089 case 3: /* DVB-S1/legacy mode */
3090 reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
3091 lock = STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD);
3102 static int stv090x_get_lock(struct stv090x_state *state, s32 timeout_dmd, s32 timeout_fec)
3108 lock = stv090x_get_dmdlock(state, timeout_dmd);
3110 lock = stv090x_get_feclock(state, timeout_fec);
3115 while ((timer < timeout_fec) && (!lock)) {
3116 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3117 lock = STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD);
3126 static int stv090x_set_s2rolloff(struct stv090x_state *state)
3130 if (state->internal->dev_ver <= 0x20) {
3131 /* rolloff to auto mode if DVBS2 */
3132 reg = STV090x_READ_DEMOD(state, DEMOD);
3133 STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x00);
3134 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
3137 /* DVB-S2 rolloff to auto mode if DVBS2 */
3138 reg = STV090x_READ_DEMOD(state, DEMOD);
3139 STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 0x00);
3140 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
3145 dprintk(FE_ERROR, 1, "I/O error");
3150 static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
3152 struct dvb_frontend *fe = &state->frontend;
3153 enum stv090x_signal_state signal_state = STV090x_NOCARRIER;
3155 s32 agc1_power, power_iq = 0, i;
3156 int lock = 0, low_sr = 0, no_signal = 0;
3158 reg = STV090x_READ_DEMOD(state, TSCFGH);
3159 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* Stop path 1 stream merger */
3160 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3163 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod stop */
3166 if (state->internal->dev_ver >= 0x20) {
3167 if (state->srate > 5000000) {
3168 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
3171 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x82) < 0)
3176 stv090x_get_lock_tmg(state);
3178 if (state->algo == STV090x_BLIND_SEARCH) {
3179 state->tuner_bw = 2 * 36000000; /* wide bw for unknown srate */
3180 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0) /* wider srate scan */
3182 if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0)
3184 if (stv090x_set_srate(state, 1000000) < 0) /* inital srate = 1Msps */
3188 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
3190 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
3193 if (state->srate < 2000000) {
3195 if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x63) < 0)
3199 if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0)
3203 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
3206 if (state->internal->dev_ver >= 0x20) {
3207 if (STV090x_WRITE_DEMOD(state, KREFTMG, 0x5a) < 0)
3209 if (state->algo == STV090x_COLD_SEARCH)
3210 state->tuner_bw = (15 * (stv090x_car_width(state->srate, state->rolloff) + 10000000)) / 10;
3211 else if (state->algo == STV090x_WARM_SEARCH)
3212 state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + 10000000;
3215 /* if cold start or warm (Symbolrate is known)
3216 * use a Narrow symbol rate scan range
3218 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0) /* narrow srate scan */
3221 if (stv090x_set_srate(state, state->srate) < 0)
3224 if (stv090x_set_max_srate(state, state->internal->mclk,
3227 if (stv090x_set_min_srate(state, state->internal->mclk,
3231 if (state->srate >= 10000000)
3238 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
3241 if (state->config->tuner_set_bbgain) {
3242 reg = state->config->tuner_bbgain;
3244 reg = 10; /* default: 10dB */
3245 if (state->config->tuner_set_bbgain(fe, reg) < 0)
3249 if (state->config->tuner_set_frequency) {
3250 if (state->config->tuner_set_frequency(fe, state->frequency) < 0)
3254 if (state->config->tuner_set_bandwidth) {
3255 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
3259 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
3264 if (state->config->tuner_get_status) {
3265 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
3267 if (state->config->tuner_get_status(fe, ®) < 0)
3269 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
3273 dprintk(FE_DEBUG, 1, "Tuner phase locked");
3275 dprintk(FE_DEBUG, 1, "Tuner unlocked");
3276 return STV090x_NOCARRIER;
3281 agc1_power = MAKEWORD16(STV090x_READ_DEMOD(state, AGCIQIN1),
3282 STV090x_READ_DEMOD(state, AGCIQIN0));
3284 if (agc1_power == 0) {
3285 /* If AGC1 integrator value is 0
3286 * then read POWERI, POWERQ
3288 for (i = 0; i < 5; i++) {
3289 power_iq += (STV090x_READ_DEMOD(state, POWERI) +
3290 STV090x_READ_DEMOD(state, POWERQ)) >> 1;
3295 if ((agc1_power == 0) && (power_iq < STV090x_IQPOWER_THRESHOLD)) {
3296 dprintk(FE_ERROR, 1, "No Signal: POWER_IQ=0x%02x", power_iq);
3298 signal_state = STV090x_NOAGC1;
3300 reg = STV090x_READ_DEMOD(state, DEMOD);
3301 STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, state->inversion);
3303 if (state->internal->dev_ver <= 0x20) {
3304 /* rolloff to auto mode if DVBS2 */
3305 STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 1);
3307 /* DVB-S2 rolloff to auto mode if DVBS2 */
3308 STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 1);
3310 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
3313 if (stv090x_delivery_search(state) < 0)
3316 if (state->algo != STV090x_BLIND_SEARCH) {
3317 if (stv090x_start_search(state) < 0)
3322 if (signal_state == STV090x_NOAGC1)
3323 return signal_state;
3325 if (state->algo == STV090x_BLIND_SEARCH)
3326 lock = stv090x_blind_search(state);
3328 else if (state->algo == STV090x_COLD_SEARCH)
3329 lock = stv090x_get_coldlock(state, state->DemodTimeout);
3331 else if (state->algo == STV090x_WARM_SEARCH)
3332 lock = stv090x_get_dmdlock(state, state->DemodTimeout);
3334 if ((!lock) && (state->algo == STV090x_COLD_SEARCH)) {
3336 if (stv090x_chk_tmg(state))
3337 lock = stv090x_sw_algo(state);
3342 signal_state = stv090x_get_sig_params(state);
3344 if ((lock) && (signal_state == STV090x_RANGEOK)) { /* signal within Range */
3345 stv090x_optimize_track(state);
3347 if (state->internal->dev_ver >= 0x20) {
3348 /* >= Cut 2.0 :release TS reset after
3349 * demod lock and optimized Tracking
3351 reg = STV090x_READ_DEMOD(state, TSCFGH);
3352 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3353 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3358 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */
3359 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3362 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3363 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3367 lock = stv090x_get_lock(state, state->FecTimeout,
3370 if (state->delsys == STV090x_DVBS2) {
3371 stv090x_set_s2rolloff(state);
3373 reg = STV090x_READ_DEMOD(state, PDELCTRL2);
3374 STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 1);
3375 if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0)
3377 /* Reset DVBS2 packet delinator error counter */
3378 reg = STV090x_READ_DEMOD(state, PDELCTRL2);
3379 STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 0);
3380 if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0)
3383 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67) < 0) /* PER */
3386 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
3389 /* Reset the Total packet counter */
3390 if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0x00) < 0)
3392 /* Reset the packet Error counter2 */
3393 if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
3396 signal_state = STV090x_NODATA;
3397 no_signal = stv090x_chk_signal(state);
3400 return signal_state;
3403 stv090x_i2c_gate_ctrl(fe, 0);
3405 dprintk(FE_ERROR, 1, "I/O error");
3409 static enum dvbfe_search stv090x_search(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
3411 struct stv090x_state *state = fe->demodulator_priv;
3412 struct dtv_frontend_properties *props = &fe->dtv_property_cache;
3414 if (p->frequency == 0)
3415 return DVBFE_ALGO_SEARCH_INVALID;
3417 state->delsys = props->delivery_system;
3418 state->frequency = p->frequency;
3419 state->srate = p->u.qpsk.symbol_rate;
3420 state->search_mode = STV090x_SEARCH_AUTO;
3421 state->algo = STV090x_COLD_SEARCH;
3422 state->fec = STV090x_PRERR;
3423 if (state->srate > 10000000) {
3424 dprintk(FE_DEBUG, 1, "Search range: 10 MHz");
3425 state->search_range = 10000000;
3427 dprintk(FE_DEBUG, 1, "Search range: 5 MHz");
3428 state->search_range = 5000000;
3431 if (stv090x_algo(state) == STV090x_RANGEOK) {
3432 dprintk(FE_DEBUG, 1, "Search success!");
3433 return DVBFE_ALGO_SEARCH_SUCCESS;
3435 dprintk(FE_DEBUG, 1, "Search failed!");
3436 return DVBFE_ALGO_SEARCH_FAILED;
3439 return DVBFE_ALGO_SEARCH_ERROR;
3442 static int stv090x_read_status(struct dvb_frontend *fe, enum fe_status *status)
3444 struct stv090x_state *state = fe->demodulator_priv;
3448 reg = STV090x_READ_DEMOD(state, DMDSTATE);
3449 search_state = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
3451 switch (search_state) {
3452 case 0: /* searching */
3453 case 1: /* first PLH detected */
3455 dprintk(FE_DEBUG, 1, "Status: Unlocked (Searching ..)");
3459 case 2: /* DVB-S2 mode */
3460 dprintk(FE_DEBUG, 1, "Delivery system: DVB-S2");
3461 reg = STV090x_READ_DEMOD(state, DSTATUS);
3462 if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) {
3463 reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
3464 if (STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD)) {
3465 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3466 if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) {
3467 *status = FE_HAS_SIGNAL |
3477 case 3: /* DVB-S1/legacy mode */
3478 dprintk(FE_DEBUG, 1, "Delivery system: DVB-S");
3479 reg = STV090x_READ_DEMOD(state, DSTATUS);
3480 if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) {
3481 reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
3482 if (STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD)) {
3483 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3484 if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) {
3485 *status = FE_HAS_SIGNAL |
3499 static int stv090x_read_per(struct dvb_frontend *fe, u32 *per)
3501 struct stv090x_state *state = fe->demodulator_priv;
3503 s32 count_4, count_3, count_2, count_1, count_0, count;
3505 enum fe_status status;
3507 stv090x_read_status(fe, &status);
3508 if (!(status & FE_HAS_LOCK)) {
3509 *per = 1 << 23; /* Max PER */
3512 reg = STV090x_READ_DEMOD(state, ERRCNT22);
3513 h = STV090x_GETFIELD_Px(reg, ERR_CNT2_FIELD);
3515 reg = STV090x_READ_DEMOD(state, ERRCNT21);
3516 m = STV090x_GETFIELD_Px(reg, ERR_CNT21_FIELD);
3518 reg = STV090x_READ_DEMOD(state, ERRCNT20);
3519 l = STV090x_GETFIELD_Px(reg, ERR_CNT20_FIELD);
3521 *per = ((h << 16) | (m << 8) | l);
3523 count_4 = STV090x_READ_DEMOD(state, FBERCPT4);
3524 count_3 = STV090x_READ_DEMOD(state, FBERCPT3);
3525 count_2 = STV090x_READ_DEMOD(state, FBERCPT2);
3526 count_1 = STV090x_READ_DEMOD(state, FBERCPT1);
3527 count_0 = STV090x_READ_DEMOD(state, FBERCPT0);
3529 if ((!count_4) && (!count_3)) {
3530 count = (count_2 & 0xff) << 16;
3531 count |= (count_1 & 0xff) << 8;
3532 count |= count_0 & 0xff;
3539 if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0) < 0)
3541 if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
3546 dprintk(FE_ERROR, 1, "I/O error");
3550 static int stv090x_table_lookup(const struct stv090x_tab *tab, int max, int val)
3555 if ((val >= tab[min].read && val < tab[max].read) ||
3556 (val >= tab[max].read && val < tab[min].read)) {
3557 while ((max - min) > 1) {
3558 med = (max + min) / 2;
3559 if ((val >= tab[min].read && val < tab[med].read) ||
3560 (val >= tab[med].read && val < tab[min].read))
3565 res = ((val - tab[min].read) *
3566 (tab[max].real - tab[min].real) /
3567 (tab[max].read - tab[min].read)) +
3570 if (tab[min].read < tab[max].read) {
3571 if (val < tab[min].read)
3572 res = tab[min].real;
3573 else if (val >= tab[max].read)
3574 res = tab[max].real;
3576 if (val >= tab[min].read)
3577 res = tab[min].real;
3578 else if (val < tab[max].read)
3579 res = tab[max].real;
3586 static int stv090x_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
3588 struct stv090x_state *state = fe->demodulator_priv;
3590 s32 agc_0, agc_1, agc;
3593 reg = STV090x_READ_DEMOD(state, AGCIQIN1);
3594 agc_1 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
3595 reg = STV090x_READ_DEMOD(state, AGCIQIN0);
3596 agc_0 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
3597 agc = MAKEWORD16(agc_1, agc_0);
3599 str = stv090x_table_lookup(stv090x_rf_tab,
3600 ARRAY_SIZE(stv090x_rf_tab) - 1, agc);
3601 if (agc > stv090x_rf_tab[0].read)
3603 else if (agc < stv090x_rf_tab[ARRAY_SIZE(stv090x_rf_tab) - 1].read)
3605 *strength = (str + 100) * 0xFFFF / 100;
3610 static int stv090x_read_cnr(struct dvb_frontend *fe, u16 *cnr)
3612 struct stv090x_state *state = fe->demodulator_priv;
3613 u32 reg_0, reg_1, reg, i;
3614 s32 val_0, val_1, val = 0;
3619 switch (state->delsys) {
3621 reg = STV090x_READ_DEMOD(state, DSTATUS);
3622 lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
3625 for (i = 0; i < 16; i++) {
3626 reg_1 = STV090x_READ_DEMOD(state, NNOSPLHT1);
3627 val_1 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD);
3628 reg_0 = STV090x_READ_DEMOD(state, NNOSPLHT0);
3629 val_0 = STV090x_GETFIELD_Px(reg_0, NOSPLHT_NORMED_FIELD);
3630 val += MAKEWORD16(val_1, val_0);
3634 last = ARRAY_SIZE(stv090x_s2cn_tab) - 1;
3635 div = stv090x_s2cn_tab[0].read -
3636 stv090x_s2cn_tab[last].read;
3637 *cnr = 0xFFFF - ((val * 0xFFFF) / div);
3643 reg = STV090x_READ_DEMOD(state, DSTATUS);
3644 lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
3647 for (i = 0; i < 16; i++) {
3648 reg_1 = STV090x_READ_DEMOD(state, NOSDATAT1);
3649 val_1 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD);
3650 reg_0 = STV090x_READ_DEMOD(state, NOSDATAT0);
3651 val_0 = STV090x_GETFIELD_Px(reg_0, NOSDATAT_UNNORMED_FIELD);
3652 val += MAKEWORD16(val_1, val_0);
3656 last = ARRAY_SIZE(stv090x_s1cn_tab) - 1;
3657 div = stv090x_s1cn_tab[0].read -
3658 stv090x_s1cn_tab[last].read;
3659 *cnr = 0xFFFF - ((val * 0xFFFF) / div);
3669 static int stv090x_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
3671 struct stv090x_state *state = fe->demodulator_priv;
3674 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3677 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
3678 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3679 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3681 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
3682 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3687 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
3688 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3689 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3698 dprintk(FE_ERROR, 1, "I/O error");
3703 static enum dvbfe_algo stv090x_frontend_algo(struct dvb_frontend *fe)
3705 return DVBFE_ALGO_CUSTOM;
3708 static int stv090x_send_diseqc_msg(struct dvb_frontend *fe, struct dvb_diseqc_master_cmd *cmd)
3710 struct stv090x_state *state = fe->demodulator_priv;
3711 u32 reg, idle = 0, fifo_full = 1;
3714 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3716 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD,
3717 (state->config->diseqc_envelope_mode) ? 4 : 2);
3718 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3719 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3721 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
3722 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3725 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
3726 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3729 for (i = 0; i < cmd->msg_len; i++) {
3732 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3733 fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
3736 if (STV090x_WRITE_DEMOD(state, DISTXDATA, cmd->msg[i]) < 0)
3739 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3740 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
3741 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3746 while ((!idle) && (i < 10)) {
3747 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3748 idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
3755 dprintk(FE_ERROR, 1, "I/O error");
3759 static int stv090x_send_diseqc_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst)
3761 struct stv090x_state *state = fe->demodulator_priv;
3762 u32 reg, idle = 0, fifo_full = 1;
3766 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3768 if (burst == SEC_MINI_A) {
3769 mode = (state->config->diseqc_envelope_mode) ? 5 : 3;
3772 mode = (state->config->diseqc_envelope_mode) ? 4 : 2;
3776 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, mode);
3777 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3778 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3780 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
3781 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3784 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
3785 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3789 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3790 fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
3793 if (STV090x_WRITE_DEMOD(state, DISTXDATA, value) < 0)
3796 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3797 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
3798 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3803 while ((!idle) && (i < 10)) {
3804 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3805 idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
3812 dprintk(FE_ERROR, 1, "I/O error");
3816 static int stv090x_recv_slave_reply(struct dvb_frontend *fe, struct dvb_diseqc_slave_reply *reply)
3818 struct stv090x_state *state = fe->demodulator_priv;
3819 u32 reg = 0, i = 0, rx_end = 0;
3821 while ((rx_end != 1) && (i < 10)) {
3824 reg = STV090x_READ_DEMOD(state, DISRX_ST0);
3825 rx_end = STV090x_GETFIELD_Px(reg, RX_END_FIELD);
3829 reply->msg_len = STV090x_GETFIELD_Px(reg, FIFO_BYTENBR_FIELD);
3830 for (i = 0; i < reply->msg_len; i++)
3831 reply->msg[i] = STV090x_READ_DEMOD(state, DISRXDATA);
3837 static int stv090x_sleep(struct dvb_frontend *fe)
3839 struct stv090x_state *state = fe->demodulator_priv;
3842 dprintk(FE_DEBUG, 1, "Set %s to sleep",
3843 state->device == STV0900 ? "STV0900" : "STV0903");
3845 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
3846 STV090x_SETFIELD(reg, STANDBY_FIELD, 0x01);
3847 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
3850 reg = stv090x_read_reg(state, STV090x_TSTTNR1);
3851 STV090x_SETFIELD(reg, ADC1_PON_FIELD, 0);
3852 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
3857 dprintk(FE_ERROR, 1, "I/O error");
3861 static int stv090x_wakeup(struct dvb_frontend *fe)
3863 struct stv090x_state *state = fe->demodulator_priv;
3866 dprintk(FE_DEBUG, 1, "Wake %s from standby",
3867 state->device == STV0900 ? "STV0900" : "STV0903");
3869 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
3870 STV090x_SETFIELD(reg, STANDBY_FIELD, 0x00);
3871 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
3874 reg = stv090x_read_reg(state, STV090x_TSTTNR1);
3875 STV090x_SETFIELD(reg, ADC1_PON_FIELD, 1);
3876 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
3881 dprintk(FE_ERROR, 1, "I/O error");
3885 static void stv090x_release(struct dvb_frontend *fe)
3887 struct stv090x_state *state = fe->demodulator_priv;
3889 state->internal->num_used--;
3890 if (state->internal->num_used <= 0) {
3892 dprintk(FE_ERROR, 1, "Actually removing");
3894 remove_dev(state->internal);
3895 kfree(state->internal);
3901 static int stv090x_ldpc_mode(struct stv090x_state *state, enum stv090x_mode ldpc_mode)
3905 reg = stv090x_read_reg(state, STV090x_GENCFG);
3907 switch (ldpc_mode) {
3910 if ((state->demod_mode != STV090x_DUAL) || (STV090x_GETFIELD(reg, DDEMOD_FIELD) != 1)) {
3911 /* set LDPC to dual mode */
3912 if (stv090x_write_reg(state, STV090x_GENCFG, 0x1d) < 0)
3915 state->demod_mode = STV090x_DUAL;
3917 reg = stv090x_read_reg(state, STV090x_TSTRES0);
3918 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
3919 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3921 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
3922 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3925 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
3927 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0)
3929 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0)
3931 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0)
3933 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0)
3935 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0)
3937 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0)
3940 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0)
3942 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0)
3944 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0)
3946 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0)
3948 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0)
3950 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0)
3952 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0)
3955 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0)
3957 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0)
3962 case STV090x_SINGLE:
3963 if (stv090x_stop_modcod(state) < 0)
3965 if (stv090x_activate_modcod_single(state) < 0)
3968 if (state->demod == STV090x_DEMODULATOR_1) {
3969 if (stv090x_write_reg(state, STV090x_GENCFG, 0x06) < 0) /* path 2 */
3972 if (stv090x_write_reg(state, STV090x_GENCFG, 0x04) < 0) /* path 1 */
3976 reg = stv090x_read_reg(state, STV090x_TSTRES0);
3977 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
3978 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3980 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
3981 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3984 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
3985 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x01);
3986 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
3988 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x00);
3989 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
3996 dprintk(FE_ERROR, 1, "I/O error");
4000 /* return (Hz), clk in Hz*/
4001 static u32 stv090x_get_mclk(struct stv090x_state *state)
4003 const struct stv090x_config *config = state->config;
4007 div = stv090x_read_reg(state, STV090x_NCOARSE);
4008 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
4009 ratio = STV090x_GETFIELD(reg, SELX1RATIO_FIELD) ? 4 : 6;
4011 return (div + 1) * config->xtal / ratio; /* kHz */
4014 static int stv090x_set_mclk(struct stv090x_state *state, u32 mclk, u32 clk)
4016 const struct stv090x_config *config = state->config;
4017 u32 reg, div, clk_sel;
4019 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
4020 clk_sel = ((STV090x_GETFIELD(reg, SELX1RATIO_FIELD) == 1) ? 4 : 6);
4022 div = ((clk_sel * mclk) / config->xtal) - 1;
4024 reg = stv090x_read_reg(state, STV090x_NCOARSE);
4025 STV090x_SETFIELD(reg, M_DIV_FIELD, div);
4026 if (stv090x_write_reg(state, STV090x_NCOARSE, reg) < 0)
4029 state->internal->mclk = stv090x_get_mclk(state);
4031 /*Set the DiseqC frequency to 22KHz */
4032 div = state->internal->mclk / 704000;
4033 if (STV090x_WRITE_DEMOD(state, F22TX, div) < 0)
4035 if (STV090x_WRITE_DEMOD(state, F22RX, div) < 0)
4040 dprintk(FE_ERROR, 1, "I/O error");
4044 static int stv090x_set_tspath(struct stv090x_state *state)
4048 if (state->internal->dev_ver >= 0x20) {
4049 switch (state->config->ts1_mode) {
4050 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4051 case STV090x_TSMODE_DVBCI:
4052 switch (state->config->ts2_mode) {
4053 case STV090x_TSMODE_SERIAL_PUNCTURED:
4054 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4056 stv090x_write_reg(state, STV090x_TSGENERAL, 0x00);
4059 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4060 case STV090x_TSMODE_DVBCI:
4061 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x06) < 0) /* Mux'd stream mode */
4063 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4064 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4065 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4067 reg = stv090x_read_reg(state, STV090x_P2_TSCFGM);
4068 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4069 if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0)
4071 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
4073 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
4079 case STV090x_TSMODE_SERIAL_PUNCTURED:
4080 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4082 switch (state->config->ts2_mode) {
4083 case STV090x_TSMODE_SERIAL_PUNCTURED:
4084 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4086 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
4090 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4091 case STV090x_TSMODE_DVBCI:
4092 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0a) < 0)
4099 switch (state->config->ts1_mode) {
4100 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4101 case STV090x_TSMODE_DVBCI:
4102 switch (state->config->ts2_mode) {
4103 case STV090x_TSMODE_SERIAL_PUNCTURED:
4104 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4106 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x10);
4109 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4110 case STV090x_TSMODE_DVBCI:
4111 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x16);
4112 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4113 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4114 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4116 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4117 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 0);
4118 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4120 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
4122 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
4128 case STV090x_TSMODE_SERIAL_PUNCTURED:
4129 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4131 switch (state->config->ts2_mode) {
4132 case STV090x_TSMODE_SERIAL_PUNCTURED:
4133 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4135 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x14);
4138 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4139 case STV090x_TSMODE_DVBCI:
4140 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x12);
4147 switch (state->config->ts1_mode) {
4148 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4149 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4150 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4151 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4152 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4156 case STV090x_TSMODE_DVBCI:
4157 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4158 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4159 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4160 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4164 case STV090x_TSMODE_SERIAL_PUNCTURED:
4165 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4166 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4167 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4168 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4172 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4173 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4174 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4175 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4176 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4184 switch (state->config->ts2_mode) {
4185 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4186 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4187 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4188 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4189 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4193 case STV090x_TSMODE_DVBCI:
4194 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4195 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4196 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4197 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4201 case STV090x_TSMODE_SERIAL_PUNCTURED:
4202 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4203 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4204 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4205 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4209 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4210 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4211 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4212 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4213 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4221 if (state->config->ts1_clk > 0) {
4224 switch (state->config->ts1_mode) {
4225 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4226 case STV090x_TSMODE_DVBCI:
4228 speed = state->internal->mclk /
4229 (state->config->ts1_clk / 4);
4235 case STV090x_TSMODE_SERIAL_PUNCTURED:
4236 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4237 speed = state->internal->mclk /
4238 (state->config->ts1_clk / 32);
4245 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4246 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4247 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4249 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, speed) < 0)
4253 if (state->config->ts2_clk > 0) {
4256 switch (state->config->ts2_mode) {
4257 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4258 case STV090x_TSMODE_DVBCI:
4260 speed = state->internal->mclk /
4261 (state->config->ts2_clk / 4);
4267 case STV090x_TSMODE_SERIAL_PUNCTURED:
4268 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4269 speed = state->internal->mclk /
4270 (state->config->ts2_clk / 32);
4277 reg = stv090x_read_reg(state, STV090x_P2_TSCFGM);
4278 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4279 if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0)
4281 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, speed) < 0)
4285 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4286 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
4287 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4289 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
4290 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4293 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4294 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
4295 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4297 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
4298 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4303 dprintk(FE_ERROR, 1, "I/O error");
4307 static int stv090x_init(struct dvb_frontend *fe)
4309 struct stv090x_state *state = fe->demodulator_priv;
4310 const struct stv090x_config *config = state->config;
4313 if (state->internal->mclk == 0) {
4314 stv090x_set_mclk(state, 135000000, config->xtal); /* 135 Mhz */
4316 if (stv090x_write_reg(state, STV090x_SYNTCTRL,
4317 0x20 | config->clk_mode) < 0)
4319 stv090x_get_mclk(state);
4322 if (stv090x_wakeup(fe) < 0) {
4323 dprintk(FE_ERROR, 1, "Error waking device");
4327 if (stv090x_ldpc_mode(state, state->demod_mode) < 0)
4330 reg = STV090x_READ_DEMOD(state, TNRCFG2);
4331 STV090x_SETFIELD_Px(reg, TUN_IQSWAP_FIELD, state->inversion);
4332 if (STV090x_WRITE_DEMOD(state, TNRCFG2, reg) < 0)
4334 reg = STV090x_READ_DEMOD(state, DEMOD);
4335 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
4336 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
4339 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
4342 if (config->tuner_set_mode) {
4343 if (config->tuner_set_mode(fe, TUNER_WAKE) < 0)
4347 if (config->tuner_init) {
4348 if (config->tuner_init(fe) < 0)
4352 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
4355 if (stv090x_set_tspath(state) < 0)
4361 stv090x_i2c_gate_ctrl(fe, 0);
4363 dprintk(FE_ERROR, 1, "I/O error");
4367 static int stv090x_setup(struct dvb_frontend *fe)
4369 struct stv090x_state *state = fe->demodulator_priv;
4370 const struct stv090x_config *config = state->config;
4371 const struct stv090x_reg *stv090x_initval = NULL;
4372 const struct stv090x_reg *stv090x_cut20_val = NULL;
4373 unsigned long t1_size = 0, t2_size = 0;
4378 if (state->device == STV0900) {
4379 dprintk(FE_DEBUG, 1, "Initializing STV0900");
4380 stv090x_initval = stv0900_initval;
4381 t1_size = ARRAY_SIZE(stv0900_initval);
4382 stv090x_cut20_val = stv0900_cut20_val;
4383 t2_size = ARRAY_SIZE(stv0900_cut20_val);
4384 } else if (state->device == STV0903) {
4385 dprintk(FE_DEBUG, 1, "Initializing STV0903");
4386 stv090x_initval = stv0903_initval;
4387 t1_size = ARRAY_SIZE(stv0903_initval);
4388 stv090x_cut20_val = stv0903_cut20_val;
4389 t2_size = ARRAY_SIZE(stv0903_cut20_val);
4395 if (stv090x_write_reg(state, STV090x_P1_DMDISTATE, 0x5c) < 0)
4397 if (stv090x_write_reg(state, STV090x_P2_DMDISTATE, 0x5c) < 0)
4402 /* Set No Tuner Mode */
4403 if (stv090x_write_reg(state, STV090x_P1_TNRCFG, 0x6c) < 0)
4405 if (stv090x_write_reg(state, STV090x_P2_TNRCFG, 0x6c) < 0)
4408 /* I2C repeater OFF */
4409 STV090x_SETFIELD_Px(reg, ENARPT_LEVEL_FIELD, config->repeater_level);
4410 if (stv090x_write_reg(state, STV090x_P1_I2CRPT, reg) < 0)
4412 if (stv090x_write_reg(state, STV090x_P2_I2CRPT, reg) < 0)
4415 if (stv090x_write_reg(state, STV090x_NCOARSE, 0x13) < 0) /* set PLL divider */
4418 if (stv090x_write_reg(state, STV090x_I2CCFG, 0x08) < 0) /* 1/41 oversampling */
4420 if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0) /* enable PLL */
4425 dprintk(FE_DEBUG, 1, "Setting up initial values");
4426 for (i = 0; i < t1_size; i++) {
4427 if (stv090x_write_reg(state, stv090x_initval[i].addr, stv090x_initval[i].data) < 0)
4431 state->internal->dev_ver = stv090x_read_reg(state, STV090x_MID);
4432 if (state->internal->dev_ver >= 0x20) {
4433 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
4436 /* write cut20_val*/
4437 dprintk(FE_DEBUG, 1, "Setting up Cut 2.0 initial values");
4438 for (i = 0; i < t2_size; i++) {
4439 if (stv090x_write_reg(state, stv090x_cut20_val[i].addr, stv090x_cut20_val[i].data) < 0)
4443 } else if (state->internal->dev_ver < 0x20) {
4444 dprintk(FE_ERROR, 1, "ERROR: Unsupported Cut: 0x%02x!",
4445 state->internal->dev_ver);
4448 } else if (state->internal->dev_ver > 0x30) {
4449 /* we shouldn't bail out from here */
4450 dprintk(FE_ERROR, 1, "INFO: Cut: 0x%02x probably incomplete support!",
4451 state->internal->dev_ver);
4455 reg = stv090x_read_reg(state, STV090x_TSTTNR1);
4456 STV090x_SETFIELD(reg, ADC1_INMODE_FIELD,
4457 (config->adc1_range == STV090x_ADC_1Vpp) ? 0 : 1);
4458 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
4462 reg = stv090x_read_reg(state, STV090x_TSTTNR3);
4463 STV090x_SETFIELD(reg, ADC2_INMODE_FIELD,
4464 (config->adc2_range == STV090x_ADC_1Vpp) ? 0 : 1);
4465 if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0)
4468 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x80) < 0)
4470 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x00) < 0)
4473 /* workaround for stuck DiSEqC output */
4474 if (config->diseqc_envelope_mode)
4475 stv090x_send_diseqc_burst(fe, SEC_MINI_A);
4479 dprintk(FE_ERROR, 1, "I/O error");
4483 static struct dvb_frontend_ops stv090x_ops = {
4486 .name = "STV090x Multistandard",
4488 .frequency_min = 950000,
4489 .frequency_max = 2150000,
4490 .frequency_stepsize = 0,
4491 .frequency_tolerance = 0,
4492 .symbol_rate_min = 1000000,
4493 .symbol_rate_max = 45000000,
4494 .caps = FE_CAN_INVERSION_AUTO |
4497 FE_CAN_2G_MODULATION
4500 .release = stv090x_release,
4501 .init = stv090x_init,
4503 .sleep = stv090x_sleep,
4504 .get_frontend_algo = stv090x_frontend_algo,
4506 .i2c_gate_ctrl = stv090x_i2c_gate_ctrl,
4508 .diseqc_send_master_cmd = stv090x_send_diseqc_msg,
4509 .diseqc_send_burst = stv090x_send_diseqc_burst,
4510 .diseqc_recv_slave_reply = stv090x_recv_slave_reply,
4511 .set_tone = stv090x_set_tone,
4513 .search = stv090x_search,
4514 .read_status = stv090x_read_status,
4515 .read_ber = stv090x_read_per,
4516 .read_signal_strength = stv090x_read_signal_strength,
4517 .read_snr = stv090x_read_cnr
4521 struct dvb_frontend *stv090x_attach(const struct stv090x_config *config,
4522 struct i2c_adapter *i2c,
4523 enum stv090x_demodulator demod)
4525 struct stv090x_state *state = NULL;
4526 struct stv090x_dev *temp_int;
4528 state = kzalloc(sizeof (struct stv090x_state), GFP_KERNEL);
4532 state->verbose = &verbose;
4533 state->config = config;
4535 state->frontend.ops = stv090x_ops;
4536 state->frontend.demodulator_priv = state;
4537 state->demod = demod;
4538 state->demod_mode = config->demod_mode; /* Single or Dual mode */
4539 state->device = config->device;
4540 state->rolloff = STV090x_RO_35; /* default */
4542 temp_int = find_dev(state->i2c,
4543 state->config->address);
4545 if ((temp_int != NULL) && (state->demod_mode == STV090x_DUAL)) {
4546 state->internal = temp_int->internal;
4547 state->internal->num_used++;
4548 dprintk(FE_INFO, 1, "Found Internal Structure!");
4549 dprintk(FE_ERROR, 1, "Attaching %s demodulator(%d) Cut=0x%02x",
4550 state->device == STV0900 ? "STV0900" : "STV0903",
4552 state->internal->dev_ver);
4553 return &state->frontend;
4555 state->internal = kmalloc(sizeof(struct stv090x_internal),
4557 temp_int = append_internal(state->internal);
4558 state->internal->num_used = 1;
4559 state->internal->mclk = 0;
4560 state->internal->dev_ver = 0;
4561 state->internal->i2c_adap = state->i2c;
4562 state->internal->i2c_addr = state->config->address;
4563 dprintk(FE_INFO, 1, "Create New Internal Structure!");
4566 mutex_init(&state->internal->demod_lock);
4567 mutex_init(&state->internal->tuner_lock);
4569 if (stv090x_sleep(&state->frontend) < 0) {
4570 dprintk(FE_ERROR, 1, "Error putting device to sleep");
4574 if (stv090x_setup(&state->frontend) < 0) {
4575 dprintk(FE_ERROR, 1, "Error setting up device");
4578 if (stv090x_wakeup(&state->frontend) < 0) {
4579 dprintk(FE_ERROR, 1, "Error waking device");
4583 dprintk(FE_ERROR, 1, "Attaching %s demodulator(%d) Cut=0x%02x",
4584 state->device == STV0900 ? "STV0900" : "STV0903",
4586 state->internal->dev_ver);
4588 return &state->frontend;
4594 EXPORT_SYMBOL(stv090x_attach);
4595 MODULE_PARM_DESC(verbose, "Set Verbosity level");
4596 MODULE_AUTHOR("Manu Abraham");
4597 MODULE_DESCRIPTION("STV090x Multi-Std Broadcast frontend");
4598 MODULE_LICENSE("GPL");