2 Driver for Zarlink VP310/MT312 Satellite Channel Decoder
4 Copyright (C) 2003 Andreas Oberritter <obi@linuxtv.org>
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 http://products.zarlink.com/product_profiles/MT312.htm
23 http://products.zarlink.com/product_profiles/SL1935.htm
26 #include <linux/delay.h>
27 #include <linux/errno.h>
28 #include <linux/init.h>
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/string.h>
32 #include <linux/slab.h>
34 #include "dvb_frontend.h"
35 #include "mt312_priv.h"
40 struct i2c_adapter *i2c;
41 /* configuration settings */
42 const struct mt312_config *config;
43 struct dvb_frontend frontend;
51 #define dprintk(args...) \
54 printk(KERN_DEBUG "mt312: " args); \
57 #define MT312_PLL_CLK 10000000UL /* 10 MHz */
59 static int mt312_read(struct mt312_state *state, const enum mt312_reg_addr reg,
60 u8 *buf, const size_t count)
63 struct i2c_msg msg[2];
64 u8 regbuf[1] = { reg };
66 msg[0].addr = state->config->demod_address;
70 msg[1].addr = state->config->demod_address;
71 msg[1].flags = I2C_M_RD;
75 ret = i2c_transfer(state->i2c, msg, 2);
78 printk(KERN_ERR "%s: ret == %d\n", __func__, ret);
84 dprintk("R(%d):", reg & 0x7f);
85 for (i = 0; i < count; i++)
86 printk(" %02x", buf[i]);
93 static int mt312_write(struct mt312_state *state, const enum mt312_reg_addr reg,
94 const u8 *src, const size_t count)
102 dprintk("W(%d):", reg & 0x7f);
103 for (i = 0; i < count; i++)
104 printk(" %02x", src[i]);
109 memcpy(&buf[1], src, count);
111 msg.addr = state->config->demod_address;
116 ret = i2c_transfer(state->i2c, &msg, 1);
119 dprintk("%s: ret == %d\n", __func__, ret);
126 static inline int mt312_readreg(struct mt312_state *state,
127 const enum mt312_reg_addr reg, u8 *val)
129 return mt312_read(state, reg, val, 1);
132 static inline int mt312_writereg(struct mt312_state *state,
133 const enum mt312_reg_addr reg, const u8 val)
135 return mt312_write(state, reg, &val, 1);
138 static inline u32 mt312_div(u32 a, u32 b)
140 return (a + (b / 2)) / b;
143 static int mt312_reset(struct mt312_state *state, const u8 full)
145 return mt312_writereg(state, RESET, full ? 0x80 : 0x40);
148 static int mt312_get_inversion(struct mt312_state *state,
149 fe_spectral_inversion_t *i)
154 ret = mt312_readreg(state, VIT_MODE, &vit_mode);
158 if (vit_mode & 0x80) /* auto inversion was used */
159 *i = (vit_mode & 0x40) ? INVERSION_ON : INVERSION_OFF;
164 static int mt312_get_symbol_rate(struct mt312_state *state, u32 *sr)
173 ret = mt312_readreg(state, SYM_RATE_H, &sym_rate_h);
177 if (sym_rate_h & 0x80) {
178 /* symbol rate search was used */
179 ret = mt312_writereg(state, MON_CTRL, 0x03);
183 ret = mt312_read(state, MONITOR_H, buf, sizeof(buf));
187 monitor = (buf[0] << 8) | buf[1];
189 dprintk("sr(auto) = %u\n",
190 mt312_div(monitor * 15625, 4));
192 ret = mt312_writereg(state, MON_CTRL, 0x05);
196 ret = mt312_read(state, MONITOR_H, buf, sizeof(buf));
200 dec_ratio = ((buf[0] >> 5) & 0x07) * 32;
202 ret = mt312_read(state, SYM_RAT_OP_H, buf, sizeof(buf));
206 sym_rat_op = (buf[0] << 8) | buf[1];
208 dprintk("sym_rat_op=%d dec_ratio=%d\n",
209 sym_rat_op, dec_ratio);
210 dprintk("*sr(manual) = %lu\n",
211 (((state->xtal * 8192) / (sym_rat_op + 8192)) *
218 static int mt312_get_code_rate(struct mt312_state *state, fe_code_rate_t *cr)
220 const fe_code_rate_t fec_tab[8] =
221 { FEC_1_2, FEC_2_3, FEC_3_4, FEC_5_6, FEC_6_7, FEC_7_8,
222 FEC_AUTO, FEC_AUTO };
227 ret = mt312_readreg(state, FEC_STATUS, &fec_status);
231 *cr = fec_tab[(fec_status >> 4) & 0x07];
236 static int mt312_initfe(struct dvb_frontend *fe)
238 struct mt312_state *state = fe->demodulator_priv;
243 ret = mt312_writereg(state, CONFIG,
244 (state->freq_mult == 6 ? 0x88 : 0x8c));
248 /* wait at least 150 usec */
252 ret = mt312_reset(state, 1);
256 /* Per datasheet, write correct values. 09/28/03 ACCJr.
257 * If we don't do this, we won't get FE_HAS_VITERBI in the VP310. */
259 u8 buf_def[8] = { 0x14, 0x12, 0x03, 0x02,
260 0x01, 0x00, 0x00, 0x00 };
262 ret = mt312_write(state, VIT_SETUP, buf_def, sizeof(buf_def));
268 buf[0] = mt312_div(state->xtal * state->freq_mult * 2, 1000000);
271 buf[1] = mt312_div(state->xtal, 22000 * 4);
273 ret = mt312_write(state, SYS_CLK, buf, sizeof(buf));
277 ret = mt312_writereg(state, SNR_THS_HIGH, 0x32);
281 ret = mt312_writereg(state, OP_CTRL, 0x53);
289 ret = mt312_write(state, TS_SW_LIM_L, buf, sizeof(buf));
293 ret = mt312_writereg(state, CS_SW_LIM, 0x69);
300 static int mt312_send_master_cmd(struct dvb_frontend *fe,
301 struct dvb_diseqc_master_cmd *c)
303 struct mt312_state *state = fe->demodulator_priv;
307 if ((c->msg_len == 0) || (c->msg_len > sizeof(c->msg)))
310 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
314 ret = mt312_write(state, (0x80 | DISEQC_INSTR), c->msg, c->msg_len);
318 ret = mt312_writereg(state, DISEQC_MODE,
319 (diseqc_mode & 0x40) | ((c->msg_len - 1) << 3)
324 /* is there a better way to wait for message to be transmitted */
327 /* set DISEQC_MODE[2:0] to zero if a return message is expected */
328 if (c->msg[0] & 0x02) {
329 ret = mt312_writereg(state, DISEQC_MODE, (diseqc_mode & 0x40));
337 static int mt312_send_burst(struct dvb_frontend *fe, const fe_sec_mini_cmd_t c)
339 struct mt312_state *state = fe->demodulator_priv;
340 const u8 mini_tab[2] = { 0x02, 0x03 };
348 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
352 ret = mt312_writereg(state, DISEQC_MODE,
353 (diseqc_mode & 0x40) | mini_tab[c]);
360 static int mt312_set_tone(struct dvb_frontend *fe, const fe_sec_tone_mode_t t)
362 struct mt312_state *state = fe->demodulator_priv;
363 const u8 tone_tab[2] = { 0x01, 0x00 };
368 if (t > SEC_TONE_OFF)
371 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
375 ret = mt312_writereg(state, DISEQC_MODE,
376 (diseqc_mode & 0x40) | tone_tab[t]);
383 static int mt312_set_voltage(struct dvb_frontend *fe, const fe_sec_voltage_t v)
385 struct mt312_state *state = fe->demodulator_priv;
386 const u8 volt_tab[3] = { 0x00, 0x40, 0x00 };
388 if (v > SEC_VOLTAGE_OFF)
391 return mt312_writereg(state, DISEQC_MODE, volt_tab[v]);
394 static int mt312_read_status(struct dvb_frontend *fe, fe_status_t *s)
396 struct mt312_state *state = fe->demodulator_priv;
402 ret = mt312_read(state, QPSK_STAT_H, status, sizeof(status));
406 dprintk("QPSK_STAT_H: 0x%02x, QPSK_STAT_L: 0x%02x,"
407 " FEC_STATUS: 0x%02x\n", status[0], status[1], status[2]);
409 if (status[0] & 0xc0)
410 *s |= FE_HAS_SIGNAL; /* signal noise ratio */
411 if (status[0] & 0x04)
412 *s |= FE_HAS_CARRIER; /* qpsk carrier lock */
413 if (status[2] & 0x02)
414 *s |= FE_HAS_VITERBI; /* viterbi lock */
415 if (status[2] & 0x04)
416 *s |= FE_HAS_SYNC; /* byte align lock */
417 if (status[0] & 0x01)
418 *s |= FE_HAS_LOCK; /* qpsk lock */
423 static int mt312_read_ber(struct dvb_frontend *fe, u32 *ber)
425 struct mt312_state *state = fe->demodulator_priv;
429 ret = mt312_read(state, RS_BERCNT_H, buf, 3);
433 *ber = ((buf[0] << 16) | (buf[1] << 8) | buf[2]) * 64;
438 static int mt312_read_signal_strength(struct dvb_frontend *fe,
439 u16 *signal_strength)
441 struct mt312_state *state = fe->demodulator_priv;
447 ret = mt312_read(state, AGC_H, buf, sizeof(buf));
451 agc = (buf[0] << 6) | (buf[1] >> 2);
452 err_db = (s16) (((buf[1] & 0x03) << 14) | buf[2] << 6) >> 6;
454 *signal_strength = agc;
456 dprintk("agc=%08x err_db=%hd\n", agc, err_db);
461 static int mt312_read_snr(struct dvb_frontend *fe, u16 *snr)
463 struct mt312_state *state = fe->demodulator_priv;
467 ret = mt312_read(state, M_SNR_H, buf, sizeof(buf));
471 *snr = 0xFFFF - ((((buf[0] & 0x7f) << 8) | buf[1]) << 1);
476 static int mt312_read_ucblocks(struct dvb_frontend *fe, u32 *ubc)
478 struct mt312_state *state = fe->demodulator_priv;
482 ret = mt312_read(state, RS_UBC_H, buf, sizeof(buf));
486 *ubc = (buf[0] << 8) | buf[1];
491 static int mt312_set_frontend(struct dvb_frontend *fe,
492 struct dvb_frontend_parameters *p)
494 struct mt312_state *state = fe->demodulator_priv;
496 u8 buf[5], config_val;
499 const u8 fec_tab[10] =
500 { 0x00, 0x01, 0x02, 0x04, 0x3f, 0x08, 0x10, 0x20, 0x3f, 0x3f };
501 const u8 inv_tab[3] = { 0x00, 0x40, 0x80 };
503 dprintk("%s: Freq %d\n", __func__, p->frequency);
505 if ((p->frequency < fe->ops.info.frequency_min)
506 || (p->frequency > fe->ops.info.frequency_max))
509 if ((p->inversion < INVERSION_OFF)
510 || (p->inversion > INVERSION_ON))
513 if ((p->u.qpsk.symbol_rate < fe->ops.info.symbol_rate_min)
514 || (p->u.qpsk.symbol_rate > fe->ops.info.symbol_rate_max))
517 if ((p->u.qpsk.fec_inner < FEC_NONE)
518 || (p->u.qpsk.fec_inner > FEC_AUTO))
521 if ((p->u.qpsk.fec_inner == FEC_4_5)
522 || (p->u.qpsk.fec_inner == FEC_8_9))
527 /* For now we will do this only for the VP310.
528 * It should be better for the mt312 as well,
529 * but tuning will be slower. ACCJr 09/29/03
531 ret = mt312_readreg(state, CONFIG, &config_val);
534 if (p->u.qpsk.symbol_rate >= 30000000) {
535 /* Note that 30MS/s should use 90MHz */
536 if (state->freq_mult == 6) {
537 /* We are running 60MHz */
538 state->freq_mult = 9;
539 ret = mt312_initfe(fe);
544 if (state->freq_mult == 9) {
545 /* We are running 90MHz */
546 state->freq_mult = 6;
547 ret = mt312_initfe(fe);
561 if (fe->ops.tuner_ops.set_params) {
562 fe->ops.tuner_ops.set_params(fe, p);
563 if (fe->ops.i2c_gate_ctrl)
564 fe->ops.i2c_gate_ctrl(fe, 0);
567 /* sr = (u16)(sr * 256.0 / 1000000.0) */
568 sr = mt312_div(p->u.qpsk.symbol_rate * 4, 15625);
571 buf[0] = (sr >> 8) & 0x3f;
572 buf[1] = (sr >> 0) & 0xff;
575 buf[2] = inv_tab[p->inversion] | fec_tab[p->u.qpsk.fec_inner];
578 buf[3] = 0x40; /* swap I and Q before QPSK demodulation */
580 if (p->u.qpsk.symbol_rate < 10000000)
581 buf[3] |= 0x04; /* use afc mode */
586 ret = mt312_write(state, SYM_RATE_H, buf, sizeof(buf));
590 mt312_reset(state, 0);
595 static int mt312_get_frontend(struct dvb_frontend *fe,
596 struct dvb_frontend_parameters *p)
598 struct mt312_state *state = fe->demodulator_priv;
601 ret = mt312_get_inversion(state, &p->inversion);
605 ret = mt312_get_symbol_rate(state, &p->u.qpsk.symbol_rate);
609 ret = mt312_get_code_rate(state, &p->u.qpsk.fec_inner);
616 static int mt312_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
618 struct mt312_state *state = fe->demodulator_priv;
621 return mt312_writereg(state, GPP_CTRL, 0x40);
623 return mt312_writereg(state, GPP_CTRL, 0x00);
627 static int mt312_sleep(struct dvb_frontend *fe)
629 struct mt312_state *state = fe->demodulator_priv;
633 /* reset all registers to defaults */
634 ret = mt312_reset(state, 1);
638 ret = mt312_readreg(state, CONFIG, &config);
643 ret = mt312_writereg(state, CONFIG, config & 0x7f);
650 static int mt312_get_tune_settings(struct dvb_frontend *fe,
651 struct dvb_frontend_tune_settings *fesettings)
653 fesettings->min_delay_ms = 50;
654 fesettings->step_size = 0;
655 fesettings->max_drift = 0;
659 static void mt312_release(struct dvb_frontend *fe)
661 struct mt312_state *state = fe->demodulator_priv;
665 #define MT312_SYS_CLK 90000000UL /* 90 MHz */
666 static struct dvb_frontend_ops vp310_mt312_ops = {
669 .name = "Zarlink ???? DVB-S",
671 .frequency_min = 950000,
672 .frequency_max = 2150000,
673 .frequency_stepsize = (MT312_PLL_CLK / 1000) / 128, /* FIXME: adjust freq to real used xtal */
674 .symbol_rate_min = MT312_SYS_CLK / 128, /* FIXME as above */
675 .symbol_rate_max = MT312_SYS_CLK / 2,
677 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
678 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
679 FE_CAN_FEC_AUTO | FE_CAN_QPSK | FE_CAN_MUTE_TS |
683 .release = mt312_release,
685 .init = mt312_initfe,
686 .sleep = mt312_sleep,
687 .i2c_gate_ctrl = mt312_i2c_gate_ctrl,
689 .set_frontend = mt312_set_frontend,
690 .get_frontend = mt312_get_frontend,
691 .get_tune_settings = mt312_get_tune_settings,
693 .read_status = mt312_read_status,
694 .read_ber = mt312_read_ber,
695 .read_signal_strength = mt312_read_signal_strength,
696 .read_snr = mt312_read_snr,
697 .read_ucblocks = mt312_read_ucblocks,
699 .diseqc_send_master_cmd = mt312_send_master_cmd,
700 .diseqc_send_burst = mt312_send_burst,
701 .set_tone = mt312_set_tone,
702 .set_voltage = mt312_set_voltage,
705 struct dvb_frontend *vp310_mt312_attach(const struct mt312_config *config,
706 struct i2c_adapter *i2c)
708 struct mt312_state *state = NULL;
710 /* allocate memory for the internal state */
711 state = kmalloc(sizeof(struct mt312_state), GFP_KERNEL);
715 /* setup the state */
716 state->config = config;
719 /* check if the demod is there */
720 if (mt312_readreg(state, ID, &state->id) < 0)
723 /* create dvb_frontend */
724 memcpy(&state->frontend.ops, &vp310_mt312_ops,
725 sizeof(struct dvb_frontend_ops));
726 state->frontend.demodulator_priv = state;
730 strcpy(state->frontend.ops.info.name, "Zarlink VP310 DVB-S");
731 state->xtal = MT312_PLL_CLK;
732 state->freq_mult = 9;
735 strcpy(state->frontend.ops.info.name, "Zarlink MT312 DVB-S");
736 state->xtal = MT312_PLL_CLK;
737 state->freq_mult = 6;
740 printk(KERN_WARNING "Only Zarlink VP310/MT312"
741 " are supported chips.\n");
745 return &state->frontend;
751 EXPORT_SYMBOL(vp310_mt312_attach);
753 module_param(debug, int, 0644);
754 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
756 MODULE_DESCRIPTION("Zarlink VP310/MT312 DVB-S Demodulator driver");
757 MODULE_AUTHOR("Andreas Oberritter <obi@linuxtv.org>");
758 MODULE_LICENSE("GPL");