drivers/media/dvb/frontends/drxk_hard.c

   1 /*
   2  * drxk_hard: DRX-K DVB-C/T demodulator driver
   3  *
   4  * Copyright (C) 2010-2011 Digital Devices GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * version 2 only, as published by the Free Software Foundation.
   9  *
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  20  * 02110-1301, USA
  21  * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/module.h>
  26 #include <linux/moduleparam.h>
  27 #include <linux/init.h>
  28 #include <linux/delay.h>
  29 #include <linux/firmware.h>
  30 #include <linux/i2c.h>
  31 #include <linux/version.h>
  32 #include <asm/div64.h>
  33
  34 #include "dvb_frontend.h"
  35 #include "drxk.h"
  36 #include "drxk_hard.h"
  37
  38 static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode);
  39 static int PowerDownQAM(struct drxk_state *state);
  40 static int SetDVBTStandard(struct drxk_state *state,
  41                            enum OperationMode oMode);
  42 static int SetQAMStandard(struct drxk_state *state,
  43                           enum OperationMode oMode);
  44 static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
  45                   s32 tunerFreqOffset);
  46 static int SetDVBTStandard(struct drxk_state *state,
  47                            enum OperationMode oMode);
  48 static int DVBTStart(struct drxk_state *state);
  49 static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
  50                    s32 tunerFreqOffset);
  51 static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus);
  52 static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus);
  53 static int SwitchAntennaToQAM(struct drxk_state *state);
  54 static int SwitchAntennaToDVBT(struct drxk_state *state);
  55
  56 static bool IsDVBT(struct drxk_state *state)
  57 {
  58         return state->m_OperationMode == OM_DVBT;
  59 }
  60
  61 static bool IsQAM(struct drxk_state *state)
  62 {
  63         return state->m_OperationMode == OM_QAM_ITU_A ||
  64             state->m_OperationMode == OM_QAM_ITU_B ||
  65             state->m_OperationMode == OM_QAM_ITU_C;
  66 }
  67
  68 bool IsA1WithPatchCode(struct drxk_state *state)
  69 {
  70         return state->m_DRXK_A1_PATCH_CODE;
  71 }
  72
  73 bool IsA1WithRomCode(struct drxk_state *state)
  74 {
  75         return state->m_DRXK_A1_ROM_CODE;
  76 }
  77
  78 #define NOA1ROM 0
  79
  80 #define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0)
  81 #define DRXDAP_FASI_LONG_FORMAT(addr)  (((addr) & 0xFC30FF80) != 0)
  82
  83 #define DEFAULT_MER_83  165
  84 #define DEFAULT_MER_93  250
  85
  86 #ifndef DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH
  87 #define DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH (0x02)
  88 #endif
  89
  90 #ifndef DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH
  91 #define DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH (0x03)
  92 #endif
  93
  94 #ifndef DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH
  95 #define DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH (0x06)
  96 #endif
  97
  98 #define DEFAULT_DRXK_MPEG_LOCK_TIMEOUT 700
  99 #define DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT 500
 100
 101 #ifndef DRXK_KI_RAGC_ATV
 102 #define DRXK_KI_RAGC_ATV   4
 103 #endif
 104 #ifndef DRXK_KI_IAGC_ATV
 105 #define DRXK_KI_IAGC_ATV   6
 106 #endif
 107 #ifndef DRXK_KI_DAGC_ATV
 108 #define DRXK_KI_DAGC_ATV   7
 109 #endif
 110
 111 #ifndef DRXK_KI_RAGC_QAM
 112 #define DRXK_KI_RAGC_QAM   3
 113 #endif
 114 #ifndef DRXK_KI_IAGC_QAM
 115 #define DRXK_KI_IAGC_QAM   4
 116 #endif
 117 #ifndef DRXK_KI_DAGC_QAM
 118 #define DRXK_KI_DAGC_QAM   7
 119 #endif
 120 #ifndef DRXK_KI_RAGC_DVBT
 121 #define DRXK_KI_RAGC_DVBT  (IsA1WithPatchCode(state) ? 3 : 2)
 122 #endif
 123 #ifndef DRXK_KI_IAGC_DVBT
 124 #define DRXK_KI_IAGC_DVBT  (IsA1WithPatchCode(state) ? 4 : 2)
 125 #endif
 126 #ifndef DRXK_KI_DAGC_DVBT
 127 #define DRXK_KI_DAGC_DVBT  (IsA1WithPatchCode(state) ? 10 : 7)
 128 #endif
 129
 130 #ifndef DRXK_AGC_DAC_OFFSET
 131 #define DRXK_AGC_DAC_OFFSET (0x800)
 132 #endif
 133
 134 #ifndef DRXK_BANDWIDTH_8MHZ_IN_HZ
 135 #define DRXK_BANDWIDTH_8MHZ_IN_HZ  (0x8B8249L)
 136 #endif
 137
 138 #ifndef DRXK_BANDWIDTH_7MHZ_IN_HZ
 139 #define DRXK_BANDWIDTH_7MHZ_IN_HZ  (0x7A1200L)
 140 #endif
 141
 142 #ifndef DRXK_BANDWIDTH_6MHZ_IN_HZ
 143 #define DRXK_BANDWIDTH_6MHZ_IN_HZ  (0x68A1B6L)
 144 #endif
 145
 146 #ifndef DRXK_QAM_SYMBOLRATE_MAX
 147 #define DRXK_QAM_SYMBOLRATE_MAX         (7233000)
 148 #endif
 149
 150 #define DRXK_BL_ROM_OFFSET_TAPS_DVBT    56
 151 #define DRXK_BL_ROM_OFFSET_TAPS_ITU_A   64
 152 #define DRXK_BL_ROM_OFFSET_TAPS_ITU_C   0x5FE0
 153 #define DRXK_BL_ROM_OFFSET_TAPS_BG      24
 154 #define DRXK_BL_ROM_OFFSET_TAPS_DKILLP  32
 155 #define DRXK_BL_ROM_OFFSET_TAPS_NTSC    40
 156 #define DRXK_BL_ROM_OFFSET_TAPS_FM      48
 157 #define DRXK_BL_ROM_OFFSET_UCODE        0
 158
 159 #define DRXK_BLC_TIMEOUT                100
 160
 161 #define DRXK_BLCC_NR_ELEMENTS_TAPS      2
 162 #define DRXK_BLCC_NR_ELEMENTS_UCODE     6
 163
 164 #define DRXK_BLDC_NR_ELEMENTS_TAPS      28
 165
 166 #ifndef DRXK_OFDM_NE_NOTCH_WIDTH
 167 #define DRXK_OFDM_NE_NOTCH_WIDTH             (4)
 168 #endif
 169
 170 #define DRXK_QAM_SL_SIG_POWER_QAM16       (40960)
 171 #define DRXK_QAM_SL_SIG_POWER_QAM32       (20480)
 172 #define DRXK_QAM_SL_SIG_POWER_QAM64       (43008)
 173 #define DRXK_QAM_SL_SIG_POWER_QAM128      (20992)
 174 #define DRXK_QAM_SL_SIG_POWER_QAM256      (43520)
 175
 176 static unsigned int debug;
 177 module_param(debug, int, 0644);
 178 MODULE_PARM_DESC(debug, "enable debug messages");
 179
 180 #define dprintk(level, fmt, arg...) do {                        \
 181 if (debug >= level)                                             \
 182         printk(KERN_DEBUG "drxk: %s" fmt, __func__, ## arg);    \
 183 } while (0)
 184
 185
 186 static inline u32 MulDiv32(u32 a, u32 b, u32 c)
 187 {
 188         u64 tmp64;
 189
 190         tmp64 = (u64) a * (u64) b;
 191         do_div(tmp64, c);
 192
 193         return (u32) tmp64;
 194 }
 195
 196 inline u32 Frac28a(u32 a, u32 c)
 197 {
 198         int i = 0;
 199         u32 Q1 = 0;
 200         u32 R0 = 0;
 201
 202         R0 = (a % c) << 4;      /* 32-28 == 4 shifts possible at max */
 203         Q1 = a / c;             /* integer part, only the 4 least significant bits
 204                                    will be visible in the result */
 205
 206         /* division using radix 16, 7 nibbles in the result */
 207         for (i = 0; i < 7; i++) {
 208                 Q1 = (Q1 << 4) | (R0 / c);
 209                 R0 = (R0 % c) << 4;
 210         }
 211         /* rounding */
 212         if ((R0 >> 3) >= c)
 213                 Q1++;
 214
 215         return Q1;
 216 }
 217
 218 static u32 Log10Times100(u32 x)
 219 {
 220         static const u8 scale = 15;
 221         static const u8 indexWidth = 5;
 222         u8 i = 0;
 223         u32 y = 0;
 224         u32 d = 0;
 225         u32 k = 0;
 226         u32 r = 0;
 227         /*
 228            log2lut[n] = (1<<scale) * 200 * log2(1.0 + ((1.0/(1<<INDEXWIDTH)) * n))
 229            0 <= n < ((1<<INDEXWIDTH)+1)
 230          */
 231
 232         static const u32 log2lut[] = {
 233                 0,              /* 0.000000 */
 234                 290941,         /* 290941.300628 */
 235                 573196,         /* 573196.476418 */
 236                 847269,         /* 847269.179851 */
 237                 1113620,        /* 1113620.489452 */
 238                 1372674,        /* 1372673.576986 */
 239                 1624818,        /* 1624817.752104 */
 240                 1870412,        /* 1870411.981536 */
 241                 2109788,        /* 2109787.962654 */
 242                 2343253,        /* 2343252.817465 */
 243                 2571091,        /* 2571091.461923 */
 244                 2793569,        /* 2793568.696416 */
 245                 3010931,        /* 3010931.055901 */
 246                 3223408,        /* 3223408.452106 */
 247                 3431216,        /* 3431215.635215 */
 248                 3634553,        /* 3634553.498355 */
 249                 3833610,        /* 3833610.244726 */
 250                 4028562,        /* 4028562.434393 */
 251                 4219576,        /* 4219575.925308 */
 252                 4406807,        /* 4406806.721144 */
 253                 4590402,        /* 4590401.736809 */
 254                 4770499,        /* 4770499.491025 */
 255                 4947231,        /* 4947230.734179 */
 256                 5120719,        /* 5120719.018555 */
 257                 5291081,        /* 5291081.217197 */
 258                 5458428,        /* 5458427.996830 */
 259                 5622864,        /* 5622864.249668 */
 260                 5784489,        /* 5784489.488298 */
 261                 5943398,        /* 5943398.207380 */
 262                 6099680,        /* 6099680.215452 */
 263                 6253421,        /* 6253420.939751 */
 264                 6404702,        /* 6404701.706649 */
 265                 6553600,        /* 6553600.000000 */
 266         };
 267
 268
 269         if (x == 0)
 270                 return 0;
 271
 272         /* Scale x (normalize) */
 273         /* computing y in log(x/y) = log(x) - log(y) */
 274         if ((x & ((0xffffffff) << (scale + 1))) == 0) {
 275                 for (k = scale; k > 0; k--) {
 276                         if (x & (((u32) 1) << scale))
 277                                 break;
 278                         x <<= 1;
 279                 }
 280         } else {
 281                 for (k = scale; k < 31; k++) {
 282                         if ((x & (((u32) (-1)) << (scale + 1))) == 0)
 283                                 break;
 284                         x >>= 1;
 285                 }
 286         }
 287         /*
 288            Now x has binary point between bit[scale] and bit[scale-1]
 289            and 1.0 <= x < 2.0 */
 290
 291         /* correction for divison: log(x) = log(x/y)+log(y) */
 292         y = k * ((((u32) 1) << scale) * 200);
 293
 294         /* remove integer part */
 295         x &= ((((u32) 1) << scale) - 1);
 296         /* get index */
 297         i = (u8) (x >> (scale - indexWidth));
 298         /* compute delta (x - a) */
 299         d = x & ((((u32) 1) << (scale - indexWidth)) - 1);
 300         /* compute log, multiplication (d* (..)) must be within range ! */
 301         y += log2lut[i] +
 302             ((d * (log2lut[i + 1] - log2lut[i])) >> (scale - indexWidth));
 303         /* Conver to log10() */
 304         y /= 108853;            /* (log2(10) << scale) */
 305         r = (y >> 1);
 306         /* rounding */
 307         if (y & ((u32) 1))
 308                 r++;
 309         return r;
 310 }
 311
 312 /****************************************************************************/
 313 /* I2C **********************************************************************/
 314 /****************************************************************************/
 315
 316 static int i2c_read1(struct i2c_adapter *adapter, u8 adr, u8 *val)
 317 {
 318         struct i2c_msg msgs[1] = { {.addr = adr, .flags = I2C_M_RD,
 319                                     .buf = val, .len = 1}
 320         };
 321         return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1;
 322 }
 323
 324 static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len)
 325 {
 326         struct i2c_msg msg = {
 327             .addr = adr, .flags = 0, .buf = data, .len = len };
 328
 329         dprintk(3, ":");
 330         if (debug > 2) {
 331                 int i;
 332                 for (i = 0; i < len; i++)
 333                         printk(KERN_CONT " %02x", data[i]);
 334                 printk(KERN_CONT "\n");
 335         }
 336         if (i2c_transfer(adap, &msg, 1) != 1) {
 337                 printk(KERN_ERR "drxk: i2c write error at addr 0x%02x\n", adr);
 338                 return -1;
 339         }
 340         return 0;
 341 }
 342
 343 static int i2c_read(struct i2c_adapter *adap,
 344                     u8 adr, u8 *msg, int len, u8 *answ, int alen)
 345 {
 346         struct i2c_msg msgs[2] = {
 347                 {.addr = adr, .flags = 0,
 348                                     .buf = msg, .len = len},
 349                 {.addr = adr, .flags = I2C_M_RD,
 350                  .buf = answ, .len = alen}
 351         };
 352         dprintk(3, ":");
 353         if (debug > 2) {
 354                 int i;
 355                 for (i = 0; i < len; i++)
 356                         printk(KERN_CONT " %02x", msg[i]);
 357                 printk(KERN_CONT "\n");
 358         }
 359         if (i2c_transfer(adap, msgs, 2) != 2) {
 360                 if (debug > 2)
 361                         printk(KERN_CONT ": ERROR!\n");
 362
 363                 printk(KERN_ERR "drxk: i2c read error at addr 0x%02x\n", adr);
 364                 return -1;
 365         }
 366         if (debug > 2) {
 367                 int i;
 368                 printk(KERN_CONT ": Read ");
 369                 for (i = 0; i < len; i++)
 370                         printk(KERN_CONT " %02x", msg[i]);
 371                 printk(KERN_CONT "\n");
 372         }
 373         return 0;
 374 }
 375
 376 static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags)
 377 {
 378         u8 adr = state->demod_address, mm1[4], mm2[2], len;
 379
 380         if (state->single_master)
 381                 flags |= 0xC0;
 382
 383         if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
 384                 mm1[0] = (((reg << 1) & 0xFF) | 0x01);
 385                 mm1[1] = ((reg >> 16) & 0xFF);
 386                 mm1[2] = ((reg >> 24) & 0xFF) | flags;
 387                 mm1[3] = ((reg >> 7) & 0xFF);
 388                 len = 4;
 389         } else {
 390                 mm1[0] = ((reg << 1) & 0xFF);
 391                 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
 392                 len = 2;
 393         }
 394         dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
 395         if (i2c_read(state->i2c, adr, mm1, len, mm2, 2) < 0)
 396                 return -1;
 397         if (data)
 398                 *data = mm2[0] | (mm2[1] << 8);
 399
 400         return 0;
 401 }
 402
 403 static int read16(struct drxk_state *state, u32 reg, u16 *data)
 404 {
 405         return read16_flags(state, reg, data, 0);
 406 }
 407
 408 static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags)
 409 {
 410         u8 adr = state->demod_address, mm1[4], mm2[4], len;
 411
 412         if (state->single_master)
 413                 flags |= 0xC0;
 414
 415         if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
 416                 mm1[0] = (((reg << 1) & 0xFF) | 0x01);
 417                 mm1[1] = ((reg >> 16) & 0xFF);
 418                 mm1[2] = ((reg >> 24) & 0xFF) | flags;
 419                 mm1[3] = ((reg >> 7) & 0xFF);
 420                 len = 4;
 421         } else {
 422                 mm1[0] = ((reg << 1) & 0xFF);
 423                 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
 424                 len = 2;
 425         }
 426         dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
 427         if (i2c_read(state->i2c, adr, mm1, len, mm2, 4) < 0)
 428                 return -1;
 429         if (data)
 430                 *data = mm2[0] | (mm2[1] << 8) |
 431                     (mm2[2] << 16) | (mm2[3] << 24);
 432
 433         return 0;
 434 }
 435
 436 static int read32(struct drxk_state *state, u32 reg, u32 *data)
 437 {
 438         return read32_flags(state, reg, data, 0);
 439 }
 440
 441 static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags)
 442 {
 443         u8 adr = state->demod_address, mm[6], len;
 444
 445         if (state->single_master)
 446                 flags |= 0xC0;
 447         if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
 448                 mm[0] = (((reg << 1) & 0xFF) | 0x01);
 449                 mm[1] = ((reg >> 16) & 0xFF);
 450                 mm[2] = ((reg >> 24) & 0xFF) | flags;
 451                 mm[3] = ((reg >> 7) & 0xFF);
 452                 len = 4;
 453         } else {
 454                 mm[0] = ((reg << 1) & 0xFF);
 455                 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
 456                 len = 2;
 457         }
 458         mm[len] = data & 0xff;
 459         mm[len + 1] = (data >> 8) & 0xff;
 460
 461         dprintk(2, "(0x%08x, 0x%04x, 0x%02x)\n", reg, data, flags);
 462         if (i2c_write(state->i2c, adr, mm, len + 2) < 0)
 463                 return -1;
 464         return 0;
 465 }
 466
 467 static int write16(struct drxk_state *state, u32 reg, u16 data)
 468 {
 469         return write16_flags(state, reg, data, 0);
 470 }
 471
 472 static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags)
 473 {
 474         u8 adr = state->demod_address, mm[8], len;
 475
 476         if (state->single_master)
 477                 flags |= 0xC0;
 478         if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
 479                 mm[0] = (((reg << 1) & 0xFF) | 0x01);
 480                 mm[1] = ((reg >> 16) & 0xFF);
 481                 mm[2] = ((reg >> 24) & 0xFF) | flags;
 482                 mm[3] = ((reg >> 7) & 0xFF);
 483                 len = 4;
 484         } else {
 485                 mm[0] = ((reg << 1) & 0xFF);
 486                 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
 487                 len = 2;
 488         }
 489         mm[len] = data & 0xff;
 490         mm[len + 1] = (data >> 8) & 0xff;
 491         mm[len + 2] = (data >> 16) & 0xff;
 492         mm[len + 3] = (data >> 24) & 0xff;
 493         dprintk(2, "(0x%08x, 0x%08x, 0x%02x)\n", reg, data, flags);
 494         if (i2c_write(state->i2c, adr, mm, len + 4) < 0)
 495                 return -1;
 496         return 0;
 497 }
 498
 499 static int write32(struct drxk_state *state, u32 reg, u32 data)
 500 {
 501         return write32_flags(state, reg, data, 0);
 502 }
 503
 504 static int write_block(struct drxk_state *state, u32 Address,
 505                       const int BlockSize, const u8 pBlock[])
 506 {
 507         int status = 0, BlkSize = BlockSize;
 508         u8 Flags = 0;
 509
 510         if (state->single_master)
 511                 Flags |= 0xC0;
 512
 513         while (BlkSize > 0) {
 514                 int Chunk = BlkSize > state->m_ChunkSize ?
 515                     state->m_ChunkSize : BlkSize;
 516                 u8 *AdrBuf = &state->Chunk[0];
 517                 u32 AdrLength = 0;
 518
 519                 if (DRXDAP_FASI_LONG_FORMAT(Address) || (Flags != 0)) {
 520                         AdrBuf[0] = (((Address << 1) & 0xFF) | 0x01);
 521                         AdrBuf[1] = ((Address >> 16) & 0xFF);
 522                         AdrBuf[2] = ((Address >> 24) & 0xFF);
 523                         AdrBuf[3] = ((Address >> 7) & 0xFF);
 524                         AdrBuf[2] |= Flags;
 525                         AdrLength = 4;
 526                         if (Chunk == state->m_ChunkSize)
 527                                 Chunk -= 2;
 528                 } else {
 529                         AdrBuf[0] = ((Address << 1) & 0xFF);
 530                         AdrBuf[1] = (((Address >> 16) & 0x0F) |
 531                                      ((Address >> 18) & 0xF0));
 532                         AdrLength = 2;
 533                 }
 534                 memcpy(&state->Chunk[AdrLength], pBlock, Chunk);
 535                 dprintk(2, "(0x%08x, 0x%02x)\n", Address, Flags);
 536                 if (debug > 1) {
 537                         int i;
 538                         if (pBlock)
 539                                 for (i = 0; i < Chunk; i++)
 540                                         printk(KERN_CONT " %02x", pBlock[i]);
 541                         printk(KERN_CONT "\n");
 542                 }
 543                 status = i2c_write(state->i2c, state->demod_address,
 544                                    &state->Chunk[0], Chunk + AdrLength);
 545                 if (status < 0) {
 546                         printk(KERN_ERR "drxk: %s: i2c write error at addr 0x%02x\n",
 547                                __func__, Address);
 548                         break;
 549                 }
 550                 pBlock += Chunk;
 551                 Address += (Chunk >> 1);
 552                 BlkSize -= Chunk;
 553         }
 554         return status;
 555 }
 556
 557 #ifndef DRXK_MAX_RETRIES_POWERUP
 558 #define DRXK_MAX_RETRIES_POWERUP 20
 559 #endif
 560
 561 int PowerUpDevice(struct drxk_state *state)
 562 {
 563         int status;
 564         u8 data = 0;
 565         u16 retryCount = 0;
 566
 567         dprintk(1, "\n");
 568
 569         status = i2c_read1(state->i2c, state->demod_address, &data);
 570         if (status < 0)
 571                 do {
 572                         data = 0;
 573                         if (i2c_write(state->i2c,
 574                                       state->demod_address, &data, 1) < 0)
 575                                 printk(KERN_ERR "drxk: powerup failed\n");
 576                         msleep(10);
 577                         retryCount++;
 578                 } while (i2c_read1(state->i2c,
 579                                    state->demod_address, &data) < 0 &&
 580                          (retryCount < DRXK_MAX_RETRIES_POWERUP));
 581         if (retryCount >= DRXK_MAX_RETRIES_POWERUP)
 582                 return -1;
 583         do {
 584                 /* Make sure all clk domains are active */
 585                 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE);
 586                 if (status < 0)
 587                         break;
 588                 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
 589                 if (status < 0)
 590                         break;
 591                 /* Enable pll lock tests */
 592                 status = write16(state, SIO_CC_PLL_LOCK__A, 1);
 593                 if (status < 0)
 594                         break;
 595                 state->m_currentPowerMode = DRX_POWER_UP;
 596         } while (0);
 597         return status;
 598 }
 599
 600
 601 static int init_state(struct drxk_state *state)
 602 {
 603         u32 ulVSBIfAgcMode = DRXK_AGC_CTRL_AUTO;
 604         u32 ulVSBIfAgcOutputLevel = 0;
 605         u32 ulVSBIfAgcMinLevel = 0;
 606         u32 ulVSBIfAgcMaxLevel = 0x7FFF;
 607         u32 ulVSBIfAgcSpeed = 3;
 608
 609         u32 ulVSBRfAgcMode = DRXK_AGC_CTRL_AUTO;
 610         u32 ulVSBRfAgcOutputLevel = 0;
 611         u32 ulVSBRfAgcMinLevel = 0;
 612         u32 ulVSBRfAgcMaxLevel = 0x7FFF;
 613         u32 ulVSBRfAgcSpeed = 3;
 614         u32 ulVSBRfAgcTop = 9500;
 615         u32 ulVSBRfAgcCutOffCurrent = 4000;
 616
 617         u32 ulATVIfAgcMode = DRXK_AGC_CTRL_AUTO;
 618         u32 ulATVIfAgcOutputLevel = 0;
 619         u32 ulATVIfAgcMinLevel = 0;
 620         u32 ulATVIfAgcMaxLevel = 0;
 621         u32 ulATVIfAgcSpeed = 3;
 622
 623         u32 ulATVRfAgcMode = DRXK_AGC_CTRL_OFF;
 624         u32 ulATVRfAgcOutputLevel = 0;
 625         u32 ulATVRfAgcMinLevel = 0;
 626         u32 ulATVRfAgcMaxLevel = 0;
 627         u32 ulATVRfAgcTop = 9500;
 628         u32 ulATVRfAgcCutOffCurrent = 4000;
 629         u32 ulATVRfAgcSpeed = 3;
 630
 631         u32 ulQual83 = DEFAULT_MER_83;
 632         u32 ulQual93 = DEFAULT_MER_93;
 633
 634         u32 ulDVBTStaticTSClock = 1;
 635         u32 ulDVBCStaticTSClock = 1;
 636
 637         u32 ulMpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
 638         u32 ulDemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
 639
 640         /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
 641         /* io_pad_cfg_mode output mode is drive always */
 642         /* io_pad_cfg_drive is set to power 2 (23 mA) */
 643         u32 ulGPIOCfg = 0x0113;
 644         u32 ulGPIO = 0;
 645         u32 ulSerialMode = 1;
 646         u32 ulInvertTSClock = 0;
 647         u32 ulTSDataStrength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH;
 648         u32 ulTSClockkStrength = DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH;
 649         u32 ulDVBTBitrate = 50000000;
 650         u32 ulDVBCBitrate = DRXK_QAM_SYMBOLRATE_MAX * 8;
 651
 652         u32 ulInsertRSByte = 0;
 653
 654         u32 ulRfMirror = 1;
 655         u32 ulPowerDown = 0;
 656
 657         u32 ulAntennaDVBT = 1;
 658         u32 ulAntennaDVBC = 0;
 659         u32 ulAntennaSwitchDVBTDVBC = 0;
 660
 661         dprintk(1, "\n");
 662
 663         state->m_hasLNA = false;
 664         state->m_hasDVBT = false;
 665         state->m_hasDVBC = false;
 666         state->m_hasATV = false;
 667         state->m_hasOOB = false;
 668         state->m_hasAudio = false;
 669
 670         state->m_ChunkSize = 124;
 671
 672         state->m_oscClockFreq = 0;
 673         state->m_smartAntInverted = false;
 674         state->m_bPDownOpenBridge = false;
 675
 676         /* real system clock frequency in kHz */
 677         state->m_sysClockFreq = 151875;
 678         /* Timing div, 250ns/Psys */
 679         /* Timing div, = (delay (nano seconds) * sysclk (kHz))/ 1000 */
 680         state->m_HICfgTimingDiv = ((state->m_sysClockFreq / 1000) *
 681                                    HI_I2C_DELAY) / 1000;
 682         /* Clipping */
 683         if (state->m_HICfgTimingDiv > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M)
 684                 state->m_HICfgTimingDiv = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M;
 685         state->m_HICfgWakeUpKey = (state->demod_address << 1);
 686         /* port/bridge/power down ctrl */
 687         state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
 688
 689         state->m_bPowerDown = (ulPowerDown != 0);
 690
 691         state->m_DRXK_A1_PATCH_CODE = false;
 692         state->m_DRXK_A1_ROM_CODE = false;
 693         state->m_DRXK_A2_ROM_CODE = false;
 694         state->m_DRXK_A3_ROM_CODE = false;
 695         state->m_DRXK_A2_PATCH_CODE = false;
 696         state->m_DRXK_A3_PATCH_CODE = false;
 697
 698         /* Init AGC and PGA parameters */
 699         /* VSB IF */
 700         state->m_vsbIfAgcCfg.ctrlMode = (ulVSBIfAgcMode);
 701         state->m_vsbIfAgcCfg.outputLevel = (ulVSBIfAgcOutputLevel);
 702         state->m_vsbIfAgcCfg.minOutputLevel = (ulVSBIfAgcMinLevel);
 703         state->m_vsbIfAgcCfg.maxOutputLevel = (ulVSBIfAgcMaxLevel);
 704         state->m_vsbIfAgcCfg.speed = (ulVSBIfAgcSpeed);
 705         state->m_vsbPgaCfg = 140;
 706
 707         /* VSB RF */
 708         state->m_vsbRfAgcCfg.ctrlMode = (ulVSBRfAgcMode);
 709         state->m_vsbRfAgcCfg.outputLevel = (ulVSBRfAgcOutputLevel);
 710         state->m_vsbRfAgcCfg.minOutputLevel = (ulVSBRfAgcMinLevel);
 711         state->m_vsbRfAgcCfg.maxOutputLevel = (ulVSBRfAgcMaxLevel);
 712         state->m_vsbRfAgcCfg.speed = (ulVSBRfAgcSpeed);
 713         state->m_vsbRfAgcCfg.top = (ulVSBRfAgcTop);
 714         state->m_vsbRfAgcCfg.cutOffCurrent = (ulVSBRfAgcCutOffCurrent);
 715         state->m_vsbPreSawCfg.reference = 0x07;
 716         state->m_vsbPreSawCfg.usePreSaw = true;
 717
 718         state->m_Quality83percent = DEFAULT_MER_83;
 719         state->m_Quality93percent = DEFAULT_MER_93;
 720         if (ulQual93 <= 500 && ulQual83 < ulQual93) {
 721                 state->m_Quality83percent = ulQual83;
 722                 state->m_Quality93percent = ulQual93;
 723         }
 724
 725         /* ATV IF */
 726         state->m_atvIfAgcCfg.ctrlMode = (ulATVIfAgcMode);
 727         state->m_atvIfAgcCfg.outputLevel = (ulATVIfAgcOutputLevel);
 728         state->m_atvIfAgcCfg.minOutputLevel = (ulATVIfAgcMinLevel);
 729         state->m_atvIfAgcCfg.maxOutputLevel = (ulATVIfAgcMaxLevel);
 730         state->m_atvIfAgcCfg.speed = (ulATVIfAgcSpeed);
 731
 732         /* ATV RF */
 733         state->m_atvRfAgcCfg.ctrlMode = (ulATVRfAgcMode);
 734         state->m_atvRfAgcCfg.outputLevel = (ulATVRfAgcOutputLevel);
 735         state->m_atvRfAgcCfg.minOutputLevel = (ulATVRfAgcMinLevel);
 736         state->m_atvRfAgcCfg.maxOutputLevel = (ulATVRfAgcMaxLevel);
 737         state->m_atvRfAgcCfg.speed = (ulATVRfAgcSpeed);
 738         state->m_atvRfAgcCfg.top = (ulATVRfAgcTop);
 739         state->m_atvRfAgcCfg.cutOffCurrent = (ulATVRfAgcCutOffCurrent);
 740         state->m_atvPreSawCfg.reference = 0x04;
 741         state->m_atvPreSawCfg.usePreSaw = true;
 742
 743
 744         /* DVBT RF */
 745         state->m_dvbtRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF;
 746         state->m_dvbtRfAgcCfg.outputLevel = 0;
 747         state->m_dvbtRfAgcCfg.minOutputLevel = 0;
 748         state->m_dvbtRfAgcCfg.maxOutputLevel = 0xFFFF;
 749         state->m_dvbtRfAgcCfg.top = 0x2100;
 750         state->m_dvbtRfAgcCfg.cutOffCurrent = 4000;
 751         state->m_dvbtRfAgcCfg.speed = 1;
 752
 753
 754         /* DVBT IF */
 755         state->m_dvbtIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO;
 756         state->m_dvbtIfAgcCfg.outputLevel = 0;
 757         state->m_dvbtIfAgcCfg.minOutputLevel = 0;
 758         state->m_dvbtIfAgcCfg.maxOutputLevel = 9000;
 759         state->m_dvbtIfAgcCfg.top = 13424;
 760         state->m_dvbtIfAgcCfg.cutOffCurrent = 0;
 761         state->m_dvbtIfAgcCfg.speed = 3;
 762         state->m_dvbtIfAgcCfg.FastClipCtrlDelay = 30;
 763         state->m_dvbtIfAgcCfg.IngainTgtMax = 30000;
 764         /* state->m_dvbtPgaCfg = 140; */
 765
 766         state->m_dvbtPreSawCfg.reference = 4;
 767         state->m_dvbtPreSawCfg.usePreSaw = false;
 768
 769         /* QAM RF */
 770         state->m_qamRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF;
 771         state->m_qamRfAgcCfg.outputLevel = 0;
 772         state->m_qamRfAgcCfg.minOutputLevel = 6023;
 773         state->m_qamRfAgcCfg.maxOutputLevel = 27000;
 774         state->m_qamRfAgcCfg.top = 0x2380;
 775         state->m_qamRfAgcCfg.cutOffCurrent = 4000;
 776         state->m_qamRfAgcCfg.speed = 3;
 777
 778         /* QAM IF */
 779         state->m_qamIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO;
 780         state->m_qamIfAgcCfg.outputLevel = 0;
 781         state->m_qamIfAgcCfg.minOutputLevel = 0;
 782         state->m_qamIfAgcCfg.maxOutputLevel = 9000;
 783         state->m_qamIfAgcCfg.top = 0x0511;
 784         state->m_qamIfAgcCfg.cutOffCurrent = 0;
 785         state->m_qamIfAgcCfg.speed = 3;
 786         state->m_qamIfAgcCfg.IngainTgtMax = 5119;
 787         state->m_qamIfAgcCfg.FastClipCtrlDelay = 50;
 788
 789         state->m_qamPgaCfg = 140;
 790         state->m_qamPreSawCfg.reference = 4;
 791         state->m_qamPreSawCfg.usePreSaw = false;
 792
 793         state->m_OperationMode = OM_NONE;
 794         state->m_DrxkState = DRXK_UNINITIALIZED;
 795
 796         /* MPEG output configuration */
 797         state->m_enableMPEGOutput = true;       /* If TRUE; enable MPEG ouput */
 798         state->m_insertRSByte = false;  /* If TRUE; insert RS byte */
 799         state->m_enableParallel = true; /* If TRUE;
 800                                            parallel out otherwise serial */
 801         state->m_invertDATA = false;    /* If TRUE; invert DATA signals */
 802         state->m_invertERR = false;     /* If TRUE; invert ERR signal */
 803         state->m_invertSTR = false;     /* If TRUE; invert STR signals */
 804         state->m_invertVAL = false;     /* If TRUE; invert VAL signals */
 805         state->m_invertCLK = (ulInvertTSClock != 0);    /* If TRUE; invert CLK signals */
 806         state->m_DVBTStaticCLK = (ulDVBTStaticTSClock != 0);
 807         state->m_DVBCStaticCLK = (ulDVBCStaticTSClock != 0);
 808         /* If TRUE; static MPEG clockrate will be used;
 809            otherwise clockrate will adapt to the bitrate of the TS */
 810
 811         state->m_DVBTBitrate = ulDVBTBitrate;
 812         state->m_DVBCBitrate = ulDVBCBitrate;
 813
 814         state->m_TSDataStrength = (ulTSDataStrength & 0x07);
 815         state->m_TSClockkStrength = (ulTSClockkStrength & 0x07);
 816
 817         /* Maximum bitrate in b/s in case static clockrate is selected */
 818         state->m_mpegTsStaticBitrate = 19392658;
 819         state->m_disableTEIhandling = false;
 820
 821         if (ulInsertRSByte)
 822                 state->m_insertRSByte = true;
 823
 824         state->m_MpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
 825         if (ulMpegLockTimeOut < 10000)
 826                 state->m_MpegLockTimeOut = ulMpegLockTimeOut;
 827         state->m_DemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
 828         if (ulDemodLockTimeOut < 10000)
 829                 state->m_DemodLockTimeOut = ulDemodLockTimeOut;
 830
 831         /* QAM defaults */
 832         state->m_Constellation = DRX_CONSTELLATION_AUTO;
 833         state->m_qamInterleaveMode = DRXK_QAM_I12_J17;
 834         state->m_fecRsPlen = 204 * 8;   /* fecRsPlen  annex A */
 835         state->m_fecRsPrescale = 1;
 836
 837         state->m_sqiSpeed = DRXK_DVBT_SQI_SPEED_MEDIUM;
 838         state->m_agcFastClipCtrlDelay = 0;
 839
 840         state->m_GPIOCfg = (ulGPIOCfg);
 841         state->m_GPIO = (ulGPIO == 0 ? 0 : 1);
 842
 843         state->m_AntennaDVBT = (ulAntennaDVBT == 0 ? 0 : 1);
 844         state->m_AntennaDVBC = (ulAntennaDVBC == 0 ? 0 : 1);
 845         state->m_AntennaSwitchDVBTDVBC =
 846             (ulAntennaSwitchDVBTDVBC == 0 ? 0 : 1);
 847
 848         state->m_bPowerDown = false;
 849         state->m_currentPowerMode = DRX_POWER_DOWN;
 850
 851         state->m_enableParallel = (ulSerialMode == 0);
 852
 853         state->m_rfmirror = (ulRfMirror == 0);
 854         state->m_IfAgcPol = false;
 855         return 0;
 856 }
 857
 858 static int DRXX_Open(struct drxk_state *state)
 859 {
 860         int status = 0;
 861         u32 jtag = 0;
 862         u16 bid = 0;
 863         u16 key = 0;
 864
 865         dprintk(1, "\n");
 866         do {
 867                 /* stop lock indicator process */
 868                 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
 869                 if (status < 0)
 870                         break;
 871                 /* Check device id */
 872                 status = read16(state, SIO_TOP_COMM_KEY__A, &key);
 873                 if (status < 0)
 874                         break;
 875                 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
 876                 if (status < 0)
 877                         break;
 878                 status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag);
 879                 if (status < 0)
 880                         break;
 881                 status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid);
 882                 if (status < 0)
 883                         break;
 884                 status = write16(state, SIO_TOP_COMM_KEY__A, key);
 885                 if (status < 0)
 886                         break;
 887         } while (0);
 888         return status;
 889 }
 890
 891 static int GetDeviceCapabilities(struct drxk_state *state)
 892 {
 893         u16 sioPdrOhwCfg = 0;
 894         u32 sioTopJtagidLo = 0;
 895         int status;
 896
 897         dprintk(1, "\n");
 898         do {
 899                 /* driver 0.9.0 */
 900                 /* stop lock indicator process */
 901                 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
 902                 if (status < 0)
 903                         break;
 904
 905                 status = write16(state, SIO_TOP_COMM_KEY__A, 0xFABA);
 906                 if (status < 0)
 907                         break;
 908                 status = read16(state, SIO_PDR_OHW_CFG__A, &sioPdrOhwCfg);
 909                 if (status < 0)
 910                         break;
 911                 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
 912                 if (status < 0)
 913                         break;
 914
 915                 switch ((sioPdrOhwCfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) {
 916                 case 0:
 917                         /* ignore (bypass ?) */
 918                         break;
 919                 case 1:
 920                         /* 27 MHz */
 921                         state->m_oscClockFreq = 27000;
 922                         break;
 923                 case 2:
 924                         /* 20.25 MHz */
 925                         state->m_oscClockFreq = 20250;
 926                         break;
 927                 case 3:
 928                         /* 4 MHz */
 929                         state->m_oscClockFreq = 20250;
 930                         break;
 931                 default:
 932                         return -1;
 933                 }
 934                 /*
 935                    Determine device capabilities
 936                    Based on pinning v14
 937                  */
 938                 status = read32(state, SIO_TOP_JTAGID_LO__A, &sioTopJtagidLo);
 939                 if (status < 0)
 940                         break;
 941                 /* driver 0.9.0 */
 942                 switch ((sioTopJtagidLo >> 29) & 0xF) {
 943                 case 0:
 944                         state->m_deviceSpin = DRXK_SPIN_A1;
 945                         break;
 946                 case 2:
 947                         state->m_deviceSpin = DRXK_SPIN_A2;
 948                         break;
 949                 case 3:
 950                         state->m_deviceSpin = DRXK_SPIN_A3;
 951                         break;
 952                 default:
 953                         state->m_deviceSpin = DRXK_SPIN_UNKNOWN;
 954                         status = -1;
 955                         break;
 956                 }
 957                 switch ((sioTopJtagidLo >> 12) & 0xFF) {
 958                 case 0x13:
 959                         /* typeId = DRX3913K_TYPE_ID */
 960                         state->m_hasLNA = false;
 961                         state->m_hasOOB = false;
 962                         state->m_hasATV = false;
 963                         state->m_hasAudio = false;
 964                         state->m_hasDVBT = true;
 965                         state->m_hasDVBC = true;
 966                         state->m_hasSAWSW = true;
 967                         state->m_hasGPIO2 = false;
 968                         state->m_hasGPIO1 = false;
 969                         state->m_hasIRQN = false;
 970                         break;
 971                 case 0x15:
 972                         /* typeId = DRX3915K_TYPE_ID */
 973                         state->m_hasLNA = false;
 974                         state->m_hasOOB = false;
 975                         state->m_hasATV = true;
 976                         state->m_hasAudio = false;
 977                         state->m_hasDVBT = true;
 978                         state->m_hasDVBC = false;
 979                         state->m_hasSAWSW = true;
 980                         state->m_hasGPIO2 = true;
 981                         state->m_hasGPIO1 = true;
 982                         state->m_hasIRQN = false;
 983                         break;
 984                 case 0x16:
 985                         /* typeId = DRX3916K_TYPE_ID */
 986                         state->m_hasLNA = false;
 987                         state->m_hasOOB = false;
 988                         state->m_hasATV = true;
 989                         state->m_hasAudio = false;
 990                         state->m_hasDVBT = true;
 991                         state->m_hasDVBC = false;
 992                         state->m_hasSAWSW = true;
 993                         state->m_hasGPIO2 = true;
 994                         state->m_hasGPIO1 = true;
 995                         state->m_hasIRQN = false;
 996                         break;
 997                 case 0x18:
 998                         /* typeId = DRX3918K_TYPE_ID */
 999                         state->m_hasLNA = false;
1000                         state->m_hasOOB = false;
1001                         state->m_hasATV = true;
1002                         state->m_hasAudio = true;
1003                         state->m_hasDVBT = true;
1004                         state->m_hasDVBC = false;
1005                         state->m_hasSAWSW = true;
1006                         state->m_hasGPIO2 = true;
1007                         state->m_hasGPIO1 = true;
1008                         state->m_hasIRQN = false;
1009                         break;
1010                 case 0x21:
1011                         /* typeId = DRX3921K_TYPE_ID */
1012                         state->m_hasLNA = false;
1013                         state->m_hasOOB = false;
1014                         state->m_hasATV = true;
1015                         state->m_hasAudio = true;
1016                         state->m_hasDVBT = true;
1017                         state->m_hasDVBC = true;
1018                         state->m_hasSAWSW = true;
1019                         state->m_hasGPIO2 = true;
1020                         state->m_hasGPIO1 = true;
1021                         state->m_hasIRQN = false;
1022                         break;
1023                 case 0x23:
1024                         /* typeId = DRX3923K_TYPE_ID */
1025                         state->m_hasLNA = false;
1026                         state->m_hasOOB = false;
1027                         state->m_hasATV = true;
1028                         state->m_hasAudio = true;
1029                         state->m_hasDVBT = true;
1030                         state->m_hasDVBC = true;
1031                         state->m_hasSAWSW = true;
1032                         state->m_hasGPIO2 = true;
1033                         state->m_hasGPIO1 = true;
1034                         state->m_hasIRQN = false;
1035                         break;
1036                 case 0x25:
1037                         /* typeId = DRX3925K_TYPE_ID */
1038                         state->m_hasLNA = false;
1039                         state->m_hasOOB = false;
1040                         state->m_hasATV = true;
1041                         state->m_hasAudio = true;
1042                         state->m_hasDVBT = true;
1043                         state->m_hasDVBC = true;
1044                         state->m_hasSAWSW = true;
1045                         state->m_hasGPIO2 = true;
1046                         state->m_hasGPIO1 = true;
1047                         state->m_hasIRQN = false;
1048                         break;
1049                 case 0x26:
1050                         /* typeId = DRX3926K_TYPE_ID */
1051                         state->m_hasLNA = false;
1052                         state->m_hasOOB = false;
1053                         state->m_hasATV = true;
1054                         state->m_hasAudio = false;
1055                         state->m_hasDVBT = true;
1056                         state->m_hasDVBC = true;
1057                         state->m_hasSAWSW = true;
1058                         state->m_hasGPIO2 = true;
1059                         state->m_hasGPIO1 = true;
1060                         state->m_hasIRQN = false;
1061                         break;
1062                 default:
1063                         printk(KERN_ERR "drxk: DeviceID not supported = %02x\n",
1064                                ((sioTopJtagidLo >> 12) & 0xFF));
1065                         status = -1;
1066                         break;
1067                 }
1068         } while (0);
1069         return status;
1070 }
1071
1072 static int HI_Command(struct drxk_state *state, u16 cmd, u16 *pResult)
1073 {
1074         int status;
1075         bool powerdown_cmd;
1076
1077         dprintk(1, "\n");
1078
1079         /* Write command */
1080         status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd);
1081         if (status < 0)
1082                 return status;
1083         if (cmd == SIO_HI_RA_RAM_CMD_RESET)
1084                 msleep(1);
1085
1086         powerdown_cmd =
1087             (bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) &&
1088                     ((state->m_HICfgCtrl) &
1089                      SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) ==
1090                     SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ);
1091         if (powerdown_cmd == false) {
1092                 /* Wait until command rdy */
1093                 u32 retryCount = 0;
1094                 u16 waitCmd;
1095
1096                 do {
1097                         msleep(1);
1098                         retryCount += 1;
1099                         status = read16(state, SIO_HI_RA_RAM_CMD__A,
1100                                           &waitCmd);
1101                 } while ((status < 0) && (retryCount < DRXK_MAX_RETRIES)
1102                          && (waitCmd != 0));
1103
1104                 if (status == 0)
1105                         status = read16(state, SIO_HI_RA_RAM_RES__A,
1106                                         pResult);
1107         }
1108         return status;
1109 }
1110
1111 static int HI_CfgCommand(struct drxk_state *state)
1112 {
1113         int status;
1114
1115         dprintk(1, "\n");
1116
1117         mutex_lock(&state->mutex);
1118         do {
1119                 status = write16(state, SIO_HI_RA_RAM_PAR_6__A, state->m_HICfgTimeout);
1120                 if (status < 0)
1121                         break;
1122                 status = write16(state, SIO_HI_RA_RAM_PAR_5__A, state->m_HICfgCtrl);
1123                 if (status < 0)
1124                         break;
1125                 status = write16(state, SIO_HI_RA_RAM_PAR_4__A, state->m_HICfgWakeUpKey);
1126                 if (status < 0)
1127                         break;
1128                 status = write16(state, SIO_HI_RA_RAM_PAR_3__A, state->m_HICfgBridgeDelay);
1129                 if (status < 0)
1130                         break;
1131                 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, state->m_HICfgTimingDiv);
1132                 if (status < 0)
1133                         break;
1134                 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
1135                 if (status < 0)
1136                         break;
1137                 status = HI_Command(state, SIO_HI_RA_RAM_CMD_CONFIG, 0);
1138                 if (status < 0)
1139                         break;
1140
1141                 state->m_HICfgCtrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1142         } while (0);
1143         mutex_unlock(&state->mutex);
1144         return status;
1145 }
1146
1147 static int InitHI(struct drxk_state *state)
1148 {
1149         dprintk(1, "\n");
1150
1151         state->m_HICfgWakeUpKey = (state->demod_address << 1);
1152         state->m_HICfgTimeout = 0x96FF;
1153         /* port/bridge/power down ctrl */
1154         state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
1155         return HI_CfgCommand(state);
1156 }
1157
1158 static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable)
1159 {
1160         int status = -1;
1161         u16 sioPdrMclkCfg = 0;
1162         u16 sioPdrMdxCfg = 0;
1163
1164         dprintk(1, "\n");
1165         do {
1166                 /* stop lock indicator process */
1167                 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1168                 if (status < 0)
1169                         break;
1170
1171                 /*  MPEG TS pad configuration */
1172                 status = write16(state, SIO_TOP_COMM_KEY__A, 0xFABA);
1173                 if (status < 0)
1174                         break;
1175
1176                 if (mpegEnable == false) {
1177                         /*  Set MPEG TS pads to inputmode */
1178                         status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000);
1179                         if (status < 0)
1180                                 break;
1181                         status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000);
1182                         if (status < 0)
1183                                 break;
1184                         status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000);
1185                         if (status < 0)
1186                                 break;
1187                         status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000);
1188                         if (status < 0)
1189                                 break;
1190                         status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000);
1191                         if (status < 0)
1192                                 break;
1193                         status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1194                         if (status < 0)
1195                                 break;
1196                         status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1197                         if (status < 0)
1198                                 break;
1199                         status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1200                         if (status < 0)
1201                                 break;
1202                         status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1203                         if (status < 0)
1204                                 break;
1205                         status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1206                         if (status < 0)
1207                                 break;
1208                         status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1209                         if (status < 0)
1210                                 break;
1211                         status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1212                         if (status < 0)
1213                                 break;
1214                 } else {
1215                         /* Enable MPEG output */
1216                         sioPdrMdxCfg =
1217                             ((state->m_TSDataStrength <<
1218                               SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003);
1219                         sioPdrMclkCfg = ((state->m_TSClockkStrength <<
1220                                           SIO_PDR_MCLK_CFG_DRIVE__B) |
1221                                          0x0003);
1222
1223                         status = write16(state, SIO_PDR_MSTRT_CFG__A, sioPdrMdxCfg);
1224                         if (status < 0)
1225                                 break;
1226                         status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000);   /* Disable */
1227                         if (status < 0)
1228                                 break;
1229                         status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000);   /* Disable */
1230                         if (status < 0)
1231                                 break;
1232                         if (state->m_enableParallel == true) {
1233                                 /* paralel -> enable MD1 to MD7 */
1234                                 status = write16(state, SIO_PDR_MD1_CFG__A, sioPdrMdxCfg);
1235                                 if (status < 0)
1236                                         break;
1237                                 status = write16(state, SIO_PDR_MD2_CFG__A, sioPdrMdxCfg);
1238                                 if (status < 0)
1239                                         break;
1240                                 status = write16(state, SIO_PDR_MD3_CFG__A, sioPdrMdxCfg);
1241                                 if (status < 0)
1242                                         break;
1243                                 status = write16(state, SIO_PDR_MD4_CFG__A, sioPdrMdxCfg);
1244                                 if (status < 0)
1245                                         break;
1246                                 status = write16(state, SIO_PDR_MD5_CFG__A, sioPdrMdxCfg);
1247                                 if (status < 0)
1248                                         break;
1249                                 status = write16(state, SIO_PDR_MD6_CFG__A, sioPdrMdxCfg);
1250                                 if (status < 0)
1251                                         break;
1252                                 status = write16(state, SIO_PDR_MD7_CFG__A, sioPdrMdxCfg);
1253                                 if (status < 0)
1254                                         break;
1255                         } else {
1256                                 sioPdrMdxCfg = ((state->m_TSDataStrength <<
1257                                                  SIO_PDR_MD0_CFG_DRIVE__B)
1258                                                 | 0x0003);
1259                                 /* serial -> disable MD1 to MD7 */
1260                                 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1261                                 if (status < 0)
1262                                         break;
1263                                 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1264                                 if (status < 0)
1265                                         break;
1266                                 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1267                                 if (status < 0)
1268                                         break;
1269                                 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1270                                 if (status < 0)
1271                                         break;
1272                                 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1273                                 if (status < 0)
1274                                         break;
1275                                 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1276                                 if (status < 0)
1277                                         break;
1278                                 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1279                                 if (status < 0)
1280                                         break;
1281                         }
1282                         status = write16(state, SIO_PDR_MCLK_CFG__A, sioPdrMclkCfg);
1283                         if (status < 0)
1284                                 break;
1285                         status = write16(state, SIO_PDR_MD0_CFG__A, sioPdrMdxCfg);
1286                         if (status < 0)
1287                                 break;
1288                 }
1289                 /*  Enable MB output over MPEG pads and ctl input */
1290                 status = write16(state, SIO_PDR_MON_CFG__A, 0x0000);
1291                 if (status < 0)
1292                         break;
1293                 /*  Write nomagic word to enable pdr reg write */
1294                 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
1295                 if (status < 0)
1296                         break;
1297         } while (0);
1298         return status;
1299 }
1300
1301 static int MPEGTSDisable(struct drxk_state *state)
1302 {
1303         dprintk(1, "\n");
1304
1305         return MPEGTSConfigurePins(state, false);
1306 }
1307
1308 static int BLChainCmd(struct drxk_state *state,
1309                       u16 romOffset, u16 nrOfElements, u32 timeOut)
1310 {
1311         u16 blStatus = 0;
1312         int status;
1313         unsigned long end;
1314
1315         dprintk(1, "\n");
1316
1317         mutex_lock(&state->mutex);
1318         do {
1319                 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN);
1320                 if (status < 0)
1321                         break;
1322                 status = write16(state, SIO_BL_CHAIN_ADDR__A, romOffset);
1323                 if (status < 0)
1324                         break;
1325                 status = write16(state, SIO_BL_CHAIN_LEN__A, nrOfElements);
1326                 if (status < 0)
1327                         break;
1328                 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
1329                 if (status < 0)
1330                         break;
1331                 end = jiffies + msecs_to_jiffies(timeOut);
1332
1333                 do {
1334                         msleep(1);
1335                         status = read16(state, SIO_BL_STATUS__A, &blStatus);
1336                         if (status < 0)
1337                                 break;
1338                 } while ((blStatus == 0x1) &&
1339                          ((time_is_after_jiffies(end))));
1340                 if (blStatus == 0x1) {
1341                         printk(KERN_ERR "drxk: SIO not ready\n");
1342                         mutex_unlock(&state->mutex);
1343                         return -1;
1344                 }
1345         } while (0);
1346         mutex_unlock(&state->mutex);
1347         return status;
1348 }
1349
1350
1351 static int DownloadMicrocode(struct drxk_state *state,
1352                              const u8 pMCImage[], u32 Length)
1353 {
1354         const u8 *pSrc = pMCImage;
1355         u16 Flags;
1356         u16 Drain;
1357         u32 Address;
1358         u16 nBlocks;
1359         u16 BlockSize;
1360         u16 BlockCRC;
1361         u32 offset = 0;
1362         u32 i;
1363         int status = 0;
1364
1365         dprintk(1, "\n");
1366
1367         /* down the drain (we don care about MAGIC_WORD) */
1368         Drain = (pSrc[0] << 8) | pSrc[1];
1369         pSrc += sizeof(u16);
1370         offset += sizeof(u16);
1371         nBlocks = (pSrc[0] << 8) | pSrc[1];
1372         pSrc += sizeof(u16);
1373         offset += sizeof(u16);
1374
1375         for (i = 0; i < nBlocks; i += 1) {
1376                 Address = (pSrc[0] << 24) | (pSrc[1] << 16) |
1377                     (pSrc[2] << 8) | pSrc[3];
1378                 pSrc += sizeof(u32);
1379                 offset += sizeof(u32);
1380
1381                 BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16);
1382                 pSrc += sizeof(u16);
1383                 offset += sizeof(u16);
1384
1385                 Flags = (pSrc[0] << 8) | pSrc[1];
1386                 pSrc += sizeof(u16);
1387                 offset += sizeof(u16);
1388
1389                 BlockCRC = (pSrc[0] << 8) | pSrc[1];
1390                 pSrc += sizeof(u16);
1391                 offset += sizeof(u16);
1392
1393                 if (offset + BlockSize > Length) {
1394                         printk(KERN_ERR "drxk: Firmware is corrupted.\n");
1395                         return -EINVAL;
1396                 }
1397
1398                 status = write_block(state, Address, BlockSize, pSrc);
1399                 if (status < 0) {
1400                         printk(KERN_ERR "drxk: Error %d while loading firmware\n", status);
1401                         break;
1402                 }
1403                 pSrc += BlockSize;
1404                 offset += BlockSize;
1405         }
1406         return status;
1407 }
1408
1409 static int DVBTEnableOFDMTokenRing(struct drxk_state *state, bool enable)
1410 {
1411         int status;
1412         u16 data = 0;
1413         u16 desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON;
1414         u16 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED;
1415         unsigned long end;
1416
1417         dprintk(1, "\n");
1418
1419         if (enable == false) {
1420                 desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF;
1421                 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN;
1422         }
1423
1424         status = (read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data));
1425
1426         if (data == desiredStatus) {
1427                 /* tokenring already has correct status */
1428                 return status;
1429         }
1430         /* Disable/enable dvbt tokenring bridge   */
1431         status =
1432             write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desiredCtrl);
1433
1434         end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT);
1435         do {
1436                 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1437                 if (status < 0)
1438                         break;
1439         } while ((data != desiredStatus) && ((time_is_after_jiffies(end))));
1440         if (data != desiredStatus) {
1441                 printk(KERN_ERR "drxk: SIO not ready\n");
1442                 return -1;
1443         }
1444         return status;
1445 }
1446
1447 static int MPEGTSStop(struct drxk_state *state)
1448 {
1449         int status = 0;
1450         u16 fecOcSncMode = 0;
1451         u16 fecOcIprMode = 0;
1452
1453         dprintk(1, "\n");
1454
1455         do {
1456                 /* Gracefull shutdown (byte boundaries) */
1457                 status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode);
1458                 if (status < 0)
1459                         break;
1460                 fecOcSncMode |= FEC_OC_SNC_MODE_SHUTDOWN__M;
1461                 status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode);
1462                 if (status < 0)
1463                         break;
1464
1465                 /* Suppress MCLK during absence of data */
1466                 status = read16(state, FEC_OC_IPR_MODE__A, &fecOcIprMode);
1467                 if (status < 0)
1468                         break;
1469                 fecOcIprMode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M;
1470                 status = write16(state, FEC_OC_IPR_MODE__A, fecOcIprMode);
1471                 if (status < 0)
1472                         break;
1473         } while (0);
1474         return status;
1475 }
1476
1477 static int scu_command(struct drxk_state *state,
1478                        u16 cmd, u8 parameterLen,
1479                        u16 *parameter, u8 resultLen, u16 *result)
1480 {
1481 #if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15
1482 #error DRXK register mapping no longer compatible with this routine!
1483 #endif
1484         u16 curCmd = 0;
1485         int status;
1486         unsigned long end;
1487
1488         dprintk(1, "\n");
1489
1490         if ((cmd == 0) || ((parameterLen > 0) && (parameter == NULL)) ||
1491             ((resultLen > 0) && (result == NULL)))
1492                 return -1;
1493
1494         mutex_lock(&state->mutex);
1495         do {
1496                 /* assume that the command register is ready
1497                    since it is checked afterwards */
1498                 u8 buffer[34];
1499                 int cnt = 0, ii;
1500
1501                 for (ii = parameterLen - 1; ii >= 0; ii -= 1) {
1502                         buffer[cnt++] = (parameter[ii] & 0xFF);
1503                         buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF);
1504                 }
1505                 buffer[cnt++] = (cmd & 0xFF);
1506                 buffer[cnt++] = ((cmd >> 8) & 0xFF);
1507
1508                 write_block(state, SCU_RAM_PARAM_0__A -
1509                            (parameterLen - 1), cnt, buffer);
1510                 /* Wait until SCU has processed command */
1511                 end = jiffies + msecs_to_jiffies(DRXK_MAX_WAITTIME);
1512                 do {
1513                         msleep(1);
1514                         status = read16(state, SCU_RAM_COMMAND__A, &curCmd);
1515                         if (status < 0)
1516                                 break;
1517                 } while (!(curCmd == DRX_SCU_READY)
1518                          && (time_is_after_jiffies(end)));
1519                 if (curCmd != DRX_SCU_READY) {
1520                         printk(KERN_ERR "drxk: SCU not ready\n");
1521                         mutex_unlock(&state->mutex);
1522                         return -1;
1523                 }
1524                 /* read results */
1525                 if ((resultLen > 0) && (result != NULL)) {
1526                         s16 err;
1527                         int ii;
1528
1529                         for (ii = resultLen - 1; ii >= 0; ii -= 1) {
1530                                 status = read16(state, SCU_RAM_PARAM_0__A - ii, &result[ii]);
1531                                 if (status < 0)
1532                                         break;
1533                         }
1534
1535                         /* Check if an error was reported by SCU */
1536                         err = (s16) result[0];
1537
1538                         /* check a few fixed error codes */
1539                         if (err == SCU_RESULT_UNKSTD) {
1540                                 printk(KERN_ERR "drxk: SCU_RESULT_UNKSTD\n");
1541                                 mutex_unlock(&state->mutex);
1542                                 return -1;
1543                         } else if (err == SCU_RESULT_UNKCMD) {
1544                                 printk(KERN_ERR "drxk: SCU_RESULT_UNKCMD\n");
1545                                 mutex_unlock(&state->mutex);
1546                                 return -1;
1547                         }
1548                         /* here it is assumed that negative means error,
1549                            and positive no error */
1550                         else if (err < 0) {
1551                                 printk(KERN_ERR "drxk: %s ERROR\n", __func__);
1552                                 mutex_unlock(&state->mutex);
1553                                 return -1;
1554                         }
1555                 }
1556         } while (0);
1557         mutex_unlock(&state->mutex);
1558         if (status < 0)
1559                 printk(KERN_ERR "drxk: %s: status = %d\n", __func__, status);
1560
1561         return status;
1562 }
1563
1564 static int SetIqmAf(struct drxk_state *state, bool active)
1565 {
1566         u16 data = 0;
1567         int status;
1568
1569         dprintk(1, "\n");
1570
1571         do {
1572                 /* Configure IQM */
1573                 status = read16(state, IQM_AF_STDBY__A, &data);
1574                 if (status < 0)
1575                         break;
1576                 if (!active) {
1577                         data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY
1578                                  | IQM_AF_STDBY_STDBY_AMP_STANDBY
1579                                  | IQM_AF_STDBY_STDBY_PD_STANDBY
1580                                  | IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY
1581                                  | IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY);
1582                 } else {        /* active */
1583
1584                         data &= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY)
1585                                  & (~IQM_AF_STDBY_STDBY_AMP_STANDBY)
1586                                  & (~IQM_AF_STDBY_STDBY_PD_STANDBY)
1587                                  & (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY)
1588                                  & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY)
1589                             );
1590                 }
1591                 status = write16(state, IQM_AF_STDBY__A, data);
1592                 if (status < 0)
1593                         break;
1594         } while (0);
1595         return status;
1596 }
1597
1598 static int CtrlPowerMode(struct drxk_state *state, enum DRXPowerMode *mode)
1599 {
1600         int status = 0;
1601         u16 sioCcPwdMode = 0;
1602
1603         dprintk(1, "\n");
1604
1605         /* Check arguments */
1606         if (mode == NULL)
1607                 return -1;
1608
1609         switch (*mode) {
1610         case DRX_POWER_UP:
1611                 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_NONE;
1612                 break;
1613         case DRXK_POWER_DOWN_OFDM:
1614                 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OFDM;
1615                 break;
1616         case DRXK_POWER_DOWN_CORE:
1617                 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_CLOCK;
1618                 break;
1619         case DRXK_POWER_DOWN_PLL:
1620                 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_PLL;
1621                 break;
1622         case DRX_POWER_DOWN:
1623                 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OSC;
1624                 break;
1625         default:
1626                 /* Unknow sleep mode */
1627                 return -1;
1628                 break;
1629         }
1630
1631         /* If already in requested power mode, do nothing */
1632         if (state->m_currentPowerMode == *mode)
1633                 return 0;
1634
1635         /* For next steps make sure to start from DRX_POWER_UP mode */
1636         if (state->m_currentPowerMode != DRX_POWER_UP) {
1637                 do {
1638                         status = PowerUpDevice(state);
1639                         if (status < 0)
1640                                 break;
1641                         status = DVBTEnableOFDMTokenRing(state, true);
1642                         if (status < 0)
1643                                 break;
1644                 } while (0);
1645         }
1646
1647         if (*mode == DRX_POWER_UP) {
1648                 /* Restore analog & pin configuartion */
1649         } else {
1650                 /* Power down to requested mode */
1651                 /* Backup some register settings */
1652                 /* Set pins with possible pull-ups connected
1653                    to them in input mode */
1654                 /* Analog power down */
1655                 /* ADC power down */
1656                 /* Power down device */
1657                 /* stop all comm_exec */
1658                 /* Stop and power down previous standard */
1659                 do {
1660                         switch (state->m_OperationMode) {
1661                         case OM_DVBT:
1662                                 status = MPEGTSStop(state);
1663                                 if (status < 0)
1664                                         break;
1665                                 status = PowerDownDVBT(state, false);
1666                                 if (status < 0)
1667                                         break;
1668                                 break;
1669                         case OM_QAM_ITU_A:
1670                         case OM_QAM_ITU_C:
1671                                 status = MPEGTSStop(state);
1672                                 if (status < 0)
1673                                         break;
1674                                 status = PowerDownQAM(state);
1675                                 if (status < 0)
1676                                         break;
1677                                 break;
1678                         default:
1679                                 break;
1680                         }
1681                         status = DVBTEnableOFDMTokenRing(state, false);
1682                         if (status < 0)
1683                                 break;
1684                         status = write16(state, SIO_CC_PWD_MODE__A, sioCcPwdMode);
1685                         if (status < 0)
1686                                 break;
1687                         status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
1688                         if (status < 0)
1689                                 break;
1690
1691                         if (*mode != DRXK_POWER_DOWN_OFDM) {
1692                                 state->m_HICfgCtrl |=
1693                                     SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1694                                 status = HI_CfgCommand(state);
1695                                 if (status < 0)
1696                                         break;
1697                         }
1698                 } while (0);
1699         }
1700         state->m_currentPowerMode = *mode;
1701         return status;
1702 }
1703
1704 static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode)
1705 {
1706         enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
1707         u16 cmdResult = 0;
1708         u16 data = 0;
1709         int status;
1710
1711         dprintk(1, "\n");
1712
1713         do {
1714                 status = read16(state, SCU_COMM_EXEC__A, &data);
1715                 if (status < 0)
1716                         break;
1717                 if (data == SCU_COMM_EXEC_ACTIVE) {
1718                         /* Send OFDM stop command */
1719                         status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
1720                         if (status < 0)
1721                                 break;
1722                         /* Send OFDM reset command */
1723                         status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
1724                         if (status < 0)
1725                                 break;
1726                 }
1727
1728                 /* Reset datapath for OFDM, processors first */
1729                 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
1730                 if (status < 0)
1731                         break;
1732                 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
1733                 if (status < 0)
1734                         break;
1735                 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
1736                 if (status < 0)
1737                         break;
1738
1739                 /* powerdown AFE                   */
1740                 status = SetIqmAf(state, false);
1741                 if (status < 0)
1742                         break;
1743
1744                 /* powerdown to OFDM mode          */
1745                 if (setPowerMode) {
1746                         status = CtrlPowerMode(state, &powerMode);
1747                         if (status < 0)
1748                                 break;
1749                 }
1750         } while (0);
1751         return status;
1752 }
1753
1754 static int SetOperationMode(struct drxk_state *state,
1755                             enum OperationMode oMode)
1756 {
1757         int status = 0;
1758
1759         dprintk(1, "\n");
1760         /*
1761            Stop and power down previous standard
1762            TODO investigate total power down instead of partial
1763            power down depending on "previous" standard.
1764          */
1765         do {
1766                 /* disable HW lock indicator */
1767                 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1768                 if (status < 0)
1769                         break;
1770
1771                 if (state->m_OperationMode != oMode) {
1772                         switch (state->m_OperationMode) {
1773                                 /* OM_NONE was added for start up */
1774                         case OM_NONE:
1775                                 break;
1776                         case OM_DVBT:
1777                                 status = MPEGTSStop(state);
1778                                 if (status < 0)
1779                                         break;
1780                                 status = PowerDownDVBT(state, true);
1781                                 if (status < 0)
1782                                         break;
1783                                 state->m_OperationMode = OM_NONE;
1784                                 break;
1785                         case OM_QAM_ITU_B:
1786                                 status = -1;
1787                                 break;
1788                         case OM_QAM_ITU_A:      /* fallthrough */
1789                         case OM_QAM_ITU_C:
1790                                 status = MPEGTSStop(state);
1791                                 if (status < 0)
1792                                         break;
1793                                 status = PowerDownQAM(state);
1794                                 if (status < 0)
1795                                         break;
1796                                 state->m_OperationMode = OM_NONE;
1797                                 break;
1798                         default:
1799                                 status = -1;
1800                         }
1801                         status = status;
1802                         if (status < 0)
1803                                 break;
1804
1805                         /*
1806                            Power up new standard
1807                          */
1808                         switch (oMode) {
1809                         case OM_DVBT:
1810                                 state->m_OperationMode = oMode;
1811                                 status = SetDVBTStandard(state, oMode);
1812                                 if (status < 0)
1813                                         break;
1814                                 break;
1815                         case OM_QAM_ITU_B:
1816                                 status = -1;
1817                                 break;
1818                         case OM_QAM_ITU_A:      /* fallthrough */
1819                         case OM_QAM_ITU_C:
1820                                 state->m_OperationMode = oMode;
1821                                 status = SetQAMStandard(state, oMode);
1822                                 if (status < 0)
1823                                         break;
1824                                 break;
1825                         default:
1826                                 status = -1;
1827                         }
1828                 }
1829                 status = status;
1830                 if (status < 0)
1831                         break;
1832         } while (0);
1833         return 0;
1834 }
1835
1836 static int Start(struct drxk_state *state, s32 offsetFreq,
1837                  s32 IntermediateFrequency)
1838 {
1839         int status = 0;
1840
1841         dprintk(1, "\n");
1842         do {
1843                 u16 IFreqkHz;
1844                 s32 OffsetkHz = offsetFreq / 1000;
1845
1846                 if (state->m_DrxkState != DRXK_STOPPED &&
1847                     state->m_DrxkState != DRXK_DTV_STARTED) {
1848                         status = -1;
1849                         break;
1850                 }
1851                 state->m_bMirrorFreqSpect =
1852                     (state->param.inversion == INVERSION_ON);
1853
1854                 if (IntermediateFrequency < 0) {
1855                         state->m_bMirrorFreqSpect =
1856                             !state->m_bMirrorFreqSpect;
1857                         IntermediateFrequency = -IntermediateFrequency;
1858                 }
1859
1860                 switch (state->m_OperationMode) {
1861                 case OM_QAM_ITU_A:
1862                 case OM_QAM_ITU_C:
1863                         IFreqkHz = (IntermediateFrequency / 1000);
1864                         status = SetQAM(state, IFreqkHz, OffsetkHz);
1865                         if (status < 0)
1866                                 break;
1867                         state->m_DrxkState = DRXK_DTV_STARTED;
1868                         break;
1869                 case OM_DVBT:
1870                         IFreqkHz = (IntermediateFrequency / 1000);
1871                         status = MPEGTSStop(state);
1872                         if (status < 0)
1873                                 break;
1874                         status = SetDVBT(state, IFreqkHz, OffsetkHz);
1875                         if (status < 0)
1876                                 break;
1877                         status = DVBTStart(state);
1878                         if (status < 0)
1879                                 break;
1880                         state->m_DrxkState = DRXK_DTV_STARTED;
1881                         break;
1882                 default:
1883                         break;
1884                 }
1885         } while (0);
1886         return status;
1887 }
1888
1889 static int ShutDown(struct drxk_state *state)
1890 {
1891         dprintk(1, "\n");
1892
1893         MPEGTSStop(state);
1894         return 0;
1895 }
1896
1897 static int GetLockStatus(struct drxk_state *state, u32 *pLockStatus,
1898                          u32 Time)
1899 {
1900         int status = 0;
1901
1902         dprintk(1, "\n");
1903
1904         if (pLockStatus == NULL)
1905                 return -1;
1906
1907         *pLockStatus = NOT_LOCKED;
1908
1909         /* define the SCU command code */
1910         switch (state->m_OperationMode) {
1911         case OM_QAM_ITU_A:
1912         case OM_QAM_ITU_B:
1913         case OM_QAM_ITU_C:
1914                 status = GetQAMLockStatus(state, pLockStatus);
1915                 break;
1916         case OM_DVBT:
1917                 status = GetDVBTLockStatus(state, pLockStatus);
1918                 break;
1919         default:
1920                 break;
1921         }
1922         return status;
1923 }
1924
1925 static int MPEGTSStart(struct drxk_state *state)
1926 {
1927         int status = 0;
1928
1929         u16 fecOcSncMode = 0;
1930
1931         do {
1932                 /* Allow OC to sync again */
1933                 status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode);
1934                 if (status < 0)
1935                         break;
1936                 fecOcSncMode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M;
1937                 status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode);
1938                 if (status < 0)
1939                         break;
1940                 status = write16(state, FEC_OC_SNC_UNLOCK__A, 1);
1941                 if (status < 0)
1942                         break;
1943         } while (0);
1944         return status;
1945 }
1946
1947 static int MPEGTSDtoInit(struct drxk_state *state)
1948 {
1949         int status = -1;
1950
1951         dprintk(1, "\n");
1952
1953         do {
1954                 /* Rate integration settings */
1955                 status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000);
1956                 if (status < 0)
1957                         break;
1958                 status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C);
1959                 if (status < 0)
1960                         break;
1961                 status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A);
1962                 if (status < 0)
1963                         break;
1964                 status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008);
1965                 if (status < 0)
1966                         break;
1967                 status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006);
1968                 if (status < 0)
1969                         break;
1970                 status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680);
1971                 if (status < 0)
1972                         break;
1973                 status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080);
1974                 if (status < 0)
1975                         break;
1976                 status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4);
1977                 if (status < 0)
1978                         break;
1979
1980                 /* Additional configuration */
1981                 status = write16(state, FEC_OC_OCR_INVERT__A, 0);
1982                 if (status < 0)
1983                         break;
1984                 status = write16(state, FEC_OC_SNC_LWM__A, 2);
1985                 if (status < 0)
1986                         break;
1987                 status = write16(state, FEC_OC_SNC_HWM__A, 12);
1988                 if (status < 0)
1989                         break;
1990         } while (0);
1991         return status;
1992 }
1993
1994 static int MPEGTSDtoSetup(struct drxk_state *state,
1995                           enum OperationMode oMode)
1996 {
1997         int status = -1;
1998
1999         u16 fecOcRegMode = 0;   /* FEC_OC_MODE       register value */
2000         u16 fecOcRegIprMode = 0;        /* FEC_OC_IPR_MODE   register value */
2001         u16 fecOcDtoMode = 0;   /* FEC_OC_IPR_INVERT register value */
2002         u16 fecOcFctMode = 0;   /* FEC_OC_IPR_INVERT register value */
2003         u16 fecOcDtoPeriod = 2; /* FEC_OC_IPR_INVERT register value */
2004         u16 fecOcDtoBurstLen = 188;     /* FEC_OC_IPR_INVERT register value */
2005         u32 fecOcRcnCtlRate = 0;        /* FEC_OC_IPR_INVERT register value */
2006         u16 fecOcTmdMode = 0;
2007         u16 fecOcTmdIntUpdRate = 0;
2008         u32 maxBitRate = 0;
2009         bool staticCLK = false;
2010
2011         dprintk(1, "\n");
2012
2013         do {
2014                 /* Check insertion of the Reed-Solomon parity bytes */
2015                 status = read16(state, FEC_OC_MODE__A, &fecOcRegMode);
2016                 if (status < 0)
2017                         break;
2018                 status = read16(state, FEC_OC_IPR_MODE__A, &fecOcRegIprMode);
2019                 if (status < 0)
2020                         break;
2021                 fecOcRegMode &= (~FEC_OC_MODE_PARITY__M);
2022                 fecOcRegIprMode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M);
2023                 if (state->m_insertRSByte == true) {
2024                         /* enable parity symbol forward */
2025                         fecOcRegMode |= FEC_OC_MODE_PARITY__M;
2026                         /* MVAL disable during parity bytes */
2027                         fecOcRegIprMode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M;
2028                         /* TS burst length to 204 */
2029                         fecOcDtoBurstLen = 204;
2030                 }
2031
2032                 /* Check serial or parrallel output */
2033                 fecOcRegIprMode &= (~(FEC_OC_IPR_MODE_SERIAL__M));
2034                 if (state->m_enableParallel == false) {
2035                         /* MPEG data output is serial -> set ipr_mode[0] */
2036                         fecOcRegIprMode |= FEC_OC_IPR_MODE_SERIAL__M;
2037                 }
2038
2039                 switch (oMode) {
2040                 case OM_DVBT:
2041                         maxBitRate = state->m_DVBTBitrate;
2042                         fecOcTmdMode = 3;
2043                         fecOcRcnCtlRate = 0xC00000;
2044                         staticCLK = state->m_DVBTStaticCLK;
2045                         break;
2046                 case OM_QAM_ITU_A:      /* fallthrough */
2047                 case OM_QAM_ITU_C:
2048                         fecOcTmdMode = 0x0004;
2049                         fecOcRcnCtlRate = 0xD2B4EE;     /* good for >63 Mb/s */
2050                         maxBitRate = state->m_DVBCBitrate;
2051                         staticCLK = state->m_DVBCStaticCLK;
2052                         break;
2053                 default:
2054                         status = -1;
2055                 }               /* switch (standard) */
2056                 status = status;
2057                 if (status < 0)
2058                         break;
2059
2060                 /* Configure DTO's */
2061                 if (staticCLK) {
2062                         u32 bitRate = 0;
2063
2064                         /* Rational DTO for MCLK source (static MCLK rate),
2065                            Dynamic DTO for optimal grouping
2066                            (avoid intra-packet gaps),
2067                            DTO offset enable to sync TS burst with MSTRT */
2068                         fecOcDtoMode = (FEC_OC_DTO_MODE_DYNAMIC__M |
2069                                         FEC_OC_DTO_MODE_OFFSET_ENABLE__M);
2070                         fecOcFctMode = (FEC_OC_FCT_MODE_RAT_ENA__M |
2071                                         FEC_OC_FCT_MODE_VIRT_ENA__M);
2072
2073                         /* Check user defined bitrate */
2074                         bitRate = maxBitRate;
2075                         if (bitRate > 75900000UL) {     /* max is 75.9 Mb/s */
2076                                 bitRate = 75900000UL;
2077                         }
2078                         /* Rational DTO period:
2079                            dto_period = (Fsys / bitrate) - 2
2080
2081                            Result should be floored,
2082                            to make sure >= requested bitrate
2083                          */
2084                         fecOcDtoPeriod = (u16) (((state->m_sysClockFreq)
2085                                                  * 1000) / bitRate);
2086                         if (fecOcDtoPeriod <= 2)
2087                                 fecOcDtoPeriod = 0;
2088                         else
2089                                 fecOcDtoPeriod -= 2;
2090                         fecOcTmdIntUpdRate = 8;
2091                 } else {
2092                         /* (commonAttr->staticCLK == false) => dynamic mode */
2093                         fecOcDtoMode = FEC_OC_DTO_MODE_DYNAMIC__M;
2094                         fecOcFctMode = FEC_OC_FCT_MODE__PRE;
2095                         fecOcTmdIntUpdRate = 5;
2096                 }
2097
2098                 /* Write appropriate registers with requested configuration */
2099                 status = write16(state, FEC_OC_DTO_BURST_LEN__A, fecOcDtoBurstLen);
2100                 if (status < 0)
2101                         break;
2102                 status = write16(state, FEC_OC_DTO_PERIOD__A, fecOcDtoPeriod);
2103                 if (status < 0)
2104                         break;
2105                 status = write16(state, FEC_OC_DTO_MODE__A, fecOcDtoMode);
2106                 if (status < 0)
2107                         break;
2108                 status = write16(state, FEC_OC_FCT_MODE__A, fecOcFctMode);
2109                 if (status < 0)
2110                         break;
2111                 status = write16(state, FEC_OC_MODE__A, fecOcRegMode);
2112                 if (status < 0)
2113                         break;
2114                 status = write16(state, FEC_OC_IPR_MODE__A, fecOcRegIprMode);
2115                 if (status < 0)
2116                         break;
2117
2118                 /* Rate integration settings */
2119                 status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fecOcRcnCtlRate);
2120                 if (status < 0)
2121                         break;
2122                 status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A, fecOcTmdIntUpdRate);
2123                 if (status < 0)
2124                         break;
2125                 status = write16(state, FEC_OC_TMD_MODE__A, fecOcTmdMode);
2126                 if (status < 0)
2127                         break;
2128         } while (0);
2129         return status;
2130 }
2131
2132 static int MPEGTSConfigurePolarity(struct drxk_state *state)
2133 {
2134         int status;
2135         u16 fecOcRegIprInvert = 0;
2136
2137         dprintk(1, "\n");
2138
2139         /* Data mask for the output data byte */
2140         u16 InvertDataMask =
2141             FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M |
2142             FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M |
2143             FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M |
2144             FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M;
2145
2146         /* Control selective inversion of output bits */
2147         fecOcRegIprInvert &= (~(InvertDataMask));
2148         if (state->m_invertDATA == true)
2149                 fecOcRegIprInvert |= InvertDataMask;
2150         fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MERR__M));
2151         if (state->m_invertERR == true)
2152                 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MERR__M;
2153         fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MSTRT__M));
2154         if (state->m_invertSTR == true)
2155                 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MSTRT__M;
2156         fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MVAL__M));
2157         if (state->m_invertVAL == true)
2158                 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MVAL__M;
2159         fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MCLK__M));
2160         if (state->m_invertCLK == true)
2161                 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MCLK__M;
2162         status = write16(state, FEC_OC_IPR_INVERT__A, fecOcRegIprInvert);
2163         return status;
2164 }
2165
2166 #define   SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000
2167
2168 static int SetAgcRf(struct drxk_state *state,
2169                     struct SCfgAgc *pAgcCfg, bool isDTV)
2170 {
2171         int status = 0;
2172         struct SCfgAgc *pIfAgcSettings;
2173
2174         dprintk(1, "\n");
2175
2176         if (pAgcCfg == NULL)
2177                 return -1;
2178
2179         do {
2180                 u16 data = 0;
2181
2182                 switch (pAgcCfg->ctrlMode) {
2183                 case DRXK_AGC_CTRL_AUTO:
2184
2185                         /* Enable RF AGC DAC */
2186                         status = read16(state, IQM_AF_STDBY__A, &data);
2187                         if (status < 0)
2188                                 break;
2189                         data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2190                         status = write16(state, IQM_AF_STDBY__A, data);
2191                         if (status < 0)
2192                                 break;
2193
2194                         status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2195                         if (status < 0)
2196                                 break;
2197
2198                         /* Enable SCU RF AGC loop */
2199                         data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2200
2201                         /* Polarity */
2202                         if (state->m_RfAgcPol)
2203                                 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2204                         else
2205                                 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2206                         status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2207                         if (status < 0)
2208                                 break;
2209
2210                         /* Set speed (using complementary reduction value) */
2211                         status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2212                         if (status < 0)
2213                                 break;
2214
2215                         data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M;
2216                         data |= (~(pAgcCfg->speed <<
2217                                    SCU_RAM_AGC_KI_RED_RAGC_RED__B)
2218                                  & SCU_RAM_AGC_KI_RED_RAGC_RED__M);
2219
2220                         status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2221                         if (status < 0)
2222                                 break;
2223
2224                         if (IsDVBT(state))
2225                                 pIfAgcSettings = &state->m_dvbtIfAgcCfg;
2226                         else if (IsQAM(state))
2227                                 pIfAgcSettings = &state->m_qamIfAgcCfg;
2228                         else
2229                                 pIfAgcSettings = &state->m_atvIfAgcCfg;
2230                         if (pIfAgcSettings == NULL)
2231                                 return -1;
2232
2233                         /* Set TOP, only if IF-AGC is in AUTO mode */
2234                         if (pIfAgcSettings->ctrlMode == DRXK_AGC_CTRL_AUTO)
2235                                 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->top);
2236                                 if (status < 0)
2237                                         break;
2238
2239                         /* Cut-Off current */
2240                         status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, pAgcCfg->cutOffCurrent);
2241                         if (status < 0)
2242                                 break;
2243
2244                         /* Max. output level */
2245                         status = write16(state, SCU_RAM_AGC_RF_MAX__A, pAgcCfg->maxOutputLevel);
2246                         if (status < 0)
2247                                 break;
2248
2249                         break;
2250
2251                 case DRXK_AGC_CTRL_USER:
2252                         /* Enable RF AGC DAC */
2253                         status = read16(state, IQM_AF_STDBY__A, &data);
2254                         if (status < 0)
2255                                 break;
2256                         data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2257                         status = write16(state, IQM_AF_STDBY__A, data);
2258                         if (status < 0)
2259                                 break;
2260
2261                         /* Disable SCU RF AGC loop */
2262                         status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2263                         if (status < 0)
2264                                 break;
2265                         data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2266                         if (state->m_RfAgcPol)
2267                                 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2268                         else
2269                                 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2270                         status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2271                         if (status < 0)
2272                                 break;
2273
2274                         /* SCU c.o.c. to 0, enabling full control range */
2275                         status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0);
2276                         if (status < 0)
2277                                 break;
2278
2279                         /* Write value to output pin */
2280                         status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, pAgcCfg->outputLevel);
2281                         if (status < 0)
2282                                 break;
2283                         break;
2284
2285                 case DRXK_AGC_CTRL_OFF:
2286                         /* Disable RF AGC DAC */
2287                         status = read16(state, IQM_AF_STDBY__A, &data);
2288                         if (status < 0)
2289                                 break;
2290                         data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2291                         status = write16(state, IQM_AF_STDBY__A, data);
2292                         if (status < 0)
2293                                 break;
2294
2295                         /* Disable SCU RF AGC loop */
2296                         status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2297                         if (status < 0)
2298                                 break;
2299                         data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2300                         status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2301                         if (status < 0)
2302                                 break;
2303                         break;
2304
2305                 default:
2306                         return -1;
2307
2308                 }               /* switch (agcsettings->ctrlMode) */
2309         } while (0);
2310         return status;
2311 }
2312
2313 #define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000
2314
2315 static int SetAgcIf(struct drxk_state *state,
2316                     struct SCfgAgc *pAgcCfg, bool isDTV)
2317 {
2318         u16 data = 0;
2319         int status = 0;
2320         struct SCfgAgc *pRfAgcSettings;
2321
2322         dprintk(1, "\n");
2323
2324         do {
2325                 switch (pAgcCfg->ctrlMode) {
2326                 case DRXK_AGC_CTRL_AUTO:
2327
2328                         /* Enable IF AGC DAC */
2329                         status = read16(state, IQM_AF_STDBY__A, &data);
2330                         if (status < 0)
2331                                 break;
2332                         data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2333                         status = write16(state, IQM_AF_STDBY__A, data);
2334                         if (status < 0)
2335                                 break;
2336
2337                         status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2338                         if (status < 0)
2339                                 break;
2340
2341                         /* Enable SCU IF AGC loop */
2342                         data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2343
2344                         /* Polarity */
2345                         if (state->m_IfAgcPol)
2346                                 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2347                         else
2348                                 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2349                         status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2350                         if (status < 0)
2351                                 break;
2352
2353                         /* Set speed (using complementary reduction value) */
2354                         status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2355                         if (status < 0)
2356                                 break;
2357                         data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M;
2358                         data |= (~(pAgcCfg->speed <<
2359                                    SCU_RAM_AGC_KI_RED_IAGC_RED__B)
2360                                  & SCU_RAM_AGC_KI_RED_IAGC_RED__M);
2361
2362                         status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2363                         if (status < 0)
2364                                 break;
2365
2366                         if (IsQAM(state))
2367                                 pRfAgcSettings = &state->m_qamRfAgcCfg;
2368                         else
2369                                 pRfAgcSettings = &state->m_atvRfAgcCfg;
2370                         if (pRfAgcSettings == NULL)
2371                                 return -1;
2372                         /* Restore TOP */
2373                         status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pRfAgcSettings->top);
2374                         if (status < 0)
2375                                 break;
2376                         break;
2377
2378                 case DRXK_AGC_CTRL_USER:
2379
2380                         /* Enable IF AGC DAC */
2381                         status = read16(state, IQM_AF_STDBY__A, &data);
2382                         if (status < 0)
2383                                 break;
2384                         data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2385                         status = write16(state, IQM_AF_STDBY__A, data);
2386                         if (status < 0)
2387                                 break;
2388
2389                         status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2390                         if (status < 0)
2391                                 break;
2392
2393                         /* Disable SCU IF AGC loop */
2394                         data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2395
2396                         /* Polarity */
2397                         if (state->m_IfAgcPol)
2398                                 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2399                         else
2400                                 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2401                         status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2402                         if (status < 0)
2403                                 break;
2404
2405                         /* Write value to output pin */
2406                         status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->outputLevel);
2407                         if (status < 0)
2408                                 break;
2409                         break;
2410
2411                 case DRXK_AGC_CTRL_OFF:
2412
2413                         /* Disable If AGC DAC */
2414                         status = read16(state, IQM_AF_STDBY__A, &data);
2415                         if (status < 0)
2416                                 break;
2417                         data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2418                         status = write16(state, IQM_AF_STDBY__A, data);
2419                         if (status < 0)
2420                                 break;
2421
2422                         /* Disable SCU IF AGC loop */
2423                         status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2424                         if (status < 0)
2425                                 break;
2426                         data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2427                         status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2428                         if (status < 0)
2429                                 break;
2430                         break;
2431                 }               /* switch (agcSettingsIf->ctrlMode) */
2432
2433                 /* always set the top to support
2434                    configurations without if-loop */
2435                 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, pAgcCfg->top);
2436                 if (status < 0)
2437                         break;
2438
2439
2440         } while (0);
2441         return status;
2442 }
2443
2444 static int ReadIFAgc(struct drxk_state *state, u32 *pValue)
2445 {
2446         u16 agcDacLvl;
2447         int status = read16(state, IQM_AF_AGC_IF__A, &agcDacLvl);
2448
2449         dprintk(1, "\n");
2450
2451         *pValue = 0;
2452
2453         if (status == 0) {
2454                 u16 Level = 0;
2455                 if (agcDacLvl > DRXK_AGC_DAC_OFFSET)
2456                         Level = agcDacLvl - DRXK_AGC_DAC_OFFSET;
2457                 if (Level < 14000)
2458                         *pValue = (14000 - Level) / 4;
2459                 else
2460                         *pValue = 0;
2461         }
2462         return status;
2463 }
2464
2465 static int GetQAMSignalToNoise(struct drxk_state *state,
2466                                s32 *pSignalToNoise)
2467 {
2468         int status = 0;
2469
2470         dprintk(1, "\n");
2471
2472         do {
2473                 /* MER calculation */
2474                 u16 qamSlErrPower = 0;  /* accum. error between
2475                                            raw and sliced symbols */
2476                 u32 qamSlSigPower = 0;  /* used for MER, depends of
2477                                            QAM constellation */
2478                 u32 qamSlMer = 0;       /* QAM MER */
2479
2480                 /* get the register value needed for MER */
2481                 status = read16(state, QAM_SL_ERR_POWER__A, &qamSlErrPower);
2482                 if (status < 0)
2483                         break;
2484
2485                 switch (state->param.u.qam.modulation) {
2486                 case QAM_16:
2487                         qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM16 << 2;
2488                         break;
2489                 case QAM_32:
2490                         qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM32 << 2;
2491                         break;
2492                 case QAM_64:
2493                         qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM64 << 2;
2494                         break;
2495                 case QAM_128:
2496                         qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM128 << 2;
2497                         break;
2498                 default:
2499                 case QAM_256:
2500                         qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM256 << 2;
2501                         break;
2502                 }
2503
2504                 if (qamSlErrPower > 0) {
2505                         qamSlMer = Log10Times100(qamSlSigPower) -
2506                             Log10Times100((u32) qamSlErrPower);
2507                 }
2508                 *pSignalToNoise = qamSlMer;
2509         } while (0);
2510         return status;
2511 }
2512
2513 static int GetDVBTSignalToNoise(struct drxk_state *state,
2514                                 s32 *pSignalToNoise)
2515 {
2516         int status = 0;
2517
2518         u16 regData = 0;
2519         u32 EqRegTdSqrErrI = 0;
2520         u32 EqRegTdSqrErrQ = 0;
2521         u16 EqRegTdSqrErrExp = 0;
2522         u16 EqRegTdTpsPwrOfs = 0;
2523         u16 EqRegTdReqSmbCnt = 0;
2524         u32 tpsCnt = 0;
2525         u32 SqrErrIQ = 0;
2526         u32 a = 0;
2527         u32 b = 0;
2528         u32 c = 0;
2529         u32 iMER = 0;
2530         u16 transmissionParams = 0;
2531
2532         dprintk(1, "\n");
2533         do {
2534                 status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, &EqRegTdTpsPwrOfs);
2535                 if (status < 0)
2536                         break;
2537                 status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, &EqRegTdReqSmbCnt);
2538                 if (status < 0)
2539                         break;
2540                 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, &EqRegTdSqrErrExp);
2541                 if (status < 0)
2542                         break;
2543                 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, &regData);
2544                 if (status < 0)
2545                         break;
2546                 /* Extend SQR_ERR_I operational range */
2547                 EqRegTdSqrErrI = (u32) regData;
2548                 if ((EqRegTdSqrErrExp > 11) &&
2549                     (EqRegTdSqrErrI < 0x00000FFFUL)) {
2550                         EqRegTdSqrErrI += 0x00010000UL;
2551                 }
2552                 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, &regData);
2553                 if (status < 0)
2554                         break;
2555                 /* Extend SQR_ERR_Q operational range */
2556                 EqRegTdSqrErrQ = (u32) regData;
2557                 if ((EqRegTdSqrErrExp > 11) &&
2558                     (EqRegTdSqrErrQ < 0x00000FFFUL))
2559                         EqRegTdSqrErrQ += 0x00010000UL;
2560
2561                 status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A, &transmissionParams);
2562                 if (status < 0)
2563                         break;
2564
2565                 /* Check input data for MER */
2566
2567                 /* MER calculation (in 0.1 dB) without math.h */
2568                 if ((EqRegTdTpsPwrOfs == 0) || (EqRegTdReqSmbCnt == 0))
2569                         iMER = 0;
2570                 else if ((EqRegTdSqrErrI + EqRegTdSqrErrQ) == 0) {
2571                         /* No error at all, this must be the HW reset value
2572                          * Apparently no first measurement yet
2573                          * Set MER to 0.0 */
2574                         iMER = 0;
2575                 } else {
2576                         SqrErrIQ = (EqRegTdSqrErrI + EqRegTdSqrErrQ) <<
2577                             EqRegTdSqrErrExp;
2578                         if ((transmissionParams &
2579                              OFDM_SC_RA_RAM_OP_PARAM_MODE__M)
2580                             == OFDM_SC_RA_RAM_OP_PARAM_MODE_2K)
2581                                 tpsCnt = 17;
2582                         else
2583                                 tpsCnt = 68;
2584
2585                         /* IMER = 100 * log10 (x)
2586                            where x = (EqRegTdTpsPwrOfs^2 *
2587                            EqRegTdReqSmbCnt * tpsCnt)/SqrErrIQ
2588
2589                            => IMER = a + b -c
2590                            where a = 100 * log10 (EqRegTdTpsPwrOfs^2)
2591                            b = 100 * log10 (EqRegTdReqSmbCnt * tpsCnt)
2592                            c = 100 * log10 (SqrErrIQ)
2593                          */
2594
2595                         /* log(x) x = 9bits * 9bits->18 bits  */
2596                         a = Log10Times100(EqRegTdTpsPwrOfs *
2597                                           EqRegTdTpsPwrOfs);
2598                         /* log(x) x = 16bits * 7bits->23 bits  */
2599                         b = Log10Times100(EqRegTdReqSmbCnt * tpsCnt);
2600                         /* log(x) x = (16bits + 16bits) << 15 ->32 bits  */
2601                         c = Log10Times100(SqrErrIQ);
2602
2603                         iMER = a + b;
2604                         /* No negative MER, clip to zero */
2605                         if (iMER > c)
2606                                 iMER -= c;
2607                         else
2608                                 iMER = 0;
2609                 }
2610                 *pSignalToNoise = iMER;
2611         } while (0);
2612
2613         return status;
2614 }
2615
2616 static int GetSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise)
2617 {
2618         dprintk(1, "\n");
2619
2620         *pSignalToNoise = 0;
2621         switch (state->m_OperationMode) {
2622         case OM_DVBT:
2623                 return GetDVBTSignalToNoise(state, pSignalToNoise);
2624         case OM_QAM_ITU_A:
2625         case OM_QAM_ITU_C:
2626                 return GetQAMSignalToNoise(state, pSignalToNoise);
2627         default:
2628                 break;
2629         }
2630         return 0;
2631 }
2632
2633 #if 0
2634 static int GetDVBTQuality(struct drxk_state *state, s32 *pQuality)
2635 {
2636         /* SNR Values for quasi errorfree reception rom Nordig 2.2 */
2637         int status = 0;
2638
2639         dprintk(1, "\n");
2640
2641         static s32 QE_SN[] = {
2642                 51,             /* QPSK 1/2 */
2643                 69,             /* QPSK 2/3 */
2644                 79,             /* QPSK 3/4 */
2645                 89,             /* QPSK 5/6 */
2646                 97,             /* QPSK 7/8 */
2647                 108,            /* 16-QAM 1/2 */
2648                 131,            /* 16-QAM 2/3 */
2649                 146,            /* 16-QAM 3/4 */
2650                 156,            /* 16-QAM 5/6 */
2651                 160,            /* 16-QAM 7/8 */
2652                 165,            /* 64-QAM 1/2 */
2653                 187,            /* 64-QAM 2/3 */
2654                 202,            /* 64-QAM 3/4 */
2655                 216,            /* 64-QAM 5/6 */
2656                 225,            /* 64-QAM 7/8 */
2657         };
2658
2659         *pQuality = 0;
2660
2661         do {
2662                 s32 SignalToNoise = 0;
2663                 u16 Constellation = 0;
2664                 u16 CodeRate = 0;
2665                 u32 SignalToNoiseRel;
2666                 u32 BERQuality;
2667
2668                 status = GetDVBTSignalToNoise(state, &SignalToNoise);
2669                 if (status < 0)
2670                         break;
2671                 status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A, &Constellation);
2672                 if (status < 0)
2673                         break;
2674                 Constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M;
2675
2676                 status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A, &CodeRate);
2677                 if (status < 0)
2678                         break;
2679                 CodeRate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M;
2680
2681                 if (Constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM ||
2682                     CodeRate > OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8)
2683                         break;
2684                 SignalToNoiseRel = SignalToNoise -
2685                     QE_SN[Constellation * 5 + CodeRate];
2686                 BERQuality = 100;
2687
2688                 if (SignalToNoiseRel < -70)
2689                         *pQuality = 0;
2690                 else if (SignalToNoiseRel < 30)
2691                         *pQuality = ((SignalToNoiseRel + 70) *
2692                                      BERQuality) / 100;
2693                 else
2694                         *pQuality = BERQuality;
2695         } while (0);
2696         return 0;
2697 };
2698
2699 static int GetDVBCQuality(struct drxk_state *state, s32 *pQuality)
2700 {
2701         int status = 0;
2702         *pQuality = 0;
2703
2704         dprintk(1, "\n");
2705
2706         do {
2707                 u32 SignalToNoise = 0;
2708                 u32 BERQuality = 100;
2709                 u32 SignalToNoiseRel = 0;
2710
2711                 status = GetQAMSignalToNoise(state, &SignalToNoise);
2712                 if (status < 0)
2713                         break;
2714
2715                 switch (state->param.u.qam.modulation) {
2716                 case QAM_16:
2717                         SignalToNoiseRel = SignalToNoise - 200;
2718                         break;
2719                 case QAM_32:
2720                         SignalToNoiseRel = SignalToNoise - 230;
2721                         break;  /* Not in NorDig */
2722                 case QAM_64:
2723                         SignalToNoiseRel = SignalToNoise - 260;
2724                         break;
2725                 case QAM_128:
2726                         SignalToNoiseRel = SignalToNoise - 290;
2727                         break;
2728                 default:
2729                 case QAM_256:
2730                         SignalToNoiseRel = SignalToNoise - 320;
2731                         break;
2732                 }
2733
2734                 if (SignalToNoiseRel < -70)
2735                         *pQuality = 0;
2736                 else if (SignalToNoiseRel < 30)
2737                         *pQuality = ((SignalToNoiseRel + 70) *
2738                                      BERQuality) / 100;
2739                 else
2740                         *pQuality = BERQuality;
2741         } while (0);
2742
2743         return status;
2744 }
2745
2746 static int GetQuality(struct drxk_state *state, s32 *pQuality)
2747 {
2748         dprintk(1, "\n");
2749
2750         switch (state->m_OperationMode) {
2751         case OM_DVBT:
2752                 return GetDVBTQuality(state, pQuality);
2753         case OM_QAM_ITU_A:
2754                 return GetDVBCQuality(state, pQuality);
2755         default:
2756                 break;
2757         }
2758
2759         return 0;
2760 }
2761 #endif
2762
2763 /* Free data ram in SIO HI */
2764 #define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040
2765 #define SIO_HI_RA_RAM_USR_END__A   0x420060
2766
2767 #define DRXK_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A)
2768 #define DRXK_HI_ATOMIC_BUF_END   (SIO_HI_RA_RAM_USR_BEGIN__A + 7)
2769 #define DRXK_HI_ATOMIC_READ      SIO_HI_RA_RAM_PAR_3_ACP_RW_READ
2770 #define DRXK_HI_ATOMIC_WRITE     SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE
2771
2772 #define DRXDAP_FASI_ADDR2BLOCK(addr)  (((addr) >> 22) & 0x3F)
2773 #define DRXDAP_FASI_ADDR2BANK(addr)   (((addr) >> 16) & 0x3F)
2774 #define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr) & 0x7FFF)
2775
2776 static int ConfigureI2CBridge(struct drxk_state *state, bool bEnableBridge)
2777 {
2778         int status;
2779
2780         dprintk(1, "\n");
2781
2782         if (state->m_DrxkState == DRXK_UNINITIALIZED)
2783                 return -1;
2784         if (state->m_DrxkState == DRXK_POWERED_DOWN)
2785                 return -1;
2786
2787         do {
2788                 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
2789                 if (status < 0)
2790                         break;
2791                 if (bEnableBridge) {
2792                         status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED);
2793                         if (status < 0)
2794                                 break;
2795                 } else {
2796                         status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN);
2797                         if (status < 0)
2798                                 break;
2799                 }
2800
2801                 status = HI_Command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, 0);
2802                 if (status < 0)
2803                         break;
2804         } while (0);
2805         return status;
2806 }
2807
2808 static int SetPreSaw(struct drxk_state *state,
2809                      struct SCfgPreSaw *pPreSawCfg)
2810 {
2811         int status;
2812
2813         dprintk(1, "\n");
2814
2815         if ((pPreSawCfg == NULL)
2816             || (pPreSawCfg->reference > IQM_AF_PDREF__M))
2817                 return -1;
2818
2819         status = write16(state, IQM_AF_PDREF__A, pPreSawCfg->reference);
2820         return status;
2821 }
2822
2823 static int BLDirectCmd(struct drxk_state *state, u32 targetAddr,
2824                        u16 romOffset, u16 nrOfElements, u32 timeOut)
2825 {
2826         u16 blStatus = 0;
2827         u16 offset = (u16) ((targetAddr >> 0) & 0x00FFFF);
2828         u16 blockbank = (u16) ((targetAddr >> 16) & 0x000FFF);
2829         int status;
2830         unsigned long end;
2831
2832         dprintk(1, "\n");
2833
2834         mutex_lock(&state->mutex);
2835         do {
2836                 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT);
2837                 if (status < 0)
2838                         break;
2839                 status = write16(state, SIO_BL_TGT_HDR__A, blockbank);
2840                 if (status < 0)
2841                         break;
2842                 status = write16(state, SIO_BL_TGT_ADDR__A, offset);
2843                 if (status < 0)
2844                         break;
2845                 status = write16(state, SIO_BL_SRC_ADDR__A, romOffset);
2846                 if (status < 0)
2847                         break;
2848                 status = write16(state, SIO_BL_SRC_LEN__A, nrOfElements);
2849                 if (status < 0)
2850                         break;
2851                 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
2852                 if (status < 0)
2853                         break;
2854
2855                 end = jiffies + msecs_to_jiffies(timeOut);
2856                 do {
2857                         status = read16(state, SIO_BL_STATUS__A, &blStatus);
2858                         if (status < 0)
2859                                 break;
2860                 } while ((blStatus == 0x1) && time_is_after_jiffies(end));
2861                 if (blStatus == 0x1) {
2862                         printk(KERN_ERR "drxk: SIO not ready\n");
2863                         mutex_unlock(&state->mutex);
2864                         return -1;
2865                 }
2866         } while (0);
2867         mutex_unlock(&state->mutex);
2868         return status;
2869
2870 }
2871
2872 static int ADCSyncMeasurement(struct drxk_state *state, u16 *count)
2873 {
2874         u16 data = 0;
2875         int status;
2876
2877         dprintk(1, "\n");
2878
2879         do {
2880                 /* Start measurement */
2881                 status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE);
2882                 if (status < 0)
2883                         break;
2884                 status = write16(state, IQM_AF_START_LOCK__A, 1);
2885                 if (status < 0)
2886                         break;
2887
2888                 *count = 0;
2889                 status = read16(state, IQM_AF_PHASE0__A, &data);
2890                 if (status < 0)
2891                         break;
2892                 if (data == 127)
2893                         *count = *count + 1;
2894                 status = read16(state, IQM_AF_PHASE1__A, &data);
2895                 if (status < 0)
2896                         break;
2897                 if (data == 127)
2898                         *count = *count + 1;
2899                 status = read16(state, IQM_AF_PHASE2__A, &data);
2900                 if (status < 0)
2901                         break;
2902                 if (data == 127)
2903                         *count = *count + 1;
2904         } while (0);
2905         return status;
2906 }
2907
2908 static int ADCSynchronization(struct drxk_state *state)
2909 {
2910         u16 count = 0;
2911         int status;
2912
2913         dprintk(1, "\n");
2914
2915         do {
2916                 status = ADCSyncMeasurement(state, &count);
2917                 if (status < 0)
2918                         break;
2919
2920                 if (count == 1) {
2921                         /* Try sampling on a diffrent edge */
2922                         u16 clkNeg = 0;
2923
2924                         status = read16(state, IQM_AF_CLKNEG__A, &clkNeg);
2925                         if (status < 0)
2926                                 break;
2927                         if ((clkNeg | IQM_AF_CLKNEG_CLKNEGDATA__M) ==
2928                             IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) {
2929                                 clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2930                                 clkNeg |=
2931                                     IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG;
2932                         } else {
2933                                 clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2934                                 clkNeg |=
2935                                     IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS;
2936                         }
2937                         status = write16(state, IQM_AF_CLKNEG__A, clkNeg);
2938                         if (status < 0)
2939                                 break;
2940                         status = ADCSyncMeasurement(state, &count);
2941                         if (status < 0)
2942                                 break;
2943                 }
2944
2945                 if (count < 2)
2946                         status = -1;
2947         } while (0);
2948         return status;
2949 }
2950
2951 static int SetFrequencyShifter(struct drxk_state *state,
2952                                u16 intermediateFreqkHz,
2953                                s32 tunerFreqOffset, bool isDTV)
2954 {
2955         bool selectPosImage = false;
2956         u32 rfFreqResidual = tunerFreqOffset;
2957         u32 fmFrequencyShift = 0;
2958         bool tunerMirror = !state->m_bMirrorFreqSpect;
2959         u32 adcFreq;
2960         bool adcFlip;
2961         int status;
2962         u32 ifFreqActual;
2963         u32 samplingFrequency = (u32) (state->m_sysClockFreq / 3);
2964         u32 frequencyShift;
2965         bool imageToSelect;
2966
2967         dprintk(1, "\n");
2968
2969         /*
2970            Program frequency shifter
2971            No need to account for mirroring on RF
2972          */
2973         if (isDTV) {
2974                 if ((state->m_OperationMode == OM_QAM_ITU_A) ||
2975                     (state->m_OperationMode == OM_QAM_ITU_C) ||
2976                     (state->m_OperationMode == OM_DVBT))
2977                         selectPosImage = true;
2978                 else
2979                         selectPosImage = false;
2980         }
2981         if (tunerMirror)
2982                 /* tuner doesn't mirror */
2983                 ifFreqActual = intermediateFreqkHz +
2984                     rfFreqResidual + fmFrequencyShift;
2985         else
2986                 /* tuner mirrors */
2987                 ifFreqActual = intermediateFreqkHz -
2988                     rfFreqResidual - fmFrequencyShift;
2989         if (ifFreqActual > samplingFrequency / 2) {
2990                 /* adc mirrors */
2991                 adcFreq = samplingFrequency - ifFreqActual;
2992                 adcFlip = true;
2993         } else {
2994                 /* adc doesn't mirror */
2995                 adcFreq = ifFreqActual;
2996                 adcFlip = false;
2997         }
2998
2999         frequencyShift = adcFreq;
3000         imageToSelect = state->m_rfmirror ^ tunerMirror ^
3001             adcFlip ^ selectPosImage;
3002         state->m_IqmFsRateOfs =
3003             Frac28a((frequencyShift), samplingFrequency);
3004
3005         if (imageToSelect)
3006                 state->m_IqmFsRateOfs = ~state->m_IqmFsRateOfs + 1;
3007
3008         /* Program frequency shifter with tuner offset compensation */
3009         /* frequencyShift += tunerFreqOffset; TODO */
3010         status = write32(state, IQM_FS_RATE_OFS_LO__A,
3011                          state->m_IqmFsRateOfs);
3012         return status;
3013 }
3014
3015 static int InitAGC(struct drxk_state *state, bool isDTV)
3016 {
3017         u16 ingainTgt = 0;
3018         u16 ingainTgtMin = 0;
3019         u16 ingainTgtMax = 0;
3020         u16 clpCyclen = 0;
3021         u16 clpSumMin = 0;
3022         u16 clpDirTo = 0;
3023         u16 snsSumMin = 0;
3024         u16 snsSumMax = 0;
3025         u16 clpSumMax = 0;
3026         u16 snsDirTo = 0;
3027         u16 kiInnergainMin = 0;
3028         u16 ifIaccuHiTgt = 0;
3029         u16 ifIaccuHiTgtMin = 0;
3030         u16 ifIaccuHiTgtMax = 0;
3031         u16 data = 0;
3032         u16 fastClpCtrlDelay = 0;
3033         u16 clpCtrlMode = 0;
3034         int status = 0;
3035
3036         dprintk(1, "\n");
3037
3038         do {
3039                 /* Common settings */
3040                 snsSumMax = 1023;
3041                 ifIaccuHiTgtMin = 2047;
3042                 clpCyclen = 500;
3043                 clpSumMax = 1023;
3044
3045                 if (IsQAM(state)) {
3046                         /* Standard specific settings */
3047                         clpSumMin = 8;
3048                         clpDirTo = (u16) -9;
3049                         clpCtrlMode = 0;
3050                         snsSumMin = 8;
3051                         snsDirTo = (u16) -9;
3052                         kiInnergainMin = (u16) -1030;
3053                 } else
3054                         status = -1;
3055                 status = (status);
3056                 if (status < 0)
3057                         break;
3058                 if (IsQAM(state)) {
3059                         ifIaccuHiTgtMax = 0x2380;
3060                         ifIaccuHiTgt = 0x2380;
3061                         ingainTgtMin = 0x0511;
3062                         ingainTgt = 0x0511;
3063                         ingainTgtMax = 5119;
3064                         fastClpCtrlDelay =
3065                             state->m_qamIfAgcCfg.FastClipCtrlDelay;
3066                 } else {
3067                         ifIaccuHiTgtMax = 0x1200;
3068                         ifIaccuHiTgt = 0x1200;
3069                         ingainTgtMin = 13424;
3070                         ingainTgt = 13424;
3071                         ingainTgtMax = 30000;
3072                         fastClpCtrlDelay =
3073                             state->m_dvbtIfAgcCfg.FastClipCtrlDelay;
3074                 }
3075                 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, fastClpCtrlDelay);
3076                 if (status < 0)
3077                         break;
3078
3079                 status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clpCtrlMode);
3080                 if (status < 0)
3081                         break;
3082                 status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingainTgt);
3083                 if (status < 0)
3084                         break;
3085                 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingainTgtMin);
3086                 if (status < 0)
3087                         break;
3088                 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingainTgtMax);
3089                 if (status < 0)
3090                         break;
3091                 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, ifIaccuHiTgtMin);
3092                 if (status < 0)
3093                         break;
3094                 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, ifIaccuHiTgtMax);
3095                 if (status < 0)
3096                         break;
3097                 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0);
3098                 if (status < 0)
3099                         break;
3100                 status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0);
3101                 if (status < 0)
3102                         break;
3103                 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0);
3104                 if (status < 0)
3105                         break;
3106                 status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0);
3107                 if (status < 0)
3108                         break;
3109                 status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clpSumMax);
3110                 if (status < 0)
3111                         break;
3112                 status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, snsSumMax);
3113                 if (status < 0)
3114                         break;
3115
3116                 status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, kiInnergainMin);
3117                 if (status < 0)
3118                         break;
3119                 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, ifIaccuHiTgt);
3120                 if (status < 0)
3121                         break;
3122                 status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clpCyclen);
3123                 if (status < 0)
3124                         break;
3125
3126                 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023);
3127                 if (status < 0)
3128                         break;
3129                 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023);
3130                 if (status < 0)
3131                         break;
3132                 status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50);
3133                 if (status < 0)
3134                         break;
3135
3136                 status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20);
3137                 if (status < 0)
3138                         break;
3139                 status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clpSumMin);
3140                 if (status < 0)
3141                         break;
3142                 status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, snsSumMin);
3143                 if (status < 0)
3144                         break;
3145                 status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clpDirTo);
3146                 if (status < 0)
3147                         break;
3148                 status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, snsDirTo);
3149                 if (status < 0)
3150                         break;
3151                 status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff);
3152                 if (status < 0)
3153                         break;
3154                 status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0);
3155                 if (status < 0)
3156                         break;
3157                 status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117);
3158                 if (status < 0)
3159                         break;
3160                 status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657);
3161                 if (status < 0)
3162                         break;
3163                 status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0);
3164                 if (status < 0)
3165                         break;
3166                 status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0);
3167                 if (status < 0)
3168                         break;
3169                 status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0);
3170                 if (status < 0)
3171                         break;
3172                 status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1);
3173                 if (status < 0)
3174                         break;
3175                 status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0);
3176                 if (status < 0)
3177                         break;
3178                 status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0);
3179                 if (status < 0)
3180                         break;
3181                 status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0);
3182                 if (status < 0)
3183                         break;
3184                 status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1);
3185                 if (status < 0)
3186                         break;
3187                 status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500);
3188                 if (status < 0)
3189                         break;
3190                 status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500);
3191                 if (status < 0)
3192                         break;
3193
3194                 /* Initialize inner-loop KI gain factors */
3195                 status = read16(state, SCU_RAM_AGC_KI__A, &data);
3196                 if (status < 0)
3197                         break;
3198                 if (IsQAM(state)) {
3199                         data = 0x0657;
3200                         data &= ~SCU_RAM_AGC_KI_RF__M;
3201                         data |= (DRXK_KI_RAGC_QAM << SCU_RAM_AGC_KI_RF__B);
3202                         data &= ~SCU_RAM_AGC_KI_IF__M;
3203                         data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B);
3204                 }
3205                 status = write16(state, SCU_RAM_AGC_KI__A, data);
3206                 if (status < 0)
3207                         break;
3208         } while (0);
3209         return status;
3210 }
3211
3212 static int DVBTQAMGetAccPktErr(struct drxk_state *state, u16 *packetErr)
3213 {
3214         int status;
3215
3216         dprintk(1, "\n");
3217         do {
3218                 if (packetErr == NULL) {
3219                         status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
3220                         if (status < 0)
3221                                 break;
3222                 } else {
3223                         status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, packetErr);
3224                         if (status < 0)
3225                                 break;
3226                 }
3227         } while (0);
3228         return status;
3229 }
3230
3231 static int DVBTScCommand(struct drxk_state *state,
3232                          u16 cmd, u16 subcmd,
3233                          u16 param0, u16 param1, u16 param2,
3234                          u16 param3, u16 param4)
3235 {
3236         u16 curCmd = 0;
3237         u16 errCode = 0;
3238         u16 retryCnt = 0;
3239         u16 scExec = 0;
3240         int status;
3241
3242         dprintk(1, "\n");
3243         status = read16(state, OFDM_SC_COMM_EXEC__A, &scExec);
3244         if (scExec != 1) {
3245                 /* SC is not running */
3246                 return -1;
3247         }
3248
3249         /* Wait until sc is ready to receive command */
3250         retryCnt = 0;
3251         do {
3252                 msleep(1);
3253                 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd);
3254                 retryCnt++;
3255         } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES));
3256         if (retryCnt >= DRXK_MAX_RETRIES)
3257                 return -1;
3258         /* Write sub-command */
3259         switch (cmd) {
3260                 /* All commands using sub-cmd */
3261         case OFDM_SC_RA_RAM_CMD_PROC_START:
3262         case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3263         case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3264                 status =
3265                     write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd);
3266                 break;
3267         default:
3268                 /* Do nothing */
3269                 break;
3270         }                       /* switch (cmd->cmd) */
3271
3272         /* Write needed parameters and the command */
3273         switch (cmd) {
3274                 /* All commands using 5 parameters */
3275                 /* All commands using 4 parameters */
3276                 /* All commands using 3 parameters */
3277                 /* All commands using 2 parameters */
3278         case OFDM_SC_RA_RAM_CMD_PROC_START:
3279         case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3280         case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3281                 status =
3282                     write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1);
3283                 /* All commands using 1 parameters */
3284         case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3285         case OFDM_SC_RA_RAM_CMD_USER_IO:
3286                 status =
3287                     write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0);
3288                 /* All commands using 0 parameters */
3289         case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3290         case OFDM_SC_RA_RAM_CMD_NULL:
3291                 /* Write command */
3292                 status = write16(state, OFDM_SC_RA_RAM_CMD__A, cmd);
3293                 break;
3294         default:
3295                 /* Unknown command */
3296                 return -EINVAL;
3297         }                       /* switch (cmd->cmd) */
3298
3299         /* Wait until sc is ready processing command */
3300         retryCnt = 0;
3301         do {
3302                 msleep(1);
3303                 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd);
3304                 retryCnt++;
3305         } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES));
3306         if (retryCnt >= DRXK_MAX_RETRIES)
3307                 return -1;
3308
3309         /* Check for illegal cmd */
3310         status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &errCode);
3311         if (errCode == 0xFFFF) {
3312                 /* illegal command */
3313                 return -EINVAL;
3314         }
3315
3316         /* Retreive results parameters from SC */
3317         switch (cmd) {
3318                 /* All commands yielding 5 results */
3319                 /* All commands yielding 4 results */
3320                 /* All commands yielding 3 results */
3321                 /* All commands yielding 2 results */
3322                 /* All commands yielding 1 result */
3323         case OFDM_SC_RA_RAM_CMD_USER_IO:
3324         case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3325                 status =
3326                     read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0));
3327                 /* All commands yielding 0 results */
3328         case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3329         case OFDM_SC_RA_RAM_CMD_SET_TIMER:
3330         case OFDM_SC_RA_RAM_CMD_PROC_START:
3331         case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3332         case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3333         case OFDM_SC_RA_RAM_CMD_NULL:
3334                 break;
3335         default:
3336                 /* Unknown command */
3337                 return -EINVAL;
3338                 break;
3339         }                       /* switch (cmd->cmd) */
3340         return status;
3341 }
3342
3343 static int PowerUpDVBT(struct drxk_state *state)
3344 {
3345         enum DRXPowerMode powerMode = DRX_POWER_UP;
3346         int status;
3347
3348         dprintk(1, "\n");
3349         do {
3350                 status = CtrlPowerMode(state, &powerMode);
3351                 if (status < 0)
3352                         break;
3353         } while (0);
3354         return status;
3355 }
3356
3357 static int DVBTCtrlSetIncEnable(struct drxk_state *state, bool *enabled)
3358 {
3359         int status;
3360
3361         dprintk(1, "\n");
3362         if (*enabled == true)
3363                 status = write16(state, IQM_CF_BYPASSDET__A, 0);
3364         else
3365                 status = write16(state, IQM_CF_BYPASSDET__A, 1);
3366
3367         return status;
3368 }
3369
3370 #define DEFAULT_FR_THRES_8K     4000
3371 static int DVBTCtrlSetFrEnable(struct drxk_state *state, bool *enabled)
3372 {
3373
3374         int status;
3375
3376         dprintk(1, "\n");
3377         if (*enabled == true) {
3378                 /* write mask to 1 */
3379                 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A,
3380                                    DEFAULT_FR_THRES_8K);
3381         } else {
3382                 /* write mask to 0 */
3383                 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0);
3384         }
3385
3386         return status;
3387 }
3388
3389 static int DVBTCtrlSetEchoThreshold(struct drxk_state *state,
3390                                     struct DRXKCfgDvbtEchoThres_t *echoThres)
3391 {
3392         u16 data = 0;
3393         int status;
3394
3395         dprintk(1, "\n");
3396         do {
3397                 status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data);
3398                 if (status < 0)
3399                         break;
3400
3401                 switch (echoThres->fftMode) {
3402                 case DRX_FFTMODE_2K:
3403                         data &= ~OFDM_SC_RA_RAM_ECHO_THRES_2K__M;
3404                         data |=
3405                             ((echoThres->threshold <<
3406                               OFDM_SC_RA_RAM_ECHO_THRES_2K__B)
3407                              & (OFDM_SC_RA_RAM_ECHO_THRES_2K__M));
3408                         break;
3409                 case DRX_FFTMODE_8K:
3410                         data &= ~OFDM_SC_RA_RAM_ECHO_THRES_8K__M;
3411                         data |=
3412                             ((echoThres->threshold <<
3413                               OFDM_SC_RA_RAM_ECHO_THRES_8K__B)
3414                              & (OFDM_SC_RA_RAM_ECHO_THRES_8K__M));
3415                         break;
3416                 default:
3417                         return -1;
3418                         break;
3419                 }
3420
3421                 status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data);
3422                 if (status < 0)
3423                         break;
3424         } while (0);
3425
3426         return status;
3427 }
3428
3429 static int DVBTCtrlSetSqiSpeed(struct drxk_state *state,
3430                                enum DRXKCfgDvbtSqiSpeed *speed)
3431 {
3432         int status;
3433
3434         dprintk(1, "\n");
3435
3436         switch (*speed) {
3437         case DRXK_DVBT_SQI_SPEED_FAST:
3438         case DRXK_DVBT_SQI_SPEED_MEDIUM:
3439         case DRXK_DVBT_SQI_SPEED_SLOW:
3440                 break;
3441         default:
3442                 return -EINVAL;
3443         }
3444         status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A,
3445                            (u16) *speed);
3446         return status;
3447 }
3448
3449 /*============================================================================*/
3450
3451 /**
3452 * \brief Activate DVBT specific presets
3453 * \param demod instance of demodulator.
3454 * \return DRXStatus_t.
3455 *
3456 * Called in DVBTSetStandard
3457 *
3458 */
3459 static int DVBTActivatePresets(struct drxk_state *state)
3460 {
3461         int status;
3462
3463         struct DRXKCfgDvbtEchoThres_t echoThres2k = { 0, DRX_FFTMODE_2K };
3464         struct DRXKCfgDvbtEchoThres_t echoThres8k = { 0, DRX_FFTMODE_8K };
3465
3466         dprintk(1, "\n");
3467         do {
3468                 bool setincenable = false;
3469                 bool setfrenable = true;
3470                 status = DVBTCtrlSetIncEnable(state, &setincenable);
3471                 if (status < 0)
3472                         break;
3473                 status = DVBTCtrlSetFrEnable(state, &setfrenable);
3474                 if (status < 0)
3475                         break;
3476                 status = DVBTCtrlSetEchoThreshold(state, &echoThres2k);
3477                 if (status < 0)
3478                         break;
3479                 status = DVBTCtrlSetEchoThreshold(state, &echoThres8k);
3480                 if (status < 0)
3481                         break;
3482                 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, state->m_dvbtIfAgcCfg.IngainTgtMax);
3483                 if (status < 0)
3484                         break;
3485         } while (0);
3486
3487         return status;
3488 }
3489
3490 /*============================================================================*/
3491
3492 /**
3493 * \brief Initialize channelswitch-independent settings for DVBT.
3494 * \param demod instance of demodulator.
3495 * \return DRXStatus_t.
3496 *
3497 * For ROM code channel filter taps are loaded from the bootloader. For microcode
3498 * the DVB-T taps from the drxk_filters.h are used.
3499 */
3500 static int SetDVBTStandard(struct drxk_state *state,
3501                            enum OperationMode oMode)
3502 {
3503         u16 cmdResult = 0;
3504         u16 data = 0;
3505         int status;
3506
3507         dprintk(1, "\n");
3508
3509         PowerUpDVBT(state);
3510         do {
3511                 /* added antenna switch */
3512                 SwitchAntennaToDVBT(state);
3513                 /* send OFDM reset command */
3514                 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
3515                 if (status < 0)
3516                         break;
3517
3518                 /* send OFDM setenv command */
3519                 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 0, NULL, 1, &cmdResult);
3520                 if (status < 0)
3521                         break;
3522
3523                 /* reset datapath for OFDM, processors first */
3524                 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3525                 if (status < 0)
3526                         break;
3527                 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3528                 if (status < 0)
3529                         break;
3530                 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
3531                 if (status < 0)
3532                         break;
3533
3534                 /* IQM setup */
3535                 /* synchronize on ofdstate->m_festart */
3536                 status = write16(state, IQM_AF_UPD_SEL__A, 1);
3537                 if (status < 0)
3538                         break;
3539                 /* window size for clipping ADC detection */
3540                 status = write16(state, IQM_AF_CLP_LEN__A, 0);
3541                 if (status < 0)
3542                         break;
3543                 /* window size for for sense pre-SAW detection */
3544                 status = write16(state, IQM_AF_SNS_LEN__A, 0);
3545                 if (status < 0)
3546                         break;
3547                 /* sense threshold for sense pre-SAW detection */
3548                 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
3549                 if (status < 0)
3550                         break;
3551                 status = SetIqmAf(state, true);
3552                 if (status < 0)
3553                         break;
3554
3555                 status = write16(state, IQM_AF_AGC_RF__A, 0);
3556                 if (status < 0)
3557                         break;
3558
3559                 /* Impulse noise cruncher setup */
3560                 status = write16(state, IQM_AF_INC_LCT__A, 0);  /* crunch in IQM_CF */
3561                 if (status < 0)
3562                         break;
3563                 status = write16(state, IQM_CF_DET_LCT__A, 0);  /* detect in IQM_CF */
3564                 if (status < 0)
3565                         break;
3566                 status = write16(state, IQM_CF_WND_LEN__A, 3);  /* peak detector window length */
3567                 if (status < 0)
3568                         break;
3569
3570                 status = write16(state, IQM_RC_STRETCH__A, 16);
3571                 if (status < 0)
3572                         break;
3573                 status = write16(state, IQM_CF_OUT_ENA__A, 0x4);        /* enable output 2 */
3574                 if (status < 0)
3575                         break;
3576                 status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */
3577                 if (status < 0)
3578                         break;
3579                 status = write16(state, IQM_CF_SCALE__A, 1600);
3580                 if (status < 0)
3581                         break;
3582                 status = write16(state, IQM_CF_SCALE_SH__A, 0);
3583                 if (status < 0)
3584                         break;
3585
3586                 /* virtual clipping threshold for clipping ADC detection */
3587                 status = write16(state, IQM_AF_CLP_TH__A, 448);
3588                 if (status < 0)
3589                         break;
3590                 status = write16(state, IQM_CF_DATATH__A, 495); /* crunching threshold */
3591                 if (status < 0)
3592                         break;
3593
3594                 status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
3595                 if (status < 0)
3596                         break;
3597
3598                 status = write16(state, IQM_CF_PKDTH__A, 2);    /* peak detector threshold */
3599                 if (status < 0)
3600                         break;
3601                 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2);
3602                 if (status < 0)
3603                         break;
3604                 /* enable power measurement interrupt */
3605                 status = write16(state, IQM_CF_COMM_INT_MSK__A, 1);
3606                 if (status < 0)
3607                         break;
3608                 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
3609                 if (status < 0)
3610                         break;
3611
3612                 /* IQM will not be reset from here, sync ADC and update/init AGC */
3613                 status = ADCSynchronization(state);
3614                 if (status < 0)
3615                         break;
3616                 status = SetPreSaw(state, &state->m_dvbtPreSawCfg);
3617                 if (status < 0)
3618                         break;
3619
3620                 /* Halt SCU to enable safe non-atomic accesses */
3621                 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3622                 if (status < 0)
3623                         break;
3624
3625                 status = SetAgcRf(state, &state->m_dvbtRfAgcCfg, true);
3626                 if (status < 0)
3627                         break;
3628                 status = SetAgcIf(state, &state->m_dvbtIfAgcCfg, true);
3629                 if (status < 0)
3630                         break;
3631
3632                 /* Set Noise Estimation notch width and enable DC fix */
3633                 status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data);
3634                 if (status < 0)
3635                         break;
3636                 data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M;
3637                 status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data);
3638                 if (status < 0)
3639                         break;
3640
3641                 /* Activate SCU to enable SCU commands */
3642                 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
3643                 if (status < 0)
3644                         break;
3645
3646                 if (!state->m_DRXK_A3_ROM_CODE) {
3647                         /* AGCInit() is not done for DVBT, so set agcFastClipCtrlDelay  */
3648                         status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, state->m_dvbtIfAgcCfg.FastClipCtrlDelay);
3649                         if (status < 0)
3650                                 break;
3651                 }
3652
3653                 /* OFDM_SC setup */
3654 #ifdef COMPILE_FOR_NONRT
3655                 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1);
3656                 if (status < 0)
3657                         break;
3658                 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2);
3659                 if (status < 0)
3660                         break;
3661 #endif
3662
3663                 /* FEC setup */
3664                 status = write16(state, FEC_DI_INPUT_CTL__A, 1);        /* OFDM input */
3665                 if (status < 0)
3666                         break;
3667
3668
3669 #ifdef COMPILE_FOR_NONRT
3670                 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400);
3671                 if (status < 0)
3672                         break;
3673 #else
3674                 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000);
3675                 if (status < 0)
3676                         break;
3677 #endif
3678                 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001);
3679                 if (status < 0)
3680                         break;
3681
3682                 /* Setup MPEG bus */
3683                 status = MPEGTSDtoSetup(state, OM_DVBT);
3684                 if (status < 0)
3685                         break;
3686                 /* Set DVBT Presets */
3687                 status = DVBTActivatePresets(state);
3688                 if (status < 0)
3689                         break;
3690
3691         } while (0);
3692
3693         if (status < 0)
3694                 printk(KERN_ERR "drxk: %s status - %08x\n", __func__, status);
3695
3696         return status;
3697 }
3698
3699 /*============================================================================*/
3700 /**
3701 * \brief Start dvbt demodulating for channel.
3702 * \param demod instance of demodulator.
3703 * \return DRXStatus_t.
3704 */
3705 static int DVBTStart(struct drxk_state *state)
3706 {
3707         u16 param1;
3708         int status;
3709         /* DRXKOfdmScCmd_t scCmd; */
3710
3711         dprintk(1, "\n");
3712         /* Start correct processes to get in lock */
3713         /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */
3714         do {
3715                 param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN;
3716                 status = DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0, OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1, 0, 0, 0);
3717                 if (status < 0)
3718                         break;
3719                 /* Start FEC OC */
3720                 status = MPEGTSStart(state);
3721                 if (status < 0)
3722                         break;
3723                 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
3724                 if (status < 0)
3725                         break;
3726         } while (0);
3727         return status;
3728 }
3729
3730
3731 /*============================================================================*/
3732
3733 /**
3734 * \brief Set up dvbt demodulator for channel.
3735 * \param demod instance of demodulator.
3736 * \return DRXStatus_t.
3737 * // original DVBTSetChannel()
3738 */
3739 static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
3740                    s32 tunerFreqOffset)
3741 {
3742         u16 cmdResult = 0;
3743         u16 transmissionParams = 0;
3744         u16 operationMode = 0;
3745         u32 iqmRcRateOfs = 0;
3746         u32 bandwidth = 0;
3747         u16 param1;
3748         int status;
3749
3750         dprintk(1, "\n");
3751         /* printk(KERN_DEBUG "drxk: %s IF =%d, TFO = %d\n", __func__, IntermediateFreqkHz, tunerFreqOffset); */
3752         do {
3753                 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
3754                 if (status < 0)
3755                         break;
3756
3757                 /* Halt SCU to enable safe non-atomic accesses */
3758                 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3759                 if (status < 0)
3760                         break;
3761
3762                 /* Stop processors */
3763                 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3764                 if (status < 0)
3765                         break;
3766                 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3767                 if (status < 0)
3768                         break;
3769
3770                 /* Mandatory fix, always stop CP, required to set spl offset back to
3771                    hardware default (is set to 0 by ucode during pilot detection */
3772                 status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP);
3773                 if (status < 0)
3774                         break;
3775
3776                 /*== Write channel settings to device =====================================*/
3777
3778                 /* mode */
3779                 switch (state->param.u.ofdm.transmission_mode) {
3780                 case TRANSMISSION_MODE_AUTO:
3781                 default:
3782                         operationMode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M;
3783                         /* fall through , try first guess DRX_FFTMODE_8K */
3784                 case TRANSMISSION_MODE_8K:
3785                         transmissionParams |=
3786                             OFDM_SC_RA_RAM_OP_PARAM_MODE_8K;
3787                         break;
3788                 case TRANSMISSION_MODE_2K:
3789                         transmissionParams |=
3790                             OFDM_SC_RA_RAM_OP_PARAM_MODE_2K;
3791                         break;
3792                 }
3793
3794                 /* guard */
3795                 switch (state->param.u.ofdm.guard_interval) {
3796                 default:
3797                 case GUARD_INTERVAL_AUTO:
3798                         operationMode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M;
3799                         /* fall through , try first guess DRX_GUARD_1DIV4 */
3800                 case GUARD_INTERVAL_1_4:
3801                         transmissionParams |=
3802                             OFDM_SC_RA_RAM_OP_PARAM_GUARD_4;
3803                         break;
3804                 case GUARD_INTERVAL_1_32:
3805                         transmissionParams |=
3806                             OFDM_SC_RA_RAM_OP_PARAM_GUARD_32;
3807                         break;
3808                 case GUARD_INTERVAL_1_16:
3809                         transmissionParams |=
3810                             OFDM_SC_RA_RAM_OP_PARAM_GUARD_16;
3811                         break;
3812                 case GUARD_INTERVAL_1_8:
3813                         transmissionParams |=
3814                             OFDM_SC_RA_RAM_OP_PARAM_GUARD_8;
3815                         break;
3816                 }
3817
3818                 /* hierarchy */
3819                 switch (state->param.u.ofdm.hierarchy_information) {
3820                 case HIERARCHY_AUTO:
3821                 case HIERARCHY_NONE:
3822                 default:
3823                         operationMode |= OFDM_SC_RA_RAM_OP_AUTO_HIER__M;
3824                         /* fall through , try first guess SC_RA_RAM_OP_PARAM_HIER_NO */
3825                         /* transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_NO; */
3826                         /* break; */
3827                 case HIERARCHY_1:
3828                         transmissionParams |=
3829                             OFDM_SC_RA_RAM_OP_PARAM_HIER_A1;
3830                         break;
3831                 case HIERARCHY_2:
3832                         transmissionParams |=
3833                             OFDM_SC_RA_RAM_OP_PARAM_HIER_A2;
3834                         break;
3835                 case HIERARCHY_4:
3836                         transmissionParams |=
3837                             OFDM_SC_RA_RAM_OP_PARAM_HIER_A4;
3838                         break;
3839                 }
3840
3841
3842                 /* constellation */
3843                 switch (state->param.u.ofdm.constellation) {
3844                 case QAM_AUTO:
3845                 default:
3846                         operationMode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M;
3847                         /* fall through , try first guess DRX_CONSTELLATION_QAM64 */
3848                 case QAM_64:
3849                         transmissionParams |=
3850                             OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64;
3851                         break;
3852                 case QPSK:
3853                         transmissionParams |=
3854                             OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK;
3855                         break;
3856                 case QAM_16:
3857                         transmissionParams |=
3858                             OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16;
3859                         break;
3860                 }
3861 #if 0
3862                 /* No hierachical channels support in BDA */
3863                 /* Priority (only for hierarchical channels) */
3864                 switch (channel->priority) {
3865                 case DRX_PRIORITY_LOW:
3866                         transmissionParams |=
3867                             OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO;
3868                         WR16(devAddr, OFDM_EC_SB_PRIOR__A,
3869                              OFDM_EC_SB_PRIOR_LO);
3870                         break;
3871                 case DRX_PRIORITY_HIGH:
3872                         transmissionParams |=
3873                             OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3874                         WR16(devAddr, OFDM_EC_SB_PRIOR__A,
3875                              OFDM_EC_SB_PRIOR_HI));
3876                         break;
3877                 case DRX_PRIORITY_UNKNOWN:      /* fall through */
3878                 default:
3879                         return DRX_STS_INVALID_ARG;
3880                         break;
3881                 }
3882 #else
3883                 /* Set Priorty high */
3884                 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3885                 status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI);
3886                 if (status < 0)
3887                         break;
3888 #endif
3889
3890                 /* coderate */
3891                 switch (state->param.u.ofdm.code_rate_HP) {
3892                 case FEC_AUTO:
3893                 default:
3894                         operationMode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M;
3895                         /* fall through , try first guess DRX_CODERATE_2DIV3 */
3896                 case FEC_2_3:
3897                         transmissionParams |=
3898                             OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3;
3899                         break;
3900                 case FEC_1_2:
3901                         transmissionParams |=
3902                             OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2;
3903                         break;
3904                 case FEC_3_4:
3905                         transmissionParams |=
3906                             OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4;
3907                         break;
3908                 case FEC_5_6:
3909                         transmissionParams |=
3910                             OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6;
3911                         break;
3912                 case FEC_7_8:
3913                         transmissionParams |=
3914                             OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8;
3915                         break;
3916                 }
3917
3918                 /* SAW filter selection: normaly not necesarry, but if wanted
3919                    the application can select a SAW filter via the driver by using UIOs */
3920                 /* First determine real bandwidth (Hz) */
3921                 /* Also set delay for impulse noise cruncher */
3922                 /* Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is changed
3923                    by SC for fix for some 8K,1/8 guard but is restored by InitEC and ResetEC
3924                    functions */
3925                 switch (state->param.u.ofdm.bandwidth) {
3926                 case BANDWIDTH_AUTO:
3927                 case BANDWIDTH_8_MHZ:
3928                         bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ;
3929                         status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3052);
3930                         if (status < 0)
3931                                 break;
3932                         /* cochannel protection for PAL 8 MHz */
3933                         status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 7);
3934                         if (status < 0)
3935                                 break;
3936                         status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 7);
3937                         if (status < 0)
3938                                 break;
3939                         status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 7);
3940                         if (status < 0)
3941                                 break;
3942                         status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
3943                         if (status < 0)
3944                                 break;
3945                         break;
3946                 case BANDWIDTH_7_MHZ:
3947                         bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ;
3948                         status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3491);
3949                         if (status < 0)
3950                                 break;
3951                         /* cochannel protection for PAL 7 MHz */
3952                         status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 8);
3953                         if (status < 0)
3954                                 break;
3955                         status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 8);
3956                         if (status < 0)
3957                                 break;
3958                         status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 4);
3959                         if (status < 0)
3960                                 break;
3961                         status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
3962                         if (status < 0)
3963                                 break;
3964                         break;
3965                 case BANDWIDTH_6_MHZ:
3966                         bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ;
3967                         status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 4073);
3968                         if (status < 0)
3969                                 break;
3970                         /* cochannel protection for NTSC 6 MHz */
3971                         status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 19);
3972                         if (status < 0)
3973                                 break;
3974                         status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 19);
3975                         if (status < 0)
3976                                 break;
3977                         status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 14);
3978                         if (status < 0)
3979                                 break;
3980                         status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
3981                         if (status < 0)
3982                                 break;
3983                         break;
3984                 default:
3985                         return -EINVAL;
3986                 }
3987
3988                 if (iqmRcRateOfs == 0) {
3989                         /* Now compute IQM_RC_RATE_OFS
3990                            (((SysFreq/BandWidth)/2)/2) -1) * 2^23)
3991                            =>
3992                            ((SysFreq / BandWidth) * (2^21)) - (2^23)
3993                          */
3994                         /* (SysFreq / BandWidth) * (2^28)  */
3995                         /* assert (MAX(sysClk)/MIN(bandwidth) < 16)
3996                            => assert(MAX(sysClk) < 16*MIN(bandwidth))
3997                            => assert(109714272 > 48000000) = true so Frac 28 can be used  */
3998                         iqmRcRateOfs = Frac28a((u32)
3999                                                ((state->m_sysClockFreq *
4000                                                  1000) / 3), bandwidth);
4001                         /* (SysFreq / BandWidth) * (2^21), rounding before truncating  */
4002                         if ((iqmRcRateOfs & 0x7fL) >= 0x40)
4003                                 iqmRcRateOfs += 0x80L;
4004                         iqmRcRateOfs = iqmRcRateOfs >> 7;
4005                         /* ((SysFreq / BandWidth) * (2^21)) - (2^23)  */
4006                         iqmRcRateOfs = iqmRcRateOfs - (1 << 23);
4007                 }
4008
4009                 iqmRcRateOfs &=
4010                     ((((u32) IQM_RC_RATE_OFS_HI__M) <<
4011                       IQM_RC_RATE_OFS_LO__W) | IQM_RC_RATE_OFS_LO__M);
4012                 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRateOfs);
4013                 if (status < 0)
4014                         break;
4015
4016                 /* Bandwidth setting done */
4017
4018 #if 0
4019                 status = DVBTSetFrequencyShift(demod, channel, tunerOffset);
4020                 if (status < 0)
4021                         break;
4022 #endif
4023                 status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true);
4024                 if (status < 0)
4025                         break;
4026
4027                 /*== Start SC, write channel settings to SC ===============================*/
4028
4029                 /* Activate SCU to enable SCU commands */
4030                 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
4031                 if (status < 0)
4032                         break;
4033
4034                 /* Enable SC after setting all other parameters */
4035                 status = write16(state, OFDM_SC_COMM_STATE__A, 0);
4036                 if (status < 0)
4037                         break;
4038                 status = write16(state, OFDM_SC_COMM_EXEC__A, 1);
4039                 if (status < 0)
4040                         break;
4041
4042
4043                 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmdResult);
4044                 if (status < 0)
4045                         break;
4046
4047                 /* Write SC parameter registers, set all AUTO flags in operation mode */
4048                 param1 = (OFDM_SC_RA_RAM_OP_AUTO_MODE__M |
4049                           OFDM_SC_RA_RAM_OP_AUTO_GUARD__M |
4050                           OFDM_SC_RA_RAM_OP_AUTO_CONST__M |
4051                           OFDM_SC_RA_RAM_OP_AUTO_HIER__M |
4052                           OFDM_SC_RA_RAM_OP_AUTO_RATE__M);
4053                 status =
4054                     DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM,
4055                                   0, transmissionParams, param1, 0, 0, 0);
4056                 if (!state->m_DRXK_A3_ROM_CODE)
4057                         status = DVBTCtrlSetSqiSpeed(state, &state->m_sqiSpeed);
4058                         if (status < 0)
4059                                 break;
4060
4061         } while (0);
4062
4063         return status;
4064 }
4065
4066
4067 /*============================================================================*/
4068
4069 /**
4070 * \brief Retreive lock status .
4071 * \param demod    Pointer to demodulator instance.
4072 * \param lockStat Pointer to lock status structure.
4073 * \return DRXStatus_t.
4074 *
4075 */
4076 static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus)
4077 {
4078         int status;
4079         const u16 mpeg_lock_mask = (OFDM_SC_RA_RAM_LOCK_MPEG__M |
4080                                     OFDM_SC_RA_RAM_LOCK_FEC__M);
4081         const u16 fec_lock_mask = (OFDM_SC_RA_RAM_LOCK_FEC__M);
4082         const u16 demod_lock_mask = OFDM_SC_RA_RAM_LOCK_DEMOD__M;
4083
4084         u16 ScRaRamLock = 0;
4085         u16 ScCommExec = 0;
4086
4087         dprintk(1, "\n");
4088
4089         /* driver 0.9.0 */
4090         /* Check if SC is running */
4091         status = read16(state, OFDM_SC_COMM_EXEC__A, &ScCommExec);
4092         if (ScCommExec == OFDM_SC_COMM_EXEC_STOP) {
4093                 /* SC not active; return DRX_NOT_LOCKED */
4094                 *pLockStatus = NOT_LOCKED;
4095                 return status;
4096         }
4097
4098         status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &ScRaRamLock);
4099
4100         if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask)
4101                 *pLockStatus = MPEG_LOCK;
4102         else if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask)
4103                 *pLockStatus = FEC_LOCK;
4104         else if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask)
4105                 *pLockStatus = DEMOD_LOCK;
4106         else if (ScRaRamLock & OFDM_SC_RA_RAM_LOCK_NODVBT__M)
4107                 *pLockStatus = NEVER_LOCK;
4108         else
4109                 *pLockStatus = NOT_LOCKED;
4110
4111         return status;
4112 }
4113
4114 static int PowerUpQAM(struct drxk_state *state)
4115 {
4116         enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
4117         int status = 0;
4118
4119         dprintk(1, "\n");
4120         do {
4121                 status = CtrlPowerMode(state, &powerMode);
4122                 if (status < 0)
4123                         break;
4124
4125         } while (0);
4126
4127         return status;
4128 }
4129
4130
4131 /** Power Down QAM */
4132 static int PowerDownQAM(struct drxk_state *state)
4133 {
4134         u16 data = 0;
4135         u16 cmdResult;
4136         int status = 0;
4137
4138         dprintk(1, "\n");
4139         do {
4140                 status = read16(state, SCU_COMM_EXEC__A, &data);
4141                 if (status < 0)
4142                         break;
4143                 if (data == SCU_COMM_EXEC_ACTIVE) {
4144                         /*
4145                            STOP demodulator
4146                            QAM and HW blocks
4147                          */
4148                         /* stop all comstate->m_exec */
4149                         status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
4150                         if (status < 0)
4151                                 break;
4152                         status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
4153                         if (status < 0)
4154                                 break;
4155                 }
4156                 /* powerdown AFE                   */
4157                 status = SetIqmAf(state, false);
4158                 if (status < 0)
4159                         break;
4160         } while (0);
4161
4162         return status;
4163 }
4164
4165 /*============================================================================*/
4166
4167 /**
4168 * \brief Setup of the QAM Measurement intervals for signal quality
4169 * \param demod instance of demod.
4170 * \param constellation current constellation.
4171 * \return DRXStatus_t.
4172 *
4173 *  NOTE:
4174 *  Take into account that for certain settings the errorcounters can overflow.
4175 *  The implementation does not check this.
4176 *
4177 */
4178 static int SetQAMMeasurement(struct drxk_state *state,
4179                              enum EDrxkConstellation constellation,
4180                              u32 symbolRate)
4181 {
4182         u32 fecBitsDesired = 0; /* BER accounting period */
4183         u32 fecRsPeriodTotal = 0;       /* Total period */
4184         u16 fecRsPrescale = 0;  /* ReedSolomon Measurement Prescale */
4185         u16 fecRsPeriod = 0;    /* Value for corresponding I2C register */
4186         int status = 0;
4187
4188         dprintk(1, "\n");
4189
4190         fecRsPrescale = 1;
4191         do {
4192
4193                 /* fecBitsDesired = symbolRate [kHz] *
4194                    FrameLenght [ms] *
4195                    (constellation + 1) *
4196                    SyncLoss (== 1) *
4197                    ViterbiLoss (==1)
4198                  */
4199                 switch (constellation) {
4200                 case DRX_CONSTELLATION_QAM16:
4201                         fecBitsDesired = 4 * symbolRate;
4202                         break;
4203                 case DRX_CONSTELLATION_QAM32:
4204                         fecBitsDesired = 5 * symbolRate;
4205                         break;
4206                 case DRX_CONSTELLATION_QAM64:
4207                         fecBitsDesired = 6 * symbolRate;
4208                         break;
4209                 case DRX_CONSTELLATION_QAM128:
4210                         fecBitsDesired = 7 * symbolRate;
4211                         break;
4212                 case DRX_CONSTELLATION_QAM256:
4213                         fecBitsDesired = 8 * symbolRate;
4214                         break;
4215                 default:
4216                         status = -EINVAL;
4217                 }
4218                 status = status;
4219                 if (status < 0)
4220                         break;
4221
4222                 fecBitsDesired /= 1000; /* symbolRate [Hz] -> symbolRate [kHz]  */
4223                 fecBitsDesired *= 500;  /* meas. period [ms] */
4224
4225                 /* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */
4226                 /* fecRsPeriodTotal = fecBitsDesired / 1632 */
4227                 fecRsPeriodTotal = (fecBitsDesired / 1632UL) + 1;       /* roughly ceil */
4228
4229                 /* fecRsPeriodTotal =  fecRsPrescale * fecRsPeriod  */
4230                 fecRsPrescale = 1 + (u16) (fecRsPeriodTotal >> 16);
4231                 if (fecRsPrescale == 0) {
4232                         /* Divide by zero (though impossible) */
4233                         status = -1;
4234                 }
4235                 status = status;
4236                 if (status < 0)
4237                         break;
4238                 fecRsPeriod =
4239                     ((u16) fecRsPeriodTotal +
4240                      (fecRsPrescale >> 1)) / fecRsPrescale;
4241
4242                 /* write corresponding registers */
4243                 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fecRsPeriod);
4244                 if (status < 0)
4245                         break;
4246                 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, fecRsPrescale);
4247                 if (status < 0)
4248                         break;
4249                 status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fecRsPeriod);
4250                 if (status < 0)
4251                         break;
4252
4253         } while (0);
4254
4255         if (status < 0)
4256                 printk(KERN_ERR "drxk: %s: status - %08x\n", __func__, status);
4257
4258         return status;
4259 }
4260
4261 static int SetQAM16(struct drxk_state *state)
4262 {
4263         int status = 0;
4264
4265         dprintk(1, "\n");
4266         do {
4267                 /* QAM Equalizer Setup */
4268                 /* Equalizer */
4269                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517);
4270                 if (status < 0)
4271                         break;
4272                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517);
4273                 if (status < 0)
4274                         break;
4275                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517);
4276                 if (status < 0)
4277                         break;
4278                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517);
4279                 if (status < 0)
4280                         break;
4281                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517);
4282                 if (status < 0)
4283                         break;
4284                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517);
4285                 if (status < 0)
4286                         break;
4287                 /* Decision Feedback Equalizer */
4288                 status = write16(state, QAM_DQ_QUAL_FUN0__A, 2);
4289                 if (status < 0)
4290                         break;
4291                 status = write16(state, QAM_DQ_QUAL_FUN1__A, 2);
4292                 if (status < 0)
4293                         break;
4294                 status = write16(state, QAM_DQ_QUAL_FUN2__A, 2);
4295                 if (status < 0)
4296                         break;
4297                 status = write16(state, QAM_DQ_QUAL_FUN3__A, 2);
4298                 if (status < 0)
4299                         break;
4300                 status = write16(state, QAM_DQ_QUAL_FUN4__A, 2);
4301                 if (status < 0)
4302                         break;
4303                 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4304                 if (status < 0)
4305                         break;
4306
4307                 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4308                 if (status < 0)
4309                         break;
4310                 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4311                 if (status < 0)
4312                         break;
4313                 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4314                 if (status < 0)
4315                         break;
4316
4317                 /* QAM Slicer Settings */
4318                 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM16);
4319                 if (status < 0)
4320                         break;
4321
4322                 /* QAM Loop Controller Coeficients */
4323                 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4324                 if (status < 0)
4325                         break;
4326                 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4327                 if (status < 0)
4328                         break;
4329                 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4330                 if (status < 0)
4331                         break;
4332                 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4333                 if (status < 0)
4334                         break;
4335                 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4336                 if (status < 0)
4337                         break;
4338                 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4339                 if (status < 0)
4340                         break;
4341                 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4342                 if (status < 0)
4343                         break;
4344                 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4345                 if (status < 0)
4346                         break;
4347
4348                 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4349                 if (status < 0)
4350                         break;
4351                 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4352                 if (status < 0)
4353                         break;
4354                 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4355                 if (status < 0)
4356                         break;
4357                 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4358                 if (status < 0)
4359                         break;
4360                 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4361                 if (status < 0)
4362                         break;
4363                 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4364                 if (status < 0)
4365                         break;
4366                 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4367                 if (status < 0)
4368                         break;
4369                 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4370                 if (status < 0)
4371                         break;
4372                 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32);
4373                 if (status < 0)
4374                         break;
4375                 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4376                 if (status < 0)
4377                         break;
4378                 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4379                 if (status < 0)
4380                         break;
4381                 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4382                 if (status < 0)
4383                         break;
4384
4385
4386                 /* QAM State Machine (FSM) Thresholds */
4387
4388                 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140);
4389                 if (status < 0)
4390                         break;
4391                 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4392                 if (status < 0)
4393                         break;
4394                 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95);
4395                 if (status < 0)
4396                         break;
4397                 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120);
4398                 if (status < 0)
4399                         break;
4400                 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230);
4401                 if (status < 0)
4402                         break;
4403                 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105);
4404                 if (status < 0)
4405                         break;
4406
4407                 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4408                 if (status < 0)
4409                         break;
4410                 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4411                 if (status < 0)
4412                         break;
4413                 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24);
4414                 if (status < 0)
4415                         break;
4416
4417
4418                 /* QAM FSM Tracking Parameters */
4419
4420                 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16);
4421                 if (status < 0)
4422                         break;
4423                 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220);
4424                 if (status < 0)
4425                         break;
4426                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25);
4427                 if (status < 0)
4428                         break;
4429                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6);
4430                 if (status < 0)
4431                         break;
4432                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24);
4433                 if (status < 0)
4434                         break;
4435                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65);
4436                 if (status < 0)
4437                         break;
4438                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127);
4439                 if (status < 0)
4440                         break;
4441         } while (0);
4442
4443         return status;
4444 }
4445
4446 /*============================================================================*/
4447
4448 /**
4449 * \brief QAM32 specific setup
4450 * \param demod instance of demod.
4451 * \return DRXStatus_t.
4452 */
4453 static int SetQAM32(struct drxk_state *state)
4454 {
4455         int status = 0;
4456
4457         dprintk(1, "\n");
4458         do {
4459                 /* QAM Equalizer Setup */
4460                 /* Equalizer */
4461                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707);
4462                 if (status < 0)
4463                         break;
4464                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707);
4465                 if (status < 0)
4466                         break;
4467                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707);
4468                 if (status < 0)
4469                         break;
4470                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707);
4471                 if (status < 0)
4472                         break;
4473                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707);
4474                 if (status < 0)
4475                         break;
4476                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707);
4477                 if (status < 0)
4478                         break;
4479
4480                 /* Decision Feedback Equalizer */
4481                 status = write16(state, QAM_DQ_QUAL_FUN0__A, 3);
4482                 if (status < 0)
4483                         break;
4484                 status = write16(state, QAM_DQ_QUAL_FUN1__A, 3);
4485                 if (status < 0)
4486                         break;
4487                 status = write16(state, QAM_DQ_QUAL_FUN2__A, 3);
4488                 if (status < 0)
4489                         break;
4490                 status = write16(state, QAM_DQ_QUAL_FUN3__A, 3);
4491                 if (status < 0)
4492                         break;
4493                 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4494                 if (status < 0)
4495                         break;
4496                 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4497                 if (status < 0)
4498                         break;
4499
4500                 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4501                 if (status < 0)
4502                         break;
4503                 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4504                 if (status < 0)
4505                         break;
4506                 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4507                 if (status < 0)
4508                         break;
4509
4510                 /* QAM Slicer Settings */
4511
4512                 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM32);
4513                 if (status < 0)
4514                         break;
4515
4516
4517                 /* QAM Loop Controller Coeficients */
4518
4519                 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4520                 if (status < 0)
4521                         break;
4522                 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4523                 if (status < 0)
4524                         break;
4525                 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4526                 if (status < 0)
4527                         break;
4528                 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4529                 if (status < 0)
4530                         break;
4531                 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4532                 if (status < 0)
4533                         break;
4534                 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4535                 if (status < 0)
4536                         break;
4537                 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4538                 if (status < 0)
4539                         break;
4540                 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4541                 if (status < 0)
4542                         break;
4543
4544                 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4545                 if (status < 0)
4546                         break;
4547                 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4548                 if (status < 0)
4549                         break;
4550                 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4551                 if (status < 0)
4552                         break;
4553                 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4554                 if (status < 0)
4555                         break;
4556                 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4557                 if (status < 0)
4558                         break;
4559                 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4560                 if (status < 0)
4561                         break;
4562                 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4563                 if (status < 0)
4564                         break;
4565                 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4566                 if (status < 0)
4567                         break;
4568                 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16);
4569                 if (status < 0)
4570                         break;
4571                 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4572                 if (status < 0)
4573                         break;
4574                 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4575                 if (status < 0)
4576                         break;
4577                 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4578                 if (status < 0)
4579                         break;
4580
4581
4582                 /* QAM State Machine (FSM) Thresholds */
4583
4584                 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90);
4585                 if (status < 0)
4586                         break;
4587                 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4588                 if (status < 0)
4589                         break;
4590                 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4591                 if (status < 0)
4592                         break;
4593                 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4594                 if (status < 0)
4595                         break;
4596                 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170);
4597                 if (status < 0)
4598                         break;
4599                 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4600                 if (status < 0)
4601                         break;
4602
4603                 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4604                 if (status < 0)
4605                         break;
4606                 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4607                 if (status < 0)
4608                         break;
4609                 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10);
4610                 if (status < 0)
4611                         break;
4612
4613
4614                 /* QAM FSM Tracking Parameters */
4615
4616                 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4617                 if (status < 0)
4618                         break;
4619                 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140);
4620                 if (status < 0)
4621                         break;
4622                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8);
4623                 if (status < 0)
4624                         break;
4625                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16);
4626                 if (status < 0)
4627                         break;
4628                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26);
4629                 if (status < 0)
4630                         break;
4631                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56);
4632                 if (status < 0)
4633                         break;
4634                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86);
4635                 if (status < 0)
4636                         break;
4637         } while (0);
4638
4639         return status;
4640 }
4641
4642 /*============================================================================*/
4643
4644 /**
4645 * \brief QAM64 specific setup
4646 * \param demod instance of demod.
4647 * \return DRXStatus_t.
4648 */
4649 static int SetQAM64(struct drxk_state *state)
4650 {
4651         int status = 0;
4652
4653         dprintk(1, "\n");
4654         do {
4655                 /* QAM Equalizer Setup */
4656                 /* Equalizer */
4657                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336);
4658                 if (status < 0)
4659                         break;
4660                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618);
4661                 if (status < 0)
4662                         break;
4663                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988);
4664                 if (status < 0)
4665                         break;
4666                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809);
4667                 if (status < 0)
4668                         break;
4669                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809);
4670                 if (status < 0)
4671                         break;
4672                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609);
4673                 if (status < 0)
4674                         break;
4675
4676                 /* Decision Feedback Equalizer */
4677                 status = write16(state, QAM_DQ_QUAL_FUN0__A, 4);
4678                 if (status < 0)
4679                         break;
4680                 status = write16(state, QAM_DQ_QUAL_FUN1__A, 4);
4681                 if (status < 0)
4682                         break;
4683                 status = write16(state, QAM_DQ_QUAL_FUN2__A, 4);
4684                 if (status < 0)
4685                         break;
4686                 status = write16(state, QAM_DQ_QUAL_FUN3__A, 4);
4687                 if (status < 0)
4688                         break;
4689                 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4690                 if (status < 0)
4691                         break;
4692                 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4693                 if (status < 0)
4694                         break;
4695
4696                 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4697                 if (status < 0)
4698                         break;
4699                 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4700                 if (status < 0)
4701                         break;
4702                 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4703                 if (status < 0)
4704                         break;
4705
4706                 /* QAM Slicer Settings */
4707                 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM64);
4708                 if (status < 0)
4709                         break;
4710
4711
4712                 /* QAM Loop Controller Coeficients */
4713
4714                 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4715                 if (status < 0)
4716                         break;
4717                 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4718                 if (status < 0)
4719                         break;
4720                 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4721                 if (status < 0)
4722                         break;
4723                 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4724                 if (status < 0)
4725                         break;
4726                 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4727                 if (status < 0)
4728                         break;
4729                 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4730                 if (status < 0)
4731                         break;
4732                 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4733                 if (status < 0)
4734                         break;
4735                 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4736                 if (status < 0)
4737                         break;
4738
4739                 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4740                 if (status < 0)
4741                         break;
4742                 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30);
4743                 if (status < 0)
4744                         break;
4745                 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100);
4746                 if (status < 0)
4747                         break;
4748                 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4749                 if (status < 0)
4750                         break;
4751                 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30);
4752                 if (status < 0)
4753                         break;
4754                 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4755                 if (status < 0)
4756                         break;
4757                 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4758                 if (status < 0)
4759                         break;
4760                 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4761                 if (status < 0)
4762                         break;
4763                 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
4764                 if (status < 0)
4765                         break;
4766                 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4767                 if (status < 0)
4768                         break;
4769                 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4770                 if (status < 0)
4771                         break;
4772                 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4773                 if (status < 0)
4774                         break;
4775
4776
4777                 /* QAM State Machine (FSM) Thresholds */
4778
4779                 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100);
4780                 if (status < 0)
4781                         break;
4782                 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4783                 if (status < 0)
4784                         break;
4785                 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4786                 if (status < 0)
4787                         break;
4788                 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110);
4789                 if (status < 0)
4790                         break;
4791                 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200);
4792                 if (status < 0)
4793                         break;
4794                 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95);
4795                 if (status < 0)
4796                         break;
4797
4798                 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4799                 if (status < 0)
4800                         break;
4801                 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4802                 if (status < 0)
4803                         break;
4804                 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15);
4805                 if (status < 0)
4806                         break;
4807
4808
4809                 /* QAM FSM Tracking Parameters */
4810
4811                 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4812                 if (status < 0)
4813                         break;
4814                 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141);
4815                 if (status < 0)
4816                         break;
4817                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7);
4818                 if (status < 0)
4819                         break;
4820                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0);
4821                 if (status < 0)
4822                         break;
4823                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15);
4824                 if (status < 0)
4825                         break;
4826                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45);
4827                 if (status < 0)
4828                         break;
4829                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80);
4830                 if (status < 0)
4831                         break;
4832         } while (0);
4833
4834         return status;
4835 }
4836
4837 /*============================================================================*/
4838
4839 /**
4840 * \brief QAM128 specific setup
4841 * \param demod: instance of demod.
4842 * \return DRXStatus_t.
4843 */
4844 static int SetQAM128(struct drxk_state *state)
4845 {
4846         int status = 0;
4847
4848         dprintk(1, "\n");
4849         do {
4850                 /* QAM Equalizer Setup */
4851                 /* Equalizer */
4852                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564);
4853                 if (status < 0)
4854                         break;
4855                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598);
4856                 if (status < 0)
4857                         break;
4858                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394);
4859                 if (status < 0)
4860                         break;
4861                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409);
4862                 if (status < 0)
4863                         break;
4864                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656);
4865                 if (status < 0)
4866                         break;
4867                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238);
4868                 if (status < 0)
4869                         break;
4870
4871                 /* Decision Feedback Equalizer */
4872                 status = write16(state, QAM_DQ_QUAL_FUN0__A, 6);
4873                 if (status < 0)
4874                         break;
4875                 status = write16(state, QAM_DQ_QUAL_FUN1__A, 6);
4876                 if (status < 0)
4877                         break;
4878                 status = write16(state, QAM_DQ_QUAL_FUN2__A, 6);
4879                 if (status < 0)
4880                         break;
4881                 status = write16(state, QAM_DQ_QUAL_FUN3__A, 6);
4882                 if (status < 0)
4883                         break;
4884                 status = write16(state, QAM_DQ_QUAL_FUN4__A, 5);
4885                 if (status < 0)
4886                         break;
4887                 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4888                 if (status < 0)
4889                         break;
4890
4891                 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4892                 if (status < 0)
4893                         break;
4894                 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4895                 if (status < 0)
4896                         break;
4897                 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4898                 if (status < 0)
4899                         break;
4900
4901
4902                 /* QAM Slicer Settings */
4903
4904                 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM128);
4905                 if (status < 0)
4906                         break;
4907
4908
4909                 /* QAM Loop Controller Coeficients */
4910
4911                 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4912                 if (status < 0)
4913                         break;
4914                 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4915                 if (status < 0)
4916                         break;
4917                 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4918                 if (status < 0)
4919                         break;
4920                 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4921                 if (status < 0)
4922                         break;
4923                 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4924                 if (status < 0)
4925                         break;
4926                 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4927                 if (status < 0)
4928                         break;
4929                 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4930                 if (status < 0)
4931                         break;
4932                 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4933                 if (status < 0)
4934                         break;
4935
4936                 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4937                 if (status < 0)
4938                         break;
4939                 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40);
4940                 if (status < 0)
4941                         break;
4942                 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120);
4943                 if (status < 0)
4944                         break;
4945                 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4946                 if (status < 0)
4947                         break;
4948                 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40);
4949                 if (status < 0)
4950                         break;
4951                 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60);
4952                 if (status < 0)
4953                         break;
4954                 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4955                 if (status < 0)
4956                         break;
4957                 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4958                 if (status < 0)
4959                         break;
4960                 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64);
4961                 if (status < 0)
4962                         break;
4963                 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4964                 if (status < 0)
4965                         break;
4966                 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4967                 if (status < 0)
4968                         break;
4969                 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4970                 if (status < 0)
4971                         break;
4972
4973
4974                 /* QAM State Machine (FSM) Thresholds */
4975
4976                 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
4977                 if (status < 0)
4978                         break;
4979                 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4980                 if (status < 0)
4981                         break;
4982                 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4983                 if (status < 0)
4984                         break;
4985                 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4986                 if (status < 0)
4987                         break;
4988                 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140);
4989                 if (status < 0)
4990                         break;
4991                 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4992                 if (status < 0)
4993                         break;
4994
4995                 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4996                 if (status < 0)
4997                         break;
4998                 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5);
4999                 if (status < 0)
5000                         break;
5001
5002                 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5003                 if (status < 0)
5004                         break;
5005
5006                 /* QAM FSM Tracking Parameters */
5007
5008                 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5009                 if (status < 0)
5010                         break;
5011                 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65);
5012                 if (status < 0)
5013                         break;
5014                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5);
5015                 if (status < 0)
5016                         break;
5017                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3);
5018                 if (status < 0)
5019                         break;
5020                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1);
5021                 if (status < 0)
5022                         break;
5023                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12);
5024                 if (status < 0)
5025                         break;
5026                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23);
5027                 if (status < 0)
5028                         break;
5029         } while (0);
5030
5031         return status;
5032 }
5033
5034 /*============================================================================*/
5035
5036 /**
5037 * \brief QAM256 specific setup
5038 * \param demod: instance of demod.
5039 * \return DRXStatus_t.
5040 */
5041 static int SetQAM256(struct drxk_state *state)
5042 {
5043         int status = 0;
5044
5045         dprintk(1, "\n");
5046         do {
5047                 /* QAM Equalizer Setup */
5048                 /* Equalizer */
5049                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502);
5050                 if (status < 0)
5051                         break;
5052                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084);
5053                 if (status < 0)
5054                         break;
5055                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543);
5056                 if (status < 0)
5057                         break;
5058                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931);
5059                 if (status < 0)
5060                         break;
5061                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629);
5062                 if (status < 0)
5063                         break;
5064                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385);
5065                 if (status < 0)
5066                         break;
5067
5068                 /* Decision Feedback Equalizer */
5069                 status = write16(state, QAM_DQ_QUAL_FUN0__A, 8);
5070                 if (status < 0)
5071                         break;
5072                 status = write16(state, QAM_DQ_QUAL_FUN1__A, 8);
5073                 if (status < 0)
5074                         break;
5075                 status = write16(state, QAM_DQ_QUAL_FUN2__A, 8);
5076                 if (status < 0)
5077                         break;
5078                 status = write16(state, QAM_DQ_QUAL_FUN3__A, 8);
5079                 if (status < 0)
5080                         break;
5081                 status = write16(state, QAM_DQ_QUAL_FUN4__A, 6);
5082                 if (status < 0)
5083                         break;
5084                 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
5085                 if (status < 0)
5086                         break;
5087
5088                 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
5089                 if (status < 0)
5090                         break;
5091                 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
5092                 if (status < 0)
5093                         break;
5094                 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
5095                 if (status < 0)
5096                         break;
5097
5098                 /* QAM Slicer Settings */
5099
5100                 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM256);
5101                 if (status < 0)
5102                         break;
5103
5104
5105                 /* QAM Loop Controller Coeficients */
5106
5107                 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
5108                 if (status < 0)
5109                         break;
5110                 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
5111                 if (status < 0)
5112                         break;
5113                 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
5114                 if (status < 0)
5115                         break;
5116                 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
5117                 if (status < 0)
5118                         break;
5119                 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
5120                 if (status < 0)
5121                         break;
5122                 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
5123                 if (status < 0)
5124                         break;
5125                 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
5126                 if (status < 0)
5127                         break;
5128                 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
5129                 if (status < 0)
5130                         break;
5131
5132                 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
5133                 if (status < 0)
5134                         break;
5135                 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50);
5136                 if (status < 0)
5137                         break;
5138                 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250);
5139                 if (status < 0)
5140                         break;
5141                 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
5142                 if (status < 0)
5143                         break;
5144                 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50);
5145                 if (status < 0)
5146                         break;
5147                 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125);
5148                 if (status < 0)
5149                         break;
5150                 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
5151                 if (status < 0)
5152                         break;
5153                 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
5154                 if (status < 0)
5155                         break;
5156                 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
5157                 if (status < 0)
5158                         break;
5159                 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
5160                 if (status < 0)
5161                         break;
5162                 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
5163                 if (status < 0)
5164                         break;
5165                 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
5166                 if (status < 0)
5167                         break;
5168
5169
5170                 /* QAM State Machine (FSM) Thresholds */
5171
5172                 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
5173                 if (status < 0)
5174                         break;
5175                 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
5176                 if (status < 0)
5177                         break;
5178                 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
5179                 if (status < 0)
5180                         break;
5181                 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
5182                 if (status < 0)
5183                         break;
5184                 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150);
5185                 if (status < 0)
5186                         break;
5187                 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110);
5188                 if (status < 0)
5189                         break;
5190
5191                 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
5192                 if (status < 0)
5193                         break;
5194                 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
5195                 if (status < 0)
5196                         break;
5197                 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5198                 if (status < 0)
5199                         break;
5200
5201
5202                 /* QAM FSM Tracking Parameters */
5203
5204                 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5205                 if (status < 0)
5206                         break;
5207                 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74);
5208                 if (status < 0)
5209                         break;
5210                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18);
5211                 if (status < 0)
5212                         break;
5213                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13);
5214                 if (status < 0)
5215                         break;
5216                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7);
5217                 if (status < 0)
5218                         break;
5219                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0);
5220                 if (status < 0)
5221                         break;
5222                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8);
5223                 if (status < 0)
5224                         break;
5225         } while (0);
5226
5227         return status;
5228 }
5229
5230
5231 /*============================================================================*/
5232 /**
5233 * \brief Reset QAM block.
5234 * \param demod:   instance of demod.
5235 * \param channel: pointer to channel data.
5236 * \return DRXStatus_t.
5237 */
5238 static int QAMResetQAM(struct drxk_state *state)
5239 {
5240         int status;
5241         u16 cmdResult;
5242
5243         dprintk(1, "\n");
5244         do {
5245                 /* Stop QAM comstate->m_exec */
5246                 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
5247                 if (status < 0)
5248                         break;
5249
5250                 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
5251                 if (status < 0)
5252                         break;
5253         } while (0);
5254
5255         /* All done, all OK */
5256         return status;
5257 }
5258
5259 /*============================================================================*/
5260
5261 /**
5262 * \brief Set QAM symbolrate.
5263 * \param demod:   instance of demod.
5264 * \param channel: pointer to channel data.
5265 * \return DRXStatus_t.
5266 */
5267 static int QAMSetSymbolrate(struct drxk_state *state)
5268 {
5269         u32 adcFrequency = 0;
5270         u32 symbFreq = 0;
5271         u32 iqmRcRate = 0;
5272         u16 ratesel = 0;
5273         u32 lcSymbRate = 0;
5274         int status;
5275
5276         dprintk(1, "\n");
5277         do {
5278                 /* Select & calculate correct IQM rate */
5279                 adcFrequency = (state->m_sysClockFreq * 1000) / 3;
5280                 ratesel = 0;
5281                 /* printk(KERN_DEBUG "drxk: SR %d\n", state->param.u.qam.symbol_rate); */
5282                 if (state->param.u.qam.symbol_rate <= 1188750)
5283                         ratesel = 3;
5284                 else if (state->param.u.qam.symbol_rate <= 2377500)
5285                         ratesel = 2;
5286                 else if (state->param.u.qam.symbol_rate <= 4755000)
5287                         ratesel = 1;
5288                 status = write16(state, IQM_FD_RATESEL__A, ratesel);
5289                 if (status < 0)
5290                         break;
5291
5292                 /*
5293                    IqmRcRate = ((Fadc / (symbolrate * (4<<ratesel))) - 1) * (1<<23)
5294                  */
5295                 symbFreq = state->param.u.qam.symbol_rate * (1 << ratesel);
5296                 if (symbFreq == 0) {
5297                         /* Divide by zero */
5298                         return -1;
5299                 }
5300                 iqmRcRate = (adcFrequency / symbFreq) * (1 << 21) +
5301                     (Frac28a((adcFrequency % symbFreq), symbFreq) >> 7) -
5302                     (1 << 23);
5303                 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRate);
5304                 if (status < 0)
5305                         break;
5306                 state->m_iqmRcRate = iqmRcRate;
5307                 /*
5308                    LcSymbFreq = round (.125 *  symbolrate / adcFreq * (1<<15))
5309                  */
5310                 symbFreq = state->param.u.qam.symbol_rate;
5311                 if (adcFrequency == 0) {
5312                         /* Divide by zero */
5313                         return -1;
5314                 }
5315                 lcSymbRate = (symbFreq / adcFrequency) * (1 << 12) +
5316                     (Frac28a((symbFreq % adcFrequency), adcFrequency) >>
5317                      16);
5318                 if (lcSymbRate > 511)
5319                         lcSymbRate = 511;
5320                 status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lcSymbRate);
5321                 if (status < 0)
5322                         break;
5323         } while (0);
5324
5325         return status;
5326 }
5327
5328 /*============================================================================*/
5329
5330 /**
5331 * \brief Get QAM lock status.
5332 * \param demod:   instance of demod.
5333 * \param channel: pointer to channel data.
5334 * \return DRXStatus_t.
5335 */
5336
5337 static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus)
5338 {
5339         int status;
5340         u16 Result[2] = { 0, 0 };
5341
5342         dprintk(1, "\n");
5343         status =
5344             scu_command(state,
5345                         SCU_RAM_COMMAND_STANDARD_QAM |
5346                         SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, 0, NULL, 2,
5347                         Result);
5348         if (status < 0)
5349                 printk(KERN_ERR "drxk: %s status = %08x\n", __func__, status);
5350
5351         if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) {
5352                 /* 0x0000 NOT LOCKED */
5353                 *pLockStatus = NOT_LOCKED;
5354         } else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) {
5355                 /* 0x4000 DEMOD LOCKED */
5356                 *pLockStatus = DEMOD_LOCK;
5357         } else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK) {
5358                 /* 0x8000 DEMOD + FEC LOCKED (system lock) */
5359                 *pLockStatus = MPEG_LOCK;
5360         } else {
5361                 /* 0xC000 NEVER LOCKED */
5362                 /* (system will never be able to lock to the signal) */
5363                 /* TODO: check this, intermediate & standard specific lock states are not
5364                    taken into account here */
5365                 *pLockStatus = NEVER_LOCK;
5366         }
5367         return status;
5368 }
5369
5370 #define QAM_MIRROR__M         0x03
5371 #define QAM_MIRROR_NORMAL     0x00
5372 #define QAM_MIRRORED          0x01
5373 #define QAM_MIRROR_AUTO_ON    0x02
5374 #define QAM_LOCKRANGE__M      0x10
5375 #define QAM_LOCKRANGE_NORMAL  0x10
5376
5377 static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
5378                   s32 tunerFreqOffset)
5379 {
5380         int status = 0;
5381         u8 parameterLen;
5382         u16 setEnvParameters[5];
5383         u16 setParamParameters[4] = { 0, 0, 0, 0 };
5384         u16 cmdResult;
5385
5386         dprintk(1, "\n");
5387         do {
5388                 /*
5389                    STEP 1: reset demodulator
5390                    resets FEC DI and FEC RS
5391                    resets QAM block
5392                    resets SCU variables
5393                  */
5394                 status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP);
5395                 if (status < 0)
5396                         break;
5397                 status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP);
5398                 if (status < 0)
5399                         break;
5400                 status = QAMResetQAM(state);
5401                 if (status < 0)
5402                         break;
5403
5404                 /*
5405                    STEP 2: configure demodulator
5406                    -set env
5407                    -set params; resets IQM,QAM,FEC HW; initializes some SCU variables
5408                  */
5409                 status = QAMSetSymbolrate(state);
5410                 if (status < 0)
5411                         break;
5412
5413                 /* Env parameters */
5414                 setEnvParameters[2] = QAM_TOP_ANNEX_A;  /* Annex */
5415                 if (state->m_OperationMode == OM_QAM_ITU_C)
5416                         setEnvParameters[2] = QAM_TOP_ANNEX_C;  /* Annex */
5417                 setParamParameters[3] |= (QAM_MIRROR_AUTO_ON);
5418                 /* check for LOCKRANGE Extented */
5419                 /* setParamParameters[3] |= QAM_LOCKRANGE_NORMAL; */
5420                 parameterLen = 4;
5421
5422                 /* Set params */
5423                 switch (state->param.u.qam.modulation) {
5424                 case QAM_256:
5425                         state->m_Constellation = DRX_CONSTELLATION_QAM256;
5426                         break;
5427                 case QAM_AUTO:
5428                 case QAM_64:
5429                         state->m_Constellation = DRX_CONSTELLATION_QAM64;
5430                         break;
5431                 case QAM_16:
5432                         state->m_Constellation = DRX_CONSTELLATION_QAM16;
5433                         break;
5434                 case QAM_32:
5435                         state->m_Constellation = DRX_CONSTELLATION_QAM32;
5436                         break;
5437                 case QAM_128:
5438                         state->m_Constellation = DRX_CONSTELLATION_QAM128;
5439                         break;
5440                 default:
5441                         status = -EINVAL;
5442                         break;
5443                 }
5444                 status = status;
5445                 if (status < 0)
5446                         break;
5447                 setParamParameters[0] = state->m_Constellation; /* constellation     */
5448                 setParamParameters[1] = DRXK_QAM_I12_J17;       /* interleave mode   */
5449
5450                 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, 4, setParamParameters, 1, &cmdResult);
5451                 if (status < 0)
5452                         break;
5453
5454
5455                 /* STEP 3: enable the system in a mode where the ADC provides valid signal
5456                    setup constellation independent registers */
5457 #if 0
5458                 status = SetFrequency (channel, tunerFreqOffset));
5459                 if (status < 0)
5460                         break;
5461 #endif
5462                 status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true);
5463                 if (status < 0)
5464                         break;
5465
5466                 /* Setup BER measurement */
5467                 status = SetQAMMeasurement(state, state->m_Constellation, state->param.u. qam.symbol_rate);
5468                 if (status < 0)
5469                         break;
5470
5471                 /* Reset default values */
5472                 status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE);
5473                 if (status < 0)
5474                         break;
5475                 status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE);
5476                 if (status < 0)
5477                         break;
5478
5479                 /* Reset default LC values */
5480                 status = write16(state, QAM_LC_RATE_LIMIT__A, 3);
5481                 if (status < 0)
5482                         break;
5483                 status = write16(state, QAM_LC_LPF_FACTORP__A, 4);
5484                 if (status < 0)
5485                         break;
5486                 status = write16(state, QAM_LC_LPF_FACTORI__A, 4);
5487                 if (status < 0)
5488                         break;
5489                 status = write16(state, QAM_LC_MODE__A, 7);
5490                 if (status < 0)
5491                         break;
5492
5493                 status = write16(state, QAM_LC_QUAL_TAB0__A, 1);
5494                 if (status < 0)
5495                         break;
5496                 status = write16(state, QAM_LC_QUAL_TAB1__A, 1);
5497                 if (status < 0)
5498                         break;
5499                 status = write16(state, QAM_LC_QUAL_TAB2__A, 1);
5500                 if (status < 0)
5501                         break;
5502                 status = write16(state, QAM_LC_QUAL_TAB3__A, 1);
5503                 if (status < 0)
5504                         break;
5505                 status = write16(state, QAM_LC_QUAL_TAB4__A, 2);
5506                 if (status < 0)
5507                         break;
5508                 status = write16(state, QAM_LC_QUAL_TAB5__A, 2);
5509                 if (status < 0)
5510                         break;
5511                 status = write16(state, QAM_LC_QUAL_TAB6__A, 2);
5512                 if (status < 0)
5513                         break;
5514                 status = write16(state, QAM_LC_QUAL_TAB8__A, 2);
5515                 if (status < 0)
5516                         break;
5517                 status = write16(state, QAM_LC_QUAL_TAB9__A, 2);
5518                 if (status < 0)
5519                         break;
5520                 status = write16(state, QAM_LC_QUAL_TAB10__A, 2);
5521                 if (status < 0)
5522                         break;
5523                 status = write16(state, QAM_LC_QUAL_TAB12__A, 2);
5524                 if (status < 0)
5525                         break;
5526                 status = write16(state, QAM_LC_QUAL_TAB15__A, 3);
5527                 if (status < 0)
5528                         break;
5529                 status = write16(state, QAM_LC_QUAL_TAB16__A, 3);
5530                 if (status < 0)
5531                         break;
5532                 status = write16(state, QAM_LC_QUAL_TAB20__A, 4);
5533                 if (status < 0)
5534                         break;
5535                 status = write16(state, QAM_LC_QUAL_TAB25__A, 4);
5536                 if (status < 0)
5537                         break;
5538
5539                 /* Mirroring, QAM-block starting point not inverted */
5540                 status = write16(state, QAM_SY_SP_INV__A, QAM_SY_SP_INV_SPECTRUM_INV_DIS);
5541                 if (status < 0)
5542                         break;
5543
5544                 /* Halt SCU to enable safe non-atomic accesses */
5545                 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5546                 if (status < 0)
5547                         break;
5548
5549                 /* STEP 4: constellation specific setup */
5550                 switch (state->param.u.qam.modulation) {
5551                 case QAM_16:
5552                         status = SetQAM16(state);
5553                         if (status < 0)
5554                                 break;
5555                         break;
5556                 case QAM_32:
5557                         status = SetQAM32(state);
5558                         if (status < 0)
5559                                 break;
5560                         break;
5561                 case QAM_AUTO:
5562                 case QAM_64:
5563                         status = SetQAM64(state);
5564                         if (status < 0)
5565                                 break;
5566                         break;
5567                 case QAM_128:
5568                         status = SetQAM128(state);
5569                         if (status < 0)
5570                                 break;
5571                         break;
5572                 case QAM_256:
5573                         status = SetQAM256(state);
5574                         if (status < 0)
5575                                 break;
5576                         break;
5577                 default:
5578                         return -1;
5579                         break;
5580                 }               /* switch */
5581                 /* Activate SCU to enable SCU commands */
5582                 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5583                 if (status < 0)
5584                         break;
5585
5586
5587                 /* Re-configure MPEG output, requires knowledge of channel bitrate */
5588                 /* extAttr->currentChannel.constellation = channel->constellation; */
5589                 /* extAttr->currentChannel.symbolrate    = channel->symbolrate; */
5590                 status = MPEGTSDtoSetup(state, state->m_OperationMode);
5591                 if (status < 0)
5592                         break;
5593
5594                 /* Start processes */
5595                 status = MPEGTSStart(state);
5596                 if (status < 0)
5597                         break;
5598                 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
5599                 if (status < 0)
5600                         break;
5601                 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE);
5602                 if (status < 0)
5603                         break;
5604                 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
5605                 if (status < 0)
5606                         break;
5607
5608                 /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */
5609                 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmdResult);
5610                 if (status < 0)
5611                         break;
5612
5613                 /* update global DRXK data container */
5614         /*?     extAttr->qamInterleaveMode = DRXK_QAM_I12_J17; */
5615
5616                 /* All done, all OK */
5617         } while (0);
5618
5619         if (status < 0)
5620                 printk(KERN_ERR "drxk: %s %d\n", __func__, status);
5621
5622         return status;
5623 }
5624
5625 static int SetQAMStandard(struct drxk_state *state,
5626                           enum OperationMode oMode)
5627 {
5628 #ifdef DRXK_QAM_TAPS
5629 #define DRXK_QAMA_TAPS_SELECT
5630 #include "drxk_filters.h"
5631 #undef DRXK_QAMA_TAPS_SELECT
5632 #else
5633         int status;
5634 #endif
5635
5636         dprintk(1, "\n");
5637         do {
5638                 /* added antenna switch */
5639                 SwitchAntennaToQAM(state);
5640
5641                 /* Ensure correct power-up mode */
5642                 status = PowerUpQAM(state);
5643                 if (status < 0)
5644                         break;
5645                 /* Reset QAM block */
5646                 status = QAMResetQAM(state);
5647                 if (status < 0)
5648                         break;
5649
5650                 /* Setup IQM */
5651
5652                 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
5653                 if (status < 0)
5654                         break;
5655                 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
5656                 if (status < 0)
5657                         break;
5658
5659                 /* Upload IQM Channel Filter settings by
5660                    boot loader from ROM table */
5661                 switch (oMode) {
5662                 case OM_QAM_ITU_A:
5663                         status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5664                         if (status < 0)
5665                                 break;
5666                         break;
5667                 case OM_QAM_ITU_C:
5668                         status = BLDirectCmd(state, IQM_CF_TAP_RE0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5669                         if (status < 0)
5670                                 break;
5671                         status = BLDirectCmd(state, IQM_CF_TAP_IM0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5672                         if (status < 0)
5673                                 break;
5674                         break;
5675                 default:
5676                         status = -EINVAL;
5677                 }
5678                 status = status;
5679                 if (status < 0)
5680                         break;
5681
5682                 status = write16(state, IQM_CF_OUT_ENA__A, (1 << IQM_CF_OUT_ENA_QAM__B));
5683                 if (status < 0)
5684                         break;
5685                 status = write16(state, IQM_CF_SYMMETRIC__A, 0);
5686                 if (status < 0)
5687                         break;
5688                 status = write16(state, IQM_CF_MIDTAP__A, ((1 << IQM_CF_MIDTAP_RE__B) | (1 << IQM_CF_MIDTAP_IM__B)));
5689                 if (status < 0)
5690                         break;
5691
5692                 status = write16(state, IQM_RC_STRETCH__A, 21);
5693                 if (status < 0)
5694                         break;
5695                 status = write16(state, IQM_AF_CLP_LEN__A, 0);
5696                 if (status < 0)
5697                         break;
5698                 status = write16(state, IQM_AF_CLP_TH__A, 448);
5699                 if (status < 0)
5700                         break;
5701                 status = write16(state, IQM_AF_SNS_LEN__A, 0);
5702                 if (status < 0)
5703                         break;
5704                 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0);
5705                 if (status < 0)
5706                         break;
5707
5708                 status = write16(state, IQM_FS_ADJ_SEL__A, 1);
5709                 if (status < 0)
5710                         break;
5711                 status = write16(state, IQM_RC_ADJ_SEL__A, 1);
5712                 if (status < 0)
5713                         break;
5714                 status = write16(state, IQM_CF_ADJ_SEL__A, 1);
5715                 if (status < 0)
5716                         break;
5717                 status = write16(state, IQM_AF_UPD_SEL__A, 0);
5718                 if (status < 0)
5719                         break;
5720
5721                 /* IQM Impulse Noise Processing Unit */
5722                 status = write16(state, IQM_CF_CLP_VAL__A, 500);
5723                 if (status < 0)
5724                         break;
5725                 status = write16(state, IQM_CF_DATATH__A, 1000);
5726                 if (status < 0)
5727                         break;
5728                 status = write16(state, IQM_CF_BYPASSDET__A, 1);
5729                 if (status < 0)
5730                         break;
5731                 status = write16(state, IQM_CF_DET_LCT__A, 0);
5732                 if (status < 0)
5733                         break;
5734                 status = write16(state, IQM_CF_WND_LEN__A, 1);
5735                 if (status < 0)
5736                         break;
5737                 status = write16(state, IQM_CF_PKDTH__A, 1);
5738                 if (status < 0)
5739                         break;
5740                 status = write16(state, IQM_AF_INC_BYPASS__A, 1);
5741                 if (status < 0)
5742                         break;
5743
5744                 /* turn on IQMAF. Must be done before setAgc**() */
5745                 status = SetIqmAf(state, true);
5746                 if (status < 0)
5747                         break;
5748                 status = write16(state, IQM_AF_START_LOCK__A, 0x01);
5749                 if (status < 0)
5750                         break;
5751
5752                 /* IQM will not be reset from here, sync ADC and update/init AGC */
5753                 status = ADCSynchronization(state);
5754                 if (status < 0)
5755                         break;
5756
5757                 /* Set the FSM step period */
5758                 status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000);
5759                 if (status < 0)
5760                         break;
5761
5762                 /* Halt SCU to enable safe non-atomic accesses */
5763                 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5764                 if (status < 0)
5765                         break;
5766
5767                 /* No more resets of the IQM, current standard correctly set =>
5768                    now AGCs can be configured. */
5769
5770                 status = InitAGC(state, true);
5771                 if (status < 0)
5772                         break;
5773                 status = SetPreSaw(state, &(state->m_qamPreSawCfg));
5774                 if (status < 0)
5775                         break;
5776
5777                 /* Configure AGC's */
5778                 status = SetAgcRf(state, &(state->m_qamRfAgcCfg), true);
5779                 if (status < 0)
5780                         break;
5781                 status = SetAgcIf(state, &(state->m_qamIfAgcCfg), true);
5782                 if (status < 0)
5783                         break;
5784
5785                 /* Activate SCU to enable SCU commands */
5786                 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5787                 if (status < 0)
5788                         break;
5789         } while (0);
5790         return status;
5791 }
5792
5793 static int WriteGPIO(struct drxk_state *state)
5794 {
5795         int status;
5796         u16 value = 0;
5797
5798         dprintk(1, "\n");
5799         do {
5800                 /* stop lock indicator process */
5801                 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
5802                 if (status < 0)
5803                         break;
5804
5805                 /*  Write magic word to enable pdr reg write               */
5806                 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
5807                 if (status < 0)
5808                         break;
5809
5810                 if (state->m_hasSAWSW) {
5811                         /* write to io pad configuration register - output mode */
5812                         status = write16(state, SIO_PDR_SMA_TX_CFG__A, state->m_GPIOCfg);
5813                         if (status < 0)
5814                                 break;
5815
5816                         /* use corresponding bit in io data output registar */
5817                         status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5818                         if (status < 0)
5819                                 break;
5820                         if (state->m_GPIO == 0)
5821                                 value &= 0x7FFF;        /* write zero to 15th bit - 1st UIO */
5822                         else
5823                                 value |= 0x8000;        /* write one to 15th bit - 1st UIO */
5824                         /* write back to io data output register */
5825                         status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5826                         if (status < 0)
5827                                 break;
5828
5829                 }
5830                 /*  Write magic word to disable pdr reg write               */
5831                 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
5832                 if (status < 0)
5833                         break;
5834         } while (0);
5835         return status;
5836 }
5837
5838 static int SwitchAntennaToQAM(struct drxk_state *state)
5839 {
5840         int status = -1;
5841
5842         dprintk(1, "\n");
5843         if (state->m_AntennaSwitchDVBTDVBC != 0) {
5844                 if (state->m_GPIO != state->m_AntennaDVBC) {
5845                         state->m_GPIO = state->m_AntennaDVBC;
5846                         status = WriteGPIO(state);
5847                 }
5848         }
5849         return status;
5850 }
5851
5852 static int SwitchAntennaToDVBT(struct drxk_state *state)
5853 {
5854         int status = -1;
5855
5856         dprintk(1, "\n");
5857         if (state->m_AntennaSwitchDVBTDVBC != 0) {
5858                 if (state->m_GPIO != state->m_AntennaDVBT) {
5859                         state->m_GPIO = state->m_AntennaDVBT;
5860                         status = WriteGPIO(state);
5861                 }
5862         }
5863         return status;
5864 }
5865
5866
5867 static int PowerDownDevice(struct drxk_state *state)
5868 {
5869         /* Power down to requested mode */
5870         /* Backup some register settings */
5871         /* Set pins with possible pull-ups connected to them in input mode */
5872         /* Analog power down */
5873         /* ADC power down */
5874         /* Power down device */
5875         int status;
5876
5877         dprintk(1, "\n");
5878         do {
5879                 if (state->m_bPDownOpenBridge) {
5880                         /* Open I2C bridge before power down of DRXK */
5881                         status = ConfigureI2CBridge(state, true);
5882                         if (status < 0)
5883                                 break;
5884                 }
5885                 /* driver 0.9.0 */
5886                 status = DVBTEnableOFDMTokenRing(state, false);
5887                 if (status < 0)
5888                         break;
5889
5890                 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_CLOCK);
5891                 if (status < 0)
5892                         break;
5893                 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
5894                 if (status < 0)
5895                         break;
5896                 state->m_HICfgCtrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
5897                 status = HI_CfgCommand(state);
5898                 if (status < 0)
5899                         break;
5900         } while (0);
5901
5902         if (status < 0)
5903                 return -1;
5904
5905         return 0;
5906 }
5907
5908 static int load_microcode(struct drxk_state *state, const char *mc_name)
5909 {
5910         const struct firmware *fw = NULL;
5911         int err = 0;
5912
5913         dprintk(1, "\n");
5914
5915         err = request_firmware(&fw, mc_name, state->i2c->dev.parent);
5916         if (err < 0) {
5917                 printk(KERN_ERR
5918                        "drxk: Could not load firmware file %s.\n", mc_name);
5919                 printk(KERN_INFO
5920                        "drxk: Copy %s to your hotplug directory!\n", mc_name);
5921                 return err;
5922         }
5923         err = DownloadMicrocode(state, fw->data, fw->size);
5924         release_firmware(fw);
5925         return err;
5926 }
5927
5928 static int init_drxk(struct drxk_state *state)
5929 {
5930         int status;
5931         enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
5932         u16 driverVersion;
5933
5934         dprintk(1, "\n");
5935         if ((state->m_DrxkState == DRXK_UNINITIALIZED)) {
5936                 do {
5937                         status = PowerUpDevice(state);
5938                         if (status < 0)
5939                                 break;
5940                         status = DRXX_Open(state);
5941                         if (status < 0)
5942                                 break;
5943                         /* Soft reset of OFDM-, sys- and osc-clockdomain */
5944                         status = write16(state, SIO_CC_SOFT_RST__A, SIO_CC_SOFT_RST_OFDM__M | SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M);
5945                         if (status < 0)
5946                                 break;
5947                         status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
5948                         if (status < 0)
5949                                 break;
5950                         /* TODO is this needed, if yes how much delay in worst case scenario */
5951                         msleep(1);
5952                         state->m_DRXK_A3_PATCH_CODE = true;
5953                         status = GetDeviceCapabilities(state);
5954                         if (status < 0)
5955                                 break;
5956
5957                         /* Bridge delay, uses oscilator clock */
5958                         /* Delay = (delay (nano seconds) * oscclk (kHz))/ 1000 */
5959                         /* SDA brdige delay */
5960                         state->m_HICfgBridgeDelay =
5961                             (u16) ((state->m_oscClockFreq / 1000) *
5962                                    HI_I2C_BRIDGE_DELAY) / 1000;
5963                         /* Clipping */
5964                         if (state->m_HICfgBridgeDelay >
5965                             SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) {
5966                                 state->m_HICfgBridgeDelay =
5967                                     SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M;
5968                         }
5969                         /* SCL bridge delay, same as SDA for now */
5970                         state->m_HICfgBridgeDelay +=
5971                             state->m_HICfgBridgeDelay <<
5972                             SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B;
5973
5974                         status = InitHI(state);
5975                         if (status < 0)
5976                                 break;
5977                         /* disable various processes */
5978 #if NOA1ROM
5979                         if (!(state->m_DRXK_A1_ROM_CODE)
5980                             && !(state->m_DRXK_A2_ROM_CODE))
5981 #endif
5982                         {
5983                                 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
5984                                 if (status < 0)
5985                                         break;
5986                         }
5987
5988                         /* disable MPEG port */
5989                         status = MPEGTSDisable(state);
5990                         if (status < 0)
5991                                 break;
5992
5993                         /* Stop AUD and SCU */
5994                         status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP);
5995                         if (status < 0)
5996                                 break;
5997                         status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP);
5998                         if (status < 0)
5999                                 break;
6000
6001                         /* enable token-ring bus through OFDM block for possible ucode upload */
6002                         status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_ON);
6003                         if (status < 0)
6004                                 break;
6005
6006                         /* include boot loader section */
6007                         status = write16(state, SIO_BL_COMM_EXEC__A, SIO_BL_COMM_EXEC_ACTIVE);
6008                         if (status < 0)
6009                                 break;
6010                         status = BLChainCmd(state, 0, 6, 100);
6011                         if (status < 0)
6012                                 break;
6013
6014                         if (!state->microcode_name)
6015                                 load_microcode(state, "drxk_a3.mc");
6016                         else
6017                                 load_microcode(state, state->microcode_name);
6018
6019                         /* disable token-ring bus through OFDM block for possible ucode upload */
6020                         status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_OFF);
6021                         if (status < 0)
6022                                 break;
6023
6024                         /* Run SCU for a little while to initialize microcode version numbers */
6025                         status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
6026                         if (status < 0)
6027                                 break;
6028                         status = DRXX_Open(state);
6029                         if (status < 0)
6030                                 break;
6031                         /* added for test */
6032                         msleep(30);
6033
6034                         powerMode = DRXK_POWER_DOWN_OFDM;
6035                         status = CtrlPowerMode(state, &powerMode);
6036                         if (status < 0)
6037                                 break;
6038
6039                         /* Stamp driver version number in SCU data RAM in BCD code
6040                            Done to enable field application engineers to retreive drxdriver version
6041                            via I2C from SCU RAM.
6042                            Not using SCU command interface for SCU register access since no
6043                            microcode may be present.
6044                          */
6045                         driverVersion =
6046                             (((DRXK_VERSION_MAJOR / 100) % 10) << 12) +
6047                             (((DRXK_VERSION_MAJOR / 10) % 10) << 8) +
6048                             ((DRXK_VERSION_MAJOR % 10) << 4) +
6049                             (DRXK_VERSION_MINOR % 10);
6050                         status = write16(state, SCU_RAM_DRIVER_VER_HI__A, driverVersion);
6051                         if (status < 0)
6052                                 break;
6053                         driverVersion =
6054                             (((DRXK_VERSION_PATCH / 1000) % 10) << 12) +
6055                             (((DRXK_VERSION_PATCH / 100) % 10) << 8) +
6056                             (((DRXK_VERSION_PATCH / 10) % 10) << 4) +
6057                             (DRXK_VERSION_PATCH % 10);
6058                         status = write16(state, SCU_RAM_DRIVER_VER_LO__A, driverVersion);
6059                         if (status < 0)
6060                                 break;
6061
6062                         printk(KERN_INFO "DRXK driver version %d.%d.%d\n",
6063                                DRXK_VERSION_MAJOR, DRXK_VERSION_MINOR,
6064                                DRXK_VERSION_PATCH);
6065
6066                         /* Dirty fix of default values for ROM/PATCH microcode
6067                            Dirty because this fix makes it impossible to setup suitable values
6068                            before calling DRX_Open. This solution requires changes to RF AGC speed
6069                            to be done via the CTRL function after calling DRX_Open */
6070
6071                         /* m_dvbtRfAgcCfg.speed = 3; */
6072
6073                         /* Reset driver debug flags to 0 */
6074                         status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0);
6075                         if (status < 0)
6076                                 break;
6077                         /* driver 0.9.0 */
6078                         /* Setup FEC OC:
6079                            NOTE: No more full FEC resets allowed afterwards!! */
6080                         status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP);
6081                         if (status < 0)
6082                                 break;
6083                         /* MPEGTS functions are still the same */
6084                         status = MPEGTSDtoInit(state);
6085                         if (status < 0)
6086                                 break;
6087                         status = MPEGTSStop(state);
6088                         if (status < 0)
6089                                 break;
6090                         status = MPEGTSConfigurePolarity(state);
6091                         if (status < 0)
6092                                 break;
6093                         status = MPEGTSConfigurePins(state, state->m_enableMPEGOutput);
6094                         if (status < 0)
6095                                 break;
6096                         /* added: configure GPIO */
6097                         status = WriteGPIO(state);
6098                         if (status < 0)
6099                                 break;
6100
6101                         state->m_DrxkState = DRXK_STOPPED;
6102
6103                         if (state->m_bPowerDown) {
6104                                 status = PowerDownDevice(state);
6105                                 if (status < 0)
6106                                         break;
6107                                 state->m_DrxkState = DRXK_POWERED_DOWN;
6108                         } else
6109                                 state->m_DrxkState = DRXK_STOPPED;
6110                 } while (0);
6111         }
6112
6113         return 0;
6114 }
6115
6116 static void drxk_c_release(struct dvb_frontend *fe)
6117 {
6118         struct drxk_state *state = fe->demodulator_priv;
6119
6120         dprintk(1, "\n");
6121         kfree(state);
6122 }
6123
6124 static int drxk_c_init(struct dvb_frontend *fe)
6125 {
6126         struct drxk_state *state = fe->demodulator_priv;
6127
6128         dprintk(1, "\n");
6129         if (mutex_trylock(&state->ctlock) == 0)
6130                 return -EBUSY;
6131         SetOperationMode(state, OM_QAM_ITU_A);
6132         return 0;
6133 }
6134
6135 static int drxk_c_sleep(struct dvb_frontend *fe)
6136 {
6137         struct drxk_state *state = fe->demodulator_priv;
6138
6139         dprintk(1, "\n");
6140         ShutDown(state);
6141         mutex_unlock(&state->ctlock);
6142         return 0;
6143 }
6144
6145 static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable)
6146 {
6147         struct drxk_state *state = fe->demodulator_priv;
6148
6149         dprintk(1, "%s\n", enable ? "enable" : "disable");
6150         return ConfigureI2CBridge(state, enable ? true : false);
6151 }
6152
6153 static int drxk_set_parameters(struct dvb_frontend *fe,
6154                                struct dvb_frontend_parameters *p)
6155 {
6156         struct drxk_state *state = fe->demodulator_priv;
6157         u32 IF;
6158
6159         dprintk(1, "\n");
6160         if (fe->ops.i2c_gate_ctrl)
6161                 fe->ops.i2c_gate_ctrl(fe, 1);
6162         if (fe->ops.tuner_ops.set_params)
6163                 fe->ops.tuner_ops.set_params(fe, p);
6164         if (fe->ops.i2c_gate_ctrl)
6165                 fe->ops.i2c_gate_ctrl(fe, 0);
6166         state->param = *p;
6167         fe->ops.tuner_ops.get_frequency(fe, &IF);
6168         Start(state, 0, IF);
6169
6170         /* printk(KERN_DEBUG "drxk: %s IF=%d done\n", __func__, IF); */
6171
6172         return 0;
6173 }
6174
6175 static int drxk_c_get_frontend(struct dvb_frontend *fe,
6176                                struct dvb_frontend_parameters *p)
6177 {
6178         dprintk(1, "\n");
6179         return 0;
6180 }
6181
6182 static int drxk_read_status(struct dvb_frontend *fe, fe_status_t *status)
6183 {
6184         struct drxk_state *state = fe->demodulator_priv;
6185         u32 stat;
6186
6187         dprintk(1, "\n");
6188         *status = 0;
6189         GetLockStatus(state, &stat, 0);
6190         if (stat == MPEG_LOCK)
6191                 *status |= 0x1f;
6192         if (stat == FEC_LOCK)
6193                 *status |= 0x0f;
6194         if (stat == DEMOD_LOCK)
6195                 *status |= 0x07;
6196         return 0;
6197 }
6198
6199 static int drxk_read_ber(struct dvb_frontend *fe, u32 *ber)
6200 {
6201         dprintk(1, "\n");
6202
6203         *ber = 0;
6204         return 0;
6205 }
6206
6207 static int drxk_read_signal_strength(struct dvb_frontend *fe,
6208                                      u16 *strength)
6209 {
6210         struct drxk_state *state = fe->demodulator_priv;
6211         u32 val;
6212
6213         dprintk(1, "\n");
6214         ReadIFAgc(state, &val);
6215         *strength = val & 0xffff;
6216         return 0;
6217 }
6218
6219 static int drxk_read_snr(struct dvb_frontend *fe, u16 *snr)
6220 {
6221         struct drxk_state *state = fe->demodulator_priv;
6222         s32 snr2;
6223
6224         dprintk(1, "\n");
6225         GetSignalToNoise(state, &snr2);
6226         *snr = snr2 & 0xffff;
6227         return 0;
6228 }
6229
6230 static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
6231 {
6232         struct drxk_state *state = fe->demodulator_priv;
6233         u16 err;
6234
6235         dprintk(1, "\n");
6236         DVBTQAMGetAccPktErr(state, &err);
6237         *ucblocks = (u32) err;
6238         return 0;
6239 }
6240
6241 static int drxk_c_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings
6242                                     *sets)
6243 {
6244         dprintk(1, "\n");
6245         sets->min_delay_ms = 3000;
6246         sets->max_drift = 0;
6247         sets->step_size = 0;
6248         return 0;
6249 }
6250
6251 static void drxk_t_release(struct dvb_frontend *fe)
6252 {
6253 #if 0
6254         struct drxk_state *state = fe->demodulator_priv;
6255
6256         dprintk(1, "\n");
6257         kfree(state);
6258 #endif
6259 }
6260
6261 static int drxk_t_init(struct dvb_frontend *fe)
6262 {
6263         struct drxk_state *state = fe->demodulator_priv;
6264
6265         dprintk(1, "\n");
6266         if (mutex_trylock(&state->ctlock) == 0)
6267                 return -EBUSY;
6268         SetOperationMode(state, OM_DVBT);
6269         return 0;
6270 }
6271
6272 static int drxk_t_sleep(struct dvb_frontend *fe)
6273 {
6274         struct drxk_state *state = fe->demodulator_priv;
6275
6276         dprintk(1, "\n");
6277         mutex_unlock(&state->ctlock);
6278         return 0;
6279 }
6280
6281 static int drxk_t_get_frontend(struct dvb_frontend *fe,
6282                                struct dvb_frontend_parameters *p)
6283 {
6284         dprintk(1, "\n");
6285
6286         return 0;
6287 }
6288
6289 static struct dvb_frontend_ops drxk_c_ops = {
6290         .info = {
6291                  .name = "DRXK DVB-C",
6292                  .type = FE_QAM,
6293                  .frequency_stepsize = 62500,
6294                  .frequency_min = 47000000,
6295                  .frequency_max = 862000000,
6296                  .symbol_rate_min = 870000,
6297                  .symbol_rate_max = 11700000,
6298                  .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
6299                  FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO},
6300         .release = drxk_c_release,
6301         .init = drxk_c_init,
6302         .sleep = drxk_c_sleep,
6303         .i2c_gate_ctrl = drxk_gate_ctrl,
6304
6305         .set_frontend = drxk_set_parameters,
6306         .get_frontend = drxk_c_get_frontend,
6307         .get_tune_settings = drxk_c_get_tune_settings,
6308
6309         .read_status = drxk_read_status,
6310         .read_ber = drxk_read_ber,
6311         .read_signal_strength = drxk_read_signal_strength,
6312         .read_snr = drxk_read_snr,
6313         .read_ucblocks = drxk_read_ucblocks,
6314 };
6315
6316 static struct dvb_frontend_ops drxk_t_ops = {
6317         .info = {
6318                  .name = "DRXK DVB-T",
6319                  .type = FE_OFDM,
6320                  .frequency_min = 47125000,
6321                  .frequency_max = 865000000,
6322                  .frequency_stepsize = 166667,
6323                  .frequency_tolerance = 0,
6324                  .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
6325                  FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
6326                  FE_CAN_FEC_AUTO |
6327                  FE_CAN_QAM_16 | FE_CAN_QAM_64 |
6328                  FE_CAN_QAM_AUTO |
6329                  FE_CAN_TRANSMISSION_MODE_AUTO |
6330                  FE_CAN_GUARD_INTERVAL_AUTO |
6331                  FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | FE_CAN_MUTE_TS},
6332         .release = drxk_t_release,
6333         .init = drxk_t_init,
6334         .sleep = drxk_t_sleep,
6335         .i2c_gate_ctrl = drxk_gate_ctrl,
6336
6337         .set_frontend = drxk_set_parameters,
6338         .get_frontend = drxk_t_get_frontend,
6339
6340         .read_status = drxk_read_status,
6341         .read_ber = drxk_read_ber,
6342         .read_signal_strength = drxk_read_signal_strength,
6343         .read_snr = drxk_read_snr,
6344         .read_ucblocks = drxk_read_ucblocks,
6345 };
6346
6347 struct dvb_frontend *drxk_attach(const struct drxk_config *config,
6348                                  struct i2c_adapter *i2c,
6349                                  struct dvb_frontend **fe_t)
6350 {
6351         struct drxk_state *state = NULL;
6352         u8 adr = config->adr;
6353
6354         dprintk(1, "\n");
6355         state = kzalloc(sizeof(struct drxk_state), GFP_KERNEL);
6356         if (!state)
6357                 return NULL;
6358
6359         state->i2c = i2c;
6360         state->demod_address = adr;
6361         state->single_master = config->single_master;
6362         state->microcode_name = config->microcode_name;
6363
6364         mutex_init(&state->mutex);
6365         mutex_init(&state->ctlock);
6366
6367         memcpy(&state->c_frontend.ops, &drxk_c_ops,
6368                sizeof(struct dvb_frontend_ops));
6369         memcpy(&state->t_frontend.ops, &drxk_t_ops,
6370                sizeof(struct dvb_frontend_ops));
6371         state->c_frontend.demodulator_priv = state;
6372         state->t_frontend.demodulator_priv = state;
6373
6374         init_state(state);
6375         if (init_drxk(state) < 0)
6376                 goto error;
6377         *fe_t = &state->t_frontend;
6378         return &state->c_frontend;
6379
6380 error:
6381         printk(KERN_ERR "drxk: not found\n");
6382         kfree(state);
6383         return NULL;
6384 }
6385 EXPORT_SYMBOL(drxk_attach);
6386
6387 MODULE_DESCRIPTION("DRX-K driver");
6388 MODULE_AUTHOR("Ralph Metzler");
6389 MODULE_LICENSE("GPL");