drivers/media/dvb/frontends/drxd_hard.c

   1 /*
   2  * drxd_hard.c: DVB-T Demodulator Micronas DRX3975D-A2,DRX397xD-B1
   3  *
   4  * Copyright (C) 2003-2007 Micronas
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * version 2 only, as published by the Free Software Foundation.
   9  *
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  20  * 02110-1301, USA
  21  * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/module.h>
  26 #include <linux/moduleparam.h>
  27 #include <linux/init.h>
  28 #include <linux/delay.h>
  29 #include <linux/firmware.h>
  30 #include <linux/i2c.h>
  31 #include <linux/version.h>
  32 #include <asm/div64.h>
  33
  34 #include "dvb_frontend.h"
  35 #include "drxd.h"
  36 #include "drxd_firm.h"
  37
  38 #define DRX_FW_FILENAME_A2 "drxd-a2-1.1.fw"
  39 #define DRX_FW_FILENAME_B1 "drxd-b1-1.1.fw"
  40
  41 #define CHUNK_SIZE 48
  42
  43 #define DRX_I2C_RMW           0x10
  44 #define DRX_I2C_BROADCAST     0x20
  45 #define DRX_I2C_CLEARCRC      0x80
  46 #define DRX_I2C_SINGLE_MASTER 0xC0
  47 #define DRX_I2C_MODEFLAGS     0xC0
  48 #define DRX_I2C_FLAGS         0xF0
  49
  50 #ifndef SIZEOF_ARRAY
  51 #define SIZEOF_ARRAY(array) (sizeof((array))/sizeof((array)[0]))
  52 #endif
  53
  54 #define DEFAULT_LOCK_TIMEOUT    1100
  55
  56 #define DRX_CHANNEL_AUTO 0
  57 #define DRX_CHANNEL_HIGH 1
  58 #define DRX_CHANNEL_LOW  2
  59
  60 #define DRX_LOCK_MPEG  1
  61 #define DRX_LOCK_FEC   2
  62 #define DRX_LOCK_DEMOD 4
  63
  64 /****************************************************************************/
  65
  66 enum CSCDState {
  67         CSCD_INIT = 0,
  68         CSCD_SET,
  69         CSCD_SAVED
  70 };
  71
  72 enum CDrxdState {
  73         DRXD_UNINITIALIZED = 0,
  74         DRXD_STOPPED,
  75         DRXD_STARTED
  76 };
  77
  78 enum AGC_CTRL_MODE {
  79         AGC_CTRL_AUTO = 0,
  80         AGC_CTRL_USER,
  81         AGC_CTRL_OFF
  82 };
  83
  84 enum OperationMode {
  85         OM_Default,
  86         OM_DVBT_Diversity_Front,
  87         OM_DVBT_Diversity_End
  88 };
  89
  90 struct SCfgAgc {
  91         enum AGC_CTRL_MODE ctrlMode;
  92         u16 outputLevel;        /* range [0, ... , 1023], 1/n of fullscale range */
  93         u16 settleLevel;        /* range [0, ... , 1023], 1/n of fullscale range */
  94         u16 minOutputLevel;     /* range [0, ... , 1023], 1/n of fullscale range */
  95         u16 maxOutputLevel;     /* range [0, ... , 1023], 1/n of fullscale range */
  96         u16 speed;              /* range [0, ... , 1023], 1/n of fullscale range */
  97
  98         u16 R1;
  99         u16 R2;
 100         u16 R3;
 101 };
 102
 103 struct SNoiseCal {
 104         int cpOpt;
 105         u16 cpNexpOfs;
 106         u16 tdCal2k;
 107         u16 tdCal8k;
 108 };
 109
 110 enum app_env {
 111         APPENV_STATIC = 0,
 112         APPENV_PORTABLE = 1,
 113         APPENV_MOBILE = 2
 114 };
 115
 116 enum EIFFilter {
 117         IFFILTER_SAW = 0,
 118         IFFILTER_DISCRETE = 1
 119 };
 120
 121 struct drxd_state {
 122         struct dvb_frontend frontend;
 123         struct dvb_frontend_ops ops;
 124         struct dvb_frontend_parameters param;
 125
 126         const struct firmware *fw;
 127         struct device *dev;
 128
 129         struct i2c_adapter *i2c;
 130         void *priv;
 131         struct drxd_config config;
 132
 133         int i2c_access;
 134         int init_done;
 135         struct mutex mutex;
 136
 137         u8 chip_adr;
 138         u16 hi_cfg_timing_div;
 139         u16 hi_cfg_bridge_delay;
 140         u16 hi_cfg_wakeup_key;
 141         u16 hi_cfg_ctrl;
 142
 143         u16 intermediate_freq;
 144         u16 osc_clock_freq;
 145
 146         enum CSCDState cscd_state;
 147         enum CDrxdState drxd_state;
 148
 149         u16 sys_clock_freq;
 150         s16 osc_clock_deviation;
 151         u16 expected_sys_clock_freq;
 152
 153         u16 insert_rs_byte;
 154         u16 enable_parallel;
 155
 156         int operation_mode;
 157
 158         struct SCfgAgc if_agc_cfg;
 159         struct SCfgAgc rf_agc_cfg;
 160
 161         struct SNoiseCal noise_cal;
 162
 163         u32 fe_fs_add_incr;
 164         u32 org_fe_fs_add_incr;
 165         u16 current_fe_if_incr;
 166
 167         u16 m_FeAgRegAgPwd;
 168         u16 m_FeAgRegAgAgcSio;
 169
 170         u16 m_EcOcRegOcModeLop;
 171         u16 m_EcOcRegSncSncLvl;
 172         u8 *m_InitAtomicRead;
 173         u8 *m_HiI2cPatch;
 174
 175         u8 *m_ResetCEFR;
 176         u8 *m_InitFE_1;
 177         u8 *m_InitFE_2;
 178         u8 *m_InitCP;
 179         u8 *m_InitCE;
 180         u8 *m_InitEQ;
 181         u8 *m_InitSC;
 182         u8 *m_InitEC;
 183         u8 *m_ResetECRAM;
 184         u8 *m_InitDiversityFront;
 185         u8 *m_InitDiversityEnd;
 186         u8 *m_DisableDiversity;
 187         u8 *m_StartDiversityFront;
 188         u8 *m_StartDiversityEnd;
 189
 190         u8 *m_DiversityDelay8MHZ;
 191         u8 *m_DiversityDelay6MHZ;
 192
 193         u8 *microcode;
 194         u32 microcode_length;
 195
 196         int type_A;
 197         int PGA;
 198         int diversity;
 199         int tuner_mirrors;
 200
 201         enum app_env app_env_default;
 202         enum app_env app_env_diversity;
 203
 204 };
 205
 206 /****************************************************************************/
 207 /* I2C **********************************************************************/
 208 /****************************************************************************/
 209
 210 static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 * data, int len)
 211 {
 212         struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = data, .len = len };
 213
 214         if (i2c_transfer(adap, &msg, 1) != 1)
 215                 return -1;
 216         return 0;
 217 }
 218
 219 static int i2c_read(struct i2c_adapter *adap,
 220                     u8 adr, u8 *msg, int len, u8 *answ, int alen)
 221 {
 222         struct i2c_msg msgs[2] = {
 223                 {
 224                         .addr = adr, .flags = 0,
 225                         .buf = msg, .len = len
 226                 }, {
 227                         .addr = adr, .flags = I2C_M_RD,
 228                         .buf = answ, .len = alen
 229                 }
 230         };
 231         if (i2c_transfer(adap, msgs, 2) != 2)
 232                 return -1;
 233         return 0;
 234 }
 235
 236 inline u32 MulDiv32(u32 a, u32 b, u32 c)
 237 {
 238         u64 tmp64;
 239
 240         tmp64 = (u64)a * (u64)b;
 241         do_div(tmp64, c);
 242
 243         return (u32) tmp64;
 244 }
 245
 246 static int Read16(struct drxd_state *state, u32 reg, u16 *data, u8 flags)
 247 {
 248         u8 adr = state->config.demod_address;
 249         u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff,
 250                 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
 251         };
 252         u8 mm2[2];
 253         if (i2c_read(state->i2c, adr, mm1, 4, mm2, 2) < 0)
 254                 return -1;
 255         if (data)
 256                 *data = mm2[0] | (mm2[1] << 8);
 257         return mm2[0] | (mm2[1] << 8);
 258 }
 259
 260 static int Read32(struct drxd_state *state, u32 reg, u32 *data, u8 flags)
 261 {
 262         u8 adr = state->config.demod_address;
 263         u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff,
 264                 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
 265         };
 266         u8 mm2[4];
 267
 268         if (i2c_read(state->i2c, adr, mm1, 4, mm2, 4) < 0)
 269                 return -1;
 270         if (data)
 271                 *data =
 272                     mm2[0] | (mm2[1] << 8) | (mm2[2] << 16) | (mm2[3] << 24);
 273         return 0;
 274 }
 275
 276 static int Write16(struct drxd_state *state, u32 reg, u16 data, u8 flags)
 277 {
 278         u8 adr = state->config.demod_address;
 279         u8 mm[6] = { reg & 0xff, (reg >> 16) & 0xff,
 280                 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff,
 281                 data & 0xff, (data >> 8) & 0xff
 282         };
 283
 284         if (i2c_write(state->i2c, adr, mm, 6) < 0)
 285                 return -1;
 286         return 0;
 287 }
 288
 289 static int Write32(struct drxd_state *state, u32 reg, u32 data, u8 flags)
 290 {
 291         u8 adr = state->config.demod_address;
 292         u8 mm[8] = { reg & 0xff, (reg >> 16) & 0xff,
 293                 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff,
 294                 data & 0xff, (data >> 8) & 0xff,
 295                 (data >> 16) & 0xff, (data >> 24) & 0xff
 296         };
 297
 298         if (i2c_write(state->i2c, adr, mm, 8) < 0)
 299                 return -1;
 300         return 0;
 301 }
 302
 303 static int write_chunk(struct drxd_state *state,
 304                        u32 reg, u8 *data, u32 len, u8 flags)
 305 {
 306         u8 adr = state->config.demod_address;
 307         u8 mm[CHUNK_SIZE + 4] = { reg & 0xff, (reg >> 16) & 0xff,
 308                 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
 309         };
 310         int i;
 311
 312         for (i = 0; i < len; i++)
 313                 mm[4 + i] = data[i];
 314         if (i2c_write(state->i2c, adr, mm, 4 + len) < 0) {
 315                 printk(KERN_ERR "error in write_chunk\n");
 316                 return -1;
 317         }
 318         return 0;
 319 }
 320
 321 static int WriteBlock(struct drxd_state *state,
 322                       u32 Address, u16 BlockSize, u8 *pBlock, u8 Flags)
 323 {
 324         while (BlockSize > 0) {
 325                 u16 Chunk = BlockSize > CHUNK_SIZE ? CHUNK_SIZE : BlockSize;
 326
 327                 if (write_chunk(state, Address, pBlock, Chunk, Flags) < 0)
 328                         return -1;
 329                 pBlock += Chunk;
 330                 Address += (Chunk >> 1);
 331                 BlockSize -= Chunk;
 332         }
 333         return 0;
 334 }
 335
 336 static int WriteTable(struct drxd_state *state, u8 * pTable)
 337 {
 338         int status = 0;
 339
 340         if (pTable == NULL)
 341                 return 0;
 342
 343         while (!status) {
 344                 u16 Length;
 345                 u32 Address = pTable[0] | (pTable[1] << 8) |
 346                     (pTable[2] << 16) | (pTable[3] << 24);
 347
 348                 if (Address == 0xFFFFFFFF)
 349                         break;
 350                 pTable += sizeof(u32);
 351
 352                 Length = pTable[0] | (pTable[1] << 8);
 353                 pTable += sizeof(u16);
 354                 if (!Length)
 355                         break;
 356                 status = WriteBlock(state, Address, Length * 2, pTable, 0);
 357                 pTable += (Length * 2);
 358         }
 359         return status;
 360 }
 361
 362 /****************************************************************************/
 363 /****************************************************************************/
 364 /****************************************************************************/
 365
 366 static int ResetCEFR(struct drxd_state *state)
 367 {
 368         return WriteTable(state, state->m_ResetCEFR);
 369 }
 370
 371 static int InitCP(struct drxd_state *state)
 372 {
 373         return WriteTable(state, state->m_InitCP);
 374 }
 375
 376 static int InitCE(struct drxd_state *state)
 377 {
 378         int status;
 379         enum app_env AppEnv = state->app_env_default;
 380
 381         do {
 382                 status = WriteTable(state, state->m_InitCE);
 383                 if (status < 0)
 384                         break;
 385
 386                 if (state->operation_mode == OM_DVBT_Diversity_Front ||
 387                     state->operation_mode == OM_DVBT_Diversity_End) {
 388                         AppEnv = state->app_env_diversity;
 389                 }
 390                 if (AppEnv == APPENV_STATIC) {
 391                         status = Write16(state, CE_REG_TAPSET__A, 0x0000, 0);
 392                         if (status < 0)
 393                                 break;
 394                 } else if (AppEnv == APPENV_PORTABLE) {
 395                         status = Write16(state, CE_REG_TAPSET__A, 0x0001, 0);
 396                         if (status < 0)
 397                                 break;
 398                 } else if (AppEnv == APPENV_MOBILE && state->type_A) {
 399                         status = Write16(state, CE_REG_TAPSET__A, 0x0002, 0);
 400                         if (status < 0)
 401                                 break;
 402                 } else if (AppEnv == APPENV_MOBILE && !state->type_A) {
 403                         status = Write16(state, CE_REG_TAPSET__A, 0x0006, 0);
 404                         if (status < 0)
 405                                 break;
 406                 }
 407
 408                 /* start ce */
 409                 status = Write16(state, B_CE_REG_COMM_EXEC__A, 0x0001, 0);
 410                 if (status < 0)
 411                         break;
 412         } while (0);
 413         return status;
 414 }
 415
 416 static int StopOC(struct drxd_state *state)
 417 {
 418         int status = 0;
 419         u16 ocSyncLvl = 0;
 420         u16 ocModeLop = state->m_EcOcRegOcModeLop;
 421         u16 dtoIncLop = 0;
 422         u16 dtoIncHip = 0;
 423
 424         do {
 425                 /* Store output configuration */
 426                 status = Read16(state, EC_OC_REG_SNC_ISC_LVL__A, &ocSyncLvl, 0);
 427                 if (status < 0)
 428                         break;
 429                 /* CHK_ERROR(Read16(EC_OC_REG_OC_MODE_LOP__A, &ocModeLop)); */
 430                 state->m_EcOcRegSncSncLvl = ocSyncLvl;
 431                 /* m_EcOcRegOcModeLop = ocModeLop; */
 432
 433                 /* Flush FIFO (byte-boundary) at fixed rate */
 434                 status = Read16(state, EC_OC_REG_RCN_MAP_LOP__A, &dtoIncLop, 0);
 435                 if (status < 0)
 436                         break;
 437                 status = Read16(state, EC_OC_REG_RCN_MAP_HIP__A, &dtoIncHip, 0);
 438                 if (status < 0)
 439                         break;
 440                 status = Write16(state, EC_OC_REG_DTO_INC_LOP__A, dtoIncLop, 0);
 441                 if (status < 0)
 442                         break;
 443                 status = Write16(state, EC_OC_REG_DTO_INC_HIP__A, dtoIncHip, 0);
 444                 if (status < 0)
 445                         break;
 446                 ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M);
 447                 ocModeLop |= EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC;
 448                 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0);
 449                 if (status < 0)
 450                         break;
 451                 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0);
 452                 if (status < 0)
 453                         break;
 454
 455                 msleep(1);
 456                 /* Output pins to '0' */
 457                 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS__M, 0);
 458                 if (status < 0)
 459                         break;
 460
 461                 /* Force the OC out of sync */
 462                 ocSyncLvl &= ~(EC_OC_REG_SNC_ISC_LVL_OSC__M);
 463                 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, ocSyncLvl, 0);
 464                 if (status < 0)
 465                         break;
 466                 ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M);
 467                 ocModeLop |= EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE;
 468                 ocModeLop |= 0x2;       /* Magically-out-of-sync */
 469                 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0);
 470                 if (status < 0)
 471                         break;
 472                 status = Write16(state, EC_OC_REG_COMM_INT_STA__A, 0x0, 0);
 473                 if (status < 0)
 474                         break;
 475                 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0);
 476                 if (status < 0)
 477                         break;
 478         } while (0);
 479
 480         return status;
 481 }
 482
 483 static int StartOC(struct drxd_state *state)
 484 {
 485         int status = 0;
 486
 487         do {
 488                 /* Stop OC */
 489                 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0);
 490                 if (status < 0)
 491                         break;
 492
 493                 /* Restore output configuration */
 494                 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, state->m_EcOcRegSncSncLvl, 0);
 495                 if (status < 0)
 496                         break;
 497                 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, state->m_EcOcRegOcModeLop, 0);
 498                 if (status < 0)
 499                         break;
 500
 501                 /* Output pins active again */
 502                 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS_INIT, 0);
 503                 if (status < 0)
 504                         break;
 505
 506                 /* Start OC */
 507                 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0);
 508                 if (status < 0)
 509                         break;
 510         } while (0);
 511         return status;
 512 }
 513
 514 static int InitEQ(struct drxd_state *state)
 515 {
 516         return WriteTable(state, state->m_InitEQ);
 517 }
 518
 519 static int InitEC(struct drxd_state *state)
 520 {
 521         return WriteTable(state, state->m_InitEC);
 522 }
 523
 524 static int InitSC(struct drxd_state *state)
 525 {
 526         return WriteTable(state, state->m_InitSC);
 527 }
 528
 529 static int InitAtomicRead(struct drxd_state *state)
 530 {
 531         return WriteTable(state, state->m_InitAtomicRead);
 532 }
 533
 534 static int CorrectSysClockDeviation(struct drxd_state *state);
 535
 536 static int DRX_GetLockStatus(struct drxd_state *state, u32 * pLockStatus)
 537 {
 538         u16 ScRaRamLock = 0;
 539         const u16 mpeg_lock_mask = (SC_RA_RAM_LOCK_MPEG__M |
 540                                     SC_RA_RAM_LOCK_FEC__M |
 541                                     SC_RA_RAM_LOCK_DEMOD__M);
 542         const u16 fec_lock_mask = (SC_RA_RAM_LOCK_FEC__M |
 543                                    SC_RA_RAM_LOCK_DEMOD__M);
 544         const u16 demod_lock_mask = SC_RA_RAM_LOCK_DEMOD__M;
 545
 546         int status;
 547
 548         *pLockStatus = 0;
 549
 550         status = Read16(state, SC_RA_RAM_LOCK__A, &ScRaRamLock, 0x0000);
 551         if (status < 0) {
 552                 printk(KERN_ERR "Can't read SC_RA_RAM_LOCK__A status = %08x\n", status);
 553                 return status;
 554         }
 555
 556         if (state->drxd_state != DRXD_STARTED)
 557                 return 0;
 558
 559         if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask) {
 560                 *pLockStatus |= DRX_LOCK_MPEG;
 561                 CorrectSysClockDeviation(state);
 562         }
 563
 564         if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask)
 565                 *pLockStatus |= DRX_LOCK_FEC;
 566
 567         if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask)
 568                 *pLockStatus |= DRX_LOCK_DEMOD;
 569         return 0;
 570 }
 571
 572 /****************************************************************************/
 573
 574 static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
 575 {
 576         int status;
 577
 578         if (cfg->outputLevel > DRXD_FE_CTRL_MAX)
 579                 return -1;
 580
 581         if (cfg->ctrlMode == AGC_CTRL_USER) {
 582                 do {
 583                         u16 FeAgRegPm1AgcWri;
 584                         u16 FeAgRegAgModeLop;
 585
 586                         status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0);
 587                         if (status < 0)
 588                                 break;
 589                         FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
 590                         FeAgRegAgModeLop |= FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC;
 591                         status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0);
 592                         if (status < 0)
 593                                 break;
 594
 595                         FeAgRegPm1AgcWri = (u16) (cfg->outputLevel &
 596                                                   FE_AG_REG_PM1_AGC_WRI__M);
 597                         status = Write16(state, FE_AG_REG_PM1_AGC_WRI__A, FeAgRegPm1AgcWri, 0);
 598                         if (status < 0)
 599                                 break;
 600                 } while (0);
 601         } else if (cfg->ctrlMode == AGC_CTRL_AUTO) {
 602                 if (((cfg->maxOutputLevel) < (cfg->minOutputLevel)) ||
 603                     ((cfg->maxOutputLevel) > DRXD_FE_CTRL_MAX) ||
 604                     ((cfg->speed) > DRXD_FE_CTRL_MAX) ||
 605                     ((cfg->settleLevel) > DRXD_FE_CTRL_MAX)
 606                     )
 607                         return -1;
 608                 do {
 609                         u16 FeAgRegAgModeLop;
 610                         u16 FeAgRegEgcSetLvl;
 611                         u16 slope, offset;
 612
 613                         /* == Mode == */
 614
 615                         status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0);
 616                         if (status < 0)
 617                                 break;
 618                         FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
 619                         FeAgRegAgModeLop |=
 620                             FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC;
 621                         status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0);
 622                         if (status < 0)
 623                                 break;
 624
 625                         /* == Settle level == */
 626
 627                         FeAgRegEgcSetLvl = (u16) ((cfg->settleLevel >> 1) &
 628                                                   FE_AG_REG_EGC_SET_LVL__M);
 629                         status = Write16(state, FE_AG_REG_EGC_SET_LVL__A, FeAgRegEgcSetLvl, 0);
 630                         if (status < 0)
 631                                 break;
 632
 633                         /* == Min/Max == */
 634
 635                         slope = (u16) ((cfg->maxOutputLevel -
 636                                         cfg->minOutputLevel) / 2);
 637                         offset = (u16) ((cfg->maxOutputLevel +
 638                                          cfg->minOutputLevel) / 2 - 511);
 639
 640                         status = Write16(state, FE_AG_REG_GC1_AGC_RIC__A, slope, 0);
 641                         if (status < 0)
 642                                 break;
 643                         status = Write16(state, FE_AG_REG_GC1_AGC_OFF__A, offset, 0);
 644                         if (status < 0)
 645                                 break;
 646
 647                         /* == Speed == */
 648                         {
 649                                 const u16 maxRur = 8;
 650                                 const u16 slowIncrDecLUT[] = { 3, 4, 4, 5, 6 };
 651                                 const u16 fastIncrDecLUT[] = { 14, 15, 15, 16,
 652                                         17, 18, 18, 19,
 653                                         20, 21, 22, 23,
 654                                         24, 26, 27, 28,
 655                                         29, 31
 656                                 };
 657
 658                                 u16 fineSteps = (DRXD_FE_CTRL_MAX + 1) /
 659                                     (maxRur + 1);
 660                                 u16 fineSpeed = (u16) (cfg->speed -
 661                                                        ((cfg->speed /
 662                                                          fineSteps) *
 663                                                         fineSteps));
 664                                 u16 invRurCount = (u16) (cfg->speed /
 665                                                          fineSteps);
 666                                 u16 rurCount;
 667                                 if (invRurCount > maxRur) {
 668                                         rurCount = 0;
 669                                         fineSpeed += fineSteps;
 670                                 } else {
 671                                         rurCount = maxRur - invRurCount;
 672                                 }
 673
 674                                 /*
 675                                    fastInc = default *
 676                                    (2^(fineSpeed/fineSteps))
 677                                    => range[default...2*default>
 678                                    slowInc = default *
 679                                    (2^(fineSpeed/fineSteps))
 680                                  */
 681                                 {
 682                                         u16 fastIncrDec =
 683                                             fastIncrDecLUT[fineSpeed /
 684                                                            ((fineSteps /
 685                                                              (14 + 1)) + 1)];
 686                                         u16 slowIncrDec =
 687                                             slowIncrDecLUT[fineSpeed /
 688                                                            (fineSteps /
 689                                                             (3 + 1))];
 690
 691                                         status = Write16(state, FE_AG_REG_EGC_RUR_CNT__A, rurCount, 0);
 692                                         if (status < 0)
 693                                                 break;
 694                                         status = Write16(state, FE_AG_REG_EGC_FAS_INC__A, fastIncrDec, 0);
 695                                         if (status < 0)
 696                                                 break;
 697                                         status = Write16(state, FE_AG_REG_EGC_FAS_DEC__A, fastIncrDec, 0);
 698                                         if (status < 0)
 699                                                 break;
 700                                         status = Write16(state, FE_AG_REG_EGC_SLO_INC__A, slowIncrDec, 0);
 701                                         if (status < 0)
 702                                                 break;
 703                                         status = Write16(state, FE_AG_REG_EGC_SLO_DEC__A, slowIncrDec, 0);
 704                                         if (status < 0)
 705                                                 break;
 706                                 }
 707                         }
 708                 } while (0);
 709
 710         } else {
 711                 /* No OFF mode for IF control */
 712                 return -1;
 713         }
 714         return status;
 715 }
 716
 717 static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
 718 {
 719         int status = 0;
 720
 721         if (cfg->outputLevel > DRXD_FE_CTRL_MAX)
 722                 return -1;
 723
 724         if (cfg->ctrlMode == AGC_CTRL_USER) {
 725                 do {
 726                         u16 AgModeLop = 0;
 727                         u16 level = (cfg->outputLevel);
 728
 729                         if (level == DRXD_FE_CTRL_MAX)
 730                                 level++;
 731
 732                         status = Write16(state, FE_AG_REG_PM2_AGC_WRI__A, level, 0x0000);
 733                         if (status < 0)
 734                                 break;
 735
 736                         /*==== Mode ====*/
 737
 738                         /* Powerdown PD2, WRI source */
 739                         state->m_FeAgRegAgPwd &= ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
 740                         state->m_FeAgRegAgPwd |=
 741                             FE_AG_REG_AG_PWD_PWD_PD2_DISABLE;
 742                         status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000);
 743                         if (status < 0)
 744                                 break;
 745
 746                         status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
 747                         if (status < 0)
 748                                 break;
 749                         AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
 750                                         FE_AG_REG_AG_MODE_LOP_MODE_E__M));
 751                         AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
 752                                       FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC);
 753                         status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
 754                         if (status < 0)
 755                                 break;
 756
 757                         /* enable AGC2 pin */
 758                         {
 759                                 u16 FeAgRegAgAgcSio = 0;
 760                                 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
 761                                 if (status < 0)
 762                                         break;
 763                                 FeAgRegAgAgcSio &=
 764                                     ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
 765                                 FeAgRegAgAgcSio |=
 766                                     FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT;
 767                                 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
 768                                 if (status < 0)
 769                                         break;
 770                         }
 771
 772                 } while (0);
 773         } else if (cfg->ctrlMode == AGC_CTRL_AUTO) {
 774                 u16 AgModeLop = 0;
 775
 776                 do {
 777                         u16 level;
 778                         /* Automatic control */
 779                         /* Powerup PD2, AGC2 as output, TGC source */
 780                         (state->m_FeAgRegAgPwd) &=
 781                             ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
 782                         (state->m_FeAgRegAgPwd) |=
 783                             FE_AG_REG_AG_PWD_PWD_PD2_DISABLE;
 784                         status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000);
 785                         if (status < 0)
 786                                 break;
 787
 788                         status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
 789                         if (status < 0)
 790                                 break;
 791                         AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
 792                                         FE_AG_REG_AG_MODE_LOP_MODE_E__M));
 793                         AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
 794                                       FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC);
 795                         status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
 796                         if (status < 0)
 797                                 break;
 798                         /* Settle level */
 799                         level = (((cfg->settleLevel) >> 4) &
 800                                  FE_AG_REG_TGC_SET_LVL__M);
 801                         status = Write16(state, FE_AG_REG_TGC_SET_LVL__A, level, 0x0000);
 802                         if (status < 0)
 803                                 break;
 804
 805                         /* Min/max: don't care */
 806
 807                         /* Speed: TODO */
 808
 809                         /* enable AGC2 pin */
 810                         {
 811                                 u16 FeAgRegAgAgcSio = 0;
 812                                 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
 813                                 if (status < 0)
 814                                         break;
 815                                 FeAgRegAgAgcSio &=
 816                                     ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
 817                                 FeAgRegAgAgcSio |=
 818                                     FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT;
 819                                 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
 820                                 if (status < 0)
 821                                         break;
 822                         }
 823
 824                 } while (0);
 825         } else {
 826                 u16 AgModeLop = 0;
 827
 828                 do {
 829                         /* No RF AGC control */
 830                         /* Powerdown PD2, AGC2 as output, WRI source */
 831                         (state->m_FeAgRegAgPwd) &=
 832                             ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
 833                         (state->m_FeAgRegAgPwd) |=
 834                             FE_AG_REG_AG_PWD_PWD_PD2_ENABLE;
 835                         status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000);
 836                         if (status < 0)
 837                                 break;
 838
 839                         status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
 840                         if (status < 0)
 841                                 break;
 842                         AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
 843                                         FE_AG_REG_AG_MODE_LOP_MODE_E__M));
 844                         AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
 845                                       FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC);
 846                         status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
 847                         if (status < 0)
 848                                 break;
 849
 850                         /* set FeAgRegAgAgcSio AGC2 (RF) as input */
 851                         {
 852                                 u16 FeAgRegAgAgcSio = 0;
 853                                 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
 854                                 if (status < 0)
 855                                         break;
 856                                 FeAgRegAgAgcSio &=
 857                                     ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
 858                                 FeAgRegAgAgcSio |=
 859                                     FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT;
 860                                 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
 861                                 if (status < 0)
 862                                         break;
 863                         }
 864                 } while (0);
 865         }
 866         return status;
 867 }
 868
 869 static int ReadIFAgc(struct drxd_state *state, u32 * pValue)
 870 {
 871         int status = 0;
 872
 873         *pValue = 0;
 874         if (state->if_agc_cfg.ctrlMode != AGC_CTRL_OFF) {
 875                 u16 Value;
 876                 status = Read16(state, FE_AG_REG_GC1_AGC_DAT__A, &Value, 0);
 877                 Value &= FE_AG_REG_GC1_AGC_DAT__M;
 878                 if (status >= 0) {
 879                         /*           3.3V
 880                            |
 881                            R1
 882                            |
 883                            Vin - R3 - * -- Vout
 884                            |
 885                            R2
 886                            |
 887                            GND
 888                          */
 889                         u32 R1 = state->if_agc_cfg.R1;
 890                         u32 R2 = state->if_agc_cfg.R2;
 891                         u32 R3 = state->if_agc_cfg.R3;
 892
 893                         u32 Vmax = (3300 * R2) / (R1 + R2);
 894                         u32 Rpar = (R2 * R3) / (R3 + R2);
 895                         u32 Vmin = (3300 * Rpar) / (R1 + Rpar);
 896                         u32 Vout = Vmin + ((Vmax - Vmin) * Value) / 1024;
 897
 898                         *pValue = Vout;
 899                 }
 900         }
 901         return status;
 902 }
 903
 904 static int load_firmware(struct drxd_state *state, const char *fw_name)
 905 {
 906         const struct firmware *fw;
 907
 908         if (request_firmware(&fw, fw_name, state->dev) < 0) {
 909                 printk(KERN_ERR "drxd: firmware load failure [%s]\n", fw_name);
 910                 return -EIO;
 911         }
 912
 913         state->microcode = kzalloc(fw->size, GFP_KERNEL);
 914         if (state->microcode == NULL) {
 915                 printk(KERN_ERR "drxd: firmware load failure: nomemory\n");
 916                 return -ENOMEM;
 917         }
 918
 919         memcpy(state->microcode, fw->data, fw->size);
 920         state->microcode_length = fw->size;
 921         return 0;
 922 }
 923
 924 static int DownloadMicrocode(struct drxd_state *state,
 925                              const u8 *pMCImage, u32 Length)
 926 {
 927         u8 *pSrc;
 928         u16 Flags;
 929         u32 Address;
 930         u16 nBlocks;
 931         u16 BlockSize;
 932         u16 BlockCRC;
 933         u32 offset = 0;
 934         int i, status = 0;
 935
 936         pSrc = (u8 *) pMCImage;
 937         Flags = (pSrc[0] << 8) | pSrc[1];
 938         pSrc += sizeof(u16);
 939         offset += sizeof(u16);
 940         nBlocks = (pSrc[0] << 8) | pSrc[1];
 941         pSrc += sizeof(u16);
 942         offset += sizeof(u16);
 943
 944         for (i = 0; i < nBlocks; i++) {
 945                 Address = (pSrc[0] << 24) | (pSrc[1] << 16) |
 946                     (pSrc[2] << 8) | pSrc[3];
 947                 pSrc += sizeof(u32);
 948                 offset += sizeof(u32);
 949
 950                 BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16);
 951                 pSrc += sizeof(u16);
 952                 offset += sizeof(u16);
 953
 954                 Flags = (pSrc[0] << 8) | pSrc[1];
 955                 pSrc += sizeof(u16);
 956                 offset += sizeof(u16);
 957
 958                 BlockCRC = (pSrc[0] << 8) | pSrc[1];
 959                 pSrc += sizeof(u16);
 960                 offset += sizeof(u16);
 961
 962                 status = WriteBlock(state, Address, BlockSize,
 963                                     pSrc, DRX_I2C_CLEARCRC);
 964                 if (status < 0)
 965                         break;
 966                 pSrc += BlockSize;
 967                 offset += BlockSize;
 968         }
 969
 970         return status;
 971 }
 972
 973 static int HI_Command(struct drxd_state *state, u16 cmd, u16 * pResult)
 974 {
 975         u32 nrRetries = 0;
 976         u16 waitCmd;
 977         int status;
 978
 979         status = Write16(state, HI_RA_RAM_SRV_CMD__A, cmd, 0);
 980         if (status < 0)
 981                 return status;
 982
 983         do {
 984                 nrRetries += 1;
 985                 if (nrRetries > DRXD_MAX_RETRIES) {
 986                         status = -1;
 987                         break;
 988                 };
 989                 status = Read16(state, HI_RA_RAM_SRV_CMD__A, &waitCmd, 0);
 990         } while (waitCmd != 0);
 991
 992         if (status >= 0)
 993                 status = Read16(state, HI_RA_RAM_SRV_RES__A, pResult, 0);
 994         return status;
 995 }
 996
 997 static int HI_CfgCommand(struct drxd_state *state)
 998 {
 999         int status = 0;
1000
1001         mutex_lock(&state->mutex);
1002         Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0);
1003         Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, state->hi_cfg_timing_div, 0);
1004         Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, state->hi_cfg_bridge_delay, 0);
1005         Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, state->hi_cfg_wakeup_key, 0);
1006         Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, state->hi_cfg_ctrl, 0);
1007
1008         Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0);
1009
1010         if ((state->hi_cfg_ctrl & HI_RA_RAM_SRV_CFG_ACT_PWD_EXE) ==
1011             HI_RA_RAM_SRV_CFG_ACT_PWD_EXE)
1012                 status = Write16(state, HI_RA_RAM_SRV_CMD__A,
1013                                  HI_RA_RAM_SRV_CMD_CONFIG, 0);
1014         else
1015                 status = HI_Command(state, HI_RA_RAM_SRV_CMD_CONFIG, 0);
1016         mutex_unlock(&state->mutex);
1017         return status;
1018 }
1019
1020 static int InitHI(struct drxd_state *state)
1021 {
1022         state->hi_cfg_wakeup_key = (state->chip_adr);
1023         /* port/bridge/power down ctrl */
1024         state->hi_cfg_ctrl = HI_RA_RAM_SRV_CFG_ACT_SLV0_ON;
1025         return HI_CfgCommand(state);
1026 }
1027
1028 static int HI_ResetCommand(struct drxd_state *state)
1029 {
1030         int status;
1031
1032         mutex_lock(&state->mutex);
1033         status = Write16(state, HI_RA_RAM_SRV_RST_KEY__A,
1034                          HI_RA_RAM_SRV_RST_KEY_ACT, 0);
1035         if (status == 0)
1036                 status = HI_Command(state, HI_RA_RAM_SRV_CMD_RESET, 0);
1037         mutex_unlock(&state->mutex);
1038         msleep(1);
1039         return status;
1040 }
1041
1042 static int DRX_ConfigureI2CBridge(struct drxd_state *state, int bEnableBridge)
1043 {
1044         state->hi_cfg_ctrl &= (~HI_RA_RAM_SRV_CFG_ACT_BRD__M);
1045         if (bEnableBridge)
1046                 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_ON;
1047         else
1048                 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_OFF;
1049
1050         return HI_CfgCommand(state);
1051 }
1052
1053 #define HI_TR_WRITE      0x9
1054 #define HI_TR_READ       0xA
1055 #define HI_TR_READ_WRITE 0xB
1056 #define HI_TR_BROADCAST  0x4
1057
1058 #if 0
1059 static int AtomicReadBlock(struct drxd_state *state,
1060                            u32 Addr, u16 DataSize, u8 *pData, u8 Flags)
1061 {
1062         int status;
1063         int i = 0;
1064
1065         /* Parameter check */
1066         if ((!pData) || ((DataSize & 1) != 0))
1067                 return -1;
1068
1069         mutex_lock(&state->mutex);
1070
1071         do {
1072                 /* Instruct HI to read n bytes */
1073                 /* TODO use proper names forthese egisters */
1074                 status = Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, (HI_TR_FUNC_ADDR & 0xFFFF), 0);
1075                 if (status < 0)
1076                         break;
1077                 status = Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, (u16) (Addr >> 16), 0);
1078                 if (status < 0)
1079                         break;
1080                 status = Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, (u16) (Addr & 0xFFFF), 0);
1081                 if (status < 0)
1082                         break;
1083                 status = Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, (u16) ((DataSize / 2) - 1), 0);
1084                 if (status < 0)
1085                         break;
1086                 status = Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, HI_TR_READ, 0);
1087                 if (status < 0)
1088                         break;
1089
1090                 status = HI_Command(state, HI_RA_RAM_SRV_CMD_EXECUTE, 0);
1091                 if (status < 0)
1092                         break;
1093
1094         } while (0);
1095
1096         if (status >= 0) {
1097                 for (i = 0; i < (DataSize / 2); i += 1) {
1098                         u16 word;
1099
1100                         status = Read16(state, (HI_RA_RAM_USR_BEGIN__A + i),
1101                                         &word, 0);
1102                         if (status < 0)
1103                                 break;
1104                         pData[2 * i] = (u8) (word & 0xFF);
1105                         pData[(2 * i) + 1] = (u8) (word >> 8);
1106                 }
1107         }
1108         mutex_unlock(&state->mutex);
1109         return status;
1110 }
1111
1112 static int AtomicReadReg32(struct drxd_state *state,
1113                            u32 Addr, u32 *pData, u8 Flags)
1114 {
1115         u8 buf[sizeof(u32)];
1116         int status;
1117
1118         if (!pData)
1119                 return -1;
1120         status = AtomicReadBlock(state, Addr, sizeof(u32), buf, Flags);
1121         *pData = (((u32) buf[0]) << 0) +
1122             (((u32) buf[1]) << 8) +
1123             (((u32) buf[2]) << 16) + (((u32) buf[3]) << 24);
1124         return status;
1125 }
1126 #endif
1127
1128 static int StopAllProcessors(struct drxd_state *state)
1129 {
1130         return Write16(state, HI_COMM_EXEC__A,
1131                        SC_COMM_EXEC_CTL_STOP, DRX_I2C_BROADCAST);
1132 }
1133
1134 static int EnableAndResetMB(struct drxd_state *state)
1135 {
1136         if (state->type_A) {
1137                 /* disable? monitor bus observe @ EC_OC */
1138                 Write16(state, EC_OC_REG_OC_MON_SIO__A, 0x0000, 0x0000);
1139         }
1140
1141         /* do inverse broadcast, followed by explicit write to HI */
1142         Write16(state, HI_COMM_MB__A, 0x0000, DRX_I2C_BROADCAST);
1143         Write16(state, HI_COMM_MB__A, 0x0000, 0x0000);
1144         return 0;
1145 }
1146
1147 static int InitCC(struct drxd_state *state)
1148 {
1149         if (state->osc_clock_freq == 0 ||
1150             state->osc_clock_freq > 20000 ||
1151             (state->osc_clock_freq % 4000) != 0) {
1152                 printk(KERN_ERR "invalid osc frequency %d\n", state->osc_clock_freq);
1153                 return -1;
1154         }
1155
1156         Write16(state, CC_REG_OSC_MODE__A, CC_REG_OSC_MODE_M20, 0);
1157         Write16(state, CC_REG_PLL_MODE__A, CC_REG_PLL_MODE_BYPASS_PLL |
1158                 CC_REG_PLL_MODE_PUMP_CUR_12, 0);
1159         Write16(state, CC_REG_REF_DIVIDE__A, state->osc_clock_freq / 4000, 0);
1160         Write16(state, CC_REG_PWD_MODE__A, CC_REG_PWD_MODE_DOWN_PLL, 0);
1161         Write16(state, CC_REG_UPDATE__A, CC_REG_UPDATE_KEY, 0);
1162
1163         return 0;
1164 }
1165
1166 static int ResetECOD(struct drxd_state *state)
1167 {
1168         int status = 0;
1169
1170         if (state->type_A)
1171                 status = Write16(state, EC_OD_REG_SYNC__A, 0x0664, 0);
1172         else
1173                 status = Write16(state, B_EC_OD_REG_SYNC__A, 0x0664, 0);
1174
1175         if (!(status < 0))
1176                 status = WriteTable(state, state->m_ResetECRAM);
1177         if (!(status < 0))
1178                 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0001, 0);
1179         return status;
1180 }
1181
1182 /* Configure PGA switch */
1183
1184 static int SetCfgPga(struct drxd_state *state, int pgaSwitch)
1185 {
1186         int status;
1187         u16 AgModeLop = 0;
1188         u16 AgModeHip = 0;
1189         do {
1190                 if (pgaSwitch) {
1191                         /* PGA on */
1192                         /* fine gain */
1193                         status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
1194                         if (status < 0)
1195                                 break;
1196                         AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M));
1197                         AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC;
1198                         status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
1199                         if (status < 0)
1200                                 break;
1201
1202                         /* coarse gain */
1203                         status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000);
1204                         if (status < 0)
1205                                 break;
1206                         AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M));
1207                         AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC;
1208                         status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000);
1209                         if (status < 0)
1210                                 break;
1211
1212                         /* enable fine and coarse gain, enable AAF,
1213                            no ext resistor */
1214                         status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN, 0x0000);
1215                         if (status < 0)
1216                                 break;
1217                 } else {
1218                         /* PGA off, bypass */
1219
1220                         /* fine gain */
1221                         status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
1222                         if (status < 0)
1223                                 break;
1224                         AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M));
1225                         AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC;
1226                         status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
1227                         if (status < 0)
1228                                 break;
1229
1230                         /* coarse gain */
1231                         status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000);
1232                         if (status < 0)
1233                                 break;
1234                         AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M));
1235                         AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC;
1236                         status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000);
1237                         if (status < 0)
1238                                 break;
1239
1240                         /* disable fine and coarse gain, enable AAF,
1241                            no ext resistor */
1242                         status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000);
1243                         if (status < 0)
1244                                 break;
1245                 }
1246         } while (0);
1247         return status;
1248 }
1249
1250 static int InitFE(struct drxd_state *state)
1251 {
1252         int status;
1253
1254         do {
1255                 status = WriteTable(state, state->m_InitFE_1);
1256                 if (status < 0)
1257                         break;
1258
1259                 if (state->type_A) {
1260                         status = Write16(state, FE_AG_REG_AG_PGA_MODE__A,
1261                                          FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN,
1262                                          0);
1263                 } else {
1264                         if (state->PGA)
1265                                 status = SetCfgPga(state, 0);
1266                         else
1267                                 status =
1268                                     Write16(state, B_FE_AG_REG_AG_PGA_MODE__A,
1269                                             B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN,
1270                                             0);
1271                 }
1272
1273                 if (status < 0)
1274                         break;
1275                 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, state->m_FeAgRegAgAgcSio, 0x0000);
1276                 if (status < 0)
1277                         break;
1278                 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000);
1279                 if (status < 0)
1280                         break;
1281
1282                 status = WriteTable(state, state->m_InitFE_2);
1283                 if (status < 0)
1284                         break;
1285
1286         } while (0);
1287
1288         return status;
1289 }
1290
1291 static int InitFT(struct drxd_state *state)
1292 {
1293         /*
1294            norm OFFSET,  MB says =2 voor 8K en =3 voor 2K waarschijnlijk
1295            SC stuff
1296          */
1297         return Write16(state, FT_REG_COMM_EXEC__A, 0x0001, 0x0000);
1298 }
1299
1300 static int SC_WaitForReady(struct drxd_state *state)
1301 {
1302         u16 curCmd;
1303         int i;
1304
1305         for (i = 0; i < DRXD_MAX_RETRIES; i += 1) {
1306                 int status = Read16(state, SC_RA_RAM_CMD__A, &curCmd, 0);
1307                 if (status == 0 || curCmd == 0)
1308                         return status;
1309         }
1310         return -1;
1311 }
1312
1313 static int SC_SendCommand(struct drxd_state *state, u16 cmd)
1314 {
1315         int status = 0;
1316         u16 errCode;
1317
1318         Write16(state, SC_RA_RAM_CMD__A, cmd, 0);
1319         SC_WaitForReady(state);
1320
1321         Read16(state, SC_RA_RAM_CMD_ADDR__A, &errCode, 0);
1322
1323         if (errCode == 0xFFFF) {
1324                 printk(KERN_ERR "Command Error\n");
1325                 status = -1;
1326         }
1327
1328         return status;
1329 }
1330
1331 static int SC_ProcStartCommand(struct drxd_state *state,
1332                                u16 subCmd, u16 param0, u16 param1)
1333 {
1334         int status = 0;
1335         u16 scExec;
1336
1337         mutex_lock(&state->mutex);
1338         do {
1339                 Read16(state, SC_COMM_EXEC__A, &scExec, 0);
1340                 if (scExec != 1) {
1341                         status = -1;
1342                         break;
1343                 }
1344                 SC_WaitForReady(state);
1345                 Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0);
1346                 Write16(state, SC_RA_RAM_PARAM1__A, param1, 0);
1347                 Write16(state, SC_RA_RAM_PARAM0__A, param0, 0);
1348
1349                 SC_SendCommand(state, SC_RA_RAM_CMD_PROC_START);
1350         } while (0);
1351         mutex_unlock(&state->mutex);
1352         return status;
1353 }
1354
1355 static int SC_SetPrefParamCommand(struct drxd_state *state,
1356                                   u16 subCmd, u16 param0, u16 param1)
1357 {
1358         int status;
1359
1360         mutex_lock(&state->mutex);
1361         do {
1362                 status = SC_WaitForReady(state);
1363                 if (status < 0)
1364                         break;
1365                 status = Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0);
1366                 if (status < 0)
1367                         break;
1368                 status = Write16(state, SC_RA_RAM_PARAM1__A, param1, 0);
1369                 if (status < 0)
1370                         break;
1371                 status = Write16(state, SC_RA_RAM_PARAM0__A, param0, 0);
1372                 if (status < 0)
1373                         break;
1374
1375                 status = SC_SendCommand(state, SC_RA_RAM_CMD_SET_PREF_PARAM);
1376                 if (status < 0)
1377                         break;
1378         } while (0);
1379         mutex_unlock(&state->mutex);
1380         return status;
1381 }
1382
1383 #if 0
1384 static int SC_GetOpParamCommand(struct drxd_state *state, u16 * result)
1385 {
1386         int status = 0;
1387
1388         mutex_lock(&state->mutex);
1389         do {
1390                 status = SC_WaitForReady(state);
1391                 if (status < 0)
1392                         break;
1393                 status = SC_SendCommand(state, SC_RA_RAM_CMD_GET_OP_PARAM);
1394                 if (status < 0)
1395                         break;
1396                 status = Read16(state, SC_RA_RAM_PARAM0__A, result, 0);
1397                 if (status < 0)
1398                         break;
1399         } while (0);
1400         mutex_unlock(&state->mutex);
1401         return status;
1402 }
1403 #endif
1404
1405 static int ConfigureMPEGOutput(struct drxd_state *state, int bEnableOutput)
1406 {
1407         int status;
1408
1409         do {
1410                 u16 EcOcRegIprInvMpg = 0;
1411                 u16 EcOcRegOcModeLop = 0;
1412                 u16 EcOcRegOcModeHip = 0;
1413                 u16 EcOcRegOcMpgSio = 0;
1414
1415                 /*CHK_ERROR(Read16(state, EC_OC_REG_OC_MODE_LOP__A, &EcOcRegOcModeLop, 0)); */
1416
1417                 if (state->operation_mode == OM_DVBT_Diversity_Front) {
1418                         if (bEnableOutput) {
1419                                 EcOcRegOcModeHip |=
1420                                     B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR;
1421                         } else
1422                                 EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M;
1423                         EcOcRegOcModeLop |=
1424                             EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE;
1425                 } else {
1426                         EcOcRegOcModeLop = state->m_EcOcRegOcModeLop;
1427
1428                         if (bEnableOutput)
1429                                 EcOcRegOcMpgSio &= (~(EC_OC_REG_OC_MPG_SIO__M));
1430                         else
1431                                 EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M;
1432
1433                         /* Don't Insert RS Byte */
1434                         if (state->insert_rs_byte) {
1435                                 EcOcRegOcModeLop &=
1436                                     (~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M));
1437                                 EcOcRegOcModeHip &=
1438                                     (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M);
1439                                 EcOcRegOcModeHip |=
1440                                     EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE;
1441                         } else {
1442                                 EcOcRegOcModeLop |=
1443                                     EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE;
1444                                 EcOcRegOcModeHip &=
1445                                     (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M);
1446                                 EcOcRegOcModeHip |=
1447                                     EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE;
1448                         }
1449
1450                         /* Mode = Parallel */
1451                         if (state->enable_parallel)
1452                                 EcOcRegOcModeLop &=
1453                                     (~(EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M));
1454                         else
1455                                 EcOcRegOcModeLop |=
1456                                     EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL;
1457                 }
1458                 /* Invert Data */
1459                 /* EcOcRegIprInvMpg |= 0x00FF; */
1460                 EcOcRegIprInvMpg &= (~(0x00FF));
1461
1462                 /* Invert Error ( we don't use the pin ) */
1463                 /*  EcOcRegIprInvMpg |= 0x0100; */
1464                 EcOcRegIprInvMpg &= (~(0x0100));
1465
1466                 /* Invert Start ( we don't use the pin ) */
1467                 /* EcOcRegIprInvMpg |= 0x0200; */
1468                 EcOcRegIprInvMpg &= (~(0x0200));
1469
1470                 /* Invert Valid ( we don't use the pin ) */
1471                 /* EcOcRegIprInvMpg |= 0x0400; */
1472                 EcOcRegIprInvMpg &= (~(0x0400));
1473
1474                 /* Invert Clock */
1475                 /* EcOcRegIprInvMpg |= 0x0800; */
1476                 EcOcRegIprInvMpg &= (~(0x0800));
1477
1478                 /* EcOcRegOcModeLop =0x05; */
1479                 status = Write16(state, EC_OC_REG_IPR_INV_MPG__A, EcOcRegIprInvMpg, 0);
1480                 if (status < 0)
1481                         break;
1482                 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, EcOcRegOcModeLop, 0);
1483                 if (status < 0)
1484                         break;
1485                 status = Write16(state, EC_OC_REG_OC_MODE_HIP__A, EcOcRegOcModeHip, 0x0000);
1486                 if (status < 0)
1487                         break;
1488                 status = Write16(state, EC_OC_REG_OC_MPG_SIO__A, EcOcRegOcMpgSio, 0);
1489                 if (status < 0)
1490                         break;
1491         } while (0);
1492         return status;
1493 }
1494
1495 static int SetDeviceTypeId(struct drxd_state *state)
1496 {
1497         int status = 0;
1498         u16 deviceId = 0;
1499
1500         do {
1501                 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0);
1502                 if (status < 0)
1503                         break;
1504                 /* TODO: why twice? */
1505                 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0);
1506                 if (status < 0)
1507                         break;
1508                 printk(KERN_INFO "drxd: deviceId = %04x\n", deviceId);
1509
1510                 state->type_A = 0;
1511                 state->PGA = 0;
1512                 state->diversity = 0;
1513                 if (deviceId == 0) {    /* on A2 only 3975 available */
1514                         state->type_A = 1;
1515                         printk(KERN_INFO "DRX3975D-A2\n");
1516                 } else {
1517                         deviceId >>= 12;
1518                         printk(KERN_INFO "DRX397%dD-B1\n", deviceId);
1519                         switch (deviceId) {
1520                         case 4:
1521                                 state->diversity = 1;
1522                         case 3:
1523                         case 7:
1524                                 state->PGA = 1;
1525                                 break;
1526                         case 6:
1527                                 state->diversity = 1;
1528                         case 5:
1529                         case 8:
1530                                 break;
1531                         default:
1532                                 status = -1;
1533                                 break;
1534                         }
1535                 }
1536         } while (0);
1537
1538         if (status < 0)
1539                 return status;
1540
1541         /* Init Table selection */
1542         state->m_InitAtomicRead = DRXD_InitAtomicRead;
1543         state->m_InitSC = DRXD_InitSC;
1544         state->m_ResetECRAM = DRXD_ResetECRAM;
1545         if (state->type_A) {
1546                 state->m_ResetCEFR = DRXD_ResetCEFR;
1547                 state->m_InitFE_1 = DRXD_InitFEA2_1;
1548                 state->m_InitFE_2 = DRXD_InitFEA2_2;
1549                 state->m_InitCP = DRXD_InitCPA2;
1550                 state->m_InitCE = DRXD_InitCEA2;
1551                 state->m_InitEQ = DRXD_InitEQA2;
1552                 state->m_InitEC = DRXD_InitECA2;
1553                 if (load_firmware(state, DRX_FW_FILENAME_A2))
1554                         return -EIO;
1555         } else {
1556                 state->m_ResetCEFR = NULL;
1557                 state->m_InitFE_1 = DRXD_InitFEB1_1;
1558                 state->m_InitFE_2 = DRXD_InitFEB1_2;
1559                 state->m_InitCP = DRXD_InitCPB1;
1560                 state->m_InitCE = DRXD_InitCEB1;
1561                 state->m_InitEQ = DRXD_InitEQB1;
1562                 state->m_InitEC = DRXD_InitECB1;
1563                 if (load_firmware(state, DRX_FW_FILENAME_B1))
1564                         return -EIO;
1565         }
1566         if (state->diversity) {
1567                 state->m_InitDiversityFront = DRXD_InitDiversityFront;
1568                 state->m_InitDiversityEnd = DRXD_InitDiversityEnd;
1569                 state->m_DisableDiversity = DRXD_DisableDiversity;
1570                 state->m_StartDiversityFront = DRXD_StartDiversityFront;
1571                 state->m_StartDiversityEnd = DRXD_StartDiversityEnd;
1572                 state->m_DiversityDelay8MHZ = DRXD_DiversityDelay8MHZ;
1573                 state->m_DiversityDelay6MHZ = DRXD_DiversityDelay6MHZ;
1574         } else {
1575                 state->m_InitDiversityFront = NULL;
1576                 state->m_InitDiversityEnd = NULL;
1577                 state->m_DisableDiversity = NULL;
1578                 state->m_StartDiversityFront = NULL;
1579                 state->m_StartDiversityEnd = NULL;
1580                 state->m_DiversityDelay8MHZ = NULL;
1581                 state->m_DiversityDelay6MHZ = NULL;
1582         }
1583
1584         return status;
1585 }
1586
1587 static int CorrectSysClockDeviation(struct drxd_state *state)
1588 {
1589         int status;
1590         s32 incr = 0;
1591         s32 nomincr = 0;
1592         u32 bandwidth = 0;
1593         u32 sysClockInHz = 0;
1594         u32 sysClockFreq = 0;   /* in kHz */
1595         s16 oscClockDeviation;
1596         s16 Diff;
1597
1598         do {
1599                 /* Retrieve bandwidth and incr, sanity check */
1600
1601                 /* These accesses should be AtomicReadReg32, but that
1602                    causes trouble (at least for diversity */
1603                 status = Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, ((u32 *) &nomincr), 0);
1604                 if (status < 0)
1605                         break;
1606                 status = Read32(state, FE_IF_REG_INCR0__A, (u32 *) &incr, 0);
1607                 if (status < 0)
1608                         break;
1609
1610                 if (state->type_A) {
1611                         if ((nomincr - incr < -500) || (nomincr - incr > 500))
1612                                 break;
1613                 } else {
1614                         if ((nomincr - incr < -2000) || (nomincr - incr > 2000))
1615                                 break;
1616                 }
1617
1618                 switch (state->param.u.ofdm.bandwidth) {
1619                 case BANDWIDTH_8_MHZ:
1620                         bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
1621                         break;
1622                 case BANDWIDTH_7_MHZ:
1623                         bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
1624                         break;
1625                 case BANDWIDTH_6_MHZ:
1626                         bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
1627                         break;
1628                 default:
1629                         return -1;
1630                         break;
1631                 }
1632
1633                 /* Compute new sysclock value
1634                    sysClockFreq = (((incr + 2^23)*bandwidth)/2^21)/1000 */
1635                 incr += (1 << 23);
1636                 sysClockInHz = MulDiv32(incr, bandwidth, 1 << 21);
1637                 sysClockFreq = (u32) (sysClockInHz / 1000);
1638                 /* rounding */
1639                 if ((sysClockInHz % 1000) > 500)
1640                         sysClockFreq++;
1641
1642                 /* Compute clock deviation in ppm */
1643                 oscClockDeviation = (u16) ((((s32) (sysClockFreq) -
1644                                              (s32)
1645                                              (state->expected_sys_clock_freq)) *
1646                                             1000000L) /
1647                                            (s32)
1648                                            (state->expected_sys_clock_freq));
1649
1650                 Diff = oscClockDeviation - state->osc_clock_deviation;
1651                 /*printk(KERN_INFO "sysclockdiff=%d\n", Diff); */
1652                 if (Diff >= -200 && Diff <= 200) {
1653                         state->sys_clock_freq = (u16) sysClockFreq;
1654                         if (oscClockDeviation != state->osc_clock_deviation) {
1655                                 if (state->config.osc_deviation) {
1656                                         state->config.osc_deviation(state->priv,
1657                                                                     oscClockDeviation,
1658                                                                     1);
1659                                         state->osc_clock_deviation =
1660                                             oscClockDeviation;
1661                                 }
1662                         }
1663                         /* switch OFF SRMM scan in SC */
1664                         status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DONT_SCAN, 0);
1665                         if (status < 0)
1666                                 break;
1667                         /* overrule FE_IF internal value for
1668                            proper re-locking */
1669                         status = Write16(state, SC_RA_RAM_IF_SAVE__AX, state->current_fe_if_incr, 0);
1670                         if (status < 0)
1671                                 break;
1672                         state->cscd_state = CSCD_SAVED;
1673                 }
1674         } while (0);
1675
1676         return status;
1677 }
1678
1679 static int DRX_Stop(struct drxd_state *state)
1680 {
1681         int status;
1682
1683         if (state->drxd_state != DRXD_STARTED)
1684                 return 0;
1685
1686         do {
1687                 if (state->cscd_state != CSCD_SAVED) {
1688                         u32 lock;
1689                         status = DRX_GetLockStatus(state, &lock);
1690                         if (status < 0)
1691                                 break;
1692                 }
1693
1694                 status = StopOC(state);
1695                 if (status < 0)
1696                         break;
1697
1698                 state->drxd_state = DRXD_STOPPED;
1699
1700                 status = ConfigureMPEGOutput(state, 0);
1701                 if (status < 0)
1702                         break;
1703
1704                 if (state->type_A) {
1705                         /* Stop relevant processors off the device */
1706                         status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0x0000);
1707                         if (status < 0)
1708                                 break;
1709
1710                         status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1711                         if (status < 0)
1712                                 break;
1713                         status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1714                         if (status < 0)
1715                                 break;
1716                 } else {
1717                         /* Stop all processors except HI & CC & FE */
1718                         status = Write16(state, B_SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1719                         if (status < 0)
1720                                 break;
1721                         status = Write16(state, B_LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1722                         if (status < 0)
1723                                 break;
1724                         status = Write16(state, B_FT_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1725                         if (status < 0)
1726                                 break;
1727                         status = Write16(state, B_CP_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1728                         if (status < 0)
1729                                 break;
1730                         status = Write16(state, B_CE_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1731                         if (status < 0)
1732                                 break;
1733                         status = Write16(state, B_EQ_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1734                         if (status < 0)
1735                                 break;
1736                         status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0);
1737                         if (status < 0)
1738                                 break;
1739                 }
1740
1741         } while (0);
1742         return status;
1743 }
1744
1745 int SetOperationMode(struct drxd_state *state, int oMode)
1746 {
1747         int status;
1748
1749         do {
1750                 if (state->drxd_state != DRXD_STOPPED) {
1751                         status = -1;
1752                         break;
1753                 }
1754
1755                 if (oMode == state->operation_mode) {
1756                         status = 0;
1757                         break;
1758                 }
1759
1760                 if (oMode != OM_Default && !state->diversity) {
1761                         status = -1;
1762                         break;
1763                 }
1764
1765                 switch (oMode) {
1766                 case OM_DVBT_Diversity_Front:
1767                         status = WriteTable(state, state->m_InitDiversityFront);
1768                         break;
1769                 case OM_DVBT_Diversity_End:
1770                         status = WriteTable(state, state->m_InitDiversityEnd);
1771                         break;
1772                 case OM_Default:
1773                         /* We need to check how to
1774                            get DRXD out of diversity */
1775                 default:
1776                         status = WriteTable(state, state->m_DisableDiversity);
1777                         break;
1778                 }
1779         } while (0);
1780
1781         if (!status)
1782                 state->operation_mode = oMode;
1783         return status;
1784 }
1785
1786 static int StartDiversity(struct drxd_state *state)
1787 {
1788         int status = 0;
1789         u16 rcControl;
1790
1791         do {
1792                 if (state->operation_mode == OM_DVBT_Diversity_Front) {
1793                         status = WriteTable(state, state->m_StartDiversityFront);
1794                         if (status < 0)
1795                                 break;
1796                 } else if (state->operation_mode == OM_DVBT_Diversity_End) {
1797                         status = WriteTable(state, state->m_StartDiversityEnd);
1798                         if (status < 0)
1799                                 break;
1800                         if (state->param.u.ofdm.bandwidth == BANDWIDTH_8_MHZ) {
1801                                 status = WriteTable(state, state->m_DiversityDelay8MHZ);
1802                                 if (status < 0)
1803                                         break;
1804                         } else {
1805                                 status = WriteTable(state, state->m_DiversityDelay6MHZ);
1806                                 if (status < 0)
1807                                         break;
1808                         }
1809
1810                         status = Read16(state, B_EQ_REG_RC_SEL_CAR__A, &rcControl, 0);
1811                         if (status < 0)
1812                                 break;
1813                         rcControl &= ~(B_EQ_REG_RC_SEL_CAR_FFTMODE__M);
1814                         rcControl |= B_EQ_REG_RC_SEL_CAR_DIV_ON |
1815                             /*  combining enabled */
1816                             B_EQ_REG_RC_SEL_CAR_MEAS_A_CC |
1817                             B_EQ_REG_RC_SEL_CAR_PASS_A_CC |
1818                             B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC;
1819                         status = Write16(state, B_EQ_REG_RC_SEL_CAR__A, rcControl, 0);
1820                         if (status < 0)
1821                                 break;
1822                 }
1823         } while (0);
1824         return status;
1825 }
1826
1827 static int SetFrequencyShift(struct drxd_state *state,
1828                              u32 offsetFreq, int channelMirrored)
1829 {
1830         int negativeShift = (state->tuner_mirrors == channelMirrored);
1831
1832         /* Handle all mirroring
1833          *
1834          * Note: ADC mirroring (aliasing) is implictly handled by limiting
1835          * feFsRegAddInc to 28 bits below
1836          * (if the result before masking is more than 28 bits, this means
1837          *  that the ADC is mirroring.
1838          * The masking is in fact the aliasing of the ADC)
1839          *
1840          */
1841
1842         /* Compute register value, unsigned computation */
1843         state->fe_fs_add_incr = MulDiv32(state->intermediate_freq +
1844                                          offsetFreq,
1845                                          1 << 28, state->sys_clock_freq);
1846         /* Remove integer part */
1847         state->fe_fs_add_incr &= 0x0FFFFFFFL;
1848         if (negativeShift)
1849                 state->fe_fs_add_incr = ((1 << 28) - state->fe_fs_add_incr);
1850
1851         /* Save the frequency shift without tunerOffset compensation
1852            for CtrlGetChannel. */
1853         state->org_fe_fs_add_incr = MulDiv32(state->intermediate_freq,
1854                                              1 << 28, state->sys_clock_freq);
1855         /* Remove integer part */
1856         state->org_fe_fs_add_incr &= 0x0FFFFFFFL;
1857         if (negativeShift)
1858                 state->org_fe_fs_add_incr = ((1L << 28) -
1859                                              state->org_fe_fs_add_incr);
1860
1861         return Write32(state, FE_FS_REG_ADD_INC_LOP__A,
1862                        state->fe_fs_add_incr, 0);
1863 }
1864
1865 static int SetCfgNoiseCalibration(struct drxd_state *state,
1866                                   struct SNoiseCal *noiseCal)
1867 {
1868         u16 beOptEna;
1869         int status = 0;
1870
1871         do {
1872                 status = Read16(state, SC_RA_RAM_BE_OPT_ENA__A, &beOptEna, 0);
1873                 if (status < 0)
1874                         break;
1875                 if (noiseCal->cpOpt) {
1876                         beOptEna |= (1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
1877                 } else {
1878                         beOptEna &= ~(1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
1879                         status = Write16(state, CP_REG_AC_NEXP_OFFS__A, noiseCal->cpNexpOfs, 0);
1880                         if (status < 0)
1881                                 break;
1882                 }
1883                 status = Write16(state, SC_RA_RAM_BE_OPT_ENA__A, beOptEna, 0);
1884                 if (status < 0)
1885                         break;
1886
1887                 if (!state->type_A) {
1888                         status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_2K__A, noiseCal->tdCal2k, 0);
1889                         if (status < 0)
1890                                 break;
1891                         status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_8K__A, noiseCal->tdCal8k, 0);
1892                         if (status < 0)
1893                                 break;
1894                 }
1895         } while (0);
1896
1897         return status;
1898 }
1899
1900 static int DRX_Start(struct drxd_state *state, s32 off)
1901 {
1902         struct dvb_ofdm_parameters *p = &state->param.u.ofdm;
1903         int status;
1904
1905         u16 transmissionParams = 0;
1906         u16 operationMode = 0;
1907         u16 qpskTdTpsPwr = 0;
1908         u16 qam16TdTpsPwr = 0;
1909         u16 qam64TdTpsPwr = 0;
1910         u32 feIfIncr = 0;
1911         u32 bandwidth = 0;
1912         int mirrorFreqSpect;
1913
1914         u16 qpskSnCeGain = 0;
1915         u16 qam16SnCeGain = 0;
1916         u16 qam64SnCeGain = 0;
1917         u16 qpskIsGainMan = 0;
1918         u16 qam16IsGainMan = 0;
1919         u16 qam64IsGainMan = 0;
1920         u16 qpskIsGainExp = 0;
1921         u16 qam16IsGainExp = 0;
1922         u16 qam64IsGainExp = 0;
1923         u16 bandwidthParam = 0;
1924
1925         if (off < 0)
1926                 off = (off - 500) / 1000;
1927         else
1928                 off = (off + 500) / 1000;
1929
1930         do {
1931                 if (state->drxd_state != DRXD_STOPPED)
1932                         return -1;
1933                 status = ResetECOD(state);
1934                 if (status < 0)
1935                         break;
1936                 if (state->type_A) {
1937                         status = InitSC(state);
1938                         if (status < 0)
1939                                 break;
1940                 } else {
1941                         status = InitFT(state);
1942                         if (status < 0)
1943                                 break;
1944                         status = InitCP(state);
1945                         if (status < 0)
1946                                 break;
1947                         status = InitCE(state);
1948                         if (status < 0)
1949                                 break;
1950                         status = InitEQ(state);
1951                         if (status < 0)
1952                                 break;
1953                         status = InitSC(state);
1954                         if (status < 0)
1955                                 break;
1956                 }
1957
1958                 /* Restore current IF & RF AGC settings */
1959
1960                 status = SetCfgIfAgc(state, &state->if_agc_cfg);
1961                 if (status < 0)
1962                         break;
1963                 status = SetCfgRfAgc(state, &state->rf_agc_cfg);
1964                 if (status < 0)
1965                         break;
1966
1967                 mirrorFreqSpect = (state->param.inversion == INVERSION_ON);
1968
1969                 switch (p->transmission_mode) {
1970                 default:        /* Not set, detect it automatically */
1971                         operationMode |= SC_RA_RAM_OP_AUTO_MODE__M;
1972                         /* fall through , try first guess DRX_FFTMODE_8K */
1973                 case TRANSMISSION_MODE_8K:
1974                         transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_8K;
1975                         if (state->type_A) {
1976                                 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_8K, 0x0000);
1977                                 if (status < 0)
1978                                         break;
1979                                 qpskSnCeGain = 99;
1980                                 qam16SnCeGain = 83;
1981                                 qam64SnCeGain = 67;
1982                         }
1983                         break;
1984                 case TRANSMISSION_MODE_2K:
1985                         transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_2K;
1986                         if (state->type_A) {
1987                                 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_2K, 0x0000);
1988                                 if (status < 0)
1989                                         break;
1990                                 qpskSnCeGain = 97;
1991                                 qam16SnCeGain = 71;
1992                                 qam64SnCeGain = 65;
1993                         }
1994                         break;
1995                 }
1996
1997                 switch (p->guard_interval) {
1998                 case GUARD_INTERVAL_1_4:
1999                         transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4;
2000                         break;
2001                 case GUARD_INTERVAL_1_8:
2002                         transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_8;
2003                         break;
2004                 case GUARD_INTERVAL_1_16:
2005                         transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_16;
2006                         break;
2007                 case GUARD_INTERVAL_1_32:
2008                         transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_32;
2009                         break;
2010                 default:        /* Not set, detect it automatically */
2011                         operationMode |= SC_RA_RAM_OP_AUTO_GUARD__M;
2012                         /* try first guess 1/4 */
2013                         transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4;
2014                         break;
2015                 }
2016
2017                 switch (p->hierarchy_information) {
2018                 case HIERARCHY_1:
2019                         transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A1;
2020                         if (state->type_A) {
2021                                 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0001, 0x0000);
2022                                 if (status < 0)
2023                                         break;
2024                                 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0001, 0x0000);
2025                                 if (status < 0)
2026                                         break;
2027
2028                                 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
2029                                 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA1;
2030                                 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA1;
2031
2032                                 qpskIsGainMan =
2033                                     SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
2034                                 qam16IsGainMan =
2035                                     SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE;
2036                                 qam64IsGainMan =
2037                                     SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE;
2038
2039                                 qpskIsGainExp =
2040                                     SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
2041                                 qam16IsGainExp =
2042                                     SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE;
2043                                 qam64IsGainExp =
2044                                     SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE;
2045                         }
2046                         break;
2047
2048                 case HIERARCHY_2:
2049                         transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A2;
2050                         if (state->type_A) {
2051                                 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0002, 0x0000);
2052                                 if (status < 0)
2053                                         break;
2054                                 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0002, 0x0000);
2055                                 if (status < 0)
2056                                         break;
2057
2058                                 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
2059                                 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA2;
2060                                 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA2;
2061
2062                                 qpskIsGainMan =
2063                                     SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
2064                                 qam16IsGainMan =
2065                                     SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE;
2066                                 qam64IsGainMan =
2067                                     SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE;
2068
2069                                 qpskIsGainExp =
2070                                     SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
2071                                 qam16IsGainExp =
2072                                     SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE;
2073                                 qam64IsGainExp =
2074                                     SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE;
2075                         }
2076                         break;
2077                 case HIERARCHY_4:
2078                         transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A4;
2079                         if (state->type_A) {
2080                                 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0003, 0x0000);
2081                                 if (status < 0)
2082                                         break;
2083                                 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0003, 0x0000);
2084                                 if (status < 0)
2085                                         break;
2086
2087                                 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
2088                                 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA4;
2089                                 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA4;
2090
2091                                 qpskIsGainMan =
2092                                     SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
2093                                 qam16IsGainMan =
2094                                     SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE;
2095                                 qam64IsGainMan =
2096                                     SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE;
2097
2098                                 qpskIsGainExp =
2099                                     SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
2100                                 qam16IsGainExp =
2101                                     SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE;
2102                                 qam64IsGainExp =
2103                                     SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE;
2104                         }
2105                         break;
2106                 case HIERARCHY_AUTO:
2107                 default:
2108                         /* Not set, detect it automatically, start with none */
2109                         operationMode |= SC_RA_RAM_OP_AUTO_HIER__M;
2110                         transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_NO;
2111                         if (state->type_A) {
2112                                 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0000, 0x0000);
2113                                 if (status < 0)
2114                                         break;
2115                                 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0000, 0x0000);
2116                                 if (status < 0)
2117                                         break;
2118
2119                                 qpskTdTpsPwr = EQ_TD_TPS_PWR_QPSK;
2120                                 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHAN;
2121                                 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHAN;
2122
2123                                 qpskIsGainMan =
2124                                     SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE;
2125                                 qam16IsGainMan =
2126                                     SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE;
2127                                 qam64IsGainMan =
2128                                     SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE;
2129
2130                                 qpskIsGainExp =
2131                                     SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE;
2132                                 qam16IsGainExp =
2133                                     SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE;
2134                                 qam64IsGainExp =
2135                                     SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE;
2136                         }
2137                         break;
2138                 }
2139                 status = status;
2140                 if (status < 0)
2141                         break;
2142
2143                 switch (p->constellation) {
2144                 default:
2145                         operationMode |= SC_RA_RAM_OP_AUTO_CONST__M;
2146                         /* fall through , try first guess
2147                            DRX_CONSTELLATION_QAM64 */
2148                 case QAM_64:
2149                         transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM64;
2150                         if (state->type_A) {
2151                                 status = Write16(state, EQ_REG_OT_CONST__A, 0x0002, 0x0000);
2152                                 if (status < 0)
2153                                         break;
2154                                 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_64QAM, 0x0000);
2155                                 if (status < 0)
2156                                         break;
2157                                 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0020, 0x0000);
2158                                 if (status < 0)
2159                                         break;
2160                                 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0008, 0x0000);
2161                                 if (status < 0)
2162                                         break;
2163                                 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0002, 0x0000);
2164                                 if (status < 0)
2165                                         break;
2166
2167                                 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam64TdTpsPwr, 0x0000);
2168                                 if (status < 0)
2169                                         break;
2170                                 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam64SnCeGain, 0x0000);
2171                                 if (status < 0)
2172                                         break;
2173                                 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam64IsGainMan, 0x0000);
2174                                 if (status < 0)
2175                                         break;
2176                                 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam64IsGainExp, 0x0000);
2177                                 if (status < 0)
2178                                         break;
2179                         }
2180                         break;
2181                 case QPSK:
2182                         transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QPSK;
2183                         if (state->type_A) {
2184                                 status = Write16(state, EQ_REG_OT_CONST__A, 0x0000, 0x0000);
2185                                 if (status < 0)
2186                                         break;
2187                                 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_QPSK, 0x0000);
2188                                 if (status < 0)
2189                                         break;
2190                                 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000);
2191                                 if (status < 0)
2192                                         break;
2193                                 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0000, 0x0000);
2194                                 if (status < 0)
2195                                         break;
2196                                 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000);
2197                                 if (status < 0)
2198                                         break;
2199
2200                                 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qpskTdTpsPwr, 0x0000);
2201                                 if (status < 0)
2202                                         break;
2203                                 status = Write16(state, EQ_REG_SN_CEGAIN__A, qpskSnCeGain, 0x0000);
2204                                 if (status < 0)
2205                                         break;
2206                                 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qpskIsGainMan, 0x0000);
2207                                 if (status < 0)
2208                                         break;
2209                                 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qpskIsGainExp, 0x0000);
2210                                 if (status < 0)
2211                                         break;
2212                         }
2213                         break;
2214
2215                 case QAM_16:
2216                         transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM16;
2217                         if (state->type_A) {
2218                                 status = Write16(state, EQ_REG_OT_CONST__A, 0x0001, 0x0000);
2219                                 if (status < 0)
2220                                         break;
2221                                 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_16QAM, 0x0000);
2222                                 if (status < 0)
2223                                         break;
2224                                 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000);
2225                                 if (status < 0)
2226                                         break;
2227                                 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0004, 0x0000);
2228                                 if (status < 0)
2229                                         break;
2230                                 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000);
2231                                 if (status < 0)
2232                                         break;
2233
2234                                 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam16TdTpsPwr, 0x0000);
2235                                 if (status < 0)
2236                                         break;
2237                                 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam16SnCeGain, 0x0000);
2238                                 if (status < 0)
2239                                         break;
2240                                 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam16IsGainMan, 0x0000);
2241                                 if (status < 0)
2242                                         break;
2243                                 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam16IsGainExp, 0x0000);
2244                                 if (status < 0)
2245                                         break;
2246                         }
2247                         break;
2248
2249                 }
2250                 status = status;
2251                 if (status < 0)
2252                         break;
2253
2254                 switch (DRX_CHANNEL_HIGH) {
2255                 default:
2256                 case DRX_CHANNEL_AUTO:
2257                 case DRX_CHANNEL_LOW:
2258                         transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_LO;
2259                         status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_LO, 0x0000);
2260                         if (status < 0)
2261                                 break;
2262                         break;
2263                 case DRX_CHANNEL_HIGH:
2264                         transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_HI;
2265                         status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_HI, 0x0000);
2266                         if (status < 0)
2267                                 break;
2268                         break;
2269
2270                 }
2271
2272                 switch (p->code_rate_HP) {
2273                 case FEC_1_2:
2274                         transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_1_2;
2275                         if (state->type_A) {
2276                                 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C1_2, 0x0000);
2277                                 if (status < 0)
2278                                         break;
2279                         }
2280                         break;
2281                 default:
2282                         operationMode |= SC_RA_RAM_OP_AUTO_RATE__M;
2283                 case FEC_2_3:
2284                         transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_2_3;
2285                         if (state->type_A) {
2286                                 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C2_3, 0x0000);
2287                                 if (status < 0)
2288                                         break;
2289                         }
2290                         break;
2291                 case FEC_3_4:
2292                         transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_3_4;
2293                         if (state->type_A) {
2294                                 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C3_4, 0x0000);
2295                                 if (status < 0)
2296                                         break;
2297                         }
2298                         break;
2299                 case FEC_5_6:
2300                         transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_5_6;
2301                         if (state->type_A) {
2302                                 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C5_6, 0x0000);
2303                                 if (status < 0)
2304                                         break;
2305                         }
2306                         break;
2307                 case FEC_7_8:
2308                         transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_7_8;
2309                         if (state->type_A) {
2310                                 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C7_8, 0x0000);
2311                                 if (status < 0)
2312                                         break;
2313                         }
2314                         break;
2315                 }
2316                 status = status;
2317                 if (status < 0)
2318                         break;
2319
2320                 /* First determine real bandwidth (Hz) */
2321                 /* Also set delay for impulse noise cruncher (only A2) */
2322                 /* Also set parameters for EC_OC fix, note
2323                    EC_OC_REG_TMD_HIL_MAR is changed
2324                    by SC for fix for some 8K,1/8 guard but is restored by
2325                    InitEC and ResetEC
2326                    functions */
2327                 switch (p->bandwidth) {
2328                 case BANDWIDTH_AUTO:
2329                 case BANDWIDTH_8_MHZ:
2330                         /* (64/7)*(8/8)*1000000 */
2331                         bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
2332
2333                         bandwidthParam = 0;
2334                         status = Write16(state,
2335                                          FE_AG_REG_IND_DEL__A, 50, 0x0000);
2336                         break;
2337                 case BANDWIDTH_7_MHZ:
2338                         /* (64/7)*(7/8)*1000000 */
2339                         bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
2340                         bandwidthParam = 0x4807;        /*binary:0100 1000 0000 0111 */
2341                         status = Write16(state,
2342                                          FE_AG_REG_IND_DEL__A, 59, 0x0000);
2343                         break;
2344                 case BANDWIDTH_6_MHZ:
2345                         /* (64/7)*(6/8)*1000000 */
2346                         bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
2347                         bandwidthParam = 0x0F07;        /*binary: 0000 1111 0000 0111 */
2348                         status = Write16(state,
2349                                          FE_AG_REG_IND_DEL__A, 71, 0x0000);
2350                         break;
2351                 default:
2352                         status = -EINVAL;
2353                 }
2354                 if (status < 0)
2355                         break;
2356
2357                 status = Write16(state, SC_RA_RAM_BAND__A, bandwidthParam, 0x0000);
2358                 if (status < 0)
2359                         break;
2360
2361                 {
2362                         u16 sc_config;
2363                         status = Read16(state, SC_RA_RAM_CONFIG__A, &sc_config, 0);
2364                         if (status < 0)
2365                                 break;
2366
2367                         /* enable SLAVE mode in 2k 1/32 to
2368                            prevent timing change glitches */
2369                         if ((p->transmission_mode == TRANSMISSION_MODE_2K) &&
2370                             (p->guard_interval == GUARD_INTERVAL_1_32)) {
2371                                 /* enable slave */
2372                                 sc_config |= SC_RA_RAM_CONFIG_SLAVE__M;
2373                         } else {
2374                                 /* disable slave */
2375                                 sc_config &= ~SC_RA_RAM_CONFIG_SLAVE__M;
2376                         }
2377                         status = Write16(state, SC_RA_RAM_CONFIG__A, sc_config, 0);
2378                         if (status < 0)
2379                                 break;
2380                 }
2381
2382                 status = SetCfgNoiseCalibration(state, &state->noise_cal);
2383                 if (status < 0)
2384                         break;
2385
2386                 if (state->cscd_state == CSCD_INIT) {
2387                         /* switch on SRMM scan in SC */
2388                         status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DO_SCAN, 0x0000);
2389                         if (status < 0)
2390                                 break;
2391 /*            CHK_ERROR(Write16(SC_RA_RAM_SAMPLE_RATE_STEP__A, DRXD_OSCDEV_STEP, 0x0000));*/
2392                         state->cscd_state = CSCD_SET;
2393                 }
2394
2395                 /* Now compute FE_IF_REG_INCR */
2396                 /*((( SysFreq/BandWidth)/2)/2) -1) * 2^23) =>
2397                    ((SysFreq / BandWidth) * (2^21) ) - (2^23) */
2398                 feIfIncr = MulDiv32(state->sys_clock_freq * 1000,
2399                                     (1ULL << 21), bandwidth) - (1 << 23);
2400                 status = Write16(state, FE_IF_REG_INCR0__A, (u16) (feIfIncr & FE_IF_REG_INCR0__M), 0x0000);
2401                 if (status < 0)
2402                         break;
2403                 status = Write16(state, FE_IF_REG_INCR1__A, (u16) ((feIfIncr >> FE_IF_REG_INCR0__W) & FE_IF_REG_INCR1__M), 0x0000);
2404                 if (status < 0)
2405                         break;
2406                 /* Bandwidth setting done */
2407
2408                 /* Mirror & frequency offset */
2409                 SetFrequencyShift(state, off, mirrorFreqSpect);
2410
2411                 /* Start SC, write channel settings to SC */
2412
2413                 /* Enable SC after setting all other parameters */
2414                 status = Write16(state, SC_COMM_STATE__A, 0, 0x0000);
2415                 if (status < 0)
2416                         break;
2417                 status = Write16(state, SC_COMM_EXEC__A, 1, 0x0000);
2418                 if (status < 0)
2419                         break;
2420
2421                 /* Write SC parameter registers, operation mode */
2422 #if 1
2423                 operationMode = (SC_RA_RAM_OP_AUTO_MODE__M |
2424                                  SC_RA_RAM_OP_AUTO_GUARD__M |
2425                                  SC_RA_RAM_OP_AUTO_CONST__M |
2426                                  SC_RA_RAM_OP_AUTO_HIER__M |
2427                                  SC_RA_RAM_OP_AUTO_RATE__M);
2428 #endif
2429                 status = SC_SetPrefParamCommand(state, 0x0000, transmissionParams, operationMode);
2430                 if (status < 0)
2431                         break;
2432
2433                 /* Start correct processes to get in lock */
2434                 status = SC_ProcStartCommand(state, SC_RA_RAM_PROC_LOCKTRACK, SC_RA_RAM_SW_EVENT_RUN_NMASK__M, SC_RA_RAM_LOCKTRACK_MIN);
2435                 if (status < 0)
2436                         break;
2437
2438                 status = StartOC(state);
2439                 if (status < 0)
2440                         break;
2441
2442                 if (state->operation_mode != OM_Default) {
2443                         status = StartDiversity(state);
2444                         if (status < 0)
2445                                 break;
2446                 }
2447
2448                 state->drxd_state = DRXD_STARTED;
2449         } while (0);
2450
2451         return status;
2452 }
2453
2454 static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency)
2455 {
2456         u32 ulRfAgcOutputLevel = 0xffffffff;
2457         u32 ulRfAgcSettleLevel = 528;   /* Optimum value for MT2060 */
2458         u32 ulRfAgcMinLevel = 0;        /* Currently unused */
2459         u32 ulRfAgcMaxLevel = DRXD_FE_CTRL_MAX; /* Currently unused */
2460         u32 ulRfAgcSpeed = 0;   /* Currently unused */
2461         u32 ulRfAgcMode = 0;    /*2;   Off */
2462         u32 ulRfAgcR1 = 820;
2463         u32 ulRfAgcR2 = 2200;
2464         u32 ulRfAgcR3 = 150;
2465         u32 ulIfAgcMode = 0;    /* Auto */
2466         u32 ulIfAgcOutputLevel = 0xffffffff;
2467         u32 ulIfAgcSettleLevel = 0xffffffff;
2468         u32 ulIfAgcMinLevel = 0xffffffff;
2469         u32 ulIfAgcMaxLevel = 0xffffffff;
2470         u32 ulIfAgcSpeed = 0xffffffff;
2471         u32 ulIfAgcR1 = 820;
2472         u32 ulIfAgcR2 = 2200;
2473         u32 ulIfAgcR3 = 150;
2474         u32 ulClock = state->config.clock;
2475         u32 ulSerialMode = 0;
2476         u32 ulEcOcRegOcModeLop = 4;     /* Dynamic DTO source */
2477         u32 ulHiI2cDelay = HI_I2C_DELAY;
2478         u32 ulHiI2cBridgeDelay = HI_I2C_BRIDGE_DELAY;
2479         u32 ulHiI2cPatch = 0;
2480         u32 ulEnvironment = APPENV_PORTABLE;
2481         u32 ulEnvironmentDiversity = APPENV_MOBILE;
2482         u32 ulIFFilter = IFFILTER_SAW;
2483
2484         state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2485         state->if_agc_cfg.outputLevel = 0;
2486         state->if_agc_cfg.settleLevel = 140;
2487         state->if_agc_cfg.minOutputLevel = 0;
2488         state->if_agc_cfg.maxOutputLevel = 1023;
2489         state->if_agc_cfg.speed = 904;
2490
2491         if (ulIfAgcMode == 1 && ulIfAgcOutputLevel <= DRXD_FE_CTRL_MAX) {
2492                 state->if_agc_cfg.ctrlMode = AGC_CTRL_USER;
2493                 state->if_agc_cfg.outputLevel = (u16) (ulIfAgcOutputLevel);
2494         }
2495
2496         if (ulIfAgcMode == 0 &&
2497             ulIfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&
2498             ulIfAgcMinLevel <= DRXD_FE_CTRL_MAX &&
2499             ulIfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&
2500             ulIfAgcSpeed <= DRXD_FE_CTRL_MAX) {
2501                 state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2502                 state->if_agc_cfg.settleLevel = (u16) (ulIfAgcSettleLevel);
2503                 state->if_agc_cfg.minOutputLevel = (u16) (ulIfAgcMinLevel);
2504                 state->if_agc_cfg.maxOutputLevel = (u16) (ulIfAgcMaxLevel);
2505                 state->if_agc_cfg.speed = (u16) (ulIfAgcSpeed);
2506         }
2507
2508         state->if_agc_cfg.R1 = (u16) (ulIfAgcR1);
2509         state->if_agc_cfg.R2 = (u16) (ulIfAgcR2);
2510         state->if_agc_cfg.R3 = (u16) (ulIfAgcR3);
2511
2512         state->rf_agc_cfg.R1 = (u16) (ulRfAgcR1);
2513         state->rf_agc_cfg.R2 = (u16) (ulRfAgcR2);
2514         state->rf_agc_cfg.R3 = (u16) (ulRfAgcR3);
2515
2516         state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2517         /* rest of the RFAgcCfg structure currently unused */
2518         if (ulRfAgcMode == 1 && ulRfAgcOutputLevel <= DRXD_FE_CTRL_MAX) {
2519                 state->rf_agc_cfg.ctrlMode = AGC_CTRL_USER;
2520                 state->rf_agc_cfg.outputLevel = (u16) (ulRfAgcOutputLevel);
2521         }
2522
2523         if (ulRfAgcMode == 0 &&
2524             ulRfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&
2525             ulRfAgcMinLevel <= DRXD_FE_CTRL_MAX &&
2526             ulRfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&
2527             ulRfAgcSpeed <= DRXD_FE_CTRL_MAX) {
2528                 state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2529                 state->rf_agc_cfg.settleLevel = (u16) (ulRfAgcSettleLevel);
2530                 state->rf_agc_cfg.minOutputLevel = (u16) (ulRfAgcMinLevel);
2531                 state->rf_agc_cfg.maxOutputLevel = (u16) (ulRfAgcMaxLevel);
2532                 state->rf_agc_cfg.speed = (u16) (ulRfAgcSpeed);
2533         }
2534
2535         if (ulRfAgcMode == 2)
2536                 state->rf_agc_cfg.ctrlMode = AGC_CTRL_OFF;
2537
2538         if (ulEnvironment <= 2)
2539                 state->app_env_default = (enum app_env)
2540                     (ulEnvironment);
2541         if (ulEnvironmentDiversity <= 2)
2542                 state->app_env_diversity = (enum app_env)
2543                     (ulEnvironmentDiversity);
2544
2545         if (ulIFFilter == IFFILTER_DISCRETE) {
2546                 /* discrete filter */
2547                 state->noise_cal.cpOpt = 0;
2548                 state->noise_cal.cpNexpOfs = 40;
2549                 state->noise_cal.tdCal2k = -40;
2550                 state->noise_cal.tdCal8k = -24;
2551         } else {
2552                 /* SAW filter */
2553                 state->noise_cal.cpOpt = 1;
2554                 state->noise_cal.cpNexpOfs = 0;
2555                 state->noise_cal.tdCal2k = -21;
2556                 state->noise_cal.tdCal8k = -24;
2557         }
2558         state->m_EcOcRegOcModeLop = (u16) (ulEcOcRegOcModeLop);
2559
2560         state->chip_adr = (state->config.demod_address << 1) | 1;
2561         switch (ulHiI2cPatch) {
2562         case 1:
2563                 state->m_HiI2cPatch = DRXD_HiI2cPatch_1;
2564                 break;
2565         case 3:
2566                 state->m_HiI2cPatch = DRXD_HiI2cPatch_3;
2567                 break;
2568         default:
2569                 state->m_HiI2cPatch = NULL;
2570         }
2571
2572         /* modify tuner and clock attributes */
2573         state->intermediate_freq = (u16) (IntermediateFrequency / 1000);
2574         /* expected system clock frequency in kHz */
2575         state->expected_sys_clock_freq = 48000;
2576         /* real system clock frequency in kHz */
2577         state->sys_clock_freq = 48000;
2578         state->osc_clock_freq = (u16) ulClock;
2579         state->osc_clock_deviation = 0;
2580         state->cscd_state = CSCD_INIT;
2581         state->drxd_state = DRXD_UNINITIALIZED;
2582
2583         state->PGA = 0;
2584         state->type_A = 0;
2585         state->tuner_mirrors = 0;
2586
2587         /* modify MPEG output attributes */
2588         state->insert_rs_byte = state->config.insert_rs_byte;
2589         state->enable_parallel = (ulSerialMode != 1);
2590
2591         /* Timing div, 250ns/Psys */
2592         /* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */
2593
2594         state->hi_cfg_timing_div = (u16) ((state->sys_clock_freq / 1000) *
2595                                           ulHiI2cDelay) / 1000;
2596         /* Bridge delay, uses oscilator clock */
2597         /* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */
2598         state->hi_cfg_bridge_delay = (u16) ((state->osc_clock_freq / 1000) *
2599                                             ulHiI2cBridgeDelay) / 1000;
2600
2601         state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER;
2602         /* state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO; */
2603         state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO;
2604         return 0;
2605 }
2606
2607 int DRXD_init(struct drxd_state *state, const u8 * fw, u32 fw_size)
2608 {
2609         int status = 0;
2610         u32 driverVersion;
2611
2612         if (state->init_done)
2613                 return 0;
2614
2615         CDRXD(state, state->config.IF ? state->config.IF : 36000000);
2616
2617         do {
2618                 state->operation_mode = OM_Default;
2619
2620                 status = SetDeviceTypeId(state);
2621                 if (status < 0)
2622                         break;
2623
2624                 /* Apply I2c address patch to B1 */
2625                 if (!state->type_A && state->m_HiI2cPatch != NULL)
2626                         status = WriteTable(state, state->m_HiI2cPatch);
2627                         if (status < 0)
2628                                 break;
2629
2630                 if (state->type_A) {
2631                         /* HI firmware patch for UIO readout,
2632                            avoid clearing of result register */
2633                         status = Write16(state, 0x43012D, 0x047f, 0);
2634                         if (status < 0)
2635                                 break;
2636                 }
2637
2638                 status = HI_ResetCommand(state);
2639                 if (status < 0)
2640                         break;
2641
2642                 status = StopAllProcessors(state);
2643                 if (status < 0)
2644                         break;
2645                 status = InitCC(state);
2646                 if (status < 0)
2647                         break;
2648
2649                 state->osc_clock_deviation = 0;
2650
2651                 if (state->config.osc_deviation)
2652                         state->osc_clock_deviation =
2653                             state->config.osc_deviation(state->priv, 0, 0);
2654                 {
2655                         /* Handle clock deviation */
2656                         s32 devB;
2657                         s32 devA = (s32) (state->osc_clock_deviation) *
2658                             (s32) (state->expected_sys_clock_freq);
2659                         /* deviation in kHz */
2660                         s32 deviation = (devA / (1000000L));
2661                         /* rounding, signed */
2662                         if (devA > 0)
2663                                 devB = (2);
2664                         else
2665                                 devB = (-2);
2666                         if ((devB * (devA % 1000000L) > 1000000L)) {
2667                                 /* add +1 or -1 */
2668                                 deviation += (devB / 2);
2669                         }
2670
2671                         state->sys_clock_freq =
2672                             (u16) ((state->expected_sys_clock_freq) +
2673                                    deviation);
2674                 }
2675                 status = InitHI(state);
2676                 if (status < 0)
2677                         break;
2678                 status = InitAtomicRead(state);
2679                 if (status < 0)
2680                         break;
2681
2682                 status = EnableAndResetMB(state);
2683                 if (status < 0)
2684                         break;
2685                 if (state->type_A)
2686                         status = ResetCEFR(state);
2687                         if (status < 0)
2688                                 break;
2689
2690                 if (fw) {
2691                         status = DownloadMicrocode(state, fw, fw_size);
2692                         if (status < 0)
2693                                 break;
2694                 } else {
2695                         status = DownloadMicrocode(state, state->microcode, state->microcode_length);
2696                         if (status < 0)
2697                                 break;
2698                 }
2699
2700                 if (state->PGA) {
2701                         state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO;
2702                         SetCfgPga(state, 0);    /* PGA = 0 dB */
2703                 } else {
2704                         state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER;
2705                 }
2706
2707                 state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO;
2708
2709                 status = InitFE(state);
2710                 if (status < 0)
2711                         break;
2712                 status = InitFT(state);
2713                 if (status < 0)
2714                         break;
2715                 status = InitCP(state);
2716                 if (status < 0)
2717                         break;
2718                 status = InitCE(state);
2719                 if (status < 0)
2720                         break;
2721                 status = InitEQ(state);
2722                 if (status < 0)
2723                         break;
2724                 status = InitEC(state);
2725                 if (status < 0)
2726                         break;
2727                 status = InitSC(state);
2728                 if (status < 0)
2729                         break;
2730
2731                 status = SetCfgIfAgc(state, &state->if_agc_cfg);
2732                 if (status < 0)
2733                         break;
2734                 status = SetCfgRfAgc(state, &state->rf_agc_cfg);
2735                 if (status < 0)
2736                         break;
2737
2738                 state->cscd_state = CSCD_INIT;
2739                 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
2740                 if (status < 0)
2741                         break;
2742                 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
2743                 if (status < 0)
2744                         break;
2745
2746                 driverVersion = (((VERSION_MAJOR / 10) << 4) +
2747                                  (VERSION_MAJOR % 10)) << 24;
2748                 driverVersion += (((VERSION_MINOR / 10) << 4) +
2749                                   (VERSION_MINOR % 10)) << 16;
2750                 driverVersion += ((VERSION_PATCH / 1000) << 12) +
2751                     ((VERSION_PATCH / 100) << 8) +
2752                     ((VERSION_PATCH / 10) << 4) + (VERSION_PATCH % 10);
2753
2754                 status = Write32(state, SC_RA_RAM_DRIVER_VERSION__AX, driverVersion, 0);
2755                 if (status < 0)
2756                         break;
2757
2758                 status = StopOC(state);
2759                 if (status < 0)
2760                         break;
2761
2762                 state->drxd_state = DRXD_STOPPED;
2763                 state->init_done = 1;
2764                 status = 0;
2765         } while (0);
2766         return status;
2767 }
2768
2769 int DRXD_status(struct drxd_state *state, u32 * pLockStatus)
2770 {
2771         DRX_GetLockStatus(state, pLockStatus);
2772
2773         /*if (*pLockStatus&DRX_LOCK_MPEG) */
2774         if (*pLockStatus & DRX_LOCK_FEC) {
2775                 ConfigureMPEGOutput(state, 1);
2776                 /* Get status again, in case we have MPEG lock now */
2777                 /*DRX_GetLockStatus(state, pLockStatus); */
2778         }
2779
2780         return 0;
2781 }
2782
2783 /****************************************************************************/
2784 /****************************************************************************/
2785 /****************************************************************************/
2786
2787 static int drxd_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
2788 {
2789         struct drxd_state *state = fe->demodulator_priv;
2790         u32 value;
2791         int res;
2792
2793         res = ReadIFAgc(state, &value);
2794         if (res < 0)
2795                 *strength = 0;
2796         else
2797                 *strength = 0xffff - (value << 4);
2798         return 0;
2799 }
2800
2801 static int drxd_read_status(struct dvb_frontend *fe, fe_status_t * status)
2802 {
2803         struct drxd_state *state = fe->demodulator_priv;
2804         u32 lock;
2805
2806         DRXD_status(state, &lock);
2807         *status = 0;
2808         /* No MPEG lock in V255 firmware, bug ? */
2809 #if 1
2810         if (lock & DRX_LOCK_MPEG)
2811                 *status |= FE_HAS_LOCK;
2812 #else
2813         if (lock & DRX_LOCK_FEC)
2814                 *status |= FE_HAS_LOCK;
2815 #endif
2816         if (lock & DRX_LOCK_FEC)
2817                 *status |= FE_HAS_VITERBI | FE_HAS_SYNC;
2818         if (lock & DRX_LOCK_DEMOD)
2819                 *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
2820
2821         return 0;
2822 }
2823
2824 static int drxd_init(struct dvb_frontend *fe)
2825 {
2826         struct drxd_state *state = fe->demodulator_priv;
2827         int err = 0;
2828
2829 /*      if (request_firmware(&state->fw, "drxd.fw", state->dev)<0) */
2830         return DRXD_init(state, 0, 0);
2831
2832         err = DRXD_init(state, state->fw->data, state->fw->size);
2833         release_firmware(state->fw);
2834         return err;
2835 }
2836
2837 int drxd_config_i2c(struct dvb_frontend *fe, int onoff)
2838 {
2839         struct drxd_state *state = fe->demodulator_priv;
2840
2841         if (state->config.disable_i2c_gate_ctrl == 1)
2842                 return 0;
2843
2844         return DRX_ConfigureI2CBridge(state, onoff);
2845 }
2846 EXPORT_SYMBOL(drxd_config_i2c);
2847
2848 static int drxd_get_tune_settings(struct dvb_frontend *fe,
2849                                   struct dvb_frontend_tune_settings *sets)
2850 {
2851         sets->min_delay_ms = 10000;
2852         sets->max_drift = 0;
2853         sets->step_size = 0;
2854         return 0;
2855 }
2856
2857 static int drxd_read_ber(struct dvb_frontend *fe, u32 * ber)
2858 {
2859         *ber = 0;
2860         return 0;
2861 }
2862
2863 static int drxd_read_snr(struct dvb_frontend *fe, u16 * snr)
2864 {
2865         *snr = 0;
2866         return 0;
2867 }
2868
2869 static int drxd_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
2870 {
2871         *ucblocks = 0;
2872         return 0;
2873 }
2874
2875 static int drxd_sleep(struct dvb_frontend *fe)
2876 {
2877         struct drxd_state *state = fe->demodulator_priv;
2878
2879         ConfigureMPEGOutput(state, 0);
2880         return 0;
2881 }
2882
2883 static int drxd_get_frontend(struct dvb_frontend *fe,
2884                              struct dvb_frontend_parameters *param)
2885 {
2886         return 0;
2887 }
2888
2889 static int drxd_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
2890 {
2891         return drxd_config_i2c(fe, enable);
2892 }
2893
2894 static int drxd_set_frontend(struct dvb_frontend *fe,
2895                              struct dvb_frontend_parameters *param)
2896 {
2897         struct drxd_state *state = fe->demodulator_priv;
2898         s32 off = 0;
2899
2900         state->param = *param;
2901         DRX_Stop(state);
2902
2903         if (fe->ops.tuner_ops.set_params) {
2904                 fe->ops.tuner_ops.set_params(fe, param);
2905                 if (fe->ops.i2c_gate_ctrl)
2906                         fe->ops.i2c_gate_ctrl(fe, 0);
2907         }
2908
2909         /* FIXME: move PLL drivers */
2910         if (state->config.pll_set &&
2911             state->config.pll_set(state->priv, param,
2912                                   state->config.pll_address,
2913                                   state->config.demoda_address, &off) < 0) {
2914                 printk(KERN_ERR "Error in pll_set\n");
2915                 return -1;
2916         }
2917
2918         msleep(200);
2919
2920         return DRX_Start(state, off);
2921 }
2922
2923 static void drxd_release(struct dvb_frontend *fe)
2924 {
2925         struct drxd_state *state = fe->demodulator_priv;
2926
2927         kfree(state);
2928 }
2929
2930 static struct dvb_frontend_ops drxd_ops = {
2931
2932         .info = {
2933                  .name = "Micronas DRXD DVB-T",
2934                  .type = FE_OFDM,
2935                  .frequency_min = 47125000,
2936                  .frequency_max = 855250000,
2937                  .frequency_stepsize = 166667,
2938                  .frequency_tolerance = 0,
2939                  .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
2940                  FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
2941                  FE_CAN_FEC_AUTO |
2942                  FE_CAN_QAM_16 | FE_CAN_QAM_64 |
2943                  FE_CAN_QAM_AUTO |
2944                  FE_CAN_TRANSMISSION_MODE_AUTO |
2945                  FE_CAN_GUARD_INTERVAL_AUTO |
2946                  FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | FE_CAN_MUTE_TS},
2947
2948         .release = drxd_release,
2949         .init = drxd_init,
2950         .sleep = drxd_sleep,
2951         .i2c_gate_ctrl = drxd_i2c_gate_ctrl,
2952
2953         .set_frontend = drxd_set_frontend,
2954         .get_frontend = drxd_get_frontend,
2955         .get_tune_settings = drxd_get_tune_settings,
2956
2957         .read_status = drxd_read_status,
2958         .read_ber = drxd_read_ber,
2959         .read_signal_strength = drxd_read_signal_strength,
2960         .read_snr = drxd_read_snr,
2961         .read_ucblocks = drxd_read_ucblocks,
2962 };
2963
2964 struct dvb_frontend *drxd_attach(const struct drxd_config *config,
2965                                  void *priv, struct i2c_adapter *i2c,
2966                                  struct device *dev)
2967 {
2968         struct drxd_state *state = NULL;
2969
2970         state = kmalloc(sizeof(struct drxd_state), GFP_KERNEL);
2971         if (!state)
2972                 return NULL;
2973         memset(state, 0, sizeof(*state));
2974
2975         memcpy(&state->ops, &drxd_ops, sizeof(struct dvb_frontend_ops));
2976         state->dev = dev;
2977         state->config = *config;
2978         state->i2c = i2c;
2979         state->priv = priv;
2980
2981         mutex_init(&state->mutex);
2982
2983         if (Read16(state, 0, 0, 0) < 0)
2984                 goto error;
2985
2986         memcpy(&state->frontend.ops, &drxd_ops,
2987                sizeof(struct dvb_frontend_ops));
2988         state->frontend.demodulator_priv = state;
2989         ConfigureMPEGOutput(state, 0);
2990         return &state->frontend;
2991
2992 error:
2993         printk(KERN_ERR "drxd: not found\n");
2994         kfree(state);
2995         return NULL;
2996 }
2997 EXPORT_SYMBOL(drxd_attach);
2998
2999 MODULE_DESCRIPTION("DRXD driver");
3000 MODULE_AUTHOR("Micronas");
3001 MODULE_LICENSE("GPL");