drivers/media/dvb/frontends/dib3000mc.c

   1 /*
   2  * Frontend driver for mobile DVB-T demodulator DiBcom 3000P/M-C
   3  * DiBcom (http://www.dibcom.fr/)
   4  *
   5  * Copyright (C) 2004-5 Patrick Boettcher (patrick.boettcher@desy.de)
   6  *
   7  * based on GPL code from DiBCom, which has
   8  *
   9  * Copyright (C) 2004 Amaury Demol for DiBcom (ademol@dibcom.fr)
  10  *
  11  *      This program is free software; you can redistribute it and/or
  12  *      modify it under the terms of the GNU General Public License as
  13  *      published by the Free Software Foundation, version 2.
  14  *
  15  * Acknowledgements
  16  *
  17  *  Amaury Demol (ademol@dibcom.fr) from DiBcom for providing specs and driver
  18  *  sources, on which this driver (and the dvb-dibusb) are based.
  19  *
  20  * see Documentation/dvb/README.dibusb for more information
  21  *
  22  */
  23 #include <linux/config.h>
  24 #include <linux/kernel.h>
  25 #include <linux/version.h>
  26 #include <linux/module.h>
  27 #include <linux/moduleparam.h>
  28 #include <linux/init.h>
  29 #include <linux/delay.h>
  30
  31 #include "dib3000-common.h"
  32 #include "dib3000mc_priv.h"
  33 #include "dib3000.h"
  34
  35 /* Version information */
  36 #define DRIVER_VERSION "0.1"
  37 #define DRIVER_DESC "DiBcom 3000M-C DVB-T demodulator"
  38 #define DRIVER_AUTHOR "Patrick Boettcher, patrick.boettcher@desy.de"
  39
  40 #ifdef CONFIG_DVB_DIBCOM_DEBUG
  41 static int debug;
  42 module_param(debug, int, 0644);
  43 MODULE_PARM_DESC(debug, "set debugging level (1=info,2=xfer,4=setfe,8=getfe,16=stat (|-able)).");
  44 #endif
  45 #define deb_info(args...) dprintk(0x01,args)
  46 #define deb_xfer(args...) dprintk(0x02,args)
  47 #define deb_setf(args...) dprintk(0x04,args)
  48 #define deb_getf(args...) dprintk(0x08,args)
  49 #define deb_stat(args...) dprintk(0x10,args)
  50
  51 static int dib3000mc_set_impulse_noise(struct dib3000_state * state, int mode,
  52         fe_transmit_mode_t transmission_mode, fe_bandwidth_t bandwidth)
  53 {
  54         switch (transmission_mode) {
  55                 case TRANSMISSION_MODE_2K:
  56                         wr_foreach(dib3000mc_reg_fft,dib3000mc_fft_modes[0]);
  57                         break;
  58                 case TRANSMISSION_MODE_8K:
  59                         wr_foreach(dib3000mc_reg_fft,dib3000mc_fft_modes[1]);
  60                         break;
  61                 default:
  62                         break;
  63         }
  64
  65         switch (bandwidth) {
  66 /*              case BANDWIDTH_5_MHZ:
  67                         wr_foreach(dib3000mc_reg_impulse_noise,dib3000mc_impluse_noise[0]);
  68                         break; */
  69                 case BANDWIDTH_6_MHZ:
  70                         wr_foreach(dib3000mc_reg_impulse_noise,dib3000mc_impluse_noise[1]);
  71                         break;
  72                 case BANDWIDTH_7_MHZ:
  73                         wr_foreach(dib3000mc_reg_impulse_noise,dib3000mc_impluse_noise[2]);
  74                         break;
  75                 case BANDWIDTH_8_MHZ:
  76                         wr_foreach(dib3000mc_reg_impulse_noise,dib3000mc_impluse_noise[3]);
  77                         break;
  78                 default:
  79                         break;
  80         }
  81
  82         switch (mode) {
  83                 case 0: /* no impulse */ /* fall through */
  84                         wr_foreach(dib3000mc_reg_imp_noise_ctl,dib3000mc_imp_noise_ctl[0]);
  85                         break;
  86                 case 1: /* new algo */
  87                         wr_foreach(dib3000mc_reg_imp_noise_ctl,dib3000mc_imp_noise_ctl[1]);
  88                         set_or(DIB3000MC_REG_IMP_NOISE_55,DIB3000MC_IMP_NEW_ALGO(0)); /* gives 1<<10 */
  89                         break;
  90                 default: /* old algo */
  91                         wr_foreach(dib3000mc_reg_imp_noise_ctl,dib3000mc_imp_noise_ctl[3]);
  92                         break;
  93         }
  94         return 0;
  95 }
  96
  97 static int dib3000mc_set_timing(struct dib3000_state *state, int upd_offset,
  98                 fe_transmit_mode_t fft, fe_bandwidth_t bw)
  99 {
 100         u16 timf_msb,timf_lsb;
 101         s32 tim_offset,tim_sgn;
 102         u64 comp1,comp2,comp=0;
 103
 104         switch (bw) {
 105                 case BANDWIDTH_8_MHZ: comp = DIB3000MC_CLOCK_REF*8; break;
 106                 case BANDWIDTH_7_MHZ: comp = DIB3000MC_CLOCK_REF*7; break;
 107                 case BANDWIDTH_6_MHZ: comp = DIB3000MC_CLOCK_REF*6; break;
 108                 default: err("unknown bandwidth (%d)",bw); break;
 109         }
 110         timf_msb = (comp >> 16) & 0xff;
 111         timf_lsb = (comp & 0xffff);
 112
 113         // Update the timing offset ;
 114         if (upd_offset > 0) {
 115                 if (!state->timing_offset_comp_done) {
 116                         msleep(200);
 117                         state->timing_offset_comp_done = 1;
 118                 }
 119                 tim_offset = rd(DIB3000MC_REG_TIMING_OFFS_MSB);
 120                 if ((tim_offset & 0x2000) == 0x2000)
 121                         tim_offset |= 0xC000;
 122                 if (fft == TRANSMISSION_MODE_2K)
 123                         tim_offset <<= 2;
 124                 state->timing_offset += tim_offset;
 125         }
 126
 127         tim_offset = state->timing_offset;
 128         if (tim_offset < 0) {
 129                 tim_sgn = 1;
 130                 tim_offset = -tim_offset;
 131         } else
 132                 tim_sgn = 0;
 133
 134         comp1 =  (u32)tim_offset * (u32)timf_lsb ;
 135         comp2 =  (u32)tim_offset * (u32)timf_msb ;
 136         comp  = ((comp1 >> 16) + comp2) >> 7;
 137
 138         if (tim_sgn == 0)
 139                 comp = (u32)(timf_msb << 16) + (u32) timf_lsb + comp;
 140         else
 141                 comp = (u32)(timf_msb << 16) + (u32) timf_lsb - comp ;
 142
 143         timf_msb = (comp >> 16) & 0xff;
 144         timf_lsb = comp & 0xffff;
 145
 146         wr(DIB3000MC_REG_TIMING_FREQ_MSB,timf_msb);
 147         wr(DIB3000MC_REG_TIMING_FREQ_LSB,timf_lsb);
 148         return 0;
 149 }
 150
 151 static int dib3000mc_init_auto_scan(struct dib3000_state *state, fe_bandwidth_t bw, int boost)
 152 {
 153         if (boost) {
 154                 wr(DIB3000MC_REG_SCAN_BOOST,DIB3000MC_SCAN_BOOST_ON);
 155         } else {
 156                 wr(DIB3000MC_REG_SCAN_BOOST,DIB3000MC_SCAN_BOOST_OFF);
 157         }
 158         switch (bw) {
 159                 case BANDWIDTH_8_MHZ:
 160                         wr_foreach(dib3000mc_reg_bandwidth,dib3000mc_bandwidth_8mhz);
 161                         break;
 162                 case BANDWIDTH_7_MHZ:
 163                         wr_foreach(dib3000mc_reg_bandwidth,dib3000mc_bandwidth_7mhz);
 164                         break;
 165                 case BANDWIDTH_6_MHZ:
 166                         wr_foreach(dib3000mc_reg_bandwidth,dib3000mc_bandwidth_6mhz);
 167                         break;
 168 /*              case BANDWIDTH_5_MHZ:
 169                         wr_foreach(dib3000mc_reg_bandwidth,dib3000mc_bandwidth_5mhz);
 170                         break;*/
 171                 case BANDWIDTH_AUTO:
 172                         return -EOPNOTSUPP;
 173                 default:
 174                         err("unknown bandwidth value (%d).",bw);
 175                         return -EINVAL;
 176         }
 177         if (boost) {
 178                 u32 timeout = (rd(DIB3000MC_REG_BW_TIMOUT_MSB) << 16) +
 179                         rd(DIB3000MC_REG_BW_TIMOUT_LSB);
 180                 timeout *= 85; timeout >>= 7;
 181                 wr(DIB3000MC_REG_BW_TIMOUT_MSB,(timeout >> 16) & 0xffff);
 182                 wr(DIB3000MC_REG_BW_TIMOUT_LSB,timeout & 0xffff);
 183         }
 184         return 0;
 185 }
 186
 187 static int dib3000mc_set_adp_cfg(struct dib3000_state *state, fe_modulation_t con)
 188 {
 189         switch (con) {
 190                 case QAM_64:
 191                         wr_foreach(dib3000mc_reg_adp_cfg,dib3000mc_adp_cfg[2]);
 192                         break;
 193                 case QAM_16:
 194                         wr_foreach(dib3000mc_reg_adp_cfg,dib3000mc_adp_cfg[1]);
 195                         break;
 196                 case QPSK:
 197                         wr_foreach(dib3000mc_reg_adp_cfg,dib3000mc_adp_cfg[0]);
 198                         break;
 199                 case QAM_AUTO:
 200                         break;
 201                 default:
 202                         warn("unkown constellation.");
 203                         break;
 204         }
 205         return 0;
 206 }
 207
 208 static int dib3000mc_set_general_cfg(struct dib3000_state *state, struct dvb_frontend_parameters *fep, int *auto_val)
 209 {
 210         struct dvb_ofdm_parameters *ofdm = &fep->u.ofdm;
 211         fe_code_rate_t fe_cr = FEC_NONE;
 212         u8 fft=0, guard=0, qam=0, alpha=0, sel_hp=0, cr=0, hrch=0;
 213         int seq;
 214
 215         switch (ofdm->transmission_mode) {
 216                 case TRANSMISSION_MODE_2K: fft = DIB3000_TRANSMISSION_MODE_2K; break;
 217                 case TRANSMISSION_MODE_8K: fft = DIB3000_TRANSMISSION_MODE_8K; break;
 218                 case TRANSMISSION_MODE_AUTO: break;
 219                 default: return -EINVAL;
 220         }
 221         switch (ofdm->guard_interval) {
 222                 case GUARD_INTERVAL_1_32: guard = DIB3000_GUARD_TIME_1_32; break;
 223                 case GUARD_INTERVAL_1_16: guard = DIB3000_GUARD_TIME_1_16; break;
 224                 case GUARD_INTERVAL_1_8:  guard = DIB3000_GUARD_TIME_1_8; break;
 225                 case GUARD_INTERVAL_1_4:  guard = DIB3000_GUARD_TIME_1_4; break;
 226                 case GUARD_INTERVAL_AUTO: break;
 227                 default: return -EINVAL;
 228         }
 229         switch (ofdm->constellation) {
 230                 case QPSK:   qam = DIB3000_CONSTELLATION_QPSK; break;
 231                 case QAM_16: qam = DIB3000_CONSTELLATION_16QAM; break;
 232                 case QAM_64: qam = DIB3000_CONSTELLATION_64QAM; break;
 233                 case QAM_AUTO: break;
 234                 default: return -EINVAL;
 235         }
 236         switch (ofdm->hierarchy_information) {
 237                 case HIERARCHY_NONE: /* fall through */
 238                 case HIERARCHY_1: alpha = DIB3000_ALPHA_1; break;
 239                 case HIERARCHY_2: alpha = DIB3000_ALPHA_2; break;
 240                 case HIERARCHY_4: alpha = DIB3000_ALPHA_4; break;
 241                 case HIERARCHY_AUTO: break;
 242                 default: return -EINVAL;
 243         }
 244         if (ofdm->hierarchy_information == HIERARCHY_NONE) {
 245                 hrch   = DIB3000_HRCH_OFF;
 246                 sel_hp = DIB3000_SELECT_HP;
 247                 fe_cr  = ofdm->code_rate_HP;
 248         } else if (ofdm->hierarchy_information != HIERARCHY_AUTO) {
 249                 hrch   = DIB3000_HRCH_ON;
 250                 sel_hp = DIB3000_SELECT_LP;
 251                 fe_cr  = ofdm->code_rate_LP;
 252         }
 253         switch (fe_cr) {
 254                 case FEC_1_2: cr = DIB3000_FEC_1_2; break;
 255                 case FEC_2_3: cr = DIB3000_FEC_2_3; break;
 256                 case FEC_3_4: cr = DIB3000_FEC_3_4; break;
 257                 case FEC_5_6: cr = DIB3000_FEC_5_6; break;
 258                 case FEC_7_8: cr = DIB3000_FEC_7_8; break;
 259                 case FEC_NONE: break;
 260                 case FEC_AUTO: break;
 261                 default: return -EINVAL;
 262         }
 263
 264         wr(DIB3000MC_REG_DEMOD_PARM,DIB3000MC_DEMOD_PARM(alpha,qam,guard,fft));
 265         wr(DIB3000MC_REG_HRCH_PARM,DIB3000MC_HRCH_PARM(sel_hp,cr,hrch));
 266
 267         switch (fep->inversion) {
 268                 case INVERSION_OFF:
 269                         wr(DIB3000MC_REG_SET_DDS_FREQ_MSB,DIB3000MC_DDS_FREQ_MSB_INV_OFF);
 270                         break;
 271                 case INVERSION_AUTO: /* fall through */
 272                 case INVERSION_ON:
 273                         wr(DIB3000MC_REG_SET_DDS_FREQ_MSB,DIB3000MC_DDS_FREQ_MSB_INV_ON);
 274                         break;
 275                 default:
 276                         return -EINVAL;
 277         }
 278
 279         seq = dib3000_seq
 280                 [ofdm->transmission_mode == TRANSMISSION_MODE_AUTO]
 281                 [ofdm->guard_interval == GUARD_INTERVAL_AUTO]
 282                 [fep->inversion == INVERSION_AUTO];
 283
 284         deb_setf("seq? %d\n", seq);
 285         wr(DIB3000MC_REG_SEQ_TPS,DIB3000MC_SEQ_TPS(seq,1));
 286         *auto_val = ofdm->constellation == QAM_AUTO ||
 287                         ofdm->hierarchy_information == HIERARCHY_AUTO ||
 288                         ofdm->guard_interval == GUARD_INTERVAL_AUTO ||
 289                         ofdm->transmission_mode == TRANSMISSION_MODE_AUTO ||
 290                         fe_cr == FEC_AUTO ||
 291                         fep->inversion == INVERSION_AUTO;
 292         return 0;
 293 }
 294
 295 static int dib3000mc_get_frontend(struct dvb_frontend* fe,
 296                                   struct dvb_frontend_parameters *fep)
 297 {
 298         struct dib3000_state* state = fe->demodulator_priv;
 299         struct dvb_ofdm_parameters *ofdm = &fep->u.ofdm;
 300         fe_code_rate_t *cr;
 301         u16 tps_val,cr_val;
 302         int inv_test1,inv_test2;
 303         u32 dds_val, threshold = 0x1000000;
 304
 305         if (!(rd(DIB3000MC_REG_LOCK_507) & DIB3000MC_LOCK_507))
 306                 return 0;
 307
 308         dds_val = (rd(DIB3000MC_REG_DDS_FREQ_MSB) << 16) + rd(DIB3000MC_REG_DDS_FREQ_LSB);
 309         deb_getf("DDS_FREQ: %6x\n",dds_val);
 310         if (dds_val < threshold)
 311                 inv_test1 = 0;
 312         else if (dds_val == threshold)
 313                 inv_test1 = 1;
 314         else
 315                 inv_test1 = 2;
 316
 317         dds_val = (rd(DIB3000MC_REG_SET_DDS_FREQ_MSB) << 16) + rd(DIB3000MC_REG_SET_DDS_FREQ_LSB);
 318         deb_getf("DDS_SET_FREQ: %6x\n",dds_val);
 319         if (dds_val < threshold)
 320                 inv_test2 = 0;
 321         else if (dds_val == threshold)
 322                 inv_test2 = 1;
 323         else
 324                 inv_test2 = 2;
 325
 326         fep->inversion =
 327                 ((inv_test2 == 2) && (inv_test1==1 || inv_test1==0)) ||
 328                 ((inv_test2 == 0) && (inv_test1==1 || inv_test1==2)) ?
 329                 INVERSION_ON : INVERSION_OFF;
 330
 331         deb_getf("inversion %d %d, %d\n", inv_test2, inv_test1, fep->inversion);
 332
 333         fep->frequency = state->last_tuned_freq;
 334         fep->u.ofdm.bandwidth= state->last_tuned_bw;
 335
 336         tps_val = rd(DIB3000MC_REG_TUNING_PARM);
 337
 338         switch (DIB3000MC_TP_QAM(tps_val)) {
 339                 case DIB3000_CONSTELLATION_QPSK:
 340                         deb_getf("QPSK ");
 341                         ofdm->constellation = QPSK;
 342                         break;
 343                 case DIB3000_CONSTELLATION_16QAM:
 344                         deb_getf("QAM16 ");
 345                         ofdm->constellation = QAM_16;
 346                         break;
 347                 case DIB3000_CONSTELLATION_64QAM:
 348                         deb_getf("QAM64 ");
 349                         ofdm->constellation = QAM_64;
 350                         break;
 351                 default:
 352                         err("Unexpected constellation returned by TPS (%d)", tps_val);
 353                         break;
 354         }
 355
 356         if (DIB3000MC_TP_HRCH(tps_val)) {
 357                 deb_getf("HRCH ON ");
 358                 cr = &ofdm->code_rate_LP;
 359                 ofdm->code_rate_HP = FEC_NONE;
 360                 switch (DIB3000MC_TP_ALPHA(tps_val)) {
 361                         case DIB3000_ALPHA_0:
 362                                 deb_getf("HIERARCHY_NONE ");
 363                                 ofdm->hierarchy_information = HIERARCHY_NONE;
 364                                 break;
 365                         case DIB3000_ALPHA_1:
 366                                 deb_getf("HIERARCHY_1 ");
 367                                 ofdm->hierarchy_information = HIERARCHY_1;
 368                                 break;
 369                         case DIB3000_ALPHA_2:
 370                                 deb_getf("HIERARCHY_2 ");
 371                                 ofdm->hierarchy_information = HIERARCHY_2;
 372                                 break;
 373                         case DIB3000_ALPHA_4:
 374                                 deb_getf("HIERARCHY_4 ");
 375                                 ofdm->hierarchy_information = HIERARCHY_4;
 376                                 break;
 377                         default:
 378                                 err("Unexpected ALPHA value returned by TPS (%d)", tps_val);
 379                                 break;
 380                 }
 381                 cr_val = DIB3000MC_TP_FEC_CR_LP(tps_val);
 382         } else {
 383                 deb_getf("HRCH OFF ");
 384                 cr = &ofdm->code_rate_HP;
 385                 ofdm->code_rate_LP = FEC_NONE;
 386                 ofdm->hierarchy_information = HIERARCHY_NONE;
 387                 cr_val = DIB3000MC_TP_FEC_CR_HP(tps_val);
 388         }
 389
 390         switch (cr_val) {
 391                 case DIB3000_FEC_1_2:
 392                         deb_getf("FEC_1_2 ");
 393                         *cr = FEC_1_2;
 394                         break;
 395                 case DIB3000_FEC_2_3:
 396                         deb_getf("FEC_2_3 ");
 397                         *cr = FEC_2_3;
 398                         break;
 399                 case DIB3000_FEC_3_4:
 400                         deb_getf("FEC_3_4 ");
 401                         *cr = FEC_3_4;
 402                         break;
 403                 case DIB3000_FEC_5_6:
 404                         deb_getf("FEC_5_6 ");
 405                         *cr = FEC_4_5;
 406                         break;
 407                 case DIB3000_FEC_7_8:
 408                         deb_getf("FEC_7_8 ");
 409                         *cr = FEC_7_8;
 410                         break;
 411                 default:
 412                         err("Unexpected FEC returned by TPS (%d)", tps_val);
 413                         break;
 414         }
 415
 416         switch (DIB3000MC_TP_GUARD(tps_val)) {
 417                 case DIB3000_GUARD_TIME_1_32:
 418                         deb_getf("GUARD_INTERVAL_1_32 ");
 419                         ofdm->guard_interval = GUARD_INTERVAL_1_32;
 420                         break;
 421                 case DIB3000_GUARD_TIME_1_16:
 422                         deb_getf("GUARD_INTERVAL_1_16 ");
 423                         ofdm->guard_interval = GUARD_INTERVAL_1_16;
 424                         break;
 425                 case DIB3000_GUARD_TIME_1_8:
 426                         deb_getf("GUARD_INTERVAL_1_8 ");
 427                         ofdm->guard_interval = GUARD_INTERVAL_1_8;
 428                         break;
 429                 case DIB3000_GUARD_TIME_1_4:
 430                         deb_getf("GUARD_INTERVAL_1_4 ");
 431                         ofdm->guard_interval = GUARD_INTERVAL_1_4;
 432                         break;
 433                 default:
 434                         err("Unexpected Guard Time returned by TPS (%d)", tps_val);
 435                         break;
 436         }
 437
 438         switch (DIB3000MC_TP_FFT(tps_val)) {
 439                 case DIB3000_TRANSMISSION_MODE_2K:
 440                         deb_getf("TRANSMISSION_MODE_2K ");
 441                         ofdm->transmission_mode = TRANSMISSION_MODE_2K;
 442                         break;
 443                 case DIB3000_TRANSMISSION_MODE_8K:
 444                         deb_getf("TRANSMISSION_MODE_8K ");
 445                         ofdm->transmission_mode = TRANSMISSION_MODE_8K;
 446                         break;
 447                 default:
 448                         err("unexpected transmission mode return by TPS (%d)", tps_val);
 449                         break;
 450         }
 451         deb_getf("\n");
 452
 453         return 0;
 454 }
 455
 456 static int dib3000mc_set_frontend(struct dvb_frontend* fe,
 457                                   struct dvb_frontend_parameters *fep, int tuner)
 458 {
 459         struct dib3000_state* state = fe->demodulator_priv;
 460         struct dvb_ofdm_parameters *ofdm = &fep->u.ofdm;
 461         int search_state,auto_val;
 462         u16 val;
 463
 464         if (tuner && state->config.pll_set) { /* initial call from dvb */
 465                 state->config.pll_set(fe,fep);
 466
 467                 state->last_tuned_freq = fep->frequency;
 468         //      if (!scanboost) {
 469                         dib3000mc_set_timing(state,0,ofdm->transmission_mode,ofdm->bandwidth);
 470                         dib3000mc_init_auto_scan(state, ofdm->bandwidth, 0);
 471                         state->last_tuned_bw = ofdm->bandwidth;
 472
 473                         wr_foreach(dib3000mc_reg_agc_bandwidth,dib3000mc_agc_bandwidth);
 474                         wr(DIB3000MC_REG_RESTART,DIB3000MC_RESTART_AGC);
 475                         wr(DIB3000MC_REG_RESTART,DIB3000MC_RESTART_OFF);
 476
 477                         /* Default cfg isi offset adp */
 478                         wr_foreach(dib3000mc_reg_offset,dib3000mc_offset[0]);
 479
 480                         wr(DIB3000MC_REG_ISI,DIB3000MC_ISI_DEFAULT | DIB3000MC_ISI_INHIBIT);
 481                         dib3000mc_set_adp_cfg(state,ofdm->constellation);
 482                         wr(DIB3000MC_REG_UNK_133,DIB3000MC_UNK_133);
 483
 484                         wr_foreach(dib3000mc_reg_bandwidth_general,dib3000mc_bandwidth_general);
 485                         /* power smoothing */
 486                         if (ofdm->bandwidth != BANDWIDTH_8_MHZ) {
 487                                 wr_foreach(dib3000mc_reg_bw,dib3000mc_bw[0]);
 488                         } else {
 489                                 wr_foreach(dib3000mc_reg_bw,dib3000mc_bw[3]);
 490                         }
 491                         auto_val = 0;
 492                         dib3000mc_set_general_cfg(state,fep,&auto_val);
 493                         dib3000mc_set_impulse_noise(state,0,ofdm->constellation,ofdm->bandwidth);
 494
 495                         val = rd(DIB3000MC_REG_DEMOD_PARM);
 496                         wr(DIB3000MC_REG_DEMOD_PARM,val|DIB3000MC_DEMOD_RST_DEMOD_ON);
 497                         wr(DIB3000MC_REG_DEMOD_PARM,val);
 498         //      }
 499                 msleep(70);
 500
 501                 /* something has to be auto searched */
 502                 if (auto_val) {
 503                         int as_count=0;
 504
 505                         deb_setf("autosearch enabled.\n");
 506
 507                         val = rd(DIB3000MC_REG_DEMOD_PARM);
 508                         wr(DIB3000MC_REG_DEMOD_PARM,val | DIB3000MC_DEMOD_RST_AUTO_SRCH_ON);
 509                         wr(DIB3000MC_REG_DEMOD_PARM,val);
 510
 511                         while ((search_state = dib3000_search_status(
 512                                                 rd(DIB3000MC_REG_AS_IRQ),1)) < 0 && as_count++ < 100)
 513                                 msleep(10);
 514
 515                         deb_info("search_state after autosearch %d after %d checks\n",search_state,as_count);
 516
 517                         if (search_state == 1) {
 518                                 struct dvb_frontend_parameters feps;
 519                                 if (dib3000mc_get_frontend(fe, &feps) == 0) {
 520                                         deb_setf("reading tuning data from frontend succeeded.\n");
 521                                         return dib3000mc_set_frontend(fe, &feps, 0);
 522                                 }
 523                         }
 524                 } else {
 525                         dib3000mc_set_impulse_noise(state,0,ofdm->transmission_mode,ofdm->bandwidth);
 526                         wr(DIB3000MC_REG_ISI,DIB3000MC_ISI_DEFAULT|DIB3000MC_ISI_ACTIVATE);
 527                         dib3000mc_set_adp_cfg(state,ofdm->constellation);
 528
 529                         /* set_offset_cfg */
 530                         wr_foreach(dib3000mc_reg_offset,
 531                                         dib3000mc_offset[(ofdm->transmission_mode == TRANSMISSION_MODE_8K)+1]);
 532                 }
 533         } else { /* second call, after autosearch (fka: set_WithKnownParams) */
 534 //              dib3000mc_set_timing(state,1,ofdm->transmission_mode,ofdm->bandwidth);
 535
 536                 auto_val = 0;
 537                 dib3000mc_set_general_cfg(state,fep,&auto_val);
 538                 if (auto_val)
 539                         deb_info("auto_val is true, even though an auto search was already performed.\n");
 540
 541                 dib3000mc_set_impulse_noise(state,0,ofdm->constellation,ofdm->bandwidth);
 542
 543                 val = rd(DIB3000MC_REG_DEMOD_PARM);
 544                 wr(DIB3000MC_REG_DEMOD_PARM,val | DIB3000MC_DEMOD_RST_AUTO_SRCH_ON);
 545                 wr(DIB3000MC_REG_DEMOD_PARM,val);
 546
 547                 msleep(30);
 548
 549                 wr(DIB3000MC_REG_ISI,DIB3000MC_ISI_DEFAULT|DIB3000MC_ISI_ACTIVATE);
 550                         dib3000mc_set_adp_cfg(state,ofdm->constellation);
 551                 wr_foreach(dib3000mc_reg_offset,
 552                                 dib3000mc_offset[(ofdm->transmission_mode == TRANSMISSION_MODE_8K)+1]);
 553         }
 554         return 0;
 555 }
 556
 557 static int dib3000mc_fe_init(struct dvb_frontend* fe, int mobile_mode)
 558 {
 559         struct dib3000_state *state = fe->demodulator_priv;
 560         deb_info("init start\n");
 561
 562         state->timing_offset = 0;
 563         state->timing_offset_comp_done = 0;
 564
 565         wr(DIB3000MC_REG_RESTART,DIB3000MC_RESTART_CONFIG);
 566         wr(DIB3000MC_REG_RESTART,DIB3000MC_RESTART_OFF);
 567         wr(DIB3000MC_REG_CLK_CFG_1,DIB3000MC_CLK_CFG_1_POWER_UP);
 568         wr(DIB3000MC_REG_CLK_CFG_2,DIB3000MC_CLK_CFG_2_PUP_MOBILE);
 569         wr(DIB3000MC_REG_CLK_CFG_3,DIB3000MC_CLK_CFG_3_POWER_UP);
 570         wr(DIB3000MC_REG_CLK_CFG_7,DIB3000MC_CLK_CFG_7_INIT);
 571
 572         wr(DIB3000MC_REG_RST_UNC,DIB3000MC_RST_UNC_OFF);
 573         wr(DIB3000MC_REG_UNK_19,DIB3000MC_UNK_19);
 574
 575         wr(33,5);
 576         wr(36,81);
 577         wr(DIB3000MC_REG_UNK_88,DIB3000MC_UNK_88);
 578
 579         wr(DIB3000MC_REG_UNK_99,DIB3000MC_UNK_99);
 580         wr(DIB3000MC_REG_UNK_111,DIB3000MC_UNK_111_PH_N_MODE_0); /* phase noise algo off */
 581
 582         /* mobile mode - portable reception */
 583         wr_foreach(dib3000mc_reg_mobile_mode,dib3000mc_mobile_mode[1]);
 584
 585 /* TUNER_PANASONIC_ENV57H12D5: */
 586         wr_foreach(dib3000mc_reg_agc_bandwidth,dib3000mc_agc_bandwidth);
 587         wr_foreach(dib3000mc_reg_agc_bandwidth_general,dib3000mc_agc_bandwidth_general);
 588         wr_foreach(dib3000mc_reg_agc,dib3000mc_agc_tuner[1]);
 589
 590         wr(DIB3000MC_REG_UNK_110,DIB3000MC_UNK_110);
 591         wr(26,0x6680);
 592         wr(DIB3000MC_REG_UNK_1,DIB3000MC_UNK_1);
 593         wr(DIB3000MC_REG_UNK_2,DIB3000MC_UNK_2);
 594         wr(DIB3000MC_REG_UNK_3,DIB3000MC_UNK_3);
 595         wr(DIB3000MC_REG_SEQ_TPS,DIB3000MC_SEQ_TPS_DEFAULT);
 596
 597         wr_foreach(dib3000mc_reg_bandwidth,dib3000mc_bandwidth_8mhz);
 598         wr_foreach(dib3000mc_reg_bandwidth_general,dib3000mc_bandwidth_general);
 599
 600         wr(DIB3000MC_REG_UNK_4,DIB3000MC_UNK_4);
 601
 602         wr(DIB3000MC_REG_SET_DDS_FREQ_MSB,DIB3000MC_DDS_FREQ_MSB_INV_OFF);
 603         wr(DIB3000MC_REG_SET_DDS_FREQ_LSB,DIB3000MC_DDS_FREQ_LSB);
 604
 605         dib3000mc_set_timing(state,0,TRANSMISSION_MODE_8K,BANDWIDTH_8_MHZ);
 606 //      wr_foreach(dib3000mc_reg_timing_freq,dib3000mc_timing_freq[3]);
 607
 608         wr(DIB3000MC_REG_UNK_120,DIB3000MC_UNK_120);
 609         wr(DIB3000MC_REG_UNK_134,DIB3000MC_UNK_134);
 610         wr(DIB3000MC_REG_FEC_CFG,DIB3000MC_FEC_CFG);
 611
 612         wr(DIB3000MC_REG_DIVERSITY3,DIB3000MC_DIVERSITY3_IN_OFF);
 613
 614         dib3000mc_set_impulse_noise(state,0,TRANSMISSION_MODE_8K,BANDWIDTH_8_MHZ);
 615
 616 /* output mode control, just the MPEG2_SLAVE */
 617 //      set_or(DIB3000MC_REG_OUTMODE,DIB3000MC_OM_SLAVE);
 618         wr(DIB3000MC_REG_OUTMODE,DIB3000MC_OM_SLAVE);
 619         wr(DIB3000MC_REG_SMO_MODE,DIB3000MC_SMO_MODE_SLAVE);
 620         wr(DIB3000MC_REG_FIFO_THRESHOLD,DIB3000MC_FIFO_THRESHOLD_SLAVE);
 621         wr(DIB3000MC_REG_ELEC_OUT,DIB3000MC_ELEC_OUT_SLAVE);
 622
 623 /* MPEG2_PARALLEL_CONTINUOUS_CLOCK
 624         wr(DIB3000MC_REG_OUTMODE,
 625                 DIB3000MC_SET_OUTMODE(DIB3000MC_OM_PAR_CONT_CLK,
 626                         rd(DIB3000MC_REG_OUTMODE)));
 627
 628         wr(DIB3000MC_REG_SMO_MODE,
 629                         DIB3000MC_SMO_MODE_DEFAULT |
 630                         DIB3000MC_SMO_MODE_188);
 631
 632         wr(DIB3000MC_REG_FIFO_THRESHOLD,DIB3000MC_FIFO_THRESHOLD_DEFAULT);
 633         wr(DIB3000MC_REG_ELEC_OUT,DIB3000MC_ELEC_OUT_DIV_OUT_ON);
 634 */
 635
 636 /* diversity */
 637         wr(DIB3000MC_REG_DIVERSITY1,DIB3000MC_DIVERSITY1_DEFAULT);
 638         wr(DIB3000MC_REG_DIVERSITY2,DIB3000MC_DIVERSITY2_DEFAULT);
 639
 640         set_and(DIB3000MC_REG_DIVERSITY3,DIB3000MC_DIVERSITY3_IN_OFF);
 641
 642         set_or(DIB3000MC_REG_CLK_CFG_7,DIB3000MC_CLK_CFG_7_DIV_IN_OFF);
 643
 644         if (state->config.pll_init)
 645                 state->config.pll_init(fe);
 646
 647         deb_info("init end\n");
 648         return 0;
 649 }
 650 static int dib3000mc_read_status(struct dvb_frontend* fe, fe_status_t *stat)
 651 {
 652         struct dib3000_state* state = fe->demodulator_priv;
 653         u16 lock = rd(DIB3000MC_REG_LOCKING);
 654
 655         *stat = 0;
 656         if (DIB3000MC_AGC_LOCK(lock))
 657                 *stat |= FE_HAS_SIGNAL;
 658         if (DIB3000MC_CARRIER_LOCK(lock))
 659                 *stat |= FE_HAS_CARRIER;
 660         if (DIB3000MC_TPS_LOCK(lock))
 661                 *stat |= FE_HAS_VITERBI;
 662         if (DIB3000MC_MPEG_SYNC_LOCK(lock))
 663                 *stat |= (FE_HAS_SYNC | FE_HAS_LOCK);
 664
 665         deb_stat("actual status is %2x fifo_level: %x,244: %x, 206: %x, 207: %x, 1040: %x\n",*stat,rd(510),rd(244),rd(206),rd(207),rd(1040));
 666
 667         return 0;
 668 }
 669
 670 static int dib3000mc_read_ber(struct dvb_frontend* fe, u32 *ber)
 671 {
 672         struct dib3000_state* state = fe->demodulator_priv;
 673         *ber = ((rd(DIB3000MC_REG_BER_MSB) << 16) | rd(DIB3000MC_REG_BER_LSB));
 674         return 0;
 675 }
 676
 677 static int dib3000mc_read_unc_blocks(struct dvb_frontend* fe, u32 *unc)
 678 {
 679         struct dib3000_state* state = fe->demodulator_priv;
 680
 681         *unc = rd(DIB3000MC_REG_PACKET_ERRORS);
 682         return 0;
 683 }
 684
 685 /* see dib3000mb.c for calculation comments */
 686 static int dib3000mc_read_signal_strength(struct dvb_frontend* fe, u16 *strength)
 687 {
 688         struct dib3000_state* state = fe->demodulator_priv;
 689         u16 val = rd(DIB3000MC_REG_SIGNAL_NOISE_LSB);
 690         *strength = (((val >> 6) & 0xff) << 8) + (val & 0x3f);
 691
 692         deb_stat("signal: mantisse = %d, exponent = %d\n",(*strength >> 8) & 0xff, *strength & 0xff);
 693         return 0;
 694 }
 695
 696 /* see dib3000mb.c for calculation comments */
 697 static int dib3000mc_read_snr(struct dvb_frontend* fe, u16 *snr)
 698 {
 699         struct dib3000_state* state = fe->demodulator_priv;
 700         u16 val = rd(DIB3000MC_REG_SIGNAL_NOISE_LSB),
 701                 val2 = rd(DIB3000MC_REG_SIGNAL_NOISE_MSB);
 702         u16 sig,noise;
 703
 704         sig =   (((val >> 6) & 0xff) << 8) + (val & 0x3f);
 705         noise = (((val >> 4) & 0xff) << 8) + ((val & 0xf) << 2) + ((val2 >> 14) & 0x3);
 706         if (noise == 0)
 707                 *snr = 0xffff;
 708         else
 709                 *snr = (u16) sig/noise;
 710
 711         deb_stat("signal: mantisse = %d, exponent = %d\n",(sig >> 8) & 0xff, sig & 0xff);
 712         deb_stat("noise:  mantisse = %d, exponent = %d\n",(noise >> 8) & 0xff, noise & 0xff);
 713         deb_stat("snr: %d\n",*snr);
 714         return 0;
 715 }
 716
 717 static int dib3000mc_sleep(struct dvb_frontend* fe)
 718 {
 719         struct dib3000_state* state = fe->demodulator_priv;
 720
 721         set_or(DIB3000MC_REG_CLK_CFG_7,DIB3000MC_CLK_CFG_7_PWR_DOWN);
 722         wr(DIB3000MC_REG_CLK_CFG_1,DIB3000MC_CLK_CFG_1_POWER_DOWN);
 723         wr(DIB3000MC_REG_CLK_CFG_2,DIB3000MC_CLK_CFG_2_POWER_DOWN);
 724         wr(DIB3000MC_REG_CLK_CFG_3,DIB3000MC_CLK_CFG_3_POWER_DOWN);
 725         return 0;
 726 }
 727
 728 static int dib3000mc_fe_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings *tune)
 729 {
 730         tune->min_delay_ms = 1000;
 731         return 0;
 732 }
 733
 734 static int dib3000mc_fe_init_nonmobile(struct dvb_frontend* fe)
 735 {
 736         return dib3000mc_fe_init(fe, 0);
 737 }
 738
 739 static int dib3000mc_set_frontend_and_tuner(struct dvb_frontend* fe, struct dvb_frontend_parameters *fep)
 740 {
 741         return dib3000mc_set_frontend(fe, fep, 1);
 742 }
 743
 744 static void dib3000mc_release(struct dvb_frontend* fe)
 745 {
 746         struct dib3000_state *state = fe->demodulator_priv;
 747         kfree(state);
 748 }
 749
 750 /* pid filter and transfer stuff */
 751 static int dib3000mc_pid_control(struct dvb_frontend *fe,int index, int pid,int onoff)
 752 {
 753         struct dib3000_state *state = fe->demodulator_priv;
 754         pid = (onoff ? pid | DIB3000_ACTIVATE_PID_FILTERING : 0);
 755         wr(index+DIB3000MC_REG_FIRST_PID,pid);
 756         return 0;
 757 }
 758
 759 static int dib3000mc_fifo_control(struct dvb_frontend *fe, int onoff)
 760 {
 761         struct dib3000_state *state = fe->demodulator_priv;
 762         u16 tmp = rd(DIB3000MC_REG_SMO_MODE);
 763
 764         deb_xfer("%s fifo\n",onoff ? "enabling" : "disabling");
 765
 766         if (onoff) {
 767                 deb_xfer("%d %x\n",tmp & DIB3000MC_SMO_MODE_FIFO_UNFLUSH,tmp & DIB3000MC_SMO_MODE_FIFO_UNFLUSH);
 768                 wr(DIB3000MC_REG_SMO_MODE,tmp & DIB3000MC_SMO_MODE_FIFO_UNFLUSH);
 769         } else {
 770                 deb_xfer("%d %x\n",tmp | DIB3000MC_SMO_MODE_FIFO_FLUSH,tmp | DIB3000MC_SMO_MODE_FIFO_FLUSH);
 771                 wr(DIB3000MC_REG_SMO_MODE,tmp | DIB3000MC_SMO_MODE_FIFO_FLUSH);
 772         }
 773         return 0;
 774 }
 775
 776 static int dib3000mc_pid_parse(struct dvb_frontend *fe, int onoff)
 777 {
 778         struct dib3000_state *state = fe->demodulator_priv;
 779         u16 tmp = rd(DIB3000MC_REG_SMO_MODE);
 780
 781         deb_xfer("%s pid parsing\n",onoff ? "enabling" : "disabling");
 782
 783         if (onoff) {
 784                 wr(DIB3000MC_REG_SMO_MODE,tmp | DIB3000MC_SMO_MODE_PID_PARSE);
 785         } else {
 786                 wr(DIB3000MC_REG_SMO_MODE,tmp & DIB3000MC_SMO_MODE_NO_PID_PARSE);
 787         }
 788         return 0;
 789 }
 790
 791 static int dib3000mc_tuner_pass_ctrl(struct dvb_frontend *fe, int onoff, u8 pll_addr)
 792 {
 793         struct dib3000_state *state = fe->demodulator_priv;
 794         if (onoff) {
 795                 wr(DIB3000MC_REG_TUNER, DIB3000_TUNER_WRITE_ENABLE(pll_addr));
 796         } else {
 797                 wr(DIB3000MC_REG_TUNER, DIB3000_TUNER_WRITE_DISABLE(pll_addr));
 798         }
 799         return 0;
 800 }
 801
 802 static int dib3000mc_demod_init(struct dib3000_state *state)
 803 {
 804         u16 default_addr = 0x0a;
 805         /* first init */
 806         if (state->config.demod_address != default_addr) {
 807                 deb_info("initializing the demod the first time. Setting demod addr to 0x%x\n",default_addr);
 808                 wr(DIB3000MC_REG_ELEC_OUT,DIB3000MC_ELEC_OUT_DIV_OUT_ON);
 809                 wr(DIB3000MC_REG_OUTMODE,DIB3000MC_OM_PAR_CONT_CLK);
 810
 811                 wr(DIB3000MC_REG_RST_I2C_ADDR,
 812                         DIB3000MC_DEMOD_ADDR(default_addr) |
 813                         DIB3000MC_DEMOD_ADDR_ON);
 814
 815                 state->config.demod_address = default_addr;
 816
 817                 wr(DIB3000MC_REG_RST_I2C_ADDR,
 818                         DIB3000MC_DEMOD_ADDR(default_addr));
 819         } else
 820                 deb_info("demod is already initialized. Demod addr: 0x%x\n",state->config.demod_address);
 821         return 0;
 822 }
 823
 824
 825 static struct dvb_frontend_ops dib3000mc_ops;
 826
 827 struct dvb_frontend* dib3000mc_attach(const struct dib3000_config* config,
 828                                       struct i2c_adapter* i2c, struct dib_fe_xfer_ops *xfer_ops)
 829 {
 830         struct dib3000_state* state = NULL;
 831         u16 devid;
 832
 833         /* allocate memory for the internal state */
 834         state = kmalloc(sizeof(struct dib3000_state), GFP_KERNEL);
 835         if (state == NULL)
 836                 goto error;
 837         memset(state,0,sizeof(struct dib3000_state));
 838
 839         /* setup the state */
 840         state->i2c = i2c;
 841         memcpy(&state->config,config,sizeof(struct dib3000_config));
 842         memcpy(&state->ops, &dib3000mc_ops, sizeof(struct dvb_frontend_ops));
 843
 844         /* check for the correct demod */
 845         if (rd(DIB3000_REG_MANUFACTOR_ID) != DIB3000_I2C_ID_DIBCOM)
 846                 goto error;
 847
 848         devid = rd(DIB3000_REG_DEVICE_ID);
 849         if (devid != DIB3000MC_DEVICE_ID && devid != DIB3000P_DEVICE_ID)
 850                 goto error;
 851
 852         switch (devid) {
 853                 case DIB3000MC_DEVICE_ID:
 854                         info("Found a DiBcom 3000M-C, interesting...");
 855                         break;
 856                 case DIB3000P_DEVICE_ID:
 857                         info("Found a DiBcom 3000P.");
 858                         break;
 859         }
 860
 861         /* create dvb_frontend */
 862         state->frontend.ops = &state->ops;
 863         state->frontend.demodulator_priv = state;
 864
 865         /* set the xfer operations */
 866         xfer_ops->pid_parse = dib3000mc_pid_parse;
 867         xfer_ops->fifo_ctrl = dib3000mc_fifo_control;
 868         xfer_ops->pid_ctrl = dib3000mc_pid_control;
 869         xfer_ops->tuner_pass_ctrl = dib3000mc_tuner_pass_ctrl;
 870
 871         dib3000mc_demod_init(state);
 872
 873         return &state->frontend;
 874
 875 error:
 876         kfree(state);
 877         return NULL;
 878 }
 879
 880 static struct dvb_frontend_ops dib3000mc_ops = {
 881
 882         .info = {
 883                 .name                   = "DiBcom 3000P/M-C DVB-T",
 884                 .type                   = FE_OFDM,
 885                 .frequency_min          = 44250000,
 886                 .frequency_max          = 867250000,
 887                 .frequency_stepsize     = 62500,
 888                 .caps = FE_CAN_INVERSION_AUTO |
 889                                 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
 890                                 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
 891                                 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
 892                                 FE_CAN_TRANSMISSION_MODE_AUTO |
 893                                 FE_CAN_GUARD_INTERVAL_AUTO |
 894                                 FE_CAN_RECOVER |
 895                                 FE_CAN_HIERARCHY_AUTO,
 896         },
 897
 898         .release = dib3000mc_release,
 899
 900         .init = dib3000mc_fe_init_nonmobile,
 901         .sleep = dib3000mc_sleep,
 902
 903         .set_frontend = dib3000mc_set_frontend_and_tuner,
 904         .get_frontend = dib3000mc_get_frontend,
 905         .get_tune_settings = dib3000mc_fe_get_tune_settings,
 906
 907         .read_status = dib3000mc_read_status,
 908         .read_ber = dib3000mc_read_ber,
 909         .read_signal_strength = dib3000mc_read_signal_strength,
 910         .read_snr = dib3000mc_read_snr,
 911         .read_ucblocks = dib3000mc_read_unc_blocks,
 912 };
 913
 914 MODULE_AUTHOR(DRIVER_AUTHOR);
 915 MODULE_DESCRIPTION(DRIVER_DESC);
 916 MODULE_LICENSE("GPL");
 917
 918 EXPORT_SYMBOL(dib3000mc_attach);