2 * Sony CXD2820R demodulator driver
4 * Copyright (C) 2010 Antti Palosaari <crope@iki.fi>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
22 #include "cxd2820r_priv.h"
24 int cxd2820r_set_frontend_t(struct dvb_frontend *fe,
25 struct dvb_frontend_parameters *p)
27 struct cxd2820r_priv *priv = fe->demodulator_priv;
28 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
33 u8 bw_params1[][5] = {
34 { 0x17, 0xea, 0xaa, 0xaa, 0xaa }, /* 6 MHz */
35 { 0x14, 0x80, 0x00, 0x00, 0x00 }, /* 7 MHz */
36 { 0x11, 0xf0, 0x00, 0x00, 0x00 }, /* 8 MHz */
38 u8 bw_params2[][2] = {
39 { 0x1f, 0xdc }, /* 6 MHz */
40 { 0x12, 0xf8 }, /* 7 MHz */
41 { 0x01, 0xe0 }, /* 8 MHz */
43 struct reg_val_mask tab[] = {
44 { 0x00080, 0x00, 0xff },
45 { 0x00081, 0x03, 0xff },
46 { 0x00085, 0x07, 0xff },
47 { 0x00088, 0x01, 0xff },
49 { 0x00070, priv->cfg.ts_mode, 0xff },
50 { 0x000cb, priv->cfg.if_agc_polarity << 6, 0x40 },
51 { 0x000a5, 0x00, 0x01 },
52 { 0x00082, 0x20, 0x60 },
53 { 0x000c2, 0xc3, 0xff },
54 { 0x0016a, 0x50, 0xff },
55 { 0x00427, 0x41, 0xff },
58 dbg("%s: RF=%d BW=%d", __func__, c->frequency, c->bandwidth_hz);
61 ret = cxd2820r_gpio(fe);
66 if (fe->ops.tuner_ops.set_params)
67 fe->ops.tuner_ops.set_params(fe, p);
69 if (priv->delivery_system != SYS_DVBT) {
70 for (i = 0; i < ARRAY_SIZE(tab); i++) {
71 ret = cxd2820r_wr_reg_mask(priv, tab[i].reg,
72 tab[i].val, tab[i].mask);
78 priv->delivery_system = SYS_DVBT;
79 priv->ber_running = 0; /* tune stops BER counter */
81 switch (c->bandwidth_hz) {
83 if_khz = priv->cfg.if_dvbt_6;
88 if_khz = priv->cfg.if_dvbt_7;
93 if_khz = priv->cfg.if_dvbt_8;
103 if_ctl = cxd2820r_div_u64_round_closest(num, 41000);
104 buf[0] = ((if_ctl >> 16) & 0xff);
105 buf[1] = ((if_ctl >> 8) & 0xff);
106 buf[2] = ((if_ctl >> 0) & 0xff);
108 ret = cxd2820r_wr_regs(priv, 0x000b6, buf, 3);
112 ret = cxd2820r_wr_regs(priv, 0x0009f, bw_params1[i], 5);
116 ret = cxd2820r_wr_reg_mask(priv, 0x000d7, bw_param << 6, 0xc0);
120 ret = cxd2820r_wr_regs(priv, 0x000d9, bw_params2[i], 2);
124 ret = cxd2820r_wr_reg(priv, 0x000ff, 0x08);
128 ret = cxd2820r_wr_reg(priv, 0x000fe, 0x01);
134 dbg("%s: failed:%d", __func__, ret);
138 int cxd2820r_get_frontend_t(struct dvb_frontend *fe,
139 struct dvb_frontend_parameters *p)
141 struct cxd2820r_priv *priv = fe->demodulator_priv;
142 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
146 ret = cxd2820r_rd_regs(priv, 0x0002f, buf, sizeof(buf));
150 switch ((buf[0] >> 6) & 0x03) {
152 c->modulation = QPSK;
155 c->modulation = QAM_16;
158 c->modulation = QAM_64;
162 switch ((buf[1] >> 1) & 0x03) {
164 c->transmission_mode = TRANSMISSION_MODE_2K;
167 c->transmission_mode = TRANSMISSION_MODE_8K;
171 switch ((buf[1] >> 3) & 0x03) {
173 c->guard_interval = GUARD_INTERVAL_1_32;
176 c->guard_interval = GUARD_INTERVAL_1_16;
179 c->guard_interval = GUARD_INTERVAL_1_8;
182 c->guard_interval = GUARD_INTERVAL_1_4;
186 switch ((buf[0] >> 3) & 0x07) {
188 c->hierarchy = HIERARCHY_NONE;
191 c->hierarchy = HIERARCHY_1;
194 c->hierarchy = HIERARCHY_2;
197 c->hierarchy = HIERARCHY_4;
201 switch ((buf[0] >> 0) & 0x07) {
203 c->code_rate_HP = FEC_1_2;
206 c->code_rate_HP = FEC_2_3;
209 c->code_rate_HP = FEC_3_4;
212 c->code_rate_HP = FEC_5_6;
215 c->code_rate_HP = FEC_7_8;
219 switch ((buf[1] >> 5) & 0x07) {
221 c->code_rate_LP = FEC_1_2;
224 c->code_rate_LP = FEC_2_3;
227 c->code_rate_LP = FEC_3_4;
230 c->code_rate_LP = FEC_5_6;
233 c->code_rate_LP = FEC_7_8;
237 ret = cxd2820r_rd_reg(priv, 0x007c6, &buf[0]);
241 switch ((buf[0] >> 0) & 0x01) {
243 c->inversion = INVERSION_OFF;
246 c->inversion = INVERSION_ON;
252 dbg("%s: failed:%d", __func__, ret);
256 int cxd2820r_read_ber_t(struct dvb_frontend *fe, u32 *ber)
258 struct cxd2820r_priv *priv = fe->demodulator_priv;
260 u8 buf[3], start_ber = 0;
263 if (priv->ber_running) {
264 ret = cxd2820r_rd_regs(priv, 0x00076, buf, sizeof(buf));
268 if ((buf[2] >> 7) & 0x01 || (buf[2] >> 4) & 0x01) {
269 *ber = (buf[2] & 0x0f) << 16 | buf[1] << 8 | buf[0];
273 priv->ber_running = 1;
279 ret = cxd2820r_wr_reg(priv, 0x00079, 0x01);
286 dbg("%s: failed:%d", __func__, ret);
290 int cxd2820r_read_signal_strength_t(struct dvb_frontend *fe,
293 struct cxd2820r_priv *priv = fe->demodulator_priv;
298 ret = cxd2820r_rd_regs(priv, 0x00026, buf, sizeof(buf));
302 tmp = (buf[0] & 0x0f) << 8 | buf[1];
305 /* scale value to 0x0000-0xffff from 0x0000-0x0fff */
306 *strength = tmp * 0xffff / 0x0fff;
310 dbg("%s: failed:%d", __func__, ret);
314 int cxd2820r_read_snr_t(struct dvb_frontend *fe, u16 *snr)
316 struct cxd2820r_priv *priv = fe->demodulator_priv;
320 /* report SNR in dB * 10 */
322 ret = cxd2820r_rd_regs(priv, 0x00028, buf, sizeof(buf));
326 tmp = (buf[0] & 0x1f) << 8 | buf[1];
327 #define CXD2820R_LOG10_8_24 15151336 /* log10(8) << 24 */
329 *snr = (intlog10(tmp) - CXD2820R_LOG10_8_24) / ((1 << 24)
334 dbg("%s: dBx10=%d val=%04x", __func__, *snr, tmp);
338 dbg("%s: failed:%d", __func__, ret);
342 int cxd2820r_read_ucblocks_t(struct dvb_frontend *fe, u32 *ucblocks)
345 /* no way to read ? */
349 int cxd2820r_read_status_t(struct dvb_frontend *fe, fe_status_t *status)
351 struct cxd2820r_priv *priv = fe->demodulator_priv;
356 ret = cxd2820r_rd_reg(priv, 0x00010, &buf[0]);
360 if ((buf[0] & 0x07) == 6) {
361 ret = cxd2820r_rd_reg(priv, 0x00073, &buf[1]);
365 if (((buf[1] >> 3) & 0x01) == 1) {
366 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
367 FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
369 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
370 FE_HAS_VITERBI | FE_HAS_SYNC;
373 ret = cxd2820r_rd_reg(priv, 0x00014, &buf[2]);
377 if ((buf[2] & 0x0f) >= 4) {
378 ret = cxd2820r_rd_reg(priv, 0x00a14, &buf[3]);
382 if (((buf[3] >> 4) & 0x01) == 1)
383 *status |= FE_HAS_SIGNAL;
387 dbg("%s: lock=%02x %02x %02x %02x", __func__,
388 buf[0], buf[1], buf[2], buf[3]);
392 dbg("%s: failed:%d", __func__, ret);
396 int cxd2820r_init_t(struct dvb_frontend *fe)
398 struct cxd2820r_priv *priv = fe->demodulator_priv;
401 ret = cxd2820r_wr_reg(priv, 0x00085, 0x07);
407 dbg("%s: failed:%d", __func__, ret);
411 int cxd2820r_sleep_t(struct dvb_frontend *fe)
413 struct cxd2820r_priv *priv = fe->demodulator_priv;
415 struct reg_val_mask tab[] = {
416 { 0x000ff, 0x1f, 0xff },
417 { 0x00085, 0x00, 0xff },
418 { 0x00088, 0x01, 0xff },
419 { 0x00081, 0x00, 0xff },
420 { 0x00080, 0x00, 0xff },
425 priv->delivery_system = SYS_UNDEFINED;
427 for (i = 0; i < ARRAY_SIZE(tab); i++) {
428 ret = cxd2820r_wr_reg_mask(priv, tab[i].reg, tab[i].val,
436 dbg("%s: failed:%d", __func__, ret);
440 int cxd2820r_get_tune_settings_t(struct dvb_frontend *fe,
441 struct dvb_frontend_tune_settings *s)
443 s->min_delay_ms = 500;
444 s->step_size = fe->ops.info.frequency_stepsize * 2;
445 s->max_drift = (fe->ops.info.frequency_stepsize * 2) + 1;