drivers/media/dvb/frontends/cx24123.c

   1 /*
   2     Conexant cx24123/cx24109 - DVB QPSK Satellite demod/tuner driver
   3
   4     Copyright (C) 2005 Steven Toth <stoth@hauppauge.com>
   5
   6     Support for KWorld DVB-S 100 by Vadim Catana <skystar@moldova.cc>
   7
   8     This program is free software; you can redistribute it and/or modify
   9     it under the terms of the GNU General Public License as published by
  10     the Free Software Foundation; either version 2 of the License, or
  11     (at your option) any later version.
  12
  13     This program is distributed in the hope that it will be useful,
  14     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16     GNU General Public License for more details.
  17
  18     You should have received a copy of the GNU General Public License
  19     along with this program; if not, write to the Free Software
  20     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21 */
  22
  23 #include <linux/slab.h>
  24 #include <linux/kernel.h>
  25 #include <linux/module.h>
  26 #include <linux/moduleparam.h>
  27 #include <linux/init.h>
  28
  29 #include "dvb_frontend.h"
  30 #include "cx24123.h"
  31
  32 #define XTAL 10111000
  33
  34 static int debug;
  35 #define dprintk(args...) \
  36         do { \
  37                 if (debug) printk (KERN_DEBUG "cx24123: " args); \
  38         } while (0)
  39
  40 struct cx24123_state
  41 {
  42         struct i2c_adapter* i2c;
  43         struct dvb_frontend_ops ops;
  44         const struct cx24123_config* config;
  45
  46         struct dvb_frontend frontend;
  47
  48         u32 lastber;
  49         u16 snr;
  50         u8  lnbreg;
  51
  52         /* Some PLL specifics for tuning */
  53         u32 VCAarg;
  54         u32 VGAarg;
  55         u32 bandselectarg;
  56         u32 pllarg;
  57         u32 FILTune;
  58
  59         /* The Demod/Tuner can't easily provide these, we cache them */
  60         u32 currentfreq;
  61         u32 currentsymbolrate;
  62 };
  63
  64 /* Various tuner defaults need to be established for a given symbol rate Sps */
  65 static struct
  66 {
  67         u32 symbolrate_low;
  68         u32 symbolrate_high;
  69         u32 VCAprogdata;
  70         u32 VGAprogdata;
  71         u32 FILTune;
  72 } cx24123_AGC_vals[] =
  73 {
  74         {
  75                 .symbolrate_low         = 1000000,
  76                 .symbolrate_high        = 4999999,
  77                 /* the specs recommend other values for VGA offsets,
  78                    but tests show they are wrong */
  79                 .VGAprogdata            = (2 << 18) | (0x180 << 9) | 0x1e0,
  80                 .VCAprogdata            = (4 << 18) | (0x07 << 9) | 0x07,
  81                 .FILTune                = 0x280 /* 0.41 V */
  82         },
  83         {
  84                 .symbolrate_low         =  5000000,
  85                 .symbolrate_high        = 14999999,
  86                 .VGAprogdata            = (2 << 18) | (0x180 << 9) | 0x1e0,
  87                 .VCAprogdata            = (4 << 18) | (0x07 << 9) | 0x1f,
  88                 .FILTune                = 0x317 /* 0.90 V */
  89         },
  90         {
  91                 .symbolrate_low         = 15000000,
  92                 .symbolrate_high        = 45000000,
  93                 .VGAprogdata            = (2 << 18) | (0x100 << 9) | 0x180,
  94                 .VCAprogdata            = (4 << 18) | (0x07 << 9) | 0x3f,
  95                 .FILTune                = 0x146 /* 2.70 V */
  96         },
  97 };
  98
  99 /*
 100  * Various tuner defaults need to be established for a given frequency kHz.
 101  * fixme: The bounds on the bands do not match the doc in real life.
 102  * fixme: Some of them have been moved, other might need adjustment.
 103  */
 104 static struct
 105 {
 106         u32 freq_low;
 107         u32 freq_high;
 108         u32 VCOdivider;
 109         u32 progdata;
 110 } cx24123_bandselect_vals[] =
 111 {
 112         {
 113                 .freq_low       = 950000,
 114                 .freq_high      = 1018999,
 115                 .VCOdivider     = 4,
 116                 .progdata       = (0 << 18) | (0 << 9) | 0x40,
 117         },
 118         {
 119                 .freq_low       = 1019000,
 120                 .freq_high      = 1074999,
 121                 .VCOdivider     = 4,
 122                 .progdata       = (0 << 18) | (0 << 9) | 0x80,
 123         },
 124         {
 125                 .freq_low       = 1075000,
 126                 .freq_high      = 1227999,
 127                 .VCOdivider     = 2,
 128                 .progdata       = (0 << 18) | (1 << 9) | 0x01,
 129         },
 130         {
 131                 .freq_low       = 1228000,
 132                 .freq_high      = 1349999,
 133                 .VCOdivider     = 2,
 134                 .progdata       = (0 << 18) | (1 << 9) | 0x02,
 135         },
 136         {
 137                 .freq_low       = 1350000,
 138                 .freq_high      = 1481999,
 139                 .VCOdivider     = 2,
 140                 .progdata       = (0 << 18) | (1 << 9) | 0x04,
 141         },
 142         {
 143                 .freq_low       = 1482000,
 144                 .freq_high      = 1595999,
 145                 .VCOdivider     = 2,
 146                 .progdata       = (0 << 18) | (1 << 9) | 0x08,
 147         },
 148         {
 149                 .freq_low       = 1596000,
 150                 .freq_high      = 1717999,
 151                 .VCOdivider     = 2,
 152                 .progdata       = (0 << 18) | (1 << 9) | 0x10,
 153         },
 154         {
 155                 .freq_low       = 1718000,
 156                 .freq_high      = 1855999,
 157                 .VCOdivider     = 2,
 158                 .progdata       = (0 << 18) | (1 << 9) | 0x20,
 159         },
 160         {
 161                 .freq_low       = 1856000,
 162                 .freq_high      = 2035999,
 163                 .VCOdivider     = 2,
 164                 .progdata       = (0 << 18) | (1 << 9) | 0x40,
 165         },
 166         {
 167                 .freq_low       = 2036000,
 168                 .freq_high      = 2149999,
 169                 .VCOdivider     = 2,
 170                 .progdata       = (0 << 18) | (1 << 9) | 0x80,
 171         },
 172 };
 173
 174 static struct {
 175         u8 reg;
 176         u8 data;
 177 } cx24123_regdata[] =
 178 {
 179         {0x00, 0x03}, /* Reset system */
 180         {0x00, 0x00}, /* Clear reset */
 181         {0x03, 0x07},
 182         {0x04, 0x10},
 183         {0x05, 0x04},
 184         {0x06, 0x31},
 185         {0x0d, 0x02},
 186         {0x0e, 0x03},
 187         {0x0f, 0xfe},
 188         {0x10, 0x01},
 189         {0x14, 0x01},
 190         {0x16, 0x00},
 191         {0x17, 0x01},
 192         {0x1b, 0x05},
 193         {0x1c, 0x80},
 194         {0x1d, 0x00},
 195         {0x1e, 0x00},
 196         {0x20, 0x41},
 197         {0x21, 0x15},
 198         {0x29, 0x00},
 199         {0x2a, 0xb0},
 200         {0x2b, 0x73},
 201         {0x2c, 0x00},
 202         {0x2d, 0x00},
 203         {0x2e, 0x00},
 204         {0x2f, 0x00},
 205         {0x30, 0x00},
 206         {0x31, 0x00},
 207         {0x32, 0x8c},
 208         {0x33, 0x00},
 209         {0x34, 0x00},
 210         {0x35, 0x03},
 211         {0x36, 0x02},
 212         {0x37, 0x3a},
 213         {0x3a, 0x00},   /* Enable AGC accumulator */
 214         {0x44, 0x00},
 215         {0x45, 0x00},
 216         {0x46, 0x05},
 217         {0x56, 0x41},
 218         {0x57, 0xff},
 219         {0x67, 0x83},
 220 };
 221
 222 static int cx24123_writereg(struct cx24123_state* state, int reg, int data)
 223 {
 224         u8 buf[] = { reg, data };
 225         struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
 226         int err;
 227
 228         if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) {
 229                 printk("%s: writereg error(err == %i, reg == 0x%02x,"
 230                          " data == 0x%02x)\n", __FUNCTION__, err, reg, data);
 231                 return -EREMOTEIO;
 232         }
 233
 234         return 0;
 235 }
 236
 237 static int cx24123_writelnbreg(struct cx24123_state* state, int reg, int data)
 238 {
 239         u8 buf[] = { reg, data };
 240         /* fixme: put the intersil addr int the config */
 241         struct i2c_msg msg = { .addr = 0x08, .flags = 0, .buf = buf, .len = 2 };
 242         int err;
 243
 244         if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) {
 245                 printk("%s: writelnbreg error (err == %i, reg == 0x%02x,"
 246                          " data == 0x%02x)\n", __FUNCTION__, err, reg, data);
 247                 return -EREMOTEIO;
 248         }
 249
 250         /* cache the write, no way to read back */
 251         state->lnbreg = data;
 252
 253         return 0;
 254 }
 255
 256 static int cx24123_readreg(struct cx24123_state* state, u8 reg)
 257 {
 258         int ret;
 259         u8 b0[] = { reg };
 260         u8 b1[] = { 0 };
 261         struct i2c_msg msg[] = {
 262                 { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 },
 263                 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 }
 264         };
 265
 266         ret = i2c_transfer(state->i2c, msg, 2);
 267
 268         if (ret != 2) {
 269                 printk("%s: reg=0x%x (error=%d)\n", __FUNCTION__, reg, ret);
 270                 return ret;
 271         }
 272
 273         return b1[0];
 274 }
 275
 276 static int cx24123_readlnbreg(struct cx24123_state* state, u8 reg)
 277 {
 278         return state->lnbreg;
 279 }
 280
 281 static int cx24123_set_inversion(struct cx24123_state* state, fe_spectral_inversion_t inversion)
 282 {
 283         switch (inversion) {
 284         case INVERSION_OFF:
 285                 cx24123_writereg(state, 0x0e, cx24123_readreg(state, 0x0e) & 0x7f);
 286                 cx24123_writereg(state, 0x10, cx24123_readreg(state, 0x10) | 0x80);
 287                 break;
 288         case INVERSION_ON:
 289                 cx24123_writereg(state, 0x0e, cx24123_readreg(state, 0x0e) | 0x80);
 290                 cx24123_writereg(state, 0x10, cx24123_readreg(state, 0x10) | 0x80);
 291                 break;
 292         case INVERSION_AUTO:
 293                 cx24123_writereg(state, 0x10, cx24123_readreg(state, 0x10) & 0x7f);
 294                 break;
 295         default:
 296                 return -EINVAL;
 297         }
 298
 299         return 0;
 300 }
 301
 302 static int cx24123_get_inversion(struct cx24123_state* state, fe_spectral_inversion_t *inversion)
 303 {
 304         u8 val;
 305
 306         val = cx24123_readreg(state, 0x1b) >> 7;
 307
 308         if (val == 0)
 309                 *inversion = INVERSION_OFF;
 310         else
 311                 *inversion = INVERSION_ON;
 312
 313         return 0;
 314 }
 315
 316 static int cx24123_set_fec(struct cx24123_state* state, fe_code_rate_t fec)
 317 {
 318         if ( (fec < FEC_NONE) || (fec > FEC_AUTO) )
 319                 fec = FEC_AUTO;
 320
 321         /* Hardware has 5/11 and 3/5 but are never unused */
 322         switch (fec) {
 323         case FEC_NONE:
 324                 return cx24123_writereg(state, 0x0f, 0x01);
 325         case FEC_1_2:
 326                 return cx24123_writereg(state, 0x0f, 0x02);
 327         case FEC_2_3:
 328                 return cx24123_writereg(state, 0x0f, 0x04);
 329         case FEC_3_4:
 330                 return cx24123_writereg(state, 0x0f, 0x08);
 331         case FEC_5_6:
 332                 return cx24123_writereg(state, 0x0f, 0x20);
 333         case FEC_7_8:
 334                 return cx24123_writereg(state, 0x0f, 0x80);
 335         case FEC_AUTO:
 336                 return cx24123_writereg(state, 0x0f, 0xae);
 337         default:
 338                 return -EOPNOTSUPP;
 339         }
 340 }
 341
 342 static int cx24123_get_fec(struct cx24123_state* state, fe_code_rate_t *fec)
 343 {
 344         int ret;
 345
 346         ret = cx24123_readreg (state, 0x1b);
 347         if (ret < 0)
 348                 return ret;
 349         ret = ret & 0x07;
 350
 351         switch (ret) {
 352         case 1:
 353                 *fec = FEC_1_2;
 354                 break;
 355         case 2:
 356                 *fec = FEC_2_3;
 357                 break;
 358         case 3:
 359                 *fec = FEC_3_4;
 360                 break;
 361         case 4:
 362                 *fec = FEC_4_5;
 363                 break;
 364         case 5:
 365                 *fec = FEC_5_6;
 366                 break;
 367         case 6:
 368                 *fec = FEC_6_7;
 369                 break;
 370         case 7:
 371                 *fec = FEC_7_8;
 372                 break;
 373         default:
 374                 *fec = FEC_NONE; // can't happen
 375                 printk("FEC_NONE ?\n");
 376         }
 377
 378         return 0;
 379 }
 380
 381 static int cx24123_set_symbolrate(struct cx24123_state* state, u32 srate)
 382 {
 383         u32 tmp, sample_rate, ratio;
 384         u8 pll_mult;
 385
 386         /*  check if symbol rate is within limits */
 387         if ((srate > state->ops.info.symbol_rate_max) ||
 388             (srate < state->ops.info.symbol_rate_min))
 389                 return -EOPNOTSUPP;;
 390
 391         /* choose the sampling rate high enough for the required operation,
 392            while optimizing the power consumed by the demodulator */
 393         if (srate < (XTAL*2)/2)
 394                 pll_mult = 2;
 395         else if (srate < (XTAL*3)/2)
 396                 pll_mult = 3;
 397         else if (srate < (XTAL*4)/2)
 398                 pll_mult = 4;
 399         else if (srate < (XTAL*5)/2)
 400                 pll_mult = 5;
 401         else if (srate < (XTAL*6)/2)
 402                 pll_mult = 6;
 403         else if (srate < (XTAL*7)/2)
 404                 pll_mult = 7;
 405         else if (srate < (XTAL*8)/2)
 406                 pll_mult = 8;
 407         else
 408                 pll_mult = 9;
 409
 410
 411         sample_rate = pll_mult * XTAL;
 412
 413         /*
 414             SYSSymbolRate[21:0] = (srate << 23) / sample_rate
 415
 416             We have to use 32 bit unsigned arithmetic without precision loss.
 417             The maximum srate is 45000000 or 0x02AEA540. This number has
 418             only 6 clear bits on top, hence we can shift it left only 6 bits
 419             at a time. Borrowed from cx24110.c
 420         */
 421
 422         tmp = srate << 6;
 423         ratio = tmp / sample_rate;
 424
 425         tmp = (tmp % sample_rate) << 6;
 426         ratio = (ratio << 6) + (tmp / sample_rate);
 427
 428         tmp = (tmp % sample_rate) << 6;
 429         ratio = (ratio << 6) + (tmp / sample_rate);
 430
 431         tmp = (tmp % sample_rate) << 5;
 432         ratio = (ratio << 5) + (tmp / sample_rate);
 433
 434
 435         cx24123_writereg(state, 0x01, pll_mult * 6);
 436
 437         cx24123_writereg(state, 0x08, (ratio >> 16) & 0x3f );
 438         cx24123_writereg(state, 0x09, (ratio >>  8) & 0xff );
 439         cx24123_writereg(state, 0x0a, (ratio      ) & 0xff );
 440
 441         dprintk("%s: srate=%d, ratio=0x%08x, sample_rate=%i\n", __FUNCTION__, srate, ratio, sample_rate);
 442
 443         return 0;
 444 }
 445
 446 /*
 447  * Based on the required frequency and symbolrate, the tuner AGC has to be configured
 448  * and the correct band selected. Calculate those values
 449  */
 450 static int cx24123_pll_calculate(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
 451 {
 452         struct cx24123_state *state = fe->demodulator_priv;
 453         u32 ndiv = 0, adiv = 0, vco_div = 0;
 454         int i = 0;
 455         int pump = 2;
 456
 457         /* Defaults for low freq, low rate */
 458         state->VCAarg = cx24123_AGC_vals[0].VCAprogdata;
 459         state->VGAarg = cx24123_AGC_vals[0].VGAprogdata;
 460         state->bandselectarg = cx24123_bandselect_vals[0].progdata;
 461         vco_div = cx24123_bandselect_vals[0].VCOdivider;
 462
 463         /* For the given symbol rate, determine the VCA, VGA and FILTUNE programming bits */
 464         for (i = 0; i < sizeof(cx24123_AGC_vals) / sizeof(cx24123_AGC_vals[0]); i++)
 465         {
 466                 if ((cx24123_AGC_vals[i].symbolrate_low <= p->u.qpsk.symbol_rate) &&
 467                     (cx24123_AGC_vals[i].symbolrate_high >= p->u.qpsk.symbol_rate) ) {
 468                         state->VCAarg = cx24123_AGC_vals[i].VCAprogdata;
 469                         state->VGAarg = cx24123_AGC_vals[i].VGAprogdata;
 470                         state->FILTune = cx24123_AGC_vals[i].FILTune;
 471                 }
 472         }
 473
 474         /* For the given frequency, determine the bandselect programming bits */
 475         for (i = 0; i < sizeof(cx24123_bandselect_vals) / sizeof(cx24123_bandselect_vals[0]); i++)
 476         {
 477                 if ((cx24123_bandselect_vals[i].freq_low <= p->frequency) &&
 478                     (cx24123_bandselect_vals[i].freq_high >= p->frequency) ) {
 479                         state->bandselectarg = cx24123_bandselect_vals[i].progdata;
 480                         vco_div = cx24123_bandselect_vals[i].VCOdivider;
 481
 482                         /* determine the charge pump current */
 483                         if ( p->frequency < (cx24123_bandselect_vals[i].freq_low + cx24123_bandselect_vals[i].freq_high)/2 )
 484                                 pump = 0x01;
 485                         else
 486                                 pump = 0x02;
 487                 }
 488         }
 489
 490         /* Determine the N/A dividers for the requested lband freq (in kHz). */
 491         /* Note: the reference divider R=10, frequency is in KHz, XTAL is in Hz */
 492         ndiv = ( ((p->frequency * vco_div * 10) / (2 * XTAL / 1000)) / 32) & 0x1ff;
 493         adiv = ( ((p->frequency * vco_div * 10) / (2 * XTAL / 1000)) % 32) & 0x1f;
 494
 495         if (adiv == 0)
 496                 ndiv++;
 497
 498         /* control bits 11, refdiv 11, charge pump polarity 1, charge pump current, ndiv, adiv */
 499         state->pllarg = (3 << 19) | (3 << 17) | (1 << 16) | (pump << 14) | (ndiv << 5) | adiv;
 500
 501         return 0;
 502 }
 503
 504 /*
 505  * Tuner data is 21 bits long, must be left-aligned in data.
 506  * Tuner cx24109 is written through a dedicated 3wire interface on the demod chip.
 507  */
 508 static int cx24123_pll_writereg(struct dvb_frontend* fe, struct dvb_frontend_parameters *p, u32 data)
 509 {
 510         struct cx24123_state *state = fe->demodulator_priv;
 511         unsigned long timeout;
 512
 513         /* align the 21 bytes into to bit23 boundary */
 514         data = data << 3;
 515
 516         /* Reset the demod pll word length to 0x15 bits */
 517         cx24123_writereg(state, 0x21, 0x15);
 518
 519         /* write the msb 8 bits, wait for the send to be completed */
 520         timeout = jiffies + msecs_to_jiffies(40);
 521         cx24123_writereg(state, 0x22, (data >> 16) & 0xff);
 522         while ((cx24123_readreg(state, 0x20) & 0x40) == 0) {
 523                 if (time_after(jiffies, timeout)) {
 524                         printk("%s:  demodulator is not responding, possibly hung, aborting.\n", __FUNCTION__);
 525                         return -EREMOTEIO;
 526                 }
 527                 msleep(10);
 528         }
 529
 530         /* send another 8 bytes, wait for the send to be completed */
 531         timeout = jiffies + msecs_to_jiffies(40);
 532         cx24123_writereg(state, 0x22, (data>>8) & 0xff );
 533         while ((cx24123_readreg(state, 0x20) & 0x40) == 0) {
 534                 if (time_after(jiffies, timeout)) {
 535                         printk("%s:  demodulator is not responding, possibly hung, aborting.\n", __FUNCTION__);
 536                         return -EREMOTEIO;
 537                 }
 538                 msleep(10);
 539         }
 540
 541         /* send the lower 5 bits of this byte, padded with 3 LBB, wait for the send to be completed */
 542         timeout = jiffies + msecs_to_jiffies(40);
 543         cx24123_writereg(state, 0x22, (data) & 0xff );
 544         while ((cx24123_readreg(state, 0x20) & 0x80)) {
 545                 if (time_after(jiffies, timeout)) {
 546                         printk("%s:  demodulator is not responding, possibly hung, aborting.\n", __FUNCTION__);
 547                         return -EREMOTEIO;
 548                 }
 549                 msleep(10);
 550         }
 551
 552         /* Trigger the demod to configure the tuner */
 553         cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) | 2);
 554         cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) & 0xfd);
 555
 556         return 0;
 557 }
 558
 559 static int cx24123_pll_tune(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
 560 {
 561         struct cx24123_state *state = fe->demodulator_priv;
 562         u8 val;
 563
 564         dprintk("frequency=%i\n", p->frequency);
 565
 566         if (cx24123_pll_calculate(fe, p) != 0) {
 567                 printk("%s: cx24123_pll_calcutate failed\n",__FUNCTION__);
 568                 return -EINVAL;
 569         }
 570
 571         /* Write the new VCO/VGA */
 572         cx24123_pll_writereg(fe, p, state->VCAarg);
 573         cx24123_pll_writereg(fe, p, state->VGAarg);
 574
 575         /* Write the new bandselect and pll args */
 576         cx24123_pll_writereg(fe, p, state->bandselectarg);
 577         cx24123_pll_writereg(fe, p, state->pllarg);
 578
 579         /* set the FILTUNE voltage */
 580         val = cx24123_readreg(state, 0x28) & ~0x3;
 581         cx24123_writereg(state, 0x27, state->FILTune >> 2);
 582         cx24123_writereg(state, 0x28, val | (state->FILTune & 0x3));
 583
 584         return 0;
 585 }
 586
 587 static int cx24123_initfe(struct dvb_frontend* fe)
 588 {
 589         struct cx24123_state *state = fe->demodulator_priv;
 590         int i;
 591
 592         /* Configure the demod to a good set of defaults */
 593         for (i = 0; i < sizeof(cx24123_regdata) / sizeof(cx24123_regdata[0]); i++)
 594                 cx24123_writereg(state, cx24123_regdata[i].reg, cx24123_regdata[i].data);
 595
 596         if (state->config->pll_init)
 597                 state->config->pll_init(fe);
 598
 599         /* Configure the LNB for 14V */
 600         if (state->config->use_isl6421)
 601                 cx24123_writelnbreg(state, 0x0, 0x2a);
 602
 603         return 0;
 604 }
 605
 606 static int cx24123_set_voltage(struct dvb_frontend* fe, fe_sec_voltage_t voltage)
 607 {
 608         struct cx24123_state *state = fe->demodulator_priv;
 609         u8 val;
 610
 611         switch (state->config->use_isl6421) {
 612
 613         case 1:
 614
 615                 val = cx24123_readlnbreg(state, 0x0);
 616
 617                 switch (voltage) {
 618                 case SEC_VOLTAGE_13:
 619                         return cx24123_writelnbreg(state, 0x0, val & 0x32); /* V 13v */
 620                 case SEC_VOLTAGE_18:
 621                         return cx24123_writelnbreg(state, 0x0, val | 0x04); /* H 18v */
 622                 case SEC_VOLTAGE_OFF:
 623                         return cx24123_writelnbreg(state, 0x0, val & 0x30);
 624                 default:
 625                         return -EINVAL;
 626                 };
 627
 628         case 0:
 629
 630                 val = cx24123_readreg(state, 0x29);
 631
 632                 switch (voltage) {
 633                 case SEC_VOLTAGE_13:
 634                         dprintk("%s: setting voltage 13V\n", __FUNCTION__);
 635                         if (state->config->enable_lnb_voltage)
 636                                 state->config->enable_lnb_voltage(fe, 1);
 637                         return cx24123_writereg(state, 0x29, val | 0x80);
 638                 case SEC_VOLTAGE_18:
 639                         dprintk("%s: setting voltage 18V\n", __FUNCTION__);
 640                         if (state->config->enable_lnb_voltage)
 641                                 state->config->enable_lnb_voltage(fe, 1);
 642                         return cx24123_writereg(state, 0x29, val & 0x7f);
 643                 case SEC_VOLTAGE_OFF:
 644                         dprintk("%s: setting voltage off\n", __FUNCTION__);
 645                         if (state->config->enable_lnb_voltage)
 646                                 state->config->enable_lnb_voltage(fe, 0);
 647                         return 0;
 648                 default:
 649                         return -EINVAL;
 650                 };
 651         }
 652
 653         return 0;
 654 }
 655
 656 static int cx24123_send_diseqc_msg(struct dvb_frontend* fe, struct dvb_diseqc_master_cmd *cmd)
 657 {
 658         struct cx24123_state *state = fe->demodulator_priv;
 659         int i, val;
 660         unsigned long timeout;
 661
 662         dprintk("%s:\n",__FUNCTION__);
 663
 664         /* check if continuous tone has been stoped */
 665         if (state->config->use_isl6421)
 666                 val = cx24123_readlnbreg(state, 0x00) & 0x10;
 667         else
 668                 val = cx24123_readreg(state, 0x29) & 0x10;
 669
 670
 671         if (val) {
 672                 printk("%s: ERROR: attempt to send diseqc command before tone is off\n", __FUNCTION__);
 673                 return -ENOTSUPP;
 674         }
 675
 676         /* select tone mode */
 677         cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) & 0xf8);
 678
 679         for (i = 0; i < cmd->msg_len; i++)
 680                 cx24123_writereg(state, 0x2C + i, cmd->msg[i]);
 681
 682         val = cx24123_readreg(state, 0x29);
 683         cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40) | ((cmd->msg_len-3) & 3));
 684
 685         timeout = jiffies + msecs_to_jiffies(100);
 686         while (!time_after(jiffies, timeout) && !(cx24123_readreg(state, 0x29) & 0x40))
 687                 ; // wait for LNB ready
 688
 689         return 0;
 690 }
 691
 692 static int cx24123_diseqc_send_burst(struct dvb_frontend* fe, fe_sec_mini_cmd_t burst)
 693 {
 694         struct cx24123_state *state = fe->demodulator_priv;
 695         int val;
 696         unsigned long timeout;
 697
 698         dprintk("%s:\n", __FUNCTION__);
 699
 700         /* check if continuous tone has been stoped */
 701         if (state->config->use_isl6421)
 702                 val = cx24123_readlnbreg(state, 0x00) & 0x10;
 703         else
 704                 val = cx24123_readreg(state, 0x29) & 0x10;
 705
 706
 707         if (val) {
 708                 printk("%s: ERROR: attempt to send diseqc command before tone is off\n", __FUNCTION__);
 709                 return -ENOTSUPP;
 710         }
 711
 712         /* select tone mode */
 713         val = cx24123_readreg(state, 0x2a) & 0xf8;
 714         cx24123_writereg(state, 0x2a, val | 0x04);
 715
 716         val = cx24123_readreg(state, 0x29);
 717
 718         if (burst == SEC_MINI_A)
 719                 cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x00));
 720         else if (burst == SEC_MINI_B)
 721                 cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x08));
 722         else
 723                 return -EINVAL;
 724
 725
 726         timeout = jiffies + msecs_to_jiffies(100);
 727         while (!time_after(jiffies, timeout) && !(cx24123_readreg(state, 0x29) & 0x40))
 728                 ; // wait for LNB ready
 729
 730         return 0;
 731 }
 732
 733 static int cx24123_read_status(struct dvb_frontend* fe, fe_status_t* status)
 734 {
 735         struct cx24123_state *state = fe->demodulator_priv;
 736
 737         int sync = cx24123_readreg(state, 0x14);
 738         int lock = cx24123_readreg(state, 0x20);
 739
 740         *status = 0;
 741         if (lock & 0x01)
 742                 *status |= FE_HAS_SIGNAL;
 743         if (sync & 0x02)
 744                 *status |= FE_HAS_CARRIER;
 745         if (sync & 0x04)
 746                 *status |= FE_HAS_VITERBI;
 747         if (sync & 0x08)
 748                 *status |= FE_HAS_SYNC;
 749         if (sync & 0x80)
 750                 *status |= FE_HAS_LOCK;
 751
 752         return 0;
 753 }
 754
 755 /*
 756  * Configured to return the measurement of errors in blocks, because no UCBLOCKS value
 757  * is available, so this value doubles up to satisfy both measurements
 758  */
 759 static int cx24123_read_ber(struct dvb_frontend* fe, u32* ber)
 760 {
 761         struct cx24123_state *state = fe->demodulator_priv;
 762
 763         state->lastber =
 764                 ((cx24123_readreg(state, 0x1c) & 0x3f) << 16) |
 765                 (cx24123_readreg(state, 0x1d) << 8 |
 766                 cx24123_readreg(state, 0x1e));
 767
 768         /* Do the signal quality processing here, it's derived from the BER. */
 769         /* Scale the BER from a 24bit to a SNR 16 bit where higher = better */
 770         if (state->lastber < 5000)
 771                 state->snr = 655*100;
 772         else if ( (state->lastber >=   5000) && (state->lastber <  55000) )
 773                 state->snr = 655*90;
 774         else if ( (state->lastber >=  55000) && (state->lastber < 150000) )
 775                 state->snr = 655*80;
 776         else if ( (state->lastber >= 150000) && (state->lastber < 250000) )
 777                 state->snr = 655*70;
 778         else if ( (state->lastber >= 250000) && (state->lastber < 450000) )
 779                 state->snr = 655*65;
 780         else
 781                 state->snr = 0;
 782
 783         *ber = state->lastber;
 784
 785         return 0;
 786 }
 787
 788 static int cx24123_read_signal_strength(struct dvb_frontend* fe, u16* signal_strength)
 789 {
 790         struct cx24123_state *state = fe->demodulator_priv;
 791         *signal_strength = cx24123_readreg(state, 0x3b) << 8; /* larger = better */
 792
 793         return 0;
 794 }
 795
 796 static int cx24123_read_snr(struct dvb_frontend* fe, u16* snr)
 797 {
 798         struct cx24123_state *state = fe->demodulator_priv;
 799         *snr = state->snr;
 800
 801         return 0;
 802 }
 803
 804 static int cx24123_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
 805 {
 806         struct cx24123_state *state = fe->demodulator_priv;
 807         *ucblocks = state->lastber;
 808
 809         return 0;
 810 }
 811
 812 static int cx24123_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
 813 {
 814         struct cx24123_state *state = fe->demodulator_priv;
 815
 816         if (state->config->set_ts_params)
 817                 state->config->set_ts_params(fe, 0);
 818
 819         state->currentfreq=p->frequency;
 820         state->currentsymbolrate = p->u.qpsk.symbol_rate;
 821
 822         cx24123_set_inversion(state, p->inversion);
 823         cx24123_set_fec(state, p->u.qpsk.fec_inner);
 824         cx24123_set_symbolrate(state, p->u.qpsk.symbol_rate);
 825         cx24123_pll_tune(fe, p);
 826
 827         /* Enable automatic aquisition and reset cycle */
 828         cx24123_writereg(state, 0x03, (cx24123_readreg(state, 0x03) | 0x07));
 829         cx24123_writereg(state, 0x00, 0x10);
 830         cx24123_writereg(state, 0x00, 0);
 831
 832         return 0;
 833 }
 834
 835 static int cx24123_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
 836 {
 837         struct cx24123_state *state = fe->demodulator_priv;
 838
 839         if (cx24123_get_inversion(state, &p->inversion) != 0) {
 840                 printk("%s: Failed to get inversion status\n",__FUNCTION__);
 841                 return -EREMOTEIO;
 842         }
 843         if (cx24123_get_fec(state, &p->u.qpsk.fec_inner) != 0) {
 844                 printk("%s: Failed to get fec status\n",__FUNCTION__);
 845                 return -EREMOTEIO;
 846         }
 847         p->frequency = state->currentfreq;
 848         p->u.qpsk.symbol_rate = state->currentsymbolrate;
 849
 850         return 0;
 851 }
 852
 853 static int cx24123_set_tone(struct dvb_frontend* fe, fe_sec_tone_mode_t tone)
 854 {
 855         struct cx24123_state *state = fe->demodulator_priv;
 856         u8 val;
 857
 858         switch (state->config->use_isl6421) {
 859         case 1:
 860
 861                 val = cx24123_readlnbreg(state, 0x0);
 862
 863                 switch (tone) {
 864                 case SEC_TONE_ON:
 865                         return cx24123_writelnbreg(state, 0x0, val | 0x10);
 866                 case SEC_TONE_OFF:
 867                         return cx24123_writelnbreg(state, 0x0, val & 0x2f);
 868                 default:
 869                         printk("%s: CASE reached default with tone=%d\n", __FUNCTION__, tone);
 870                         return -EINVAL;
 871                 }
 872
 873         case 0:
 874
 875                 val = cx24123_readreg(state, 0x29);
 876
 877                 switch (tone) {
 878                 case SEC_TONE_ON:
 879                         dprintk("%s: setting tone on\n", __FUNCTION__);
 880                         return cx24123_writereg(state, 0x29, val | 0x10);
 881                 case SEC_TONE_OFF:
 882                         dprintk("%s: setting tone off\n",__FUNCTION__);
 883                         return cx24123_writereg(state, 0x29, val & 0xef);
 884                 default:
 885                         printk("%s: CASE reached default with tone=%d\n", __FUNCTION__, tone);
 886                         return -EINVAL;
 887                 }
 888         }
 889
 890         return 0;
 891 }
 892
 893 static void cx24123_release(struct dvb_frontend* fe)
 894 {
 895         struct cx24123_state* state = fe->demodulator_priv;
 896         dprintk("%s\n",__FUNCTION__);
 897         kfree(state);
 898 }
 899
 900 static struct dvb_frontend_ops cx24123_ops;
 901
 902 struct dvb_frontend* cx24123_attach(const struct cx24123_config* config,
 903                                     struct i2c_adapter* i2c)
 904 {
 905         struct cx24123_state* state = NULL;
 906         int ret;
 907
 908         dprintk("%s\n",__FUNCTION__);
 909
 910         /* allocate memory for the internal state */
 911         state = kmalloc(sizeof(struct cx24123_state), GFP_KERNEL);
 912         if (state == NULL) {
 913                 printk("Unable to kmalloc\n");
 914                 goto error;
 915         }
 916
 917         /* setup the state */
 918         state->config = config;
 919         state->i2c = i2c;
 920         memcpy(&state->ops, &cx24123_ops, sizeof(struct dvb_frontend_ops));
 921         state->lastber = 0;
 922         state->snr = 0;
 923         state->lnbreg = 0;
 924         state->VCAarg = 0;
 925         state->VGAarg = 0;
 926         state->bandselectarg = 0;
 927         state->pllarg = 0;
 928         state->currentfreq = 0;
 929         state->currentsymbolrate = 0;
 930
 931         /* check if the demod is there */
 932         ret = cx24123_readreg(state, 0x00);
 933         if ((ret != 0xd1) && (ret != 0xe1)) {
 934                 printk("Version != d1 or e1\n");
 935                 goto error;
 936         }
 937
 938         /* create dvb_frontend */
 939         state->frontend.ops = &state->ops;
 940         state->frontend.demodulator_priv = state;
 941         return &state->frontend;
 942
 943 error:
 944         kfree(state);
 945
 946         return NULL;
 947 }
 948
 949 static struct dvb_frontend_ops cx24123_ops = {
 950
 951         .info = {
 952                 .name = "Conexant CX24123/CX24109",
 953                 .type = FE_QPSK,
 954                 .frequency_min = 950000,
 955                 .frequency_max = 2150000,
 956                 .frequency_stepsize = 1011, /* kHz for QPSK frontends */
 957                 .frequency_tolerance = 29500,
 958                 .symbol_rate_min = 1000000,
 959                 .symbol_rate_max = 45000000,
 960                 .caps = FE_CAN_INVERSION_AUTO |
 961                         FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
 962                         FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
 963                         FE_CAN_QPSK | FE_CAN_RECOVER
 964         },
 965
 966         .release = cx24123_release,
 967
 968         .init = cx24123_initfe,
 969         .set_frontend = cx24123_set_frontend,
 970         .get_frontend = cx24123_get_frontend,
 971         .read_status = cx24123_read_status,
 972         .read_ber = cx24123_read_ber,
 973         .read_signal_strength = cx24123_read_signal_strength,
 974         .read_snr = cx24123_read_snr,
 975         .read_ucblocks = cx24123_read_ucblocks,
 976         .diseqc_send_master_cmd = cx24123_send_diseqc_msg,
 977         .diseqc_send_burst = cx24123_diseqc_send_burst,
 978         .set_tone = cx24123_set_tone,
 979         .set_voltage = cx24123_set_voltage,
 980 };
 981
 982 module_param(debug, int, 0644);
 983 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
 984
 985 MODULE_DESCRIPTION("DVB Frontend module for Conexant cx24123/cx24109 hardware");
 986 MODULE_AUTHOR("Steven Toth");
 987 MODULE_LICENSE("GPL");
 988
 989 EXPORT_SYMBOL(cx24123_attach);