2 * Device driver for the PMU on 68K-based Apple PowerBooks
4 * The VIA (versatile interface adapter) interfaces to the PMU,
5 * a 6805 microprocessor core whose primary function is to control
6 * battery charging and system power on the PowerBooks.
7 * The PMU also controls the ADB (Apple Desktop Bus) which connects
8 * to the keyboard and mouse, as well as the non-volatile RAM
9 * and the RTC (real time clock) chip.
11 * Adapted for 68K PMU by Joshua M. Thompson
13 * Based largely on the PowerMac PMU code by Paul Mackerras and
16 * Also based on the PMU driver from MkLinux by Apple Computer, Inc.
17 * and the Open Software Foundation, Inc.
21 #include <linux/types.h>
22 #include <linux/errno.h>
23 #include <linux/kernel.h>
24 #include <linux/delay.h>
25 #include <linux/miscdevice.h>
26 #include <linux/blkdev.h>
27 #include <linux/pci.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
31 #include <linux/adb.h>
32 #include <linux/pmu.h>
33 #include <linux/cuda.h>
35 #include <asm/macintosh.h>
36 #include <asm/macints.h>
37 #include <asm/mac_via.h>
39 #include <asm/pgtable.h>
40 #include <asm/system.h>
42 #include <asm/uaccess.h>
44 /* Misc minor number allocated for /dev/pmu */
47 /* VIA registers - spaced 0x200 bytes apart */
48 #define RS 0x200 /* skip between registers */
49 #define B 0 /* B-side data */
50 #define A RS /* A-side data */
51 #define DIRB (2*RS) /* B-side direction (1=output) */
52 #define DIRA (3*RS) /* A-side direction (1=output) */
53 #define T1CL (4*RS) /* Timer 1 ctr/latch (low 8 bits) */
54 #define T1CH (5*RS) /* Timer 1 counter (high 8 bits) */
55 #define T1LL (6*RS) /* Timer 1 latch (low 8 bits) */
56 #define T1LH (7*RS) /* Timer 1 latch (high 8 bits) */
57 #define T2CL (8*RS) /* Timer 2 ctr/latch (low 8 bits) */
58 #define T2CH (9*RS) /* Timer 2 counter (high 8 bits) */
59 #define SR (10*RS) /* Shift register */
60 #define ACR (11*RS) /* Auxiliary control register */
61 #define PCR (12*RS) /* Peripheral control register */
62 #define IFR (13*RS) /* Interrupt flag register */
63 #define IER (14*RS) /* Interrupt enable register */
64 #define ANH (15*RS) /* A-side data, no handshake */
66 /* Bits in B data register: both active low */
67 #define TACK 0x02 /* Transfer acknowledge (input) */
68 #define TREQ 0x04 /* Transfer request (output) */
71 #define SR_CTRL 0x1c /* Shift register control bits */
72 #define SR_EXT 0x0c /* Shift on external clock */
73 #define SR_OUT 0x10 /* Shift out if 1 */
75 /* Bits in IFR and IER */
76 #define SR_INT 0x04 /* Shift register full/empty */
77 #define CB1_INT 0x10 /* transition on CB1 input */
79 static enum pmu_state {
87 static struct adb_request *current_req;
88 static struct adb_request *last_req;
89 static struct adb_request *req_awaiting_reply;
90 static unsigned char interrupt_data[32];
91 static unsigned char *reply_ptr;
92 static int data_index;
94 static int adb_int_pending;
95 static int pmu_adb_flags;
96 static int adb_dev_map;
97 static struct adb_request bright_req_1, bright_req_2, bright_req_3;
98 static int pmu_kind = PMU_UNKNOWN;
99 static int pmu_fully_inited;
103 static int pmu_probe(void);
104 static int pmu_init(void);
105 static void pmu_start(void);
106 static irqreturn_t pmu_interrupt(int irq, void *arg);
107 static int pmu_send_request(struct adb_request *req, int sync);
108 static int pmu_autopoll(int devs);
110 static int pmu_reset_bus(void);
112 static void pmu_start(void);
113 static void send_byte(int x);
114 static void recv_byte(void);
115 static void pmu_done(struct adb_request *req);
116 static void pmu_handle_data(unsigned char *data, int len);
117 static void set_volume(int level);
118 static void pmu_enable_backlight(int on);
119 static void pmu_set_brightness(int level);
121 struct adb_driver via_pmu_driver = {
132 * This table indicates for each PMU opcode:
133 * - the number of data bytes to be sent with the command, or -1
134 * if a length byte should be sent,
135 * - the number of response bytes which the PMU will return, or
136 * -1 if it will send a length byte.
138 static s8 pmu_data_len[256][2] = {
139 /* 0 1 2 3 4 5 6 7 */
140 /*00*/ {-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
141 /*08*/ {-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},
142 /*10*/ { 1, 0},{ 1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
143 /*18*/ { 0, 1},{ 0, 1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{ 0, 0},
144 /*20*/ {-1, 0},{ 0, 0},{ 2, 0},{ 1, 0},{ 1, 0},{-1, 0},{-1, 0},{-1, 0},
145 /*28*/ { 0,-1},{ 0,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{ 0,-1},
146 /*30*/ { 4, 0},{20, 0},{-1, 0},{ 3, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
147 /*38*/ { 0, 4},{ 0,20},{ 2,-1},{ 2, 1},{ 3,-1},{-1,-1},{-1,-1},{ 4, 0},
148 /*40*/ { 1, 0},{ 1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
149 /*48*/ { 0, 1},{ 0, 1},{-1,-1},{ 1, 0},{ 1, 0},{-1,-1},{-1,-1},{-1,-1},
150 /*50*/ { 1, 0},{ 0, 0},{ 2, 0},{ 2, 0},{-1, 0},{ 1, 0},{ 3, 0},{ 1, 0},
151 /*58*/ { 0, 1},{ 1, 0},{ 0, 2},{ 0, 2},{ 0,-1},{-1,-1},{-1,-1},{-1,-1},
152 /*60*/ { 2, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
153 /*68*/ { 0, 3},{ 0, 3},{ 0, 2},{ 0, 8},{ 0,-1},{ 0,-1},{-1,-1},{-1,-1},
154 /*70*/ { 1, 0},{ 1, 0},{ 1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
155 /*78*/ { 0,-1},{ 0,-1},{-1,-1},{-1,-1},{-1,-1},{ 5, 1},{ 4, 1},{ 4, 1},
156 /*80*/ { 4, 0},{-1, 0},{ 0, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
157 /*88*/ { 0, 5},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},
158 /*90*/ { 1, 0},{ 2, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
159 /*98*/ { 0, 1},{ 0, 1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},
160 /*a0*/ { 2, 0},{ 2, 0},{ 2, 0},{ 4, 0},{-1, 0},{ 0, 0},{-1, 0},{-1, 0},
161 /*a8*/ { 1, 1},{ 1, 0},{ 3, 0},{ 2, 0},{-1,-1},{-1,-1},{-1,-1},{-1,-1},
162 /*b0*/ {-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
163 /*b8*/ {-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},
164 /*c0*/ {-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
165 /*c8*/ {-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},
166 /*d0*/ { 0, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
167 /*d8*/ { 1, 1},{ 1, 1},{-1,-1},{-1,-1},{ 0, 1},{ 0,-1},{-1,-1},{-1,-1},
168 /*e0*/ {-1, 0},{ 4, 0},{ 0, 1},{-1, 0},{-1, 0},{ 4, 0},{-1, 0},{-1, 0},
169 /*e8*/ { 3,-1},{-1,-1},{ 0, 1},{-1,-1},{ 0,-1},{-1,-1},{-1,-1},{ 0, 0},
170 /*f0*/ {-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
171 /*f8*/ {-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},
176 if (macintosh_config->adb_type == MAC_ADB_PB1) {
177 pmu_kind = PMU_68K_V1;
178 } else if (macintosh_config->adb_type == MAC_ADB_PB2) {
179 pmu_kind = PMU_68K_V2;
193 volatile struct adb_request req;
195 via2[B] |= TREQ; /* negate TREQ */
196 via2[DIRB] = (via2[DIRB] | TREQ) & ~TACK; /* TACK in, TREQ out */
198 pmu_request((struct adb_request *) &req, NULL, 2, PMU_SET_INTR_MASK, PMU_INT_ADB);
200 while (!req.complete) {
202 printk(KERN_ERR "pmu_init: no response from PMU\n");
209 /* ack all pending interrupts */
211 interrupt_data[0] = 1;
212 while (interrupt_data[0] || pmu_state != idle) {
214 printk(KERN_ERR "pmu_init: timed out acking intrs\n");
217 if (pmu_state == idle) {
219 pmu_interrupt(0, NULL);
225 pmu_request((struct adb_request *) &req, NULL, 2, PMU_SET_INTR_MASK,
226 PMU_INT_ADB_AUTO|PMU_INT_SNDBRT|PMU_INT_ADB);
228 while (!req.complete) {
230 printk(KERN_ERR "pmu_init: no response from PMU\n");
237 bright_req_1.complete = 1;
238 bright_req_2.complete = 1;
239 bright_req_3.complete = 1;
241 if (request_irq(IRQ_MAC_ADB_SR, pmu_interrupt, 0, "pmu-shift",
243 printk(KERN_ERR "pmu_init: can't get irq %d\n",
247 if (request_irq(IRQ_MAC_ADB_CL, pmu_interrupt, 0, "pmu-clock",
249 printk(KERN_ERR "pmu_init: can't get irq %d\n",
251 free_irq(IRQ_MAC_ADB_SR, pmu_interrupt);
255 pmu_fully_inited = 1;
257 /* Enable backlight */
258 pmu_enable_backlight(1);
260 printk("adb: PMU 68K driver v0.5 for Unified ADB.\n");
271 /* Send an ADB command */
273 pmu_send_request(struct adb_request *req, int sync)
277 if (!pmu_fully_inited)
285 switch (req->data[0]) {
287 for (i = 0; i < req->nbytes - 1; ++i)
288 req->data[i] = req->data[i+1];
290 if (pmu_data_len[req->data[0]][1] != 0) {
291 req->reply[0] = ADB_RET_OK;
295 ret = pmu_queue_request(req);
298 switch (req->data[1]) {
300 if (req->nbytes != 2)
302 req->data[0] = PMU_READ_RTC;
305 req->reply[0] = CUDA_PACKET;
307 req->reply[2] = CUDA_GET_TIME;
308 ret = pmu_queue_request(req);
311 if (req->nbytes != 6)
313 req->data[0] = PMU_SET_RTC;
315 for (i = 1; i <= 4; ++i)
316 req->data[i] = req->data[i+1];
318 req->reply[0] = CUDA_PACKET;
320 req->reply[2] = CUDA_SET_TIME;
321 ret = pmu_queue_request(req);
324 if (req->nbytes != 4)
326 req->data[0] = PMU_READ_NVRAM;
327 req->data[1] = req->data[2];
328 req->data[2] = req->data[3];
331 req->reply[0] = CUDA_PACKET;
333 req->reply[2] = CUDA_GET_PRAM;
334 ret = pmu_queue_request(req);
337 if (req->nbytes != 5)
339 req->data[0] = PMU_WRITE_NVRAM;
340 req->data[1] = req->data[2];
341 req->data[2] = req->data[3];
342 req->data[3] = req->data[4];
345 req->reply[0] = CUDA_PACKET;
347 req->reply[2] = CUDA_SET_PRAM;
348 ret = pmu_queue_request(req);
353 for (i = req->nbytes - 1; i > 1; --i)
354 req->data[i+2] = req->data[i];
355 req->data[3] = req->nbytes - 2;
356 req->data[2] = pmu_adb_flags;
357 /*req->data[1] = req->data[1];*/
358 req->data[0] = PMU_ADB_CMD;
360 req->reply_expected = 1;
362 ret = pmu_queue_request(req);
372 while (!req->complete)
379 /* Enable/disable autopolling */
381 pmu_autopoll(int devs)
383 struct adb_request req;
385 if (!pmu_fully_inited) return -ENXIO;
389 pmu_request(&req, NULL, 5, PMU_ADB_CMD, 0, 0x86,
390 adb_dev_map >> 8, adb_dev_map);
393 pmu_request(&req, NULL, 1, PMU_ADB_POLL_OFF);
396 while (!req.complete)
401 /* Reset the ADB bus */
405 struct adb_request req;
407 int save_autopoll = adb_dev_map;
409 if (!pmu_fully_inited) return -ENXIO;
411 /* anyone got a better idea?? */
416 req.data[0] = PMU_ADB_CMD;
418 req.data[2] = 3; /* ADB_BUSRESET ??? */
422 req.reply_expected = 1;
423 if (pmu_queue_request(&req) != 0)
425 printk(KERN_ERR "pmu_adb_reset_bus: pmu_queue_request failed\n");
428 while (!req.complete)
431 while (!req.complete) {
433 printk(KERN_ERR "pmu_adb_reset_bus (reset): no response from PMU\n");
440 if (save_autopoll != 0)
441 pmu_autopoll(save_autopoll);
446 /* Construct and send a pmu request */
448 pmu_request(struct adb_request *req, void (*done)(struct adb_request *),
454 if (nbytes < 0 || nbytes > 32) {
455 printk(KERN_ERR "pmu_request: bad nbytes (%d)\n", nbytes);
459 req->nbytes = nbytes;
461 va_start(list, nbytes);
462 for (i = 0; i < nbytes; ++i)
463 req->data[i] = va_arg(list, int);
465 if (pmu_data_len[req->data[0]][1] != 0) {
466 req->reply[0] = ADB_RET_OK;
470 req->reply_expected = 0;
471 return pmu_queue_request(req);
475 pmu_queue_request(struct adb_request *req)
480 if (req->nbytes <= 0) {
484 nsend = pmu_data_len[req->data[0]][0];
485 if (nsend >= 0 && req->nbytes != nsend + 1) {
493 local_irq_save(flags);
495 if (current_req != 0) {
496 last_req->next = req;
501 if (pmu_state == idle)
505 local_irq_restore(flags);
512 via1[ACR] |= SR_CTRL;
514 via2[B] &= ~TREQ; /* assert TREQ */
522 via1[ACR] = (via1[ACR] | SR_EXT) & ~SR_OUT;
523 c = via1[SR]; /* resets SR */
531 struct adb_request *req;
533 /* assert pmu_state == idle */
534 /* get the packet to send */
535 local_irq_save(flags);
537 if (req == 0 || pmu_state != idle
538 || (req->reply_expected && req_awaiting_reply))
543 data_len = pmu_data_len[req->data[0]][0];
545 /* set the shift register to shift out and send a byte */
546 send_byte(req->data[0]);
549 local_irq_restore(flags);
557 local_irq_save(flags);
558 if (via1[IFR] & SR_INT) {
560 pmu_interrupt(IRQ_MAC_ADB_SR, NULL);
562 if (via1[IFR] & CB1_INT) {
564 pmu_interrupt(IRQ_MAC_ADB_CL, NULL);
566 local_irq_restore(flags);
570 pmu_interrupt(int irq, void *dev_id)
572 struct adb_request *req;
573 int timeout, bite = 0; /* to prevent compiler warning */
576 printk("pmu_interrupt: irq %d state %d acr %02X, b %02X data_index %d/%d adb_int_pending %d\n",
577 irq, pmu_state, (uint) via1[ACR], (uint) via2[B], data_index, data_len, adb_int_pending);
580 if (irq == IRQ_MAC_ADB_CL) { /* CB1 interrupt */
582 } else if (irq == IRQ_MAC_ADB_SR) { /* SR interrupt */
583 if (via2[B] & TACK) {
584 printk(KERN_DEBUG "PMU: SR_INT but ack still high! (%x)\n", via2[B]);
587 /* if reading grab the byte */
588 if ((via1[ACR] & SR_OUT) == 0) bite = via1[SR];
590 /* reset TREQ and wait for TACK to go high */
593 while (!(via2[B] & TACK)) {
595 printk(KERN_ERR "PMU not responding (!ack)\n");
605 data_len = req->nbytes - 1;
609 if (data_index <= data_len) {
610 send_byte(req->data[data_index++]);
614 data_len = pmu_data_len[req->data[0]][1];
617 current_req = req->next;
618 if (req->reply_expected)
619 req_awaiting_reply = req;
625 reply_ptr = req->reply + req->reply_len;
633 pmu_state = reading_intr;
634 reply_ptr = interrupt_data;
640 if (data_len == -1) {
643 printk(KERN_ERR "PMU: bad reply len %d\n",
646 reply_ptr[data_index++] = bite;
648 if (data_index < data_len) {
653 if (pmu_state == reading_intr) {
654 pmu_handle_data(interrupt_data, data_index);
657 current_req = req->next;
658 req->reply_len += data_index;
666 printk(KERN_ERR "pmu_interrupt: unknown state %d?\n",
671 if (pmu_state == idle) {
672 if (adb_int_pending) {
674 send_byte(PMU_INT_ACK);
676 } else if (current_req) {
682 printk("pmu_interrupt: exit state %d acr %02X, b %02X data_index %d/%d adb_int_pending %d\n",
683 pmu_state, (uint) via1[ACR], (uint) via2[B], data_index, data_len, adb_int_pending);
689 pmu_done(struct adb_request *req)
696 /* Interrupt data could be the result data from an ADB cmd */
698 pmu_handle_data(unsigned char *data, int len)
700 static int show_pmu_ints = 1;
707 if (data[0] & PMU_INT_ADB) {
708 if ((data[0] & PMU_INT_ADB_AUTO) == 0) {
709 struct adb_request *req = req_awaiting_reply;
711 printk(KERN_ERR "PMU: extra ADB reply\n");
714 req_awaiting_reply = NULL;
718 memcpy(req->reply, data + 1, len - 1);
719 req->reply_len = len - 1;
723 adb_input(data+1, len-1, 1);
726 if (data[0] == 0x08 && len == 3) {
727 /* sound/brightness buttons pressed */
728 pmu_set_brightness(data[1] >> 3);
730 } else if (show_pmu_ints
731 && !(data[0] == PMU_INT_TICK && len == 1)) {
733 printk(KERN_DEBUG "pmu intr");
734 for (i = 0; i < len; ++i)
735 printk(" %.2x", data[i]);
741 static int backlight_level = -1;
742 static int backlight_enabled = 0;
744 #define LEVEL_TO_BRIGHT(lev) ((lev) < 1? 0x7f: 0x4a - ((lev) << 1))
747 pmu_enable_backlight(int on)
749 struct adb_request req;
752 /* first call: get current backlight value */
753 if (backlight_level < 0) {
757 pmu_request(&req, NULL, 3, PMU_READ_NVRAM, 0x14, 0xe);
758 while (!req.complete)
760 printk(KERN_DEBUG "pmu: nvram returned bright: %d\n", (int)req.reply[1]);
761 backlight_level = req.reply[1];
764 backlight_enabled = 0;
768 pmu_request(&req, NULL, 2, PMU_BACKLIGHT_BRIGHT,
769 LEVEL_TO_BRIGHT(backlight_level));
770 while (!req.complete)
773 pmu_request(&req, NULL, 2, PMU_POWER_CTRL,
774 PMU_POW_BACKLIGHT | (on ? PMU_POW_ON : PMU_POW_OFF));
775 while (!req.complete)
777 backlight_enabled = on;
781 pmu_set_brightness(int level)
785 backlight_level = level;
786 bright = LEVEL_TO_BRIGHT(level);
787 if (!backlight_enabled)
789 if (bright_req_1.complete)
790 pmu_request(&bright_req_1, NULL, 2, PMU_BACKLIGHT_BRIGHT,
792 if (bright_req_2.complete)
793 pmu_request(&bright_req_2, NULL, 2, PMU_POWER_CTRL,
794 PMU_POW_BACKLIGHT | (bright < 0x7f ? PMU_POW_ON : PMU_POW_OFF));
798 pmu_enable_irled(int on)
800 struct adb_request req;
802 pmu_request(&req, NULL, 2, PMU_POWER_CTRL, PMU_POW_IRLED |
803 (on ? PMU_POW_ON : PMU_POW_OFF));
804 while (!req.complete)
809 set_volume(int level)
816 return (pmu_kind != PMU_UNKNOWN);