2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
20 #include "x86_emulate.h"
23 #include "segment_descriptor.h"
25 #include <linux/module.h>
26 #include <linux/kernel.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
35 MODULE_AUTHOR("Qumranet");
36 MODULE_LICENSE("GPL");
38 static int bypass_guest_pf = 1;
39 module_param(bypass_guest_pf, bool, 0);
51 struct kvm_msr_entry *guest_msrs;
52 struct kvm_msr_entry *host_msrs;
57 int msr_offset_kernel_gs_base;
62 u16 fs_sel, gs_sel, ldt_sel;
63 int gs_ldt_reload_needed;
65 int guest_efer_loaded;
70 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
72 return container_of(vcpu, struct vcpu_vmx, vcpu);
75 static int init_rmode_tss(struct kvm *kvm);
77 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
78 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
80 static struct page *vmx_io_bitmap_a;
81 static struct page *vmx_io_bitmap_b;
83 static struct vmcs_config {
87 u32 pin_based_exec_ctrl;
88 u32 cpu_based_exec_ctrl;
93 #define VMX_SEGMENT_FIELD(seg) \
94 [VCPU_SREG_##seg] = { \
95 .selector = GUEST_##seg##_SELECTOR, \
96 .base = GUEST_##seg##_BASE, \
97 .limit = GUEST_##seg##_LIMIT, \
98 .ar_bytes = GUEST_##seg##_AR_BYTES, \
101 static struct kvm_vmx_segment_field {
106 } kvm_vmx_segment_fields[] = {
107 VMX_SEGMENT_FIELD(CS),
108 VMX_SEGMENT_FIELD(DS),
109 VMX_SEGMENT_FIELD(ES),
110 VMX_SEGMENT_FIELD(FS),
111 VMX_SEGMENT_FIELD(GS),
112 VMX_SEGMENT_FIELD(SS),
113 VMX_SEGMENT_FIELD(TR),
114 VMX_SEGMENT_FIELD(LDTR),
118 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
119 * away by decrementing the array size.
121 static const u32 vmx_msr_index[] = {
123 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
125 MSR_EFER, MSR_K6_STAR,
127 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
129 static void load_msrs(struct kvm_msr_entry *e, int n)
133 for (i = 0; i < n; ++i)
134 wrmsrl(e[i].index, e[i].data);
137 static void save_msrs(struct kvm_msr_entry *e, int n)
141 for (i = 0; i < n; ++i)
142 rdmsrl(e[i].index, e[i].data);
145 static inline int is_page_fault(u32 intr_info)
147 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
148 INTR_INFO_VALID_MASK)) ==
149 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
152 static inline int is_no_device(u32 intr_info)
154 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
155 INTR_INFO_VALID_MASK)) ==
156 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
159 static inline int is_invalid_opcode(u32 intr_info)
161 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
162 INTR_INFO_VALID_MASK)) ==
163 (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
166 static inline int is_external_interrupt(u32 intr_info)
168 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
169 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
172 static inline int cpu_has_vmx_tpr_shadow(void)
174 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
177 static inline int vm_need_tpr_shadow(struct kvm *kvm)
179 return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
182 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
186 for (i = 0; i < vmx->nmsrs; ++i)
187 if (vmx->guest_msrs[i].index == msr)
192 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
196 i = __find_msr_index(vmx, msr);
198 return &vmx->guest_msrs[i];
202 static void vmcs_clear(struct vmcs *vmcs)
204 u64 phys_addr = __pa(vmcs);
207 asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
208 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
211 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
215 static void __vcpu_clear(void *arg)
217 struct vcpu_vmx *vmx = arg;
218 int cpu = raw_smp_processor_id();
220 if (vmx->vcpu.cpu == cpu)
221 vmcs_clear(vmx->vmcs);
222 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
223 per_cpu(current_vmcs, cpu) = NULL;
224 rdtscll(vmx->vcpu.host_tsc);
227 static void vcpu_clear(struct vcpu_vmx *vmx)
229 if (vmx->vcpu.cpu == -1)
231 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 0, 1);
235 static unsigned long vmcs_readl(unsigned long field)
239 asm volatile (ASM_VMX_VMREAD_RDX_RAX
240 : "=a"(value) : "d"(field) : "cc");
244 static u16 vmcs_read16(unsigned long field)
246 return vmcs_readl(field);
249 static u32 vmcs_read32(unsigned long field)
251 return vmcs_readl(field);
254 static u64 vmcs_read64(unsigned long field)
257 return vmcs_readl(field);
259 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
263 static noinline void vmwrite_error(unsigned long field, unsigned long value)
265 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
266 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
270 static void vmcs_writel(unsigned long field, unsigned long value)
274 asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
275 : "=q"(error) : "a"(value), "d"(field) : "cc");
277 vmwrite_error(field, value);
280 static void vmcs_write16(unsigned long field, u16 value)
282 vmcs_writel(field, value);
285 static void vmcs_write32(unsigned long field, u32 value)
287 vmcs_writel(field, value);
290 static void vmcs_write64(unsigned long field, u64 value)
293 vmcs_writel(field, value);
295 vmcs_writel(field, value);
297 vmcs_writel(field+1, value >> 32);
301 static void vmcs_clear_bits(unsigned long field, u32 mask)
303 vmcs_writel(field, vmcs_readl(field) & ~mask);
306 static void vmcs_set_bits(unsigned long field, u32 mask)
308 vmcs_writel(field, vmcs_readl(field) | mask);
311 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
315 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
316 if (!vcpu->fpu_active)
317 eb |= 1u << NM_VECTOR;
318 if (vcpu->guest_debug.enabled)
320 if (vcpu->rmode.active)
322 vmcs_write32(EXCEPTION_BITMAP, eb);
325 static void reload_tss(void)
327 #ifndef CONFIG_X86_64
330 * VT restores TR but not its size. Useless.
332 struct descriptor_table gdt;
333 struct segment_descriptor *descs;
336 descs = (void *)gdt.base;
337 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
342 static void load_transition_efer(struct vcpu_vmx *vmx)
344 int efer_offset = vmx->msr_offset_efer;
345 u64 host_efer = vmx->host_msrs[efer_offset].data;
346 u64 guest_efer = vmx->guest_msrs[efer_offset].data;
352 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
355 ignore_bits = EFER_NX | EFER_SCE;
357 ignore_bits |= EFER_LMA | EFER_LME;
358 /* SCE is meaningful only in long mode on Intel */
359 if (guest_efer & EFER_LMA)
360 ignore_bits &= ~(u64)EFER_SCE;
362 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
365 vmx->host_state.guest_efer_loaded = 1;
366 guest_efer &= ~ignore_bits;
367 guest_efer |= host_efer & ignore_bits;
368 wrmsrl(MSR_EFER, guest_efer);
369 vmx->vcpu.stat.efer_reload++;
372 static void reload_host_efer(struct vcpu_vmx *vmx)
374 if (vmx->host_state.guest_efer_loaded) {
375 vmx->host_state.guest_efer_loaded = 0;
376 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
380 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
382 struct vcpu_vmx *vmx = to_vmx(vcpu);
384 if (vmx->host_state.loaded)
387 vmx->host_state.loaded = 1;
389 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
390 * allow segment selectors with cpl > 0 or ti == 1.
392 vmx->host_state.ldt_sel = read_ldt();
393 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
394 vmx->host_state.fs_sel = read_fs();
395 if (!(vmx->host_state.fs_sel & 7)) {
396 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
397 vmx->host_state.fs_reload_needed = 0;
399 vmcs_write16(HOST_FS_SELECTOR, 0);
400 vmx->host_state.fs_reload_needed = 1;
402 vmx->host_state.gs_sel = read_gs();
403 if (!(vmx->host_state.gs_sel & 7))
404 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
406 vmcs_write16(HOST_GS_SELECTOR, 0);
407 vmx->host_state.gs_ldt_reload_needed = 1;
411 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
412 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
414 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
415 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
419 if (is_long_mode(&vmx->vcpu))
420 save_msrs(vmx->host_msrs +
421 vmx->msr_offset_kernel_gs_base, 1);
424 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
425 load_transition_efer(vmx);
428 static void vmx_load_host_state(struct vcpu_vmx *vmx)
432 if (!vmx->host_state.loaded)
435 vmx->host_state.loaded = 0;
436 if (vmx->host_state.fs_reload_needed)
437 load_fs(vmx->host_state.fs_sel);
438 if (vmx->host_state.gs_ldt_reload_needed) {
439 load_ldt(vmx->host_state.ldt_sel);
441 * If we have to reload gs, we must take care to
442 * preserve our gs base.
444 local_irq_save(flags);
445 load_gs(vmx->host_state.gs_sel);
447 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
449 local_irq_restore(flags);
452 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
453 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
454 reload_host_efer(vmx);
458 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
459 * vcpu mutex is already taken.
461 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
463 struct vcpu_vmx *vmx = to_vmx(vcpu);
464 u64 phys_addr = __pa(vmx->vmcs);
467 if (vcpu->cpu != cpu) {
469 kvm_migrate_apic_timer(vcpu);
472 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
475 per_cpu(current_vmcs, cpu) = vmx->vmcs;
476 asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
477 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
480 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
481 vmx->vmcs, phys_addr);
484 if (vcpu->cpu != cpu) {
485 struct descriptor_table dt;
486 unsigned long sysenter_esp;
490 * Linux uses per-cpu TSS and GDT, so set these when switching
493 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
495 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
497 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
498 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
501 * Make sure the time stamp counter is monotonous.
504 delta = vcpu->host_tsc - tsc_this;
505 vmcs_write64(TSC_OFFSET, vmcs_read64(TSC_OFFSET) + delta);
509 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
511 vmx_load_host_state(to_vmx(vcpu));
512 kvm_put_guest_fpu(vcpu);
515 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
517 if (vcpu->fpu_active)
519 vcpu->fpu_active = 1;
520 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
521 if (vcpu->cr0 & X86_CR0_TS)
522 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
523 update_exception_bitmap(vcpu);
526 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
528 if (!vcpu->fpu_active)
530 vcpu->fpu_active = 0;
531 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
532 update_exception_bitmap(vcpu);
535 static void vmx_vcpu_decache(struct kvm_vcpu *vcpu)
537 vcpu_clear(to_vmx(vcpu));
540 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
542 return vmcs_readl(GUEST_RFLAGS);
545 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
547 if (vcpu->rmode.active)
548 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
549 vmcs_writel(GUEST_RFLAGS, rflags);
552 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
555 u32 interruptibility;
557 rip = vmcs_readl(GUEST_RIP);
558 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
559 vmcs_writel(GUEST_RIP, rip);
562 * We emulated an instruction, so temporary interrupt blocking
563 * should be removed, if set.
565 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
566 if (interruptibility & 3)
567 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
568 interruptibility & ~3);
569 vcpu->interrupt_window_open = 1;
572 static void vmx_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
574 printk(KERN_DEBUG "inject_general_protection: rip 0x%lx\n",
575 vmcs_readl(GUEST_RIP));
576 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
577 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
579 INTR_TYPE_EXCEPTION |
580 INTR_INFO_DELIEVER_CODE_MASK |
581 INTR_INFO_VALID_MASK);
584 static void vmx_inject_ud(struct kvm_vcpu *vcpu)
586 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
588 INTR_TYPE_EXCEPTION |
589 INTR_INFO_VALID_MASK);
593 * Swap MSR entry in host/guest MSR entry array.
596 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
598 struct kvm_msr_entry tmp;
600 tmp = vmx->guest_msrs[to];
601 vmx->guest_msrs[to] = vmx->guest_msrs[from];
602 vmx->guest_msrs[from] = tmp;
603 tmp = vmx->host_msrs[to];
604 vmx->host_msrs[to] = vmx->host_msrs[from];
605 vmx->host_msrs[from] = tmp;
610 * Set up the vmcs to automatically save and restore system
611 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
612 * mode, as fiddling with msrs is very expensive.
614 static void setup_msrs(struct vcpu_vmx *vmx)
620 if (is_long_mode(&vmx->vcpu)) {
623 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
625 move_msr_up(vmx, index, save_nmsrs++);
626 index = __find_msr_index(vmx, MSR_LSTAR);
628 move_msr_up(vmx, index, save_nmsrs++);
629 index = __find_msr_index(vmx, MSR_CSTAR);
631 move_msr_up(vmx, index, save_nmsrs++);
632 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
634 move_msr_up(vmx, index, save_nmsrs++);
636 * MSR_K6_STAR is only needed on long mode guests, and only
637 * if efer.sce is enabled.
639 index = __find_msr_index(vmx, MSR_K6_STAR);
640 if ((index >= 0) && (vmx->vcpu.shadow_efer & EFER_SCE))
641 move_msr_up(vmx, index, save_nmsrs++);
644 vmx->save_nmsrs = save_nmsrs;
647 vmx->msr_offset_kernel_gs_base =
648 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
650 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
654 * reads and returns guest's timestamp counter "register"
655 * guest_tsc = host_tsc + tsc_offset -- 21.3
657 static u64 guest_read_tsc(void)
659 u64 host_tsc, tsc_offset;
662 tsc_offset = vmcs_read64(TSC_OFFSET);
663 return host_tsc + tsc_offset;
667 * writes 'guest_tsc' into guest's timestamp counter "register"
668 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
670 static void guest_write_tsc(u64 guest_tsc)
675 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
679 * Reads an msr value (of 'msr_index') into 'pdata'.
680 * Returns 0 on success, non-0 otherwise.
681 * Assumes vcpu_load() was already called.
683 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
686 struct kvm_msr_entry *msr;
689 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
696 data = vmcs_readl(GUEST_FS_BASE);
699 data = vmcs_readl(GUEST_GS_BASE);
702 return kvm_get_msr_common(vcpu, msr_index, pdata);
704 case MSR_IA32_TIME_STAMP_COUNTER:
705 data = guest_read_tsc();
707 case MSR_IA32_SYSENTER_CS:
708 data = vmcs_read32(GUEST_SYSENTER_CS);
710 case MSR_IA32_SYSENTER_EIP:
711 data = vmcs_readl(GUEST_SYSENTER_EIP);
713 case MSR_IA32_SYSENTER_ESP:
714 data = vmcs_readl(GUEST_SYSENTER_ESP);
717 msr = find_msr_entry(to_vmx(vcpu), msr_index);
722 return kvm_get_msr_common(vcpu, msr_index, pdata);
730 * Writes msr value into into the appropriate "register".
731 * Returns 0 on success, non-0 otherwise.
732 * Assumes vcpu_load() was already called.
734 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
736 struct vcpu_vmx *vmx = to_vmx(vcpu);
737 struct kvm_msr_entry *msr;
743 ret = kvm_set_msr_common(vcpu, msr_index, data);
744 if (vmx->host_state.loaded) {
745 reload_host_efer(vmx);
746 load_transition_efer(vmx);
750 vmcs_writel(GUEST_FS_BASE, data);
753 vmcs_writel(GUEST_GS_BASE, data);
756 case MSR_IA32_SYSENTER_CS:
757 vmcs_write32(GUEST_SYSENTER_CS, data);
759 case MSR_IA32_SYSENTER_EIP:
760 vmcs_writel(GUEST_SYSENTER_EIP, data);
762 case MSR_IA32_SYSENTER_ESP:
763 vmcs_writel(GUEST_SYSENTER_ESP, data);
765 case MSR_IA32_TIME_STAMP_COUNTER:
766 guest_write_tsc(data);
769 msr = find_msr_entry(vmx, msr_index);
772 if (vmx->host_state.loaded)
773 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
776 ret = kvm_set_msr_common(vcpu, msr_index, data);
783 * Sync the rsp and rip registers into the vcpu structure. This allows
784 * registers to be accessed by indexing vcpu->regs.
786 static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
788 vcpu->regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
789 vcpu->rip = vmcs_readl(GUEST_RIP);
793 * Syncs rsp and rip back into the vmcs. Should be called after possible
796 static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
798 vmcs_writel(GUEST_RSP, vcpu->regs[VCPU_REGS_RSP]);
799 vmcs_writel(GUEST_RIP, vcpu->rip);
802 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
804 unsigned long dr7 = 0x400;
807 old_singlestep = vcpu->guest_debug.singlestep;
809 vcpu->guest_debug.enabled = dbg->enabled;
810 if (vcpu->guest_debug.enabled) {
813 dr7 |= 0x200; /* exact */
814 for (i = 0; i < 4; ++i) {
815 if (!dbg->breakpoints[i].enabled)
817 vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
818 dr7 |= 2 << (i*2); /* global enable */
819 dr7 |= 0 << (i*4+16); /* execution breakpoint */
822 vcpu->guest_debug.singlestep = dbg->singlestep;
824 vcpu->guest_debug.singlestep = 0;
826 if (old_singlestep && !vcpu->guest_debug.singlestep) {
829 flags = vmcs_readl(GUEST_RFLAGS);
830 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
831 vmcs_writel(GUEST_RFLAGS, flags);
834 update_exception_bitmap(vcpu);
835 vmcs_writel(GUEST_DR7, dr7);
840 static int vmx_get_irq(struct kvm_vcpu *vcpu)
844 idtv_info_field = vmcs_read32(IDT_VECTORING_INFO_FIELD);
845 if (idtv_info_field & INTR_INFO_VALID_MASK) {
846 if (is_external_interrupt(idtv_info_field))
847 return idtv_info_field & VECTORING_INFO_VECTOR_MASK;
849 printk(KERN_DEBUG "pending exception: not handled yet\n");
854 static __init int cpu_has_kvm_support(void)
856 unsigned long ecx = cpuid_ecx(1);
857 return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
860 static __init int vmx_disabled_by_bios(void)
864 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
865 return (msr & (MSR_IA32_FEATURE_CONTROL_LOCKED |
866 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
867 == MSR_IA32_FEATURE_CONTROL_LOCKED;
868 /* locked but not enabled */
871 static void hardware_enable(void *garbage)
873 int cpu = raw_smp_processor_id();
874 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
877 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
878 if ((old & (MSR_IA32_FEATURE_CONTROL_LOCKED |
879 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
880 != (MSR_IA32_FEATURE_CONTROL_LOCKED |
881 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
882 /* enable and lock */
883 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
884 MSR_IA32_FEATURE_CONTROL_LOCKED |
885 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED);
886 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
887 asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr)
891 static void hardware_disable(void *garbage)
893 asm volatile (ASM_VMX_VMXOFF : : : "cc");
896 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
897 u32 msr, u32 *result)
899 u32 vmx_msr_low, vmx_msr_high;
900 u32 ctl = ctl_min | ctl_opt;
902 rdmsr(msr, vmx_msr_low, vmx_msr_high);
904 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
905 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
907 /* Ensure minimum (required) set of control bits are supported. */
915 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
917 u32 vmx_msr_low, vmx_msr_high;
919 u32 _pin_based_exec_control = 0;
920 u32 _cpu_based_exec_control = 0;
921 u32 _vmexit_control = 0;
922 u32 _vmentry_control = 0;
924 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
926 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
927 &_pin_based_exec_control) < 0)
930 min = CPU_BASED_HLT_EXITING |
932 CPU_BASED_CR8_LOAD_EXITING |
933 CPU_BASED_CR8_STORE_EXITING |
935 CPU_BASED_USE_IO_BITMAPS |
936 CPU_BASED_MOV_DR_EXITING |
937 CPU_BASED_USE_TSC_OFFSETING;
939 opt = CPU_BASED_TPR_SHADOW;
943 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
944 &_cpu_based_exec_control) < 0)
947 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
948 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
949 ~CPU_BASED_CR8_STORE_EXITING;
954 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
957 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
958 &_vmexit_control) < 0)
962 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
963 &_vmentry_control) < 0)
966 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
968 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
969 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
973 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
974 if (vmx_msr_high & (1u<<16))
978 /* Require Write-Back (WB) memory type for VMCS accesses. */
979 if (((vmx_msr_high >> 18) & 15) != 6)
982 vmcs_conf->size = vmx_msr_high & 0x1fff;
983 vmcs_conf->order = get_order(vmcs_config.size);
984 vmcs_conf->revision_id = vmx_msr_low;
986 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
987 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
988 vmcs_conf->vmexit_ctrl = _vmexit_control;
989 vmcs_conf->vmentry_ctrl = _vmentry_control;
994 static struct vmcs *alloc_vmcs_cpu(int cpu)
996 int node = cpu_to_node(cpu);
1000 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
1003 vmcs = page_address(pages);
1004 memset(vmcs, 0, vmcs_config.size);
1005 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1009 static struct vmcs *alloc_vmcs(void)
1011 return alloc_vmcs_cpu(raw_smp_processor_id());
1014 static void free_vmcs(struct vmcs *vmcs)
1016 free_pages((unsigned long)vmcs, vmcs_config.order);
1019 static void free_kvm_area(void)
1023 for_each_online_cpu(cpu)
1024 free_vmcs(per_cpu(vmxarea, cpu));
1027 static __init int alloc_kvm_area(void)
1031 for_each_online_cpu(cpu) {
1034 vmcs = alloc_vmcs_cpu(cpu);
1040 per_cpu(vmxarea, cpu) = vmcs;
1045 static __init int hardware_setup(void)
1047 if (setup_vmcs_config(&vmcs_config) < 0)
1049 return alloc_kvm_area();
1052 static __exit void hardware_unsetup(void)
1057 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1059 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1061 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1062 vmcs_write16(sf->selector, save->selector);
1063 vmcs_writel(sf->base, save->base);
1064 vmcs_write32(sf->limit, save->limit);
1065 vmcs_write32(sf->ar_bytes, save->ar);
1067 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1069 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1073 static void enter_pmode(struct kvm_vcpu *vcpu)
1075 unsigned long flags;
1077 vcpu->rmode.active = 0;
1079 vmcs_writel(GUEST_TR_BASE, vcpu->rmode.tr.base);
1080 vmcs_write32(GUEST_TR_LIMIT, vcpu->rmode.tr.limit);
1081 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->rmode.tr.ar);
1083 flags = vmcs_readl(GUEST_RFLAGS);
1084 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1085 flags |= (vcpu->rmode.save_iopl << IOPL_SHIFT);
1086 vmcs_writel(GUEST_RFLAGS, flags);
1088 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1089 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1091 update_exception_bitmap(vcpu);
1093 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->rmode.es);
1094 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->rmode.ds);
1095 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->rmode.gs);
1096 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->rmode.fs);
1098 vmcs_write16(GUEST_SS_SELECTOR, 0);
1099 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1101 vmcs_write16(GUEST_CS_SELECTOR,
1102 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1103 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1106 static gva_t rmode_tss_base(struct kvm *kvm)
1108 gfn_t base_gfn = kvm->memslots[0].base_gfn + kvm->memslots[0].npages - 3;
1109 return base_gfn << PAGE_SHIFT;
1112 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1114 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1116 save->selector = vmcs_read16(sf->selector);
1117 save->base = vmcs_readl(sf->base);
1118 save->limit = vmcs_read32(sf->limit);
1119 save->ar = vmcs_read32(sf->ar_bytes);
1120 vmcs_write16(sf->selector, vmcs_readl(sf->base) >> 4);
1121 vmcs_write32(sf->limit, 0xffff);
1122 vmcs_write32(sf->ar_bytes, 0xf3);
1125 static void enter_rmode(struct kvm_vcpu *vcpu)
1127 unsigned long flags;
1129 vcpu->rmode.active = 1;
1131 vcpu->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1132 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1134 vcpu->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1135 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1137 vcpu->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1138 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1140 flags = vmcs_readl(GUEST_RFLAGS);
1141 vcpu->rmode.save_iopl = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1143 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1145 vmcs_writel(GUEST_RFLAGS, flags);
1146 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1147 update_exception_bitmap(vcpu);
1149 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1150 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1151 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1153 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1154 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1155 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1156 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1157 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1159 fix_rmode_seg(VCPU_SREG_ES, &vcpu->rmode.es);
1160 fix_rmode_seg(VCPU_SREG_DS, &vcpu->rmode.ds);
1161 fix_rmode_seg(VCPU_SREG_GS, &vcpu->rmode.gs);
1162 fix_rmode_seg(VCPU_SREG_FS, &vcpu->rmode.fs);
1164 kvm_mmu_reset_context(vcpu);
1165 init_rmode_tss(vcpu->kvm);
1168 #ifdef CONFIG_X86_64
1170 static void enter_lmode(struct kvm_vcpu *vcpu)
1174 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1175 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1176 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1178 vmcs_write32(GUEST_TR_AR_BYTES,
1179 (guest_tr_ar & ~AR_TYPE_MASK)
1180 | AR_TYPE_BUSY_64_TSS);
1183 vcpu->shadow_efer |= EFER_LMA;
1185 find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
1186 vmcs_write32(VM_ENTRY_CONTROLS,
1187 vmcs_read32(VM_ENTRY_CONTROLS)
1188 | VM_ENTRY_IA32E_MODE);
1191 static void exit_lmode(struct kvm_vcpu *vcpu)
1193 vcpu->shadow_efer &= ~EFER_LMA;
1195 vmcs_write32(VM_ENTRY_CONTROLS,
1196 vmcs_read32(VM_ENTRY_CONTROLS)
1197 & ~VM_ENTRY_IA32E_MODE);
1202 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1204 vcpu->cr4 &= KVM_GUEST_CR4_MASK;
1205 vcpu->cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1208 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1210 vmx_fpu_deactivate(vcpu);
1212 if (vcpu->rmode.active && (cr0 & X86_CR0_PE))
1215 if (!vcpu->rmode.active && !(cr0 & X86_CR0_PE))
1218 #ifdef CONFIG_X86_64
1219 if (vcpu->shadow_efer & EFER_LME) {
1220 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1222 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1227 vmcs_writel(CR0_READ_SHADOW, cr0);
1228 vmcs_writel(GUEST_CR0,
1229 (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
1232 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1233 vmx_fpu_activate(vcpu);
1236 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1238 vmcs_writel(GUEST_CR3, cr3);
1239 if (vcpu->cr0 & X86_CR0_PE)
1240 vmx_fpu_deactivate(vcpu);
1243 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1245 vmcs_writel(CR4_READ_SHADOW, cr4);
1246 vmcs_writel(GUEST_CR4, cr4 | (vcpu->rmode.active ?
1247 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON));
1251 #ifdef CONFIG_X86_64
1253 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1255 struct vcpu_vmx *vmx = to_vmx(vcpu);
1256 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1258 vcpu->shadow_efer = efer;
1259 if (efer & EFER_LMA) {
1260 vmcs_write32(VM_ENTRY_CONTROLS,
1261 vmcs_read32(VM_ENTRY_CONTROLS) |
1262 VM_ENTRY_IA32E_MODE);
1266 vmcs_write32(VM_ENTRY_CONTROLS,
1267 vmcs_read32(VM_ENTRY_CONTROLS) &
1268 ~VM_ENTRY_IA32E_MODE);
1270 msr->data = efer & ~EFER_LME;
1277 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1279 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1281 return vmcs_readl(sf->base);
1284 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1285 struct kvm_segment *var, int seg)
1287 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1290 var->base = vmcs_readl(sf->base);
1291 var->limit = vmcs_read32(sf->limit);
1292 var->selector = vmcs_read16(sf->selector);
1293 ar = vmcs_read32(sf->ar_bytes);
1294 if (ar & AR_UNUSABLE_MASK)
1296 var->type = ar & 15;
1297 var->s = (ar >> 4) & 1;
1298 var->dpl = (ar >> 5) & 3;
1299 var->present = (ar >> 7) & 1;
1300 var->avl = (ar >> 12) & 1;
1301 var->l = (ar >> 13) & 1;
1302 var->db = (ar >> 14) & 1;
1303 var->g = (ar >> 15) & 1;
1304 var->unusable = (ar >> 16) & 1;
1307 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1314 ar = var->type & 15;
1315 ar |= (var->s & 1) << 4;
1316 ar |= (var->dpl & 3) << 5;
1317 ar |= (var->present & 1) << 7;
1318 ar |= (var->avl & 1) << 12;
1319 ar |= (var->l & 1) << 13;
1320 ar |= (var->db & 1) << 14;
1321 ar |= (var->g & 1) << 15;
1323 if (ar == 0) /* a 0 value means unusable */
1324 ar = AR_UNUSABLE_MASK;
1329 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1330 struct kvm_segment *var, int seg)
1332 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1335 if (vcpu->rmode.active && seg == VCPU_SREG_TR) {
1336 vcpu->rmode.tr.selector = var->selector;
1337 vcpu->rmode.tr.base = var->base;
1338 vcpu->rmode.tr.limit = var->limit;
1339 vcpu->rmode.tr.ar = vmx_segment_access_rights(var);
1342 vmcs_writel(sf->base, var->base);
1343 vmcs_write32(sf->limit, var->limit);
1344 vmcs_write16(sf->selector, var->selector);
1345 if (vcpu->rmode.active && var->s) {
1347 * Hack real-mode segments into vm86 compatibility.
1349 if (var->base == 0xffff0000 && var->selector == 0xf000)
1350 vmcs_writel(sf->base, 0xf0000);
1353 ar = vmx_segment_access_rights(var);
1354 vmcs_write32(sf->ar_bytes, ar);
1357 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1359 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1361 *db = (ar >> 14) & 1;
1362 *l = (ar >> 13) & 1;
1365 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1367 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1368 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1371 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1373 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1374 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1377 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1379 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1380 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1383 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1385 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1386 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1389 static int init_rmode_tss(struct kvm *kvm)
1391 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1395 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1398 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1399 r = kvm_write_guest_page(kvm, fn++, &data, 0x66, sizeof(u16));
1402 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1405 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1409 r = kvm_write_guest_page(kvm, fn, &data, RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1416 static void seg_setup(int seg)
1418 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1420 vmcs_write16(sf->selector, 0);
1421 vmcs_writel(sf->base, 0);
1422 vmcs_write32(sf->limit, 0xffff);
1423 vmcs_write32(sf->ar_bytes, 0x93);
1427 * Sets up the vmcs for emulated real mode.
1429 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
1431 u32 host_sysenter_cs;
1434 struct descriptor_table dt;
1436 unsigned long kvm_vmx_return;
1440 vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
1441 vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
1443 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1446 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
1447 vmcs_config.pin_based_exec_ctrl);
1449 exec_control = vmcs_config.cpu_based_exec_ctrl;
1450 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
1451 exec_control &= ~CPU_BASED_TPR_SHADOW;
1452 #ifdef CONFIG_X86_64
1453 exec_control |= CPU_BASED_CR8_STORE_EXITING |
1454 CPU_BASED_CR8_LOAD_EXITING;
1457 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
1459 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
1460 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
1461 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
1463 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
1464 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
1465 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
1467 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
1468 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1469 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1470 vmcs_write16(HOST_FS_SELECTOR, read_fs()); /* 22.2.4 */
1471 vmcs_write16(HOST_GS_SELECTOR, read_gs()); /* 22.2.4 */
1472 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1473 #ifdef CONFIG_X86_64
1474 rdmsrl(MSR_FS_BASE, a);
1475 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1476 rdmsrl(MSR_GS_BASE, a);
1477 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1479 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1480 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1483 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
1486 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
1488 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
1489 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
1490 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
1491 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
1492 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
1494 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1495 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1496 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1497 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
1498 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1499 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
1501 for (i = 0; i < NR_VMX_MSR; ++i) {
1502 u32 index = vmx_msr_index[i];
1503 u32 data_low, data_high;
1507 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1509 if (wrmsr_safe(index, data_low, data_high) < 0)
1511 data = data_low | ((u64)data_high << 32);
1512 vmx->host_msrs[j].index = index;
1513 vmx->host_msrs[j].reserved = 0;
1514 vmx->host_msrs[j].data = data;
1515 vmx->guest_msrs[j] = vmx->host_msrs[j];
1519 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
1521 /* 22.2.1, 20.8.1 */
1522 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
1524 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
1525 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1530 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
1532 struct vcpu_vmx *vmx = to_vmx(vcpu);
1536 if (!init_rmode_tss(vmx->vcpu.kvm)) {
1541 vmx->vcpu.rmode.active = 0;
1543 vmx->vcpu.regs[VCPU_REGS_RDX] = get_rdx_init_val();
1544 set_cr8(&vmx->vcpu, 0);
1545 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1546 if (vmx->vcpu.vcpu_id == 0)
1547 msr |= MSR_IA32_APICBASE_BSP;
1548 kvm_set_apic_base(&vmx->vcpu, msr);
1550 fx_init(&vmx->vcpu);
1553 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
1554 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
1556 if (vmx->vcpu.vcpu_id == 0) {
1557 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
1558 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
1560 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.sipi_vector << 8);
1561 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.sipi_vector << 12);
1563 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1564 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1566 seg_setup(VCPU_SREG_DS);
1567 seg_setup(VCPU_SREG_ES);
1568 seg_setup(VCPU_SREG_FS);
1569 seg_setup(VCPU_SREG_GS);
1570 seg_setup(VCPU_SREG_SS);
1572 vmcs_write16(GUEST_TR_SELECTOR, 0);
1573 vmcs_writel(GUEST_TR_BASE, 0);
1574 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
1575 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1577 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
1578 vmcs_writel(GUEST_LDTR_BASE, 0);
1579 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
1580 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
1582 vmcs_write32(GUEST_SYSENTER_CS, 0);
1583 vmcs_writel(GUEST_SYSENTER_ESP, 0);
1584 vmcs_writel(GUEST_SYSENTER_EIP, 0);
1586 vmcs_writel(GUEST_RFLAGS, 0x02);
1587 if (vmx->vcpu.vcpu_id == 0)
1588 vmcs_writel(GUEST_RIP, 0xfff0);
1590 vmcs_writel(GUEST_RIP, 0);
1591 vmcs_writel(GUEST_RSP, 0);
1593 /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */
1594 vmcs_writel(GUEST_DR7, 0x400);
1596 vmcs_writel(GUEST_GDTR_BASE, 0);
1597 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
1599 vmcs_writel(GUEST_IDTR_BASE, 0);
1600 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
1602 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
1603 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
1604 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
1608 /* Special registers */
1609 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
1613 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
1615 #ifdef CONFIG_X86_64
1616 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
1617 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
1618 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
1619 page_to_phys(vmx->vcpu.apic->regs_page));
1620 vmcs_write32(TPR_THRESHOLD, 0);
1623 vmx->vcpu.cr0 = 0x60000010;
1624 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.cr0); /* enter rmode */
1625 vmx_set_cr4(&vmx->vcpu, 0);
1626 #ifdef CONFIG_X86_64
1627 vmx_set_efer(&vmx->vcpu, 0);
1629 vmx_fpu_activate(&vmx->vcpu);
1630 update_exception_bitmap(&vmx->vcpu);
1638 static void inject_rmode_irq(struct kvm_vcpu *vcpu, int irq)
1643 unsigned long flags;
1644 unsigned long ss_base = vmcs_readl(GUEST_SS_BASE);
1645 u16 sp = vmcs_readl(GUEST_RSP);
1646 u32 ss_limit = vmcs_read32(GUEST_SS_LIMIT);
1648 if (sp > ss_limit || sp < 6) {
1649 vcpu_printf(vcpu, "%s: #SS, rsp 0x%lx ss 0x%lx limit 0x%x\n",
1651 vmcs_readl(GUEST_RSP),
1652 vmcs_readl(GUEST_SS_BASE),
1653 vmcs_read32(GUEST_SS_LIMIT));
1657 if (emulator_read_std(irq * sizeof(ent), &ent, sizeof(ent), vcpu) !=
1659 vcpu_printf(vcpu, "%s: read guest err\n", __FUNCTION__);
1663 flags = vmcs_readl(GUEST_RFLAGS);
1664 cs = vmcs_readl(GUEST_CS_BASE) >> 4;
1665 ip = vmcs_readl(GUEST_RIP);
1668 if (emulator_write_emulated(
1669 ss_base + sp - 2, &flags, 2, vcpu) != X86EMUL_CONTINUE ||
1670 emulator_write_emulated(
1671 ss_base + sp - 4, &cs, 2, vcpu) != X86EMUL_CONTINUE ||
1672 emulator_write_emulated(
1673 ss_base + sp - 6, &ip, 2, vcpu) != X86EMUL_CONTINUE) {
1674 vcpu_printf(vcpu, "%s: write guest err\n", __FUNCTION__);
1678 vmcs_writel(GUEST_RFLAGS, flags &
1679 ~(X86_EFLAGS_IF | X86_EFLAGS_AC | X86_EFLAGS_TF));
1680 vmcs_write16(GUEST_CS_SELECTOR, ent[1]) ;
1681 vmcs_writel(GUEST_CS_BASE, ent[1] << 4);
1682 vmcs_writel(GUEST_RIP, ent[0]);
1683 vmcs_writel(GUEST_RSP, (vmcs_readl(GUEST_RSP) & ~0xffff) | (sp - 6));
1686 static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
1688 if (vcpu->rmode.active) {
1689 inject_rmode_irq(vcpu, irq);
1692 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1693 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1696 static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1698 int word_index = __ffs(vcpu->irq_summary);
1699 int bit_index = __ffs(vcpu->irq_pending[word_index]);
1700 int irq = word_index * BITS_PER_LONG + bit_index;
1702 clear_bit(bit_index, &vcpu->irq_pending[word_index]);
1703 if (!vcpu->irq_pending[word_index])
1704 clear_bit(word_index, &vcpu->irq_summary);
1705 vmx_inject_irq(vcpu, irq);
1709 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1710 struct kvm_run *kvm_run)
1712 u32 cpu_based_vm_exec_control;
1714 vcpu->interrupt_window_open =
1715 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
1716 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1718 if (vcpu->interrupt_window_open &&
1719 vcpu->irq_summary &&
1720 !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
1722 * If interrupts enabled, and not blocked by sti or mov ss. Good.
1724 kvm_do_inject_irq(vcpu);
1726 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
1727 if (!vcpu->interrupt_window_open &&
1728 (vcpu->irq_summary || kvm_run->request_interrupt_window))
1730 * Interrupts blocked. Wait for unblock.
1732 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
1734 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
1735 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
1738 static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
1740 struct kvm_guest_debug *dbg = &vcpu->guest_debug;
1742 set_debugreg(dbg->bp[0], 0);
1743 set_debugreg(dbg->bp[1], 1);
1744 set_debugreg(dbg->bp[2], 2);
1745 set_debugreg(dbg->bp[3], 3);
1747 if (dbg->singlestep) {
1748 unsigned long flags;
1750 flags = vmcs_readl(GUEST_RFLAGS);
1751 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1752 vmcs_writel(GUEST_RFLAGS, flags);
1756 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
1757 int vec, u32 err_code)
1759 if (!vcpu->rmode.active)
1763 * Instruction with address size override prefix opcode 0x67
1764 * Cause the #SS fault with 0 error code in VM86 mode.
1766 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
1767 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
1772 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1774 u32 intr_info, error_code;
1775 unsigned long cr2, rip;
1777 enum emulation_result er;
1780 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1781 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
1783 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
1784 !is_page_fault(intr_info))
1785 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
1786 "intr info 0x%x\n", __FUNCTION__, vect_info, intr_info);
1788 if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
1789 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
1790 set_bit(irq, vcpu->irq_pending);
1791 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
1794 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
1795 return 1; /* already handled by vmx_vcpu_run() */
1797 if (is_no_device(intr_info)) {
1798 vmx_fpu_activate(vcpu);
1802 if (is_invalid_opcode(intr_info)) {
1803 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
1804 if (er != EMULATE_DONE)
1805 vmx_inject_ud(vcpu);
1811 rip = vmcs_readl(GUEST_RIP);
1812 if (intr_info & INTR_INFO_DELIEVER_CODE_MASK)
1813 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
1814 if (is_page_fault(intr_info)) {
1815 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1817 mutex_lock(&vcpu->kvm->lock);
1818 r = kvm_mmu_page_fault(vcpu, cr2, error_code);
1820 mutex_unlock(&vcpu->kvm->lock);
1824 mutex_unlock(&vcpu->kvm->lock);
1828 er = emulate_instruction(vcpu, kvm_run, cr2, error_code, 0);
1829 mutex_unlock(&vcpu->kvm->lock);
1834 case EMULATE_DO_MMIO:
1835 ++vcpu->stat.mmio_exits;
1838 kvm_report_emulation_failure(vcpu, "pagetable");
1845 if (vcpu->rmode.active &&
1846 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
1848 if (vcpu->halt_request) {
1849 vcpu->halt_request = 0;
1850 return kvm_emulate_halt(vcpu);
1855 if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) ==
1856 (INTR_TYPE_EXCEPTION | 1)) {
1857 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1860 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
1861 kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
1862 kvm_run->ex.error_code = error_code;
1866 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
1867 struct kvm_run *kvm_run)
1869 ++vcpu->stat.irq_exits;
1873 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1875 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1879 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1881 unsigned long exit_qualification;
1882 int size, down, in, string, rep;
1885 ++vcpu->stat.io_exits;
1886 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1887 string = (exit_qualification & 16) != 0;
1890 if (emulate_instruction(vcpu,
1891 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1896 size = (exit_qualification & 7) + 1;
1897 in = (exit_qualification & 8) != 0;
1898 down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
1899 rep = (exit_qualification & 32) != 0;
1900 port = exit_qualification >> 16;
1902 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
1906 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1909 * Patch in the VMCALL instruction:
1911 hypercall[0] = 0x0f;
1912 hypercall[1] = 0x01;
1913 hypercall[2] = 0xc1;
1916 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1918 unsigned long exit_qualification;
1922 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1923 cr = exit_qualification & 15;
1924 reg = (exit_qualification >> 8) & 15;
1925 switch ((exit_qualification >> 4) & 3) {
1926 case 0: /* mov to cr */
1929 vcpu_load_rsp_rip(vcpu);
1930 set_cr0(vcpu, vcpu->regs[reg]);
1931 skip_emulated_instruction(vcpu);
1934 vcpu_load_rsp_rip(vcpu);
1935 set_cr3(vcpu, vcpu->regs[reg]);
1936 skip_emulated_instruction(vcpu);
1939 vcpu_load_rsp_rip(vcpu);
1940 set_cr4(vcpu, vcpu->regs[reg]);
1941 skip_emulated_instruction(vcpu);
1944 vcpu_load_rsp_rip(vcpu);
1945 set_cr8(vcpu, vcpu->regs[reg]);
1946 skip_emulated_instruction(vcpu);
1947 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1952 vcpu_load_rsp_rip(vcpu);
1953 vmx_fpu_deactivate(vcpu);
1954 vcpu->cr0 &= ~X86_CR0_TS;
1955 vmcs_writel(CR0_READ_SHADOW, vcpu->cr0);
1956 vmx_fpu_activate(vcpu);
1957 skip_emulated_instruction(vcpu);
1959 case 1: /*mov from cr*/
1962 vcpu_load_rsp_rip(vcpu);
1963 vcpu->regs[reg] = vcpu->cr3;
1964 vcpu_put_rsp_rip(vcpu);
1965 skip_emulated_instruction(vcpu);
1968 vcpu_load_rsp_rip(vcpu);
1969 vcpu->regs[reg] = get_cr8(vcpu);
1970 vcpu_put_rsp_rip(vcpu);
1971 skip_emulated_instruction(vcpu);
1976 lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
1978 skip_emulated_instruction(vcpu);
1983 kvm_run->exit_reason = 0;
1984 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
1985 (int)(exit_qualification >> 4) & 3, cr);
1989 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1991 unsigned long exit_qualification;
1996 * FIXME: this code assumes the host is debugging the guest.
1997 * need to deal with guest debugging itself too.
1999 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2000 dr = exit_qualification & 7;
2001 reg = (exit_qualification >> 8) & 15;
2002 vcpu_load_rsp_rip(vcpu);
2003 if (exit_qualification & 16) {
2015 vcpu->regs[reg] = val;
2019 vcpu_put_rsp_rip(vcpu);
2020 skip_emulated_instruction(vcpu);
2024 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2026 kvm_emulate_cpuid(vcpu);
2030 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2032 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
2035 if (vmx_get_msr(vcpu, ecx, &data)) {
2036 vmx_inject_gp(vcpu, 0);
2040 /* FIXME: handling of bits 32:63 of rax, rdx */
2041 vcpu->regs[VCPU_REGS_RAX] = data & -1u;
2042 vcpu->regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2043 skip_emulated_instruction(vcpu);
2047 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2049 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
2050 u64 data = (vcpu->regs[VCPU_REGS_RAX] & -1u)
2051 | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32);
2053 if (vmx_set_msr(vcpu, ecx, data) != 0) {
2054 vmx_inject_gp(vcpu, 0);
2058 skip_emulated_instruction(vcpu);
2062 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2063 struct kvm_run *kvm_run)
2068 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2069 struct kvm_run *kvm_run)
2071 u32 cpu_based_vm_exec_control;
2073 /* clear pending irq */
2074 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2075 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2076 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2078 * If the user space waits to inject interrupts, exit as soon as
2081 if (kvm_run->request_interrupt_window &&
2082 !vcpu->irq_summary) {
2083 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2084 ++vcpu->stat.irq_window_exits;
2090 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2092 skip_emulated_instruction(vcpu);
2093 return kvm_emulate_halt(vcpu);
2096 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2098 skip_emulated_instruction(vcpu);
2099 kvm_emulate_hypercall(vcpu);
2104 * The exit handlers return 1 if the exit was handled fully and guest execution
2105 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
2106 * to be done to userspace and return 0.
2108 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
2109 struct kvm_run *kvm_run) = {
2110 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
2111 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
2112 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
2113 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
2114 [EXIT_REASON_CR_ACCESS] = handle_cr,
2115 [EXIT_REASON_DR_ACCESS] = handle_dr,
2116 [EXIT_REASON_CPUID] = handle_cpuid,
2117 [EXIT_REASON_MSR_READ] = handle_rdmsr,
2118 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
2119 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
2120 [EXIT_REASON_HLT] = handle_halt,
2121 [EXIT_REASON_VMCALL] = handle_vmcall,
2122 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold
2125 static const int kvm_vmx_max_exit_handlers =
2126 ARRAY_SIZE(kvm_vmx_exit_handlers);
2129 * The guest has exited. See if we can fix it or if we need userspace
2132 static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2134 u32 vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2135 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
2136 struct vcpu_vmx *vmx = to_vmx(vcpu);
2138 if (unlikely(vmx->fail)) {
2139 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2140 kvm_run->fail_entry.hardware_entry_failure_reason
2141 = vmcs_read32(VM_INSTRUCTION_ERROR);
2145 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
2146 exit_reason != EXIT_REASON_EXCEPTION_NMI)
2147 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
2148 "exit reason is 0x%x\n", __FUNCTION__, exit_reason);
2149 if (exit_reason < kvm_vmx_max_exit_handlers
2150 && kvm_vmx_exit_handlers[exit_reason])
2151 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
2153 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2154 kvm_run->hw.hardware_exit_reason = exit_reason;
2159 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2163 static void update_tpr_threshold(struct kvm_vcpu *vcpu)
2167 if (!vm_need_tpr_shadow(vcpu->kvm))
2170 if (!kvm_lapic_enabled(vcpu) ||
2171 ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
2172 vmcs_write32(TPR_THRESHOLD, 0);
2176 tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
2177 vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
2180 static void enable_irq_window(struct kvm_vcpu *vcpu)
2182 u32 cpu_based_vm_exec_control;
2184 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2185 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2186 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2189 static void vmx_intr_assist(struct kvm_vcpu *vcpu)
2191 u32 idtv_info_field, intr_info_field;
2192 int has_ext_irq, interrupt_window_open;
2195 update_tpr_threshold(vcpu);
2197 has_ext_irq = kvm_cpu_has_interrupt(vcpu);
2198 intr_info_field = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD);
2199 idtv_info_field = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2200 if (intr_info_field & INTR_INFO_VALID_MASK) {
2201 if (idtv_info_field & INTR_INFO_VALID_MASK) {
2202 /* TODO: fault when IDT_Vectoring */
2203 printk(KERN_ERR "Fault when IDT_Vectoring\n");
2206 enable_irq_window(vcpu);
2209 if (unlikely(idtv_info_field & INTR_INFO_VALID_MASK)) {
2210 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, idtv_info_field);
2211 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2212 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
2214 if (unlikely(idtv_info_field & INTR_INFO_DELIEVER_CODE_MASK))
2215 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
2216 vmcs_read32(IDT_VECTORING_ERROR_CODE));
2217 if (unlikely(has_ext_irq))
2218 enable_irq_window(vcpu);
2223 interrupt_window_open =
2224 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2225 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
2226 if (interrupt_window_open) {
2227 vector = kvm_cpu_get_interrupt(vcpu);
2228 vmx_inject_irq(vcpu, vector);
2229 kvm_timer_intr_post(vcpu, vector);
2231 enable_irq_window(vcpu);
2234 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2236 struct vcpu_vmx *vmx = to_vmx(vcpu);
2240 * Loading guest fpu may have cleared host cr0.ts
2242 vmcs_writel(HOST_CR0, read_cr0());
2245 /* Store host registers */
2246 #ifdef CONFIG_X86_64
2247 "push %%rax; push %%rbx; push %%rdx;"
2248 "push %%rsi; push %%rdi; push %%rbp;"
2249 "push %%r8; push %%r9; push %%r10; push %%r11;"
2250 "push %%r12; push %%r13; push %%r14; push %%r15;"
2252 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
2254 "pusha; push %%ecx \n\t"
2255 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
2257 /* Check if vmlaunch of vmresume is needed */
2259 /* Load guest registers. Don't clobber flags. */
2260 #ifdef CONFIG_X86_64
2261 "mov %c[cr2](%3), %%rax \n\t"
2262 "mov %%rax, %%cr2 \n\t"
2263 "mov %c[rax](%3), %%rax \n\t"
2264 "mov %c[rbx](%3), %%rbx \n\t"
2265 "mov %c[rdx](%3), %%rdx \n\t"
2266 "mov %c[rsi](%3), %%rsi \n\t"
2267 "mov %c[rdi](%3), %%rdi \n\t"
2268 "mov %c[rbp](%3), %%rbp \n\t"
2269 "mov %c[r8](%3), %%r8 \n\t"
2270 "mov %c[r9](%3), %%r9 \n\t"
2271 "mov %c[r10](%3), %%r10 \n\t"
2272 "mov %c[r11](%3), %%r11 \n\t"
2273 "mov %c[r12](%3), %%r12 \n\t"
2274 "mov %c[r13](%3), %%r13 \n\t"
2275 "mov %c[r14](%3), %%r14 \n\t"
2276 "mov %c[r15](%3), %%r15 \n\t"
2277 "mov %c[rcx](%3), %%rcx \n\t" /* kills %3 (rcx) */
2279 "mov %c[cr2](%3), %%eax \n\t"
2280 "mov %%eax, %%cr2 \n\t"
2281 "mov %c[rax](%3), %%eax \n\t"
2282 "mov %c[rbx](%3), %%ebx \n\t"
2283 "mov %c[rdx](%3), %%edx \n\t"
2284 "mov %c[rsi](%3), %%esi \n\t"
2285 "mov %c[rdi](%3), %%edi \n\t"
2286 "mov %c[rbp](%3), %%ebp \n\t"
2287 "mov %c[rcx](%3), %%ecx \n\t" /* kills %3 (ecx) */
2289 /* Enter guest mode */
2290 "jne .Llaunched \n\t"
2291 ASM_VMX_VMLAUNCH "\n\t"
2292 "jmp .Lkvm_vmx_return \n\t"
2293 ".Llaunched: " ASM_VMX_VMRESUME "\n\t"
2294 ".Lkvm_vmx_return: "
2295 /* Save guest registers, load host registers, keep flags */
2296 #ifdef CONFIG_X86_64
2297 "xchg %3, (%%rsp) \n\t"
2298 "mov %%rax, %c[rax](%3) \n\t"
2299 "mov %%rbx, %c[rbx](%3) \n\t"
2300 "pushq (%%rsp); popq %c[rcx](%3) \n\t"
2301 "mov %%rdx, %c[rdx](%3) \n\t"
2302 "mov %%rsi, %c[rsi](%3) \n\t"
2303 "mov %%rdi, %c[rdi](%3) \n\t"
2304 "mov %%rbp, %c[rbp](%3) \n\t"
2305 "mov %%r8, %c[r8](%3) \n\t"
2306 "mov %%r9, %c[r9](%3) \n\t"
2307 "mov %%r10, %c[r10](%3) \n\t"
2308 "mov %%r11, %c[r11](%3) \n\t"
2309 "mov %%r12, %c[r12](%3) \n\t"
2310 "mov %%r13, %c[r13](%3) \n\t"
2311 "mov %%r14, %c[r14](%3) \n\t"
2312 "mov %%r15, %c[r15](%3) \n\t"
2313 "mov %%cr2, %%rax \n\t"
2314 "mov %%rax, %c[cr2](%3) \n\t"
2315 "mov (%%rsp), %3 \n\t"
2317 "pop %%rcx; pop %%r15; pop %%r14; pop %%r13; pop %%r12;"
2318 "pop %%r11; pop %%r10; pop %%r9; pop %%r8;"
2319 "pop %%rbp; pop %%rdi; pop %%rsi;"
2320 "pop %%rdx; pop %%rbx; pop %%rax \n\t"
2322 "xchg %3, (%%esp) \n\t"
2323 "mov %%eax, %c[rax](%3) \n\t"
2324 "mov %%ebx, %c[rbx](%3) \n\t"
2325 "pushl (%%esp); popl %c[rcx](%3) \n\t"
2326 "mov %%edx, %c[rdx](%3) \n\t"
2327 "mov %%esi, %c[rsi](%3) \n\t"
2328 "mov %%edi, %c[rdi](%3) \n\t"
2329 "mov %%ebp, %c[rbp](%3) \n\t"
2330 "mov %%cr2, %%eax \n\t"
2331 "mov %%eax, %c[cr2](%3) \n\t"
2332 "mov (%%esp), %3 \n\t"
2334 "pop %%ecx; popa \n\t"
2338 : "r"(vmx->launched), "d"((unsigned long)HOST_RSP),
2340 [rax]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RAX])),
2341 [rbx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBX])),
2342 [rcx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RCX])),
2343 [rdx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDX])),
2344 [rsi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RSI])),
2345 [rdi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDI])),
2346 [rbp]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBP])),
2347 #ifdef CONFIG_X86_64
2348 [r8]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R8])),
2349 [r9]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R9])),
2350 [r10]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R10])),
2351 [r11]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R11])),
2352 [r12]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R12])),
2353 [r13]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R13])),
2354 [r14]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R14])),
2355 [r15]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R15])),
2357 [cr2]"i"(offsetof(struct kvm_vcpu, cr2))
2360 vcpu->interrupt_window_open =
2361 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0;
2363 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
2366 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2368 /* We need to handle NMIs before interrupts are enabled */
2369 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
2373 static void vmx_inject_page_fault(struct kvm_vcpu *vcpu,
2377 u32 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2379 ++vcpu->stat.pf_guest;
2381 if (is_page_fault(vect_info)) {
2382 printk(KERN_DEBUG "inject_page_fault: "
2383 "double fault 0x%lx @ 0x%lx\n",
2384 addr, vmcs_readl(GUEST_RIP));
2385 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, 0);
2386 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2388 INTR_TYPE_EXCEPTION |
2389 INTR_INFO_DELIEVER_CODE_MASK |
2390 INTR_INFO_VALID_MASK);
2394 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, err_code);
2395 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2397 INTR_TYPE_EXCEPTION |
2398 INTR_INFO_DELIEVER_CODE_MASK |
2399 INTR_INFO_VALID_MASK);
2403 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
2405 struct vcpu_vmx *vmx = to_vmx(vcpu);
2408 on_each_cpu(__vcpu_clear, vmx, 0, 1);
2409 free_vmcs(vmx->vmcs);
2414 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
2416 struct vcpu_vmx *vmx = to_vmx(vcpu);
2418 vmx_free_vmcs(vcpu);
2419 kfree(vmx->host_msrs);
2420 kfree(vmx->guest_msrs);
2421 kvm_vcpu_uninit(vcpu);
2422 kmem_cache_free(kvm_vcpu_cache, vmx);
2425 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
2428 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
2432 return ERR_PTR(-ENOMEM);
2434 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
2438 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2439 if (!vmx->guest_msrs) {
2444 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2445 if (!vmx->host_msrs)
2446 goto free_guest_msrs;
2448 vmx->vmcs = alloc_vmcs();
2452 vmcs_clear(vmx->vmcs);
2455 vmx_vcpu_load(&vmx->vcpu, cpu);
2456 err = vmx_vcpu_setup(vmx);
2457 vmx_vcpu_put(&vmx->vcpu);
2465 free_vmcs(vmx->vmcs);
2467 kfree(vmx->host_msrs);
2469 kfree(vmx->guest_msrs);
2471 kvm_vcpu_uninit(&vmx->vcpu);
2473 kmem_cache_free(kvm_vcpu_cache, vmx);
2474 return ERR_PTR(err);
2477 static void __init vmx_check_processor_compat(void *rtn)
2479 struct vmcs_config vmcs_conf;
2482 if (setup_vmcs_config(&vmcs_conf) < 0)
2484 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
2485 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
2486 smp_processor_id());
2491 static struct kvm_x86_ops vmx_x86_ops = {
2492 .cpu_has_kvm_support = cpu_has_kvm_support,
2493 .disabled_by_bios = vmx_disabled_by_bios,
2494 .hardware_setup = hardware_setup,
2495 .hardware_unsetup = hardware_unsetup,
2496 .check_processor_compatibility = vmx_check_processor_compat,
2497 .hardware_enable = hardware_enable,
2498 .hardware_disable = hardware_disable,
2500 .vcpu_create = vmx_create_vcpu,
2501 .vcpu_free = vmx_free_vcpu,
2502 .vcpu_reset = vmx_vcpu_reset,
2504 .prepare_guest_switch = vmx_save_host_state,
2505 .vcpu_load = vmx_vcpu_load,
2506 .vcpu_put = vmx_vcpu_put,
2507 .vcpu_decache = vmx_vcpu_decache,
2509 .set_guest_debug = set_guest_debug,
2510 .guest_debug_pre = kvm_guest_debug_pre,
2511 .get_msr = vmx_get_msr,
2512 .set_msr = vmx_set_msr,
2513 .get_segment_base = vmx_get_segment_base,
2514 .get_segment = vmx_get_segment,
2515 .set_segment = vmx_set_segment,
2516 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
2517 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
2518 .set_cr0 = vmx_set_cr0,
2519 .set_cr3 = vmx_set_cr3,
2520 .set_cr4 = vmx_set_cr4,
2521 #ifdef CONFIG_X86_64
2522 .set_efer = vmx_set_efer,
2524 .get_idt = vmx_get_idt,
2525 .set_idt = vmx_set_idt,
2526 .get_gdt = vmx_get_gdt,
2527 .set_gdt = vmx_set_gdt,
2528 .cache_regs = vcpu_load_rsp_rip,
2529 .decache_regs = vcpu_put_rsp_rip,
2530 .get_rflags = vmx_get_rflags,
2531 .set_rflags = vmx_set_rflags,
2533 .tlb_flush = vmx_flush_tlb,
2534 .inject_page_fault = vmx_inject_page_fault,
2536 .inject_gp = vmx_inject_gp,
2538 .run = vmx_vcpu_run,
2539 .handle_exit = kvm_handle_exit,
2540 .skip_emulated_instruction = skip_emulated_instruction,
2541 .patch_hypercall = vmx_patch_hypercall,
2542 .get_irq = vmx_get_irq,
2543 .set_irq = vmx_inject_irq,
2544 .inject_pending_irq = vmx_intr_assist,
2545 .inject_pending_vectors = do_interrupt_requests,
2548 static int __init vmx_init(void)
2553 vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2554 if (!vmx_io_bitmap_a)
2557 vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2558 if (!vmx_io_bitmap_b) {
2564 * Allow direct access to the PC debug port (it is often used for I/O
2565 * delays, but the vmexits simply slow things down).
2567 iova = kmap(vmx_io_bitmap_a);
2568 memset(iova, 0xff, PAGE_SIZE);
2569 clear_bit(0x80, iova);
2570 kunmap(vmx_io_bitmap_a);
2572 iova = kmap(vmx_io_bitmap_b);
2573 memset(iova, 0xff, PAGE_SIZE);
2574 kunmap(vmx_io_bitmap_b);
2576 r = kvm_init_x86(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
2580 if (bypass_guest_pf)
2581 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
2586 __free_page(vmx_io_bitmap_b);
2588 __free_page(vmx_io_bitmap_a);
2592 static void __exit vmx_exit(void)
2594 __free_page(vmx_io_bitmap_b);
2595 __free_page(vmx_io_bitmap_a);
2600 module_init(vmx_init)
2601 module_exit(vmx_exit)