1 /* $Id: jade.c,v 1.9.2.4 2004/01/14 16:04:48 keil Exp $
3 * JADE stuff (derived from original hscx.c)
5 * Author Roland Klabunde
6 * Copyright by Roland Klabunde <R.Klabunde@Berkom.de>
8 * This software may be used and distributed according to the terms
9 * of the GNU General Public License, incorporated herein by reference.
14 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/slab.h>
24 JadeVersion(struct IsdnCardState *cs, char *s)
28 cs->BC_Write_Reg(cs, -1, 0x50, 0x19);
32 ver = cs->BC_Read_Reg(cs, -1, 0x60);
37 printk(KERN_INFO "%s JADE version not obtainable\n", s);
41 /* Wait for the JADE */
44 ver = cs->BC_Read_Reg(cs, -1, 0x60);
45 printk(KERN_INFO "%s JADE version: %d\n", s, ver);
49 /* Write to indirect accessible jade register set */
51 jade_write_indirect(struct IsdnCardState *cs, u_char reg, u_char value)
57 cs->BC_Write_Reg(cs, -1, COMM_JADE+1, value);
58 /* Say JADE we wanna write indirect reg 'reg' */
59 cs->BC_Write_Reg(cs, -1, COMM_JADE, reg);
61 /* Wait for RDY goes high */
64 ret = cs->BC_Read_Reg(cs, -1, COMM_JADE);
70 printk(KERN_INFO "Can not see ready bit from JADE DSP (reg=0x%X, value=0x%X)\n", reg, value);
79 modejade(struct BCState *bcs, int mode, int bc)
81 struct IsdnCardState *cs = bcs->cs;
82 int jade = bcs->hw.hscx.hscx;
84 if (cs->debug & L1_DEB_HSCX) {
86 sprintf(tmp, "jade %c mode %d ichan %d",
87 'A' + jade, mode, bc);
93 cs->BC_Write_Reg(cs, jade, jade_HDLC_MODE, (mode == L1_MODE_TRANS ? jadeMODE_TMO:0x00));
94 cs->BC_Write_Reg(cs, jade, jade_HDLC_CCR0, (jadeCCR0_PU|jadeCCR0_ITF));
95 cs->BC_Write_Reg(cs, jade, jade_HDLC_CCR1, 0x00);
97 jade_write_indirect(cs, jade_HDLC1SERRXPATH, 0x08);
98 jade_write_indirect(cs, jade_HDLC2SERRXPATH, 0x08);
99 jade_write_indirect(cs, jade_HDLC1SERTXPATH, 0x00);
100 jade_write_indirect(cs, jade_HDLC2SERTXPATH, 0x00);
102 cs->BC_Write_Reg(cs, jade, jade_HDLC_XCCR, 0x07);
103 cs->BC_Write_Reg(cs, jade, jade_HDLC_RCCR, 0x07);
106 cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAX, 0x00);
107 cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAR, 0x00);
109 cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAX, 0x04);
110 cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAR, 0x04);
114 cs->BC_Write_Reg(cs, jade, jade_HDLC_MODE, jadeMODE_TMO);
116 case (L1_MODE_TRANS):
117 cs->BC_Write_Reg(cs, jade, jade_HDLC_MODE, (jadeMODE_TMO|jadeMODE_RAC|jadeMODE_XAC));
120 cs->BC_Write_Reg(cs, jade, jade_HDLC_MODE, (jadeMODE_RAC|jadeMODE_XAC));
124 cs->BC_Write_Reg(cs, jade, jade_HDLC_RCMD, (jadeRCMD_RRES|jadeRCMD_RMC));
125 cs->BC_Write_Reg(cs, jade, jade_HDLC_XCMD, jadeXCMD_XRES);
127 cs->BC_Write_Reg(cs, jade, jade_HDLC_IMR, 0xF8);
131 cs->BC_Write_Reg(cs, jade, jade_HDLC_IMR, 0x00);
135 jade_l2l1(struct PStack *st, int pr, void *arg)
137 struct BCState *bcs = st->l1.bcs;
138 struct sk_buff *skb = arg;
142 case (PH_DATA | REQUEST):
143 spin_lock_irqsave(&bcs->cs->lock, flags);
145 skb_queue_tail(&bcs->squeue, skb);
148 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
149 bcs->hw.hscx.count = 0;
150 bcs->cs->BC_Send_Data(bcs);
152 spin_unlock_irqrestore(&bcs->cs->lock, flags);
154 case (PH_PULL | INDICATION):
155 spin_lock_irqsave(&bcs->cs->lock, flags);
157 printk(KERN_WARNING "jade_l2l1: this shouldn't happen\n");
159 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
161 bcs->hw.hscx.count = 0;
162 bcs->cs->BC_Send_Data(bcs);
164 spin_unlock_irqrestore(&bcs->cs->lock, flags);
166 case (PH_PULL | REQUEST):
168 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
169 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
171 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
173 case (PH_ACTIVATE | REQUEST):
174 spin_lock_irqsave(&bcs->cs->lock, flags);
175 test_and_set_bit(BC_FLG_ACTIV, &bcs->Flag);
176 modejade(bcs, st->l1.mode, st->l1.bc);
177 spin_unlock_irqrestore(&bcs->cs->lock, flags);
178 l1_msg_b(st, pr, arg);
180 case (PH_DEACTIVATE | REQUEST):
181 l1_msg_b(st, pr, arg);
183 case (PH_DEACTIVATE | CONFIRM):
184 spin_lock_irqsave(&bcs->cs->lock, flags);
185 test_and_clear_bit(BC_FLG_ACTIV, &bcs->Flag);
186 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
187 modejade(bcs, 0, st->l1.bc);
188 spin_unlock_irqrestore(&bcs->cs->lock, flags);
189 st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
195 close_jadestate(struct BCState *bcs)
197 modejade(bcs, 0, bcs->channel);
198 if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
199 kfree(bcs->hw.hscx.rcvbuf);
200 bcs->hw.hscx.rcvbuf = NULL;
203 skb_queue_purge(&bcs->rqueue);
204 skb_queue_purge(&bcs->squeue);
206 dev_kfree_skb_any(bcs->tx_skb);
208 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
214 open_jadestate(struct IsdnCardState *cs, struct BCState *bcs)
216 if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
217 if (!(bcs->hw.hscx.rcvbuf = kmalloc(HSCX_BUFMAX, GFP_ATOMIC))) {
219 "HiSax: No memory for hscx.rcvbuf\n");
220 test_and_clear_bit(BC_FLG_INIT, &bcs->Flag);
223 if (!(bcs->blog = kmalloc(MAX_BLOG_SPACE, GFP_ATOMIC))) {
225 "HiSax: No memory for bcs->blog\n");
226 test_and_clear_bit(BC_FLG_INIT, &bcs->Flag);
227 kfree(bcs->hw.hscx.rcvbuf);
228 bcs->hw.hscx.rcvbuf = NULL;
231 skb_queue_head_init(&bcs->rqueue);
232 skb_queue_head_init(&bcs->squeue);
235 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
237 bcs->hw.hscx.rcvidx = 0;
244 setstack_jade(struct PStack *st, struct BCState *bcs)
246 bcs->channel = st->l1.bc;
247 if (open_jadestate(st->l1.hardware, bcs))
250 st->l2.l2l1 = jade_l2l1;
251 setstack_manager(st);
258 clear_pending_jade_ints(struct IsdnCardState *cs)
263 cs->BC_Write_Reg(cs, 0, jade_HDLC_IMR, 0x00);
264 cs->BC_Write_Reg(cs, 1, jade_HDLC_IMR, 0x00);
266 val = cs->BC_Read_Reg(cs, 1, jade_HDLC_ISR);
267 sprintf(tmp, "jade B ISTA %x", val);
269 val = cs->BC_Read_Reg(cs, 0, jade_HDLC_ISR);
270 sprintf(tmp, "jade A ISTA %x", val);
272 val = cs->BC_Read_Reg(cs, 1, jade_HDLC_STAR);
273 sprintf(tmp, "jade B STAR %x", val);
275 val = cs->BC_Read_Reg(cs, 0, jade_HDLC_STAR);
276 sprintf(tmp, "jade A STAR %x", val);
279 cs->BC_Write_Reg(cs, 0, jade_HDLC_IMR, 0xF8);
280 cs->BC_Write_Reg(cs, 1, jade_HDLC_IMR, 0xF8);
284 initjade(struct IsdnCardState *cs)
286 cs->bcs[0].BC_SetStack = setstack_jade;
287 cs->bcs[1].BC_SetStack = setstack_jade;
288 cs->bcs[0].BC_Close = close_jadestate;
289 cs->bcs[1].BC_Close = close_jadestate;
290 cs->bcs[0].hw.hscx.hscx = 0;
291 cs->bcs[1].hw.hscx.hscx = 1;
293 /* Stop DSP audio tx/rx */
294 jade_write_indirect(cs, 0x11, 0x0f);
295 jade_write_indirect(cs, 0x17, 0x2f);
297 /* Transparent Mode, RxTx inactive, No Test, No RFS/TFS */
298 cs->BC_Write_Reg(cs, 0, jade_HDLC_MODE, jadeMODE_TMO);
299 cs->BC_Write_Reg(cs, 1, jade_HDLC_MODE, jadeMODE_TMO);
300 /* Power down, 1-Idle, RxTx least significant bit first */
301 cs->BC_Write_Reg(cs, 0, jade_HDLC_CCR0, 0x00);
302 cs->BC_Write_Reg(cs, 1, jade_HDLC_CCR0, 0x00);
303 /* Mask all interrupts */
304 cs->BC_Write_Reg(cs, 0, jade_HDLC_IMR, 0x00);
305 cs->BC_Write_Reg(cs, 1, jade_HDLC_IMR, 0x00);
306 /* Setup host access to hdlc controller */
307 jade_write_indirect(cs, jade_HDLCCNTRACCESS, (jadeINDIRECT_HAH1|jadeINDIRECT_HAH2));
308 /* Unmask HDLC int (don't forget DSP int later on)*/
309 cs->BC_Write_Reg(cs, -1,jade_INT, (jadeINT_HDLC1|jadeINT_HDLC2));
311 /* once again TRANSPARENT */
312 modejade(cs->bcs, 0, 0);
313 modejade(cs->bcs + 1, 0, 0);