2 * Keyboard class input driver for the NVIDIA Tegra SoC internal matrix
5 * Copyright (c) 2009-2011, NVIDIA Corporation.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
22 #include <linux/module.h>
23 #include <linux/input.h>
24 #include <linux/platform_device.h>
25 #include <linux/delay.h>
27 #include <linux/interrupt.h>
28 #include <linux/clk.h>
29 #include <linux/slab.h>
33 #define KBC_MAX_DEBOUNCE_CNT 0x3ffu
35 /* KBC row scan time and delay for beginning the row scan. */
36 #define KBC_ROW_SCAN_TIME 16
37 #define KBC_ROW_SCAN_DLY 5
39 /* KBC uses a 32KHz clock so a cycle = 1/32Khz */
40 #define KBC_CYCLE_USEC 32
44 /* KBC Control Register */
45 #define KBC_CONTROL_0 0x0
46 #define KBC_FIFO_TH_CNT_SHIFT(cnt) (cnt << 14)
47 #define KBC_DEBOUNCE_CNT_SHIFT(cnt) (cnt << 4)
48 #define KBC_CONTROL_FIFO_CNT_INT_EN (1 << 3)
49 #define KBC_CONTROL_KBC_EN (1 << 0)
51 /* KBC Interrupt Register */
53 #define KBC_INT_FIFO_CNT_INT_STATUS (1 << 2)
55 #define KBC_ROW_CFG0_0 0x8
56 #define KBC_COL_CFG0_0 0x18
57 #define KBC_INIT_DLY_0 0x28
58 #define KBC_RPT_DLY_0 0x2c
59 #define KBC_KP_ENT0_0 0x30
60 #define KBC_KP_ENT1_0 0x34
61 #define KBC_ROW0_MASK_0 0x38
63 #define KBC_ROW_SHIFT 3
67 struct input_dev *idev;
69 unsigned int wake_enable_rows;
70 unsigned int wake_enable_cols;
72 unsigned int repoll_dly;
73 unsigned long cp_dly_jiffies;
74 const struct tegra_kbc_platform_data *pdata;
75 unsigned short keycode[KBC_MAX_KEY];
76 unsigned short current_keys[KBC_MAX_KPENT];
77 unsigned int num_pressed_keys;
78 struct timer_list timer;
82 static const u32 tegra_kbc_default_keymap[] = {
91 KEY(2, 6, KEY_RIGHTALT),
92 KEY(2, 7, KEY_LEFTALT),
109 KEY(4, 7, KEY_SPACE),
118 KEY(5, 7, KEY_BACKSLASH),
120 KEY(6, 0, KEY_MINUS),
126 KEY(6, 6, KEY_COMMA),
129 KEY(7, 1, KEY_EQUAL),
130 KEY(7, 2, KEY_RIGHTBRACE),
131 KEY(7, 3, KEY_ENTER),
134 KEY(8, 4, KEY_RIGHTSHIFT),
135 KEY(8, 5, KEY_LEFTSHIFT),
137 KEY(9, 5, KEY_RIGHTCTRL),
138 KEY(9, 7, KEY_LEFTCTRL),
140 KEY(11, 0, KEY_LEFTBRACE),
142 KEY(11, 2, KEY_APOSTROPHE),
143 KEY(11, 3, KEY_SEMICOLON),
144 KEY(11, 4, KEY_SLASH),
149 KEY(12, 2, KEY_BACKSPACE),
153 KEY(12, 6, KEY_PRINT),
154 KEY(12, 7, KEY_PAUSE),
156 KEY(13, 0, KEY_INSERT),
157 KEY(13, 1, KEY_DELETE),
158 KEY(13, 3, KEY_PAGEUP),
159 KEY(13, 4, KEY_PAGEDOWN),
160 KEY(13, 5, KEY_RIGHT),
161 KEY(13, 6, KEY_DOWN),
162 KEY(13, 7, KEY_LEFT),
174 KEY(15, 1, KEY_GRAVE),
179 KEY(15, 6, KEY_CAPSLOCK),
183 static const struct matrix_keymap_data tegra_kbc_default_keymap_data = {
184 .keymap = tegra_kbc_default_keymap,
185 .keymap_size = ARRAY_SIZE(tegra_kbc_default_keymap),
188 static void tegra_kbc_report_released_keys(struct input_dev *input,
189 unsigned short old_keycodes[],
190 unsigned int old_num_keys,
191 unsigned short new_keycodes[],
192 unsigned int new_num_keys)
196 for (i = 0; i < old_num_keys; i++) {
197 for (j = 0; j < new_num_keys; j++)
198 if (old_keycodes[i] == new_keycodes[j])
201 if (j == new_num_keys)
202 input_report_key(input, old_keycodes[i], 0);
206 static void tegra_kbc_report_pressed_keys(struct input_dev *input,
207 unsigned char scancodes[],
208 unsigned short keycodes[],
209 unsigned int num_pressed_keys)
213 for (i = 0; i < num_pressed_keys; i++) {
214 input_event(input, EV_MSC, MSC_SCAN, scancodes[i]);
215 input_report_key(input, keycodes[i], 1);
219 static void tegra_kbc_report_keys(struct tegra_kbc *kbc)
221 unsigned char scancodes[KBC_MAX_KPENT];
222 unsigned short keycodes[KBC_MAX_KPENT];
225 unsigned int num_down = 0;
228 spin_lock_irqsave(&kbc->lock, flags);
229 for (i = 0; i < KBC_MAX_KPENT; i++) {
231 val = readl(kbc->mmio + KBC_KP_ENT0_0 + i);
234 unsigned int col = val & 0x07;
235 unsigned int row = (val >> 3) & 0x0f;
236 unsigned char scancode =
237 MATRIX_SCAN_CODE(row, col, KBC_ROW_SHIFT);
239 scancodes[num_down] = scancode;
240 keycodes[num_down++] = kbc->keycode[scancode];
245 spin_unlock_irqrestore(&kbc->lock, flags);
247 tegra_kbc_report_released_keys(kbc->idev,
248 kbc->current_keys, kbc->num_pressed_keys,
250 tegra_kbc_report_pressed_keys(kbc->idev, scancodes, keycodes, num_down);
251 input_sync(kbc->idev);
253 memcpy(kbc->current_keys, keycodes, sizeof(kbc->current_keys));
254 kbc->num_pressed_keys = num_down;
257 static void tegra_kbc_keypress_timer(unsigned long data)
259 struct tegra_kbc *kbc = (struct tegra_kbc *)data;
264 val = (readl(kbc->mmio + KBC_INT_0) >> 4) & 0xf;
268 tegra_kbc_report_keys(kbc);
271 * If more than one keys are pressed we need not wait
272 * for the repoll delay.
274 dly = (val == 1) ? kbc->repoll_dly : 1;
275 mod_timer(&kbc->timer, jiffies + msecs_to_jiffies(dly));
277 /* Release any pressed keys and exit the polling loop */
278 for (i = 0; i < kbc->num_pressed_keys; i++)
279 input_report_key(kbc->idev, kbc->current_keys[i], 0);
280 input_sync(kbc->idev);
282 kbc->num_pressed_keys = 0;
284 /* All keys are released so enable the keypress interrupt */
285 spin_lock_irqsave(&kbc->lock, flags);
286 val = readl(kbc->mmio + KBC_CONTROL_0);
287 val |= KBC_CONTROL_FIFO_CNT_INT_EN;
288 writel(val, kbc->mmio + KBC_CONTROL_0);
289 spin_unlock_irqrestore(&kbc->lock, flags);
293 static irqreturn_t tegra_kbc_isr(int irq, void *args)
295 struct tegra_kbc *kbc = args;
299 * Until all keys are released, defer further processing to
300 * the polling loop in tegra_kbc_keypress_timer
302 ctl = readl(kbc->mmio + KBC_CONTROL_0);
303 ctl &= ~KBC_CONTROL_FIFO_CNT_INT_EN;
304 writel(ctl, kbc->mmio + KBC_CONTROL_0);
307 * Quickly bail out & reenable interrupts if the fifo threshold
308 * count interrupt wasn't the interrupt source
310 val = readl(kbc->mmio + KBC_INT_0);
311 writel(val, kbc->mmio + KBC_INT_0);
313 if (val & KBC_INT_FIFO_CNT_INT_STATUS) {
315 * Schedule timer to run when hardware is in continuous
318 mod_timer(&kbc->timer, jiffies + kbc->cp_dly_jiffies);
320 ctl |= KBC_CONTROL_FIFO_CNT_INT_EN;
321 writel(ctl, kbc->mmio + KBC_CONTROL_0);
327 static void tegra_kbc_setup_wakekeys(struct tegra_kbc *kbc, bool filter)
329 const struct tegra_kbc_platform_data *pdata = kbc->pdata;
331 unsigned int rst_val;
333 BUG_ON(pdata->wake_cnt > KBC_MAX_KEY);
334 rst_val = (filter && pdata->wake_cnt) ? ~0 : 0;
336 for (i = 0; i < KBC_MAX_ROW; i++)
337 writel(rst_val, kbc->mmio + KBC_ROW0_MASK_0 + i * 4);
340 for (i = 0; i < pdata->wake_cnt; i++) {
342 addr = pdata->wake_cfg[i].row * 4 + KBC_ROW0_MASK_0;
343 val = readl(kbc->mmio + addr);
344 val &= ~(1 << pdata->wake_cfg[i].col);
345 writel(val, kbc->mmio + addr);
350 static void tegra_kbc_config_pins(struct tegra_kbc *kbc)
352 const struct tegra_kbc_platform_data *pdata = kbc->pdata;
355 for (i = 0; i < KBC_MAX_GPIO; i++) {
356 u32 r_shft = 5 * (i % 6);
357 u32 c_shft = 4 * (i % 8);
358 u32 r_mask = 0x1f << r_shift;
359 u32 c_mask = 0x0f << c_shift;
360 u32 r_offs = (i / 6) * 4 + KBC_ROW_CFG0_0;
361 u32 c_offs = (i / 8) * 4 + KBC_COL_CFG0_0;
362 u32 row_cfg = readl(kbc->mmio + r_offs);
363 u32 col_cfg = readl(kbc->mmio + c_offs);
368 if (pdata->pin_cfg[i].is_row)
369 row_cfg |= ((pdata->pin_cfg[i].num << 1) | 1) << r_shft;
371 col_cfg |= ((pdata->pin_cfg[i].num << 1) | 1) << c_shft;
373 writel(row_cfg, kbc->mmio + r_offs);
374 writel(col_cfg, kbc->mmio + c_offs);
378 static int tegra_kbc_start(struct tegra_kbc *kbc)
380 const struct tegra_kbc_platform_data *pdata = kbc->pdata;
382 unsigned int debounce_cnt;
385 clk_enable(kbc->clk);
387 /* Reset the KBC controller to clear all previous status.*/
388 tegra_periph_reset_assert(kbc->clk);
390 tegra_periph_reset_deassert(kbc->clk);
393 tegra_kbc_config_pins(kbc);
394 tegra_kbc_setup_wakekeys(kbc, false);
396 writel(pdata->repeat_cnt, kbc->mmio + KBC_RPT_DLY_0);
398 /* Keyboard debounce count is maximum of 12 bits. */
399 debounce_cnt = min(pdata->debounce_cnt, KBC_MAX_DEBOUNCE_CNT);
400 val = KBC_DEBOUNCE_CNT_SHIFT(debounce_cnt);
401 val |= KBC_FIFO_TH_CNT_SHIFT(1); /* set fifo interrupt threshold to 1 */
402 val |= KBC_CONTROL_FIFO_CNT_INT_EN; /* interrupt on FIFO threshold */
403 val |= KBC_CONTROL_KBC_EN; /* enable */
404 writel(val, kbc->mmio + KBC_CONTROL_0);
407 * Compute the delay(ns) from interrupt mode to continuous polling
408 * mode so the timer routine is scheduled appropriately.
410 val = readl(kbc->mmio + KBC_INIT_DLY_0);
411 kbc->cp_dly_jiffies = usecs_to_jiffies((val & 0xfffff) * 32);
413 kbc->num_pressed_keys = 0;
416 * Atomically clear out any remaining entries in the key FIFO
417 * and enable keyboard interrupts.
419 spin_lock_irqsave(&kbc->lock, flags);
421 val = readl(kbc->mmio + KBC_INT_0);
426 val = readl(kbc->mmio + KBC_KP_ENT0_0);
427 val = readl(kbc->mmio + KBC_KP_ENT1_0);
429 writel(0x7, kbc->mmio + KBC_INT_0);
430 spin_unlock_irqrestore(&kbc->lock, flags);
432 enable_irq(kbc->irq);
437 static void tegra_kbc_stop(struct tegra_kbc *kbc)
442 spin_lock_irqsave(&kbc->lock, flags);
443 val = readl(kbc->mmio + KBC_CONTROL_0);
445 writel(val, kbc->mmio + KBC_CONTROL_0);
446 spin_unlock_irqrestore(&kbc->lock, flags);
448 disable_irq(kbc->irq);
449 del_timer_sync(&kbc->timer);
451 clk_disable(kbc->clk);
454 static int tegra_kbc_open(struct input_dev *dev)
456 struct tegra_kbc *kbc = input_get_drvdata(dev);
458 return tegra_kbc_start(kbc);
461 static void tegra_kbc_close(struct input_dev *dev)
463 struct tegra_kbc *kbc = input_get_drvdata(dev);
465 return tegra_kbc_stop(kbc);
468 static bool __devinit
469 tegra_kbc_check_pin_cfg(const struct tegra_kbc_platform_data *pdata,
470 struct device *dev, unsigned int *num_rows)
476 for (i = 0; i < KBC_MAX_GPIO; i++) {
477 const struct tegra_kbc_pin_cfg *pin_cfg = &pdata->pin_cfg[i];
479 if (pin_cfg->is_row) {
480 if (pin_cfg->num >= KBC_MAX_ROW) {
482 "pin_cfg[%d]: invalid row number %d\n",
488 if (pin_cfg->num >= KBC_MAX_COL) {
490 "pin_cfg[%d]: invalid column number %d\n",
500 static int __devinit tegra_kbc_probe(struct platform_device *pdev)
502 const struct tegra_kbc_platform_data *pdata = pdev->dev.platform_data;
503 const struct matrix_keymap_data *keymap_data;
504 struct tegra_kbc *kbc;
505 struct input_dev *input_dev;
506 struct resource *res;
511 unsigned int debounce_cnt;
512 unsigned int scan_time_rows;
517 if (!tegra_kbc_check_pin_cfg(pdata, &pdev->dev, &num_rows))
520 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
522 dev_err(&pdev->dev, "failed to get I/O memory\n");
526 irq = platform_get_irq(pdev, 0);
528 dev_err(&pdev->dev, "failed to get keyboard IRQ\n");
532 kbc = kzalloc(sizeof(*kbc), GFP_KERNEL);
533 input_dev = input_allocate_device();
534 if (!kbc || !input_dev) {
540 kbc->idev = input_dev;
542 spin_lock_init(&kbc->lock);
543 setup_timer(&kbc->timer, tegra_kbc_keypress_timer, (unsigned long)kbc);
545 res = request_mem_region(res->start, resource_size(res), pdev->name);
547 dev_err(&pdev->dev, "failed to request I/O memory\n");
552 kbc->mmio = ioremap(res->start, resource_size(res));
554 dev_err(&pdev->dev, "failed to remap I/O memory\n");
556 goto err_free_mem_region;
559 kbc->clk = clk_get(&pdev->dev, NULL);
560 if (IS_ERR(kbc->clk)) {
561 dev_err(&pdev->dev, "failed to get keyboard clock\n");
562 err = PTR_ERR(kbc->clk);
566 kbc->wake_enable_rows = 0;
567 kbc->wake_enable_cols = 0;
568 for (i = 0; i < pdata->wake_cnt; i++) {
569 kbc->wake_enable_rows |= (1 << pdata->wake_cfg[i].row);
570 kbc->wake_enable_cols |= (1 << pdata->wake_cfg[i].col);
574 * The time delay between two consecutive reads of the FIFO is
575 * the sum of the repeat time and the time taken for scanning
576 * the rows. There is an additional delay before the row scanning
577 * starts. The repoll delay is computed in milliseconds.
579 debounce_cnt = min(pdata->debounce_cnt, KBC_MAX_DEBOUNCE_CNT);
580 scan_time_rows = (KBC_ROW_SCAN_TIME + debounce_cnt) * num_rows;
581 kbc->repoll_dly = KBC_ROW_SCAN_DLY + scan_time_rows + pdata->repeat_cnt;
582 kbc->repoll_dly = ((kbc->repoll_dly * KBC_CYCLE_USEC) + 999) / 1000;
584 input_dev->name = pdev->name;
585 input_dev->id.bustype = BUS_HOST;
586 input_dev->dev.parent = &pdev->dev;
587 input_dev->open = tegra_kbc_open;
588 input_dev->close = tegra_kbc_close;
590 input_set_drvdata(input_dev, kbc);
592 input_dev->evbit[0] = BIT_MASK(EV_KEY);
593 input_set_capability(input_dev, EV_MSC, MSC_SCAN);
595 input_dev->keycode = kbc->keycode;
596 input_dev->keycodesize = sizeof(kbc->keycode[0]);
597 input_dev->keycodemax = ARRAY_SIZE(kbc->keycode);
599 keymap_data = pdata->keymap_data ?: &tegra_kbc_default_keymap_data;
600 matrix_keypad_build_keymap(keymap_data, KBC_ROW_SHIFT,
601 input_dev->keycode, input_dev->keybit);
603 err = request_irq(kbc->irq, tegra_kbc_isr, IRQF_TRIGGER_HIGH,
606 dev_err(&pdev->dev, "failed to request keyboard IRQ\n");
610 disable_irq(kbc->irq);
612 err = input_register_device(kbc->idev);
614 dev_err(&pdev->dev, "failed to register input device\n");
618 platform_set_drvdata(pdev, kbc);
619 device_init_wakeup(&pdev->dev, pdata->wakeup);
624 free_irq(kbc->irq, pdev);
630 release_mem_region(res->start, resource_size(res));
632 input_free_device(kbc->idev);
638 static int __devexit tegra_kbc_remove(struct platform_device *pdev)
640 struct tegra_kbc *kbc = platform_get_drvdata(pdev);
641 struct resource *res;
643 free_irq(kbc->irq, pdev);
646 input_unregister_device(kbc->idev);
648 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
649 release_mem_region(res->start, resource_size(res));
653 platform_set_drvdata(pdev, NULL);
658 #ifdef CONFIG_PM_SLEEP
659 static int tegra_kbc_suspend(struct device *dev)
661 struct platform_device *pdev = to_platform_device(dev);
662 struct tegra_kbc *kbc = platform_get_drvdata(pdev);
664 if (device_may_wakeup(&pdev->dev)) {
665 tegra_kbc_setup_wakekeys(kbc, true);
666 enable_irq_wake(kbc->irq);
667 /* Forcefully clear the interrupt status */
668 writel(0x7, kbc->mmio + KBC_INT_0);
671 mutex_lock(&kbc->idev->mutex);
672 if (kbc->idev->users)
674 mutex_unlock(&kbc->idev->mutex);
680 static int tegra_kbc_resume(struct device *dev)
682 struct platform_device *pdev = to_platform_device(dev);
683 struct tegra_kbc *kbc = platform_get_drvdata(pdev);
686 if (device_may_wakeup(&pdev->dev)) {
687 disable_irq_wake(kbc->irq);
688 tegra_kbc_setup_wakekeys(kbc, false);
690 mutex_lock(&kbc->idev->mutex);
691 if (kbc->idev->users)
692 err = tegra_kbc_start(kbc);
693 mutex_unlock(&kbc->idev->mutex);
700 static SIMPLE_DEV_PM_OPS(tegra_kbc_pm_ops, tegra_kbc_suspend, tegra_kbc_resume);
702 static struct platform_driver tegra_kbc_driver = {
703 .probe = tegra_kbc_probe,
704 .remove = __devexit_p(tegra_kbc_remove),
707 .owner = THIS_MODULE,
708 .pm = &tegra_kbc_pm_ops,
712 static void __exit tegra_kbc_exit(void)
714 platform_driver_unregister(&tegra_kbc_driver);
716 module_exit(tegra_kbc_exit);
718 static int __init tegra_kbc_init(void)
720 return platform_driver_register(&tegra_kbc_driver);
722 module_init(tegra_kbc_init);
724 MODULE_LICENSE("GPL");
725 MODULE_AUTHOR("Rakesh Iyer <riyer@nvidia.com>");
726 MODULE_DESCRIPTION("Tegra matrix keyboard controller driver");
727 MODULE_ALIAS("platform:tegra-kbc");