drivers/infiniband/hw/nes/nes_hw.h

   1 /*
   2 * Copyright (c) 2006 - 2009 Intel Corporation.  All rights reserved.
   3 *
   4 * This software is available to you under a choice of one of two
   5 * licenses.  You may choose to be licensed under the terms of the GNU
   6 * General Public License (GPL) Version 2, available from the file
   7 * COPYING in the main directory of this source tree, or the
   8 * OpenIB.org BSD license below:
   9 *
  10 *     Redistribution and use in source and binary forms, with or
  11 *     without modification, are permitted provided that the following
  12 *     conditions are met:
  13 *
  14 *      - Redistributions of source code must retain the above
  15 *        copyright notice, this list of conditions and the following
  16 *        disclaimer.
  17 *
  18 *      - Redistributions in binary form must reproduce the above
  19 *        copyright notice, this list of conditions and the following
  20 *        disclaimer in the documentation and/or other materials
  21 *        provided with the distribution.
  22 *
  23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30 * SOFTWARE.
  31 */
  32
  33 #ifndef __NES_HW_H
  34 #define __NES_HW_H
  35
  36 #include <linux/inet_lro.h>
  37
  38 #define NES_PHY_TYPE_CX4       1
  39 #define NES_PHY_TYPE_1G        2
  40 #define NES_PHY_TYPE_ARGUS     4
  41 #define NES_PHY_TYPE_PUMA_1G   5
  42 #define NES_PHY_TYPE_PUMA_10G  6
  43 #define NES_PHY_TYPE_GLADIUS   7
  44 #define NES_PHY_TYPE_SFP_D     8
  45 #define NES_PHY_TYPE_KR        9
  46
  47 #define NES_MULTICAST_PF_MAX 8
  48
  49 enum pci_regs {
  50         NES_INT_STAT = 0x0000,
  51         NES_INT_MASK = 0x0004,
  52         NES_INT_PENDING = 0x0008,
  53         NES_INTF_INT_STAT = 0x000C,
  54         NES_INTF_INT_MASK = 0x0010,
  55         NES_TIMER_STAT = 0x0014,
  56         NES_PERIODIC_CONTROL = 0x0018,
  57         NES_ONE_SHOT_CONTROL = 0x001C,
  58         NES_EEPROM_COMMAND = 0x0020,
  59         NES_EEPROM_DATA = 0x0024,
  60         NES_FLASH_COMMAND = 0x0028,
  61         NES_FLASH_DATA  = 0x002C,
  62         NES_SOFTWARE_RESET = 0x0030,
  63         NES_CQ_ACK = 0x0034,
  64         NES_WQE_ALLOC = 0x0040,
  65         NES_CQE_ALLOC = 0x0044,
  66         NES_AEQ_ALLOC = 0x0048
  67 };
  68
  69 enum indexed_regs {
  70         NES_IDX_CREATE_CQP_LOW = 0x0000,
  71         NES_IDX_CREATE_CQP_HIGH = 0x0004,
  72         NES_IDX_QP_CONTROL = 0x0040,
  73         NES_IDX_FLM_CONTROL = 0x0080,
  74         NES_IDX_INT_CPU_STATUS = 0x00a0,
  75         NES_IDX_GPIO_CONTROL = 0x00f0,
  76         NES_IDX_GPIO_DATA = 0x00f4,
  77         NES_IDX_TCP_CONFIG0 = 0x01e4,
  78         NES_IDX_TCP_TIMER_CONFIG = 0x01ec,
  79         NES_IDX_TCP_NOW = 0x01f0,
  80         NES_IDX_QP_MAX_CFG_SIZES = 0x0200,
  81         NES_IDX_QP_CTX_SIZE = 0x0218,
  82         NES_IDX_TCP_TIMER_SIZE0 = 0x0238,
  83         NES_IDX_TCP_TIMER_SIZE1 = 0x0240,
  84         NES_IDX_ARP_CACHE_SIZE = 0x0258,
  85         NES_IDX_CQ_CTX_SIZE = 0x0260,
  86         NES_IDX_MRT_SIZE = 0x0278,
  87         NES_IDX_PBL_REGION_SIZE = 0x0280,
  88         NES_IDX_IRRQ_COUNT = 0x02b0,
  89         NES_IDX_RX_WINDOW_BUFFER_PAGE_TABLE_SIZE = 0x02f0,
  90         NES_IDX_RX_WINDOW_BUFFER_SIZE = 0x0300,
  91         NES_IDX_DST_IP_ADDR = 0x0400,
  92         NES_IDX_PCIX_DIAG = 0x08e8,
  93         NES_IDX_MPP_DEBUG = 0x0a00,
  94         NES_IDX_PORT_RX_DISCARDS = 0x0a30,
  95         NES_IDX_PORT_TX_DISCARDS = 0x0a34,
  96         NES_IDX_MPP_LB_DEBUG = 0x0b00,
  97         NES_IDX_DENALI_CTL_22 = 0x1058,
  98         NES_IDX_MAC_TX_CONTROL = 0x2000,
  99         NES_IDX_MAC_TX_CONFIG = 0x2004,
 100         NES_IDX_MAC_TX_PAUSE_QUANTA = 0x2008,
 101         NES_IDX_MAC_RX_CONTROL = 0x200c,
 102         NES_IDX_MAC_RX_CONFIG = 0x2010,
 103         NES_IDX_MAC_EXACT_MATCH_BOTTOM = 0x201c,
 104         NES_IDX_MAC_MDIO_CONTROL = 0x2084,
 105         NES_IDX_MAC_TX_OCTETS_LOW = 0x2100,
 106         NES_IDX_MAC_TX_OCTETS_HIGH = 0x2104,
 107         NES_IDX_MAC_TX_FRAMES_LOW = 0x2108,
 108         NES_IDX_MAC_TX_FRAMES_HIGH = 0x210c,
 109         NES_IDX_MAC_TX_PAUSE_FRAMES = 0x2118,
 110         NES_IDX_MAC_TX_ERRORS = 0x2138,
 111         NES_IDX_MAC_RX_OCTETS_LOW = 0x213c,
 112         NES_IDX_MAC_RX_OCTETS_HIGH = 0x2140,
 113         NES_IDX_MAC_RX_FRAMES_LOW = 0x2144,
 114         NES_IDX_MAC_RX_FRAMES_HIGH = 0x2148,
 115         NES_IDX_MAC_RX_BC_FRAMES_LOW = 0x214c,
 116         NES_IDX_MAC_RX_MC_FRAMES_HIGH = 0x2150,
 117         NES_IDX_MAC_RX_PAUSE_FRAMES = 0x2154,
 118         NES_IDX_MAC_RX_SHORT_FRAMES = 0x2174,
 119         NES_IDX_MAC_RX_OVERSIZED_FRAMES = 0x2178,
 120         NES_IDX_MAC_RX_JABBER_FRAMES = 0x217c,
 121         NES_IDX_MAC_RX_CRC_ERR_FRAMES = 0x2180,
 122         NES_IDX_MAC_RX_LENGTH_ERR_FRAMES = 0x2184,
 123         NES_IDX_MAC_RX_SYMBOL_ERR_FRAMES = 0x2188,
 124         NES_IDX_MAC_INT_STATUS = 0x21f0,
 125         NES_IDX_MAC_INT_MASK = 0x21f4,
 126         NES_IDX_PHY_PCS_CONTROL_STATUS0 = 0x2800,
 127         NES_IDX_PHY_PCS_CONTROL_STATUS1 = 0x2a00,
 128         NES_IDX_ETH_SERDES_COMMON_CONTROL0 = 0x2808,
 129         NES_IDX_ETH_SERDES_COMMON_CONTROL1 = 0x2a08,
 130         NES_IDX_ETH_SERDES_COMMON_STATUS0 = 0x280c,
 131         NES_IDX_ETH_SERDES_COMMON_STATUS1 = 0x2a0c,
 132         NES_IDX_ETH_SERDES_TX_EMP0 = 0x2810,
 133         NES_IDX_ETH_SERDES_TX_EMP1 = 0x2a10,
 134         NES_IDX_ETH_SERDES_TX_DRIVE0 = 0x2814,
 135         NES_IDX_ETH_SERDES_TX_DRIVE1 = 0x2a14,
 136         NES_IDX_ETH_SERDES_RX_MODE0 = 0x2818,
 137         NES_IDX_ETH_SERDES_RX_MODE1 = 0x2a18,
 138         NES_IDX_ETH_SERDES_RX_SIGDET0 = 0x281c,
 139         NES_IDX_ETH_SERDES_RX_SIGDET1 = 0x2a1c,
 140         NES_IDX_ETH_SERDES_BYPASS0 = 0x2820,
 141         NES_IDX_ETH_SERDES_BYPASS1 = 0x2a20,
 142         NES_IDX_ETH_SERDES_LOOPBACK_CONTROL0 = 0x2824,
 143         NES_IDX_ETH_SERDES_LOOPBACK_CONTROL1 = 0x2a24,
 144         NES_IDX_ETH_SERDES_RX_EQ_CONTROL0 = 0x2828,
 145         NES_IDX_ETH_SERDES_RX_EQ_CONTROL1 = 0x2a28,
 146         NES_IDX_ETH_SERDES_RX_EQ_STATUS0 = 0x282c,
 147         NES_IDX_ETH_SERDES_RX_EQ_STATUS1 = 0x2a2c,
 148         NES_IDX_ETH_SERDES_CDR_RESET0 = 0x2830,
 149         NES_IDX_ETH_SERDES_CDR_RESET1 = 0x2a30,
 150         NES_IDX_ETH_SERDES_CDR_CONTROL0 = 0x2834,
 151         NES_IDX_ETH_SERDES_CDR_CONTROL1 = 0x2a34,
 152         NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE0 = 0x2838,
 153         NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE1 = 0x2a38,
 154         NES_IDX_ENDNODE0_NSTAT_RX_DISCARD = 0x3080,
 155         NES_IDX_ENDNODE0_NSTAT_RX_OCTETS_LO = 0x3000,
 156         NES_IDX_ENDNODE0_NSTAT_RX_OCTETS_HI = 0x3004,
 157         NES_IDX_ENDNODE0_NSTAT_RX_FRAMES_LO = 0x3008,
 158         NES_IDX_ENDNODE0_NSTAT_RX_FRAMES_HI = 0x300c,
 159         NES_IDX_ENDNODE0_NSTAT_TX_OCTETS_LO = 0x7000,
 160         NES_IDX_ENDNODE0_NSTAT_TX_OCTETS_HI = 0x7004,
 161         NES_IDX_ENDNODE0_NSTAT_TX_FRAMES_LO = 0x7008,
 162         NES_IDX_ENDNODE0_NSTAT_TX_FRAMES_HI = 0x700c,
 163         NES_IDX_WQM_CONFIG0 = 0x5000,
 164         NES_IDX_WQM_CONFIG1 = 0x5004,
 165         NES_IDX_CM_CONFIG = 0x5100,
 166         NES_IDX_NIC_LOGPORT_TO_PHYPORT = 0x6000,
 167         NES_IDX_NIC_PHYPORT_TO_USW = 0x6008,
 168         NES_IDX_NIC_ACTIVE = 0x6010,
 169         NES_IDX_NIC_UNICAST_ALL = 0x6018,
 170         NES_IDX_NIC_MULTICAST_ALL = 0x6020,
 171         NES_IDX_NIC_MULTICAST_ENABLE = 0x6028,
 172         NES_IDX_NIC_BROADCAST_ON = 0x6030,
 173         NES_IDX_USED_CHUNKS_TX = 0x60b0,
 174         NES_IDX_TX_POOL_SIZE = 0x60b8,
 175         NES_IDX_QUAD_HASH_TABLE_SIZE = 0x6148,
 176         NES_IDX_PERFECT_FILTER_LOW = 0x6200,
 177         NES_IDX_PERFECT_FILTER_HIGH = 0x6204,
 178         NES_IDX_IPV4_TCP_REXMITS = 0x7080,
 179         NES_IDX_DEBUG_ERROR_CONTROL_STATUS = 0x913c,
 180         NES_IDX_DEBUG_ERROR_MASKS0 = 0x9140,
 181         NES_IDX_DEBUG_ERROR_MASKS1 = 0x9144,
 182         NES_IDX_DEBUG_ERROR_MASKS2 = 0x9148,
 183         NES_IDX_DEBUG_ERROR_MASKS3 = 0x914c,
 184         NES_IDX_DEBUG_ERROR_MASKS4 = 0x9150,
 185         NES_IDX_DEBUG_ERROR_MASKS5 = 0x9154,
 186 };
 187
 188 #define NES_IDX_MAC_TX_CONFIG_ENABLE_PAUSE   1
 189 #define NES_IDX_MPP_DEBUG_PORT_DISABLE_PAUSE (1 << 17)
 190
 191 enum nes_cqp_opcodes {
 192         NES_CQP_CREATE_QP = 0x00,
 193         NES_CQP_MODIFY_QP = 0x01,
 194         NES_CQP_DESTROY_QP = 0x02,
 195         NES_CQP_CREATE_CQ = 0x03,
 196         NES_CQP_MODIFY_CQ = 0x04,
 197         NES_CQP_DESTROY_CQ = 0x05,
 198         NES_CQP_ALLOCATE_STAG = 0x09,
 199         NES_CQP_REGISTER_STAG = 0x0a,
 200         NES_CQP_QUERY_STAG = 0x0b,
 201         NES_CQP_REGISTER_SHARED_STAG = 0x0c,
 202         NES_CQP_DEALLOCATE_STAG = 0x0d,
 203         NES_CQP_MANAGE_ARP_CACHE = 0x0f,
 204         NES_CQP_SUSPEND_QPS = 0x11,
 205         NES_CQP_UPLOAD_CONTEXT = 0x13,
 206         NES_CQP_CREATE_CEQ = 0x16,
 207         NES_CQP_DESTROY_CEQ = 0x18,
 208         NES_CQP_CREATE_AEQ = 0x19,
 209         NES_CQP_DESTROY_AEQ = 0x1b,
 210         NES_CQP_LMI_ACCESS = 0x20,
 211         NES_CQP_FLUSH_WQES = 0x22,
 212         NES_CQP_MANAGE_APBVT = 0x23
 213 };
 214
 215 enum nes_cqp_wqe_word_idx {
 216         NES_CQP_WQE_OPCODE_IDX = 0,
 217         NES_CQP_WQE_ID_IDX = 1,
 218         NES_CQP_WQE_COMP_CTX_LOW_IDX = 2,
 219         NES_CQP_WQE_COMP_CTX_HIGH_IDX = 3,
 220         NES_CQP_WQE_COMP_SCRATCH_LOW_IDX = 4,
 221         NES_CQP_WQE_COMP_SCRATCH_HIGH_IDX = 5,
 222 };
 223
 224 enum nes_cqp_cq_wqeword_idx {
 225         NES_CQP_CQ_WQE_PBL_LOW_IDX = 6,
 226         NES_CQP_CQ_WQE_PBL_HIGH_IDX = 7,
 227         NES_CQP_CQ_WQE_CQ_CONTEXT_LOW_IDX = 8,
 228         NES_CQP_CQ_WQE_CQ_CONTEXT_HIGH_IDX = 9,
 229         NES_CQP_CQ_WQE_DOORBELL_INDEX_HIGH_IDX = 10,
 230 };
 231
 232 enum nes_cqp_stag_wqeword_idx {
 233         NES_CQP_STAG_WQE_PBL_BLK_COUNT_IDX = 1,
 234         NES_CQP_STAG_WQE_LEN_HIGH_PD_IDX = 6,
 235         NES_CQP_STAG_WQE_LEN_LOW_IDX = 7,
 236         NES_CQP_STAG_WQE_STAG_IDX = 8,
 237         NES_CQP_STAG_WQE_VA_LOW_IDX = 10,
 238         NES_CQP_STAG_WQE_VA_HIGH_IDX = 11,
 239         NES_CQP_STAG_WQE_PA_LOW_IDX = 12,
 240         NES_CQP_STAG_WQE_PA_HIGH_IDX = 13,
 241         NES_CQP_STAG_WQE_PBL_LEN_IDX = 14
 242 };
 243
 244 #define NES_CQP_OP_IWARP_STATE_SHIFT 28
 245 #define NES_CQP_OP_TERMLEN_SHIFT     28
 246
 247 enum nes_cqp_qp_bits {
 248         NES_CQP_QP_ARP_VALID = (1<<8),
 249         NES_CQP_QP_WINBUF_VALID = (1<<9),
 250         NES_CQP_QP_CONTEXT_VALID = (1<<10),
 251         NES_CQP_QP_ORD_VALID = (1<<11),
 252         NES_CQP_QP_WINBUF_DATAIND_EN = (1<<12),
 253         NES_CQP_QP_VIRT_WQS = (1<<13),
 254         NES_CQP_QP_DEL_HTE = (1<<14),
 255         NES_CQP_QP_CQS_VALID = (1<<15),
 256         NES_CQP_QP_TYPE_TSA = 0,
 257         NES_CQP_QP_TYPE_IWARP = (1<<16),
 258         NES_CQP_QP_TYPE_CQP = (4<<16),
 259         NES_CQP_QP_TYPE_NIC = (5<<16),
 260         NES_CQP_QP_MSS_CHG = (1<<20),
 261         NES_CQP_QP_STATIC_RESOURCES = (1<<21),
 262         NES_CQP_QP_IGNORE_MW_BOUND = (1<<22),
 263         NES_CQP_QP_VWQ_USE_LMI = (1<<23),
 264         NES_CQP_QP_IWARP_STATE_IDLE = (1<<NES_CQP_OP_IWARP_STATE_SHIFT),
 265         NES_CQP_QP_IWARP_STATE_RTS = (2<<NES_CQP_OP_IWARP_STATE_SHIFT),
 266         NES_CQP_QP_IWARP_STATE_CLOSING = (3<<NES_CQP_OP_IWARP_STATE_SHIFT),
 267         NES_CQP_QP_IWARP_STATE_TERMINATE = (5<<NES_CQP_OP_IWARP_STATE_SHIFT),
 268         NES_CQP_QP_IWARP_STATE_ERROR = (6<<NES_CQP_OP_IWARP_STATE_SHIFT),
 269         NES_CQP_QP_IWARP_STATE_MASK = (7<<NES_CQP_OP_IWARP_STATE_SHIFT),
 270         NES_CQP_QP_TERM_DONT_SEND_FIN = (1<<24),
 271         NES_CQP_QP_TERM_DONT_SEND_TERM_MSG = (1<<25),
 272         NES_CQP_QP_RESET = (1<<31),
 273 };
 274
 275 enum nes_cqp_qp_wqe_word_idx {
 276         NES_CQP_QP_WQE_CONTEXT_LOW_IDX = 6,
 277         NES_CQP_QP_WQE_CONTEXT_HIGH_IDX = 7,
 278         NES_CQP_QP_WQE_FLUSH_SQ_CODE = 8,
 279         NES_CQP_QP_WQE_FLUSH_RQ_CODE = 9,
 280         NES_CQP_QP_WQE_NEW_MSS_IDX = 15,
 281 };
 282
 283 enum nes_nic_ctx_bits {
 284         NES_NIC_CTX_RQ_SIZE_32 = (3<<8),
 285         NES_NIC_CTX_RQ_SIZE_512 = (3<<8),
 286         NES_NIC_CTX_SQ_SIZE_32 = (1<<10),
 287         NES_NIC_CTX_SQ_SIZE_512 = (3<<10),
 288 };
 289
 290 enum nes_nic_qp_ctx_word_idx {
 291         NES_NIC_CTX_MISC_IDX = 0,
 292         NES_NIC_CTX_SQ_LOW_IDX = 2,
 293         NES_NIC_CTX_SQ_HIGH_IDX = 3,
 294         NES_NIC_CTX_RQ_LOW_IDX = 4,
 295         NES_NIC_CTX_RQ_HIGH_IDX = 5,
 296 };
 297
 298 enum nes_cqp_cq_bits {
 299         NES_CQP_CQ_CEQE_MASK = (1<<9),
 300         NES_CQP_CQ_CEQ_VALID = (1<<10),
 301         NES_CQP_CQ_RESIZE = (1<<11),
 302         NES_CQP_CQ_CHK_OVERFLOW = (1<<12),
 303         NES_CQP_CQ_4KB_CHUNK = (1<<14),
 304         NES_CQP_CQ_VIRT = (1<<15),
 305 };
 306
 307 enum nes_cqp_stag_bits {
 308         NES_CQP_STAG_VA_TO = (1<<9),
 309         NES_CQP_STAG_DEALLOC_PBLS = (1<<10),
 310         NES_CQP_STAG_PBL_BLK_SIZE = (1<<11),
 311         NES_CQP_STAG_MR = (1<<13),
 312         NES_CQP_STAG_RIGHTS_LOCAL_READ = (1<<16),
 313         NES_CQP_STAG_RIGHTS_LOCAL_WRITE = (1<<17),
 314         NES_CQP_STAG_RIGHTS_REMOTE_READ = (1<<18),
 315         NES_CQP_STAG_RIGHTS_REMOTE_WRITE = (1<<19),
 316         NES_CQP_STAG_RIGHTS_WINDOW_BIND = (1<<20),
 317         NES_CQP_STAG_REM_ACC_EN = (1<<21),
 318         NES_CQP_STAG_LEAVE_PENDING = (1<<31),
 319 };
 320
 321 enum nes_cqp_ceq_wqeword_idx {
 322         NES_CQP_CEQ_WQE_ELEMENT_COUNT_IDX = 1,
 323         NES_CQP_CEQ_WQE_PBL_LOW_IDX = 6,
 324         NES_CQP_CEQ_WQE_PBL_HIGH_IDX = 7,
 325 };
 326
 327 enum nes_cqp_ceq_bits {
 328         NES_CQP_CEQ_4KB_CHUNK = (1<<14),
 329         NES_CQP_CEQ_VIRT = (1<<15),
 330 };
 331
 332 enum nes_cqp_aeq_wqeword_idx {
 333         NES_CQP_AEQ_WQE_ELEMENT_COUNT_IDX = 1,
 334         NES_CQP_AEQ_WQE_PBL_LOW_IDX = 6,
 335         NES_CQP_AEQ_WQE_PBL_HIGH_IDX = 7,
 336 };
 337
 338 enum nes_cqp_aeq_bits {
 339         NES_CQP_AEQ_4KB_CHUNK = (1<<14),
 340         NES_CQP_AEQ_VIRT = (1<<15),
 341 };
 342
 343 enum nes_cqp_lmi_wqeword_idx {
 344         NES_CQP_LMI_WQE_LMI_OFFSET_IDX = 1,
 345         NES_CQP_LMI_WQE_FRAG_LOW_IDX = 8,
 346         NES_CQP_LMI_WQE_FRAG_HIGH_IDX = 9,
 347         NES_CQP_LMI_WQE_FRAG_LEN_IDX = 10,
 348 };
 349
 350 enum nes_cqp_arp_wqeword_idx {
 351         NES_CQP_ARP_WQE_MAC_ADDR_LOW_IDX = 6,
 352         NES_CQP_ARP_WQE_MAC_HIGH_IDX = 7,
 353         NES_CQP_ARP_WQE_REACHABILITY_MAX_IDX = 1,
 354 };
 355
 356 enum nes_cqp_upload_wqeword_idx {
 357         NES_CQP_UPLOAD_WQE_CTXT_LOW_IDX = 6,
 358         NES_CQP_UPLOAD_WQE_CTXT_HIGH_IDX = 7,
 359         NES_CQP_UPLOAD_WQE_HTE_IDX = 8,
 360 };
 361
 362 enum nes_cqp_arp_bits {
 363         NES_CQP_ARP_VALID = (1<<8),
 364         NES_CQP_ARP_PERM = (1<<9),
 365 };
 366
 367 enum nes_cqp_flush_bits {
 368         NES_CQP_FLUSH_SQ = (1<<30),
 369         NES_CQP_FLUSH_RQ = (1<<31),
 370         NES_CQP_FLUSH_MAJ_MIN = (1<<28),
 371 };
 372
 373 enum nes_cqe_opcode_bits {
 374         NES_CQE_STAG_VALID = (1<<6),
 375         NES_CQE_ERROR = (1<<7),
 376         NES_CQE_SQ = (1<<8),
 377         NES_CQE_SE = (1<<9),
 378         NES_CQE_PSH = (1<<29),
 379         NES_CQE_FIN = (1<<30),
 380         NES_CQE_VALID = (1<<31),
 381 };
 382
 383
 384 enum nes_cqe_word_idx {
 385         NES_CQE_PAYLOAD_LENGTH_IDX = 0,
 386         NES_CQE_COMP_COMP_CTX_LOW_IDX = 2,
 387         NES_CQE_COMP_COMP_CTX_HIGH_IDX = 3,
 388         NES_CQE_INV_STAG_IDX = 4,
 389         NES_CQE_QP_ID_IDX = 5,
 390         NES_CQE_ERROR_CODE_IDX = 6,
 391         NES_CQE_OPCODE_IDX = 7,
 392 };
 393
 394 enum nes_ceqe_word_idx {
 395         NES_CEQE_CQ_CTX_LOW_IDX = 0,
 396         NES_CEQE_CQ_CTX_HIGH_IDX = 1,
 397 };
 398
 399 enum nes_ceqe_status_bit {
 400         NES_CEQE_VALID = (1<<31),
 401 };
 402
 403 enum nes_int_bits {
 404         NES_INT_CEQ0 = (1<<0),
 405         NES_INT_CEQ1 = (1<<1),
 406         NES_INT_CEQ2 = (1<<2),
 407         NES_INT_CEQ3 = (1<<3),
 408         NES_INT_CEQ4 = (1<<4),
 409         NES_INT_CEQ5 = (1<<5),
 410         NES_INT_CEQ6 = (1<<6),
 411         NES_INT_CEQ7 = (1<<7),
 412         NES_INT_CEQ8 = (1<<8),
 413         NES_INT_CEQ9 = (1<<9),
 414         NES_INT_CEQ10 = (1<<10),
 415         NES_INT_CEQ11 = (1<<11),
 416         NES_INT_CEQ12 = (1<<12),
 417         NES_INT_CEQ13 = (1<<13),
 418         NES_INT_CEQ14 = (1<<14),
 419         NES_INT_CEQ15 = (1<<15),
 420         NES_INT_AEQ0 = (1<<16),
 421         NES_INT_AEQ1 = (1<<17),
 422         NES_INT_AEQ2 = (1<<18),
 423         NES_INT_AEQ3 = (1<<19),
 424         NES_INT_AEQ4 = (1<<20),
 425         NES_INT_AEQ5 = (1<<21),
 426         NES_INT_AEQ6 = (1<<22),
 427         NES_INT_AEQ7 = (1<<23),
 428         NES_INT_MAC0 = (1<<24),
 429         NES_INT_MAC1 = (1<<25),
 430         NES_INT_MAC2 = (1<<26),
 431         NES_INT_MAC3 = (1<<27),
 432         NES_INT_TSW = (1<<28),
 433         NES_INT_TIMER = (1<<29),
 434         NES_INT_INTF = (1<<30),
 435 };
 436
 437 enum nes_intf_int_bits {
 438         NES_INTF_INT_PCIERR = (1<<0),
 439         NES_INTF_PERIODIC_TIMER = (1<<2),
 440         NES_INTF_ONE_SHOT_TIMER = (1<<3),
 441         NES_INTF_INT_CRITERR = (1<<14),
 442         NES_INTF_INT_AEQ0_OFLOW = (1<<16),
 443         NES_INTF_INT_AEQ1_OFLOW = (1<<17),
 444         NES_INTF_INT_AEQ2_OFLOW = (1<<18),
 445         NES_INTF_INT_AEQ3_OFLOW = (1<<19),
 446         NES_INTF_INT_AEQ4_OFLOW = (1<<20),
 447         NES_INTF_INT_AEQ5_OFLOW = (1<<21),
 448         NES_INTF_INT_AEQ6_OFLOW = (1<<22),
 449         NES_INTF_INT_AEQ7_OFLOW = (1<<23),
 450         NES_INTF_INT_AEQ_OFLOW = (0xff<<16),
 451 };
 452
 453 enum nes_mac_int_bits {
 454         NES_MAC_INT_LINK_STAT_CHG = (1<<1),
 455         NES_MAC_INT_XGMII_EXT = (1<<2),
 456         NES_MAC_INT_TX_UNDERFLOW = (1<<6),
 457         NES_MAC_INT_TX_ERROR = (1<<7),
 458 };
 459
 460 enum nes_cqe_allocate_bits {
 461         NES_CQE_ALLOC_INC_SELECT = (1<<28),
 462         NES_CQE_ALLOC_NOTIFY_NEXT = (1<<29),
 463         NES_CQE_ALLOC_NOTIFY_SE = (1<<30),
 464         NES_CQE_ALLOC_RESET = (1<<31),
 465 };
 466
 467 enum nes_nic_rq_wqe_word_idx {
 468         NES_NIC_RQ_WQE_LENGTH_1_0_IDX = 0,
 469         NES_NIC_RQ_WQE_LENGTH_3_2_IDX = 1,
 470         NES_NIC_RQ_WQE_FRAG0_LOW_IDX = 2,
 471         NES_NIC_RQ_WQE_FRAG0_HIGH_IDX = 3,
 472         NES_NIC_RQ_WQE_FRAG1_LOW_IDX = 4,
 473         NES_NIC_RQ_WQE_FRAG1_HIGH_IDX = 5,
 474         NES_NIC_RQ_WQE_FRAG2_LOW_IDX = 6,
 475         NES_NIC_RQ_WQE_FRAG2_HIGH_IDX = 7,
 476         NES_NIC_RQ_WQE_FRAG3_LOW_IDX = 8,
 477         NES_NIC_RQ_WQE_FRAG3_HIGH_IDX = 9,
 478 };
 479
 480 enum nes_nic_sq_wqe_word_idx {
 481         NES_NIC_SQ_WQE_MISC_IDX = 0,
 482         NES_NIC_SQ_WQE_TOTAL_LENGTH_IDX = 1,
 483         NES_NIC_SQ_WQE_LSO_INFO_IDX = 2,
 484         NES_NIC_SQ_WQE_LENGTH_0_TAG_IDX = 3,
 485         NES_NIC_SQ_WQE_LENGTH_2_1_IDX = 4,
 486         NES_NIC_SQ_WQE_LENGTH_4_3_IDX = 5,
 487         NES_NIC_SQ_WQE_FRAG0_LOW_IDX = 6,
 488         NES_NIC_SQ_WQE_FRAG0_HIGH_IDX = 7,
 489         NES_NIC_SQ_WQE_FRAG1_LOW_IDX = 8,
 490         NES_NIC_SQ_WQE_FRAG1_HIGH_IDX = 9,
 491         NES_NIC_SQ_WQE_FRAG2_LOW_IDX = 10,
 492         NES_NIC_SQ_WQE_FRAG2_HIGH_IDX = 11,
 493         NES_NIC_SQ_WQE_FRAG3_LOW_IDX = 12,
 494         NES_NIC_SQ_WQE_FRAG3_HIGH_IDX = 13,
 495         NES_NIC_SQ_WQE_FRAG4_LOW_IDX = 14,
 496         NES_NIC_SQ_WQE_FRAG4_HIGH_IDX = 15,
 497 };
 498
 499 enum nes_iwarp_sq_wqe_word_idx {
 500         NES_IWARP_SQ_WQE_MISC_IDX = 0,
 501         NES_IWARP_SQ_WQE_TOTAL_PAYLOAD_IDX = 1,
 502         NES_IWARP_SQ_WQE_COMP_CTX_LOW_IDX = 2,
 503         NES_IWARP_SQ_WQE_COMP_CTX_HIGH_IDX = 3,
 504         NES_IWARP_SQ_WQE_COMP_SCRATCH_LOW_IDX = 4,
 505         NES_IWARP_SQ_WQE_COMP_SCRATCH_HIGH_IDX = 5,
 506         NES_IWARP_SQ_WQE_INV_STAG_LOW_IDX = 7,
 507         NES_IWARP_SQ_WQE_RDMA_TO_LOW_IDX = 8,
 508         NES_IWARP_SQ_WQE_RDMA_TO_HIGH_IDX = 9,
 509         NES_IWARP_SQ_WQE_RDMA_LENGTH_IDX = 10,
 510         NES_IWARP_SQ_WQE_RDMA_STAG_IDX = 11,
 511         NES_IWARP_SQ_WQE_IMM_DATA_START_IDX = 12,
 512         NES_IWARP_SQ_WQE_FRAG0_LOW_IDX = 16,
 513         NES_IWARP_SQ_WQE_FRAG0_HIGH_IDX = 17,
 514         NES_IWARP_SQ_WQE_LENGTH0_IDX = 18,
 515         NES_IWARP_SQ_WQE_STAG0_IDX = 19,
 516         NES_IWARP_SQ_WQE_FRAG1_LOW_IDX = 20,
 517         NES_IWARP_SQ_WQE_FRAG1_HIGH_IDX = 21,
 518         NES_IWARP_SQ_WQE_LENGTH1_IDX = 22,
 519         NES_IWARP_SQ_WQE_STAG1_IDX = 23,
 520         NES_IWARP_SQ_WQE_FRAG2_LOW_IDX = 24,
 521         NES_IWARP_SQ_WQE_FRAG2_HIGH_IDX = 25,
 522         NES_IWARP_SQ_WQE_LENGTH2_IDX = 26,
 523         NES_IWARP_SQ_WQE_STAG2_IDX = 27,
 524         NES_IWARP_SQ_WQE_FRAG3_LOW_IDX = 28,
 525         NES_IWARP_SQ_WQE_FRAG3_HIGH_IDX = 29,
 526         NES_IWARP_SQ_WQE_LENGTH3_IDX = 30,
 527         NES_IWARP_SQ_WQE_STAG3_IDX = 31,
 528 };
 529
 530 enum nes_iwarp_sq_bind_wqe_word_idx {
 531         NES_IWARP_SQ_BIND_WQE_MR_IDX = 6,
 532         NES_IWARP_SQ_BIND_WQE_MW_IDX = 7,
 533         NES_IWARP_SQ_BIND_WQE_LENGTH_LOW_IDX = 8,
 534         NES_IWARP_SQ_BIND_WQE_LENGTH_HIGH_IDX = 9,
 535         NES_IWARP_SQ_BIND_WQE_VA_FBO_LOW_IDX = 10,
 536         NES_IWARP_SQ_BIND_WQE_VA_FBO_HIGH_IDX = 11,
 537 };
 538
 539 enum nes_iwarp_sq_fmr_wqe_word_idx {
 540         NES_IWARP_SQ_FMR_WQE_MR_STAG_IDX = 7,
 541         NES_IWARP_SQ_FMR_WQE_LENGTH_LOW_IDX = 8,
 542         NES_IWARP_SQ_FMR_WQE_LENGTH_HIGH_IDX = 9,
 543         NES_IWARP_SQ_FMR_WQE_VA_FBO_LOW_IDX = 10,
 544         NES_IWARP_SQ_FMR_WQE_VA_FBO_HIGH_IDX = 11,
 545         NES_IWARP_SQ_FMR_WQE_PBL_ADDR_LOW_IDX = 12,
 546         NES_IWARP_SQ_FMR_WQE_PBL_ADDR_HIGH_IDX = 13,
 547         NES_IWARP_SQ_FMR_WQE_PBL_LENGTH_IDX = 14,
 548 };
 549
 550 enum nes_iwarp_sq_fmr_opcodes {
 551         NES_IWARP_SQ_FMR_WQE_ZERO_BASED                 = (1<<6),
 552         NES_IWARP_SQ_FMR_WQE_PAGE_SIZE_4K               = (0<<7),
 553         NES_IWARP_SQ_FMR_WQE_PAGE_SIZE_2M               = (1<<7),
 554         NES_IWARP_SQ_FMR_WQE_RIGHTS_ENABLE_LOCAL_READ   = (1<<16),
 555         NES_IWARP_SQ_FMR_WQE_RIGHTS_ENABLE_LOCAL_WRITE  = (1<<17),
 556         NES_IWARP_SQ_FMR_WQE_RIGHTS_ENABLE_REMOTE_READ  = (1<<18),
 557         NES_IWARP_SQ_FMR_WQE_RIGHTS_ENABLE_REMOTE_WRITE = (1<<19),
 558         NES_IWARP_SQ_FMR_WQE_RIGHTS_ENABLE_WINDOW_BIND  = (1<<20),
 559 };
 560
 561 #define NES_IWARP_SQ_FMR_WQE_MR_LENGTH_HIGH_MASK        0xFF;
 562
 563 enum nes_iwarp_sq_locinv_wqe_word_idx {
 564         NES_IWARP_SQ_LOCINV_WQE_INV_STAG_IDX = 6,
 565 };
 566
 567 enum nes_iwarp_rq_wqe_word_idx {
 568         NES_IWARP_RQ_WQE_TOTAL_PAYLOAD_IDX = 1,
 569         NES_IWARP_RQ_WQE_COMP_CTX_LOW_IDX = 2,
 570         NES_IWARP_RQ_WQE_COMP_CTX_HIGH_IDX = 3,
 571         NES_IWARP_RQ_WQE_COMP_SCRATCH_LOW_IDX = 4,
 572         NES_IWARP_RQ_WQE_COMP_SCRATCH_HIGH_IDX = 5,
 573         NES_IWARP_RQ_WQE_FRAG0_LOW_IDX = 8,
 574         NES_IWARP_RQ_WQE_FRAG0_HIGH_IDX = 9,
 575         NES_IWARP_RQ_WQE_LENGTH0_IDX = 10,
 576         NES_IWARP_RQ_WQE_STAG0_IDX = 11,
 577         NES_IWARP_RQ_WQE_FRAG1_LOW_IDX = 12,
 578         NES_IWARP_RQ_WQE_FRAG1_HIGH_IDX = 13,
 579         NES_IWARP_RQ_WQE_LENGTH1_IDX = 14,
 580         NES_IWARP_RQ_WQE_STAG1_IDX = 15,
 581         NES_IWARP_RQ_WQE_FRAG2_LOW_IDX = 16,
 582         NES_IWARP_RQ_WQE_FRAG2_HIGH_IDX = 17,
 583         NES_IWARP_RQ_WQE_LENGTH2_IDX = 18,
 584         NES_IWARP_RQ_WQE_STAG2_IDX = 19,
 585         NES_IWARP_RQ_WQE_FRAG3_LOW_IDX = 20,
 586         NES_IWARP_RQ_WQE_FRAG3_HIGH_IDX = 21,
 587         NES_IWARP_RQ_WQE_LENGTH3_IDX = 22,
 588         NES_IWARP_RQ_WQE_STAG3_IDX = 23,
 589 };
 590
 591 enum nes_nic_sq_wqe_bits {
 592         NES_NIC_SQ_WQE_PHDR_CS_READY =  (1<<21),
 593         NES_NIC_SQ_WQE_LSO_ENABLE = (1<<22),
 594         NES_NIC_SQ_WQE_TAGVALUE_ENABLE = (1<<23),
 595         NES_NIC_SQ_WQE_DISABLE_CHKSUM = (1<<30),
 596         NES_NIC_SQ_WQE_COMPLETION = (1<<31),
 597 };
 598
 599 enum nes_nic_cqe_word_idx {
 600         NES_NIC_CQE_ACCQP_ID_IDX = 0,
 601         NES_NIC_CQE_TAG_PKT_TYPE_IDX = 2,
 602         NES_NIC_CQE_MISC_IDX = 3,
 603 };
 604
 605 #define NES_PKT_TYPE_APBVT_BITS 0xC112
 606 #define NES_PKT_TYPE_APBVT_MASK 0xff3e
 607
 608 #define NES_PKT_TYPE_PVALID_BITS 0x10000000
 609 #define NES_PKT_TYPE_PVALID_MASK 0x30000000
 610
 611 #define NES_PKT_TYPE_TCPV4_BITS 0x0110
 612 #define NES_PKT_TYPE_TCPV4_MASK 0x3f30
 613
 614 #define NES_PKT_TYPE_UDPV4_BITS 0x0210
 615 #define NES_PKT_TYPE_UDPV4_MASK 0x3f30
 616
 617 #define NES_PKT_TYPE_IPV4_BITS  0x0010
 618 #define NES_PKT_TYPE_IPV4_MASK  0x3f30
 619
 620 #define NES_PKT_TYPE_OTHER_BITS 0x0000
 621 #define NES_PKT_TYPE_OTHER_MASK 0x0030
 622
 623 #define NES_NIC_CQE_ERRV_SHIFT 16
 624 enum nes_nic_ev_bits {
 625         NES_NIC_ERRV_BITS_MODE = (1<<0),
 626         NES_NIC_ERRV_BITS_IPV4_CSUM_ERR = (1<<1),
 627         NES_NIC_ERRV_BITS_TCPUDP_CSUM_ERR = (1<<2),
 628         NES_NIC_ERRV_BITS_WQE_OVERRUN = (1<<3),
 629         NES_NIC_ERRV_BITS_IPH_ERR = (1<<4),
 630 };
 631
 632 enum nes_nic_cqe_bits {
 633         NES_NIC_CQE_ERRV_MASK = (0xff<<NES_NIC_CQE_ERRV_SHIFT),
 634         NES_NIC_CQE_SQ = (1<<24),
 635         NES_NIC_CQE_ACCQP_PORT = (1<<28),
 636         NES_NIC_CQE_ACCQP_VALID = (1<<29),
 637         NES_NIC_CQE_TAG_VALID = (1<<30),
 638         NES_NIC_CQE_VALID = (1<<31),
 639 };
 640
 641 enum nes_aeqe_word_idx {
 642         NES_AEQE_COMP_CTXT_LOW_IDX = 0,
 643         NES_AEQE_COMP_CTXT_HIGH_IDX = 1,
 644         NES_AEQE_COMP_QP_CQ_ID_IDX = 2,
 645         NES_AEQE_MISC_IDX = 3,
 646 };
 647
 648 enum nes_aeqe_bits {
 649         NES_AEQE_QP = (1<<16),
 650         NES_AEQE_CQ = (1<<17),
 651         NES_AEQE_SQ = (1<<18),
 652         NES_AEQE_INBOUND_RDMA = (1<<19),
 653         NES_AEQE_IWARP_STATE_MASK = (7<<20),
 654         NES_AEQE_TCP_STATE_MASK = (0xf<<24),
 655         NES_AEQE_Q2_DATA_WRITTEN = (0x3<<28),
 656         NES_AEQE_VALID = (1<<31),
 657 };
 658
 659 #define NES_AEQE_IWARP_STATE_SHIFT      20
 660 #define NES_AEQE_TCP_STATE_SHIFT        24
 661 #define NES_AEQE_Q2_DATA_ETHERNET       (1<<28)
 662 #define NES_AEQE_Q2_DATA_MPA            (1<<29)
 663
 664 enum nes_aeqe_iwarp_state {
 665         NES_AEQE_IWARP_STATE_NON_EXISTANT = 0,
 666         NES_AEQE_IWARP_STATE_IDLE = 1,
 667         NES_AEQE_IWARP_STATE_RTS = 2,
 668         NES_AEQE_IWARP_STATE_CLOSING = 3,
 669         NES_AEQE_IWARP_STATE_TERMINATE = 5,
 670         NES_AEQE_IWARP_STATE_ERROR = 6
 671 };
 672
 673 enum nes_aeqe_tcp_state {
 674         NES_AEQE_TCP_STATE_NON_EXISTANT = 0,
 675         NES_AEQE_TCP_STATE_CLOSED = 1,
 676         NES_AEQE_TCP_STATE_LISTEN = 2,
 677         NES_AEQE_TCP_STATE_SYN_SENT = 3,
 678         NES_AEQE_TCP_STATE_SYN_RCVD = 4,
 679         NES_AEQE_TCP_STATE_ESTABLISHED = 5,
 680         NES_AEQE_TCP_STATE_CLOSE_WAIT = 6,
 681         NES_AEQE_TCP_STATE_FIN_WAIT_1 = 7,
 682         NES_AEQE_TCP_STATE_CLOSING = 8,
 683         NES_AEQE_TCP_STATE_LAST_ACK = 9,
 684         NES_AEQE_TCP_STATE_FIN_WAIT_2 = 10,
 685         NES_AEQE_TCP_STATE_TIME_WAIT = 11
 686 };
 687
 688 enum nes_aeqe_aeid {
 689         NES_AEQE_AEID_AMP_UNALLOCATED_STAG                            = 0x0102,
 690         NES_AEQE_AEID_AMP_INVALID_STAG                                = 0x0103,
 691         NES_AEQE_AEID_AMP_BAD_QP                                      = 0x0104,
 692         NES_AEQE_AEID_AMP_BAD_PD                                      = 0x0105,
 693         NES_AEQE_AEID_AMP_BAD_STAG_KEY                                = 0x0106,
 694         NES_AEQE_AEID_AMP_BAD_STAG_INDEX                              = 0x0107,
 695         NES_AEQE_AEID_AMP_BOUNDS_VIOLATION                            = 0x0108,
 696         NES_AEQE_AEID_AMP_RIGHTS_VIOLATION                            = 0x0109,
 697         NES_AEQE_AEID_AMP_TO_WRAP                                     = 0x010a,
 698         NES_AEQE_AEID_AMP_FASTREG_SHARED                              = 0x010b,
 699         NES_AEQE_AEID_AMP_FASTREG_VALID_STAG                          = 0x010c,
 700         NES_AEQE_AEID_AMP_FASTREG_MW_STAG                             = 0x010d,
 701         NES_AEQE_AEID_AMP_FASTREG_INVALID_RIGHTS                      = 0x010e,
 702         NES_AEQE_AEID_AMP_FASTREG_PBL_TABLE_OVERFLOW                  = 0x010f,
 703         NES_AEQE_AEID_AMP_FASTREG_INVALID_LENGTH                      = 0x0110,
 704         NES_AEQE_AEID_AMP_INVALIDATE_SHARED                           = 0x0111,
 705         NES_AEQE_AEID_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS          = 0x0112,
 706         NES_AEQE_AEID_AMP_INVALIDATE_MR_WITH_BOUND_WINDOWS            = 0x0113,
 707         NES_AEQE_AEID_AMP_MWBIND_VALID_STAG                           = 0x0114,
 708         NES_AEQE_AEID_AMP_MWBIND_OF_MR_STAG                           = 0x0115,
 709         NES_AEQE_AEID_AMP_MWBIND_TO_ZERO_BASED_STAG                   = 0x0116,
 710         NES_AEQE_AEID_AMP_MWBIND_TO_MW_STAG                           = 0x0117,
 711         NES_AEQE_AEID_AMP_MWBIND_INVALID_RIGHTS                       = 0x0118,
 712         NES_AEQE_AEID_AMP_MWBIND_INVALID_BOUNDS                       = 0x0119,
 713         NES_AEQE_AEID_AMP_MWBIND_TO_INVALID_PARENT                    = 0x011a,
 714         NES_AEQE_AEID_AMP_MWBIND_BIND_DISABLED                        = 0x011b,
 715         NES_AEQE_AEID_BAD_CLOSE                                       = 0x0201,
 716         NES_AEQE_AEID_RDMAP_ROE_BAD_LLP_CLOSE                         = 0x0202,
 717         NES_AEQE_AEID_CQ_OPERATION_ERROR                              = 0x0203,
 718         NES_AEQE_AEID_PRIV_OPERATION_DENIED                           = 0x0204,
 719         NES_AEQE_AEID_RDMA_READ_WHILE_ORD_ZERO                        = 0x0205,
 720         NES_AEQE_AEID_STAG_ZERO_INVALID                               = 0x0206,
 721         NES_AEQE_AEID_DDP_INVALID_MSN_GAP_IN_MSN                      = 0x0301,
 722         NES_AEQE_AEID_DDP_INVALID_MSN_RANGE_IS_NOT_VALID              = 0x0302,
 723         NES_AEQE_AEID_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER = 0x0303,
 724         NES_AEQE_AEID_DDP_UBE_INVALID_DDP_VERSION                     = 0x0304,
 725         NES_AEQE_AEID_DDP_UBE_INVALID_MO                              = 0x0305,
 726         NES_AEQE_AEID_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE         = 0x0306,
 727         NES_AEQE_AEID_DDP_UBE_INVALID_QN                              = 0x0307,
 728         NES_AEQE_AEID_DDP_NO_L_BIT                                    = 0x0308,
 729         NES_AEQE_AEID_RDMAP_ROE_INVALID_RDMAP_VERSION                 = 0x0311,
 730         NES_AEQE_AEID_RDMAP_ROE_UNEXPECTED_OPCODE                     = 0x0312,
 731         NES_AEQE_AEID_ROE_INVALID_RDMA_READ_REQUEST                   = 0x0313,
 732         NES_AEQE_AEID_ROE_INVALID_RDMA_WRITE_OR_READ_RESP             = 0x0314,
 733         NES_AEQE_AEID_INVALID_ARP_ENTRY                               = 0x0401,
 734         NES_AEQE_AEID_INVALID_TCP_OPTION_RCVD                         = 0x0402,
 735         NES_AEQE_AEID_STALE_ARP_ENTRY                                 = 0x0403,
 736         NES_AEQE_AEID_LLP_CLOSE_COMPLETE                              = 0x0501,
 737         NES_AEQE_AEID_LLP_CONNECTION_RESET                            = 0x0502,
 738         NES_AEQE_AEID_LLP_FIN_RECEIVED                                = 0x0503,
 739         NES_AEQE_AEID_LLP_RECEIVED_MARKER_AND_LENGTH_FIELDS_DONT_MATCH =  0x0504,
 740         NES_AEQE_AEID_LLP_RECEIVED_MPA_CRC_ERROR                      = 0x0505,
 741         NES_AEQE_AEID_LLP_SEGMENT_TOO_LARGE                           = 0x0506,
 742         NES_AEQE_AEID_LLP_SEGMENT_TOO_SMALL                           = 0x0507,
 743         NES_AEQE_AEID_LLP_SYN_RECEIVED                                = 0x0508,
 744         NES_AEQE_AEID_LLP_TERMINATE_RECEIVED                          = 0x0509,
 745         NES_AEQE_AEID_LLP_TOO_MANY_RETRIES                            = 0x050a,
 746         NES_AEQE_AEID_LLP_TOO_MANY_KEEPALIVE_RETRIES                  = 0x050b,
 747         NES_AEQE_AEID_RESET_SENT                                      = 0x0601,
 748         NES_AEQE_AEID_TERMINATE_SENT                                  = 0x0602,
 749         NES_AEQE_AEID_DDP_LCE_LOCAL_CATASTROPHIC                      = 0x0700
 750 };
 751
 752 enum nes_iwarp_sq_opcodes {
 753         NES_IWARP_SQ_WQE_WRPDU = (1<<15),
 754         NES_IWARP_SQ_WQE_PSH = (1<<21),
 755         NES_IWARP_SQ_WQE_STREAMING = (1<<23),
 756         NES_IWARP_SQ_WQE_IMM_DATA = (1<<28),
 757         NES_IWARP_SQ_WQE_READ_FENCE = (1<<29),
 758         NES_IWARP_SQ_WQE_LOCAL_FENCE = (1<<30),
 759         NES_IWARP_SQ_WQE_SIGNALED_COMPL = (1<<31),
 760 };
 761
 762 enum nes_iwarp_sq_wqe_bits {
 763         NES_IWARP_SQ_OP_RDMAW = 0,
 764         NES_IWARP_SQ_OP_RDMAR = 1,
 765         NES_IWARP_SQ_OP_SEND = 3,
 766         NES_IWARP_SQ_OP_SENDINV = 4,
 767         NES_IWARP_SQ_OP_SENDSE = 5,
 768         NES_IWARP_SQ_OP_SENDSEINV = 6,
 769         NES_IWARP_SQ_OP_BIND = 8,
 770         NES_IWARP_SQ_OP_FAST_REG = 9,
 771         NES_IWARP_SQ_OP_LOCINV = 10,
 772         NES_IWARP_SQ_OP_RDMAR_LOCINV = 11,
 773         NES_IWARP_SQ_OP_NOP = 12,
 774 };
 775
 776 enum nes_iwarp_cqe_major_code {
 777         NES_IWARP_CQE_MAJOR_FLUSH = 1,
 778         NES_IWARP_CQE_MAJOR_DRV = 0x8000
 779 };
 780
 781 enum nes_iwarp_cqe_minor_code {
 782         NES_IWARP_CQE_MINOR_FLUSH = 1
 783 };
 784
 785 #define NES_EEPROM_READ_REQUEST (1<<16)
 786 #define NES_MAC_ADDR_VALID      (1<<20)
 787
 788 /*
 789  * NES index registers init values.
 790  */
 791 struct nes_init_values {
 792         u32 index;
 793         u32 data;
 794         u8  wrt;
 795 };
 796
 797 /*
 798  * NES registers in BAR0.
 799  */
 800 struct nes_pci_regs {
 801         u32 int_status;
 802         u32 int_mask;
 803         u32 int_pending;
 804         u32 intf_int_status;
 805         u32 intf_int_mask;
 806         u32 other_regs[59];      /* pad out to 256 bytes for now */
 807 };
 808
 809 #define NES_CQP_SQ_SIZE    128
 810 #define NES_CCQ_SIZE       128
 811 #define NES_NIC_WQ_SIZE    512
 812 #define NES_NIC_CTX_SIZE   ((NES_NIC_CTX_RQ_SIZE_512) | (NES_NIC_CTX_SQ_SIZE_512))
 813 #define NES_NIC_BACK_STORE 0x00038000
 814
 815 struct nes_device;
 816
 817 struct nes_hw_nic_qp_context {
 818         __le32 context_words[6];
 819 };
 820
 821 struct nes_hw_nic_sq_wqe {
 822         __le32 wqe_words[16];
 823 };
 824
 825 struct nes_hw_nic_rq_wqe {
 826         __le32 wqe_words[16];
 827 };
 828
 829 struct nes_hw_nic_cqe {
 830         __le32 cqe_words[4];
 831 };
 832
 833 struct nes_hw_cqp_qp_context {
 834         __le32 context_words[4];
 835 };
 836
 837 struct nes_hw_cqp_wqe {
 838         __le32 wqe_words[16];
 839 };
 840
 841 struct nes_hw_qp_wqe {
 842         __le32 wqe_words[32];
 843 };
 844
 845 struct nes_hw_cqe {
 846         __le32 cqe_words[8];
 847 };
 848
 849 struct nes_hw_ceqe {
 850         __le32 ceqe_words[2];
 851 };
 852
 853 struct nes_hw_aeqe {
 854         __le32 aeqe_words[4];
 855 };
 856
 857 struct nes_cqp_request {
 858         union {
 859                 u64 cqp_callback_context;
 860                 void *cqp_callback_pointer;
 861         };
 862         wait_queue_head_t     waitq;
 863         struct nes_hw_cqp_wqe cqp_wqe;
 864         struct list_head      list;
 865         atomic_t              refcount;
 866         void (*cqp_callback)(struct nes_device *nesdev, struct nes_cqp_request *cqp_request);
 867         u16                   major_code;
 868         u16                   minor_code;
 869         u8                    waiting;
 870         u8                    request_done;
 871         u8                    dynamic;
 872         u8                    callback;
 873 };
 874
 875 struct nes_hw_cqp {
 876         struct nes_hw_cqp_wqe *sq_vbase;
 877         dma_addr_t            sq_pbase;
 878         spinlock_t            lock;
 879         wait_queue_head_t     waitq;
 880         u16                   qp_id;
 881         u16                   sq_head;
 882         u16                   sq_tail;
 883         u16                   sq_size;
 884 };
 885
 886 #define NES_FIRST_FRAG_SIZE 128
 887 struct nes_first_frag {
 888         u8 buffer[NES_FIRST_FRAG_SIZE];
 889 };
 890
 891 struct nes_hw_nic {
 892         struct nes_first_frag    *first_frag_vbase;     /* virtual address of first frags */
 893         struct nes_hw_nic_sq_wqe *sq_vbase;                     /* virtual address of sq */
 894         struct nes_hw_nic_rq_wqe *rq_vbase;                     /* virtual address of rq */
 895         struct sk_buff           *tx_skb[NES_NIC_WQ_SIZE];
 896         struct sk_buff           *rx_skb[NES_NIC_WQ_SIZE];
 897         dma_addr_t frag_paddr[NES_NIC_WQ_SIZE];
 898         unsigned long first_frag_overflow[BITS_TO_LONGS(NES_NIC_WQ_SIZE)];
 899         dma_addr_t sq_pbase;                    /* PCI memory for host rings */
 900         dma_addr_t rq_pbase;                    /* PCI memory for host rings */
 901
 902         u16 qp_id;
 903         u16 sq_head;
 904         u16 sq_tail;
 905         u16 sq_size;
 906         u16 rq_head;
 907         u16 rq_tail;
 908         u16 rq_size;
 909         u8 replenishing_rq;
 910         u8 reserved;
 911
 912         spinlock_t rq_lock;
 913 };
 914
 915 struct nes_hw_nic_cq {
 916         struct nes_hw_nic_cqe volatile *cq_vbase;       /* PCI memory for host rings */
 917         void (*ce_handler)(struct nes_device *nesdev, struct nes_hw_nic_cq *cq);
 918         dma_addr_t cq_pbase;    /* PCI memory for host rings */
 919         int rx_cqes_completed;
 920         int cqe_allocs_pending;
 921         int rx_pkts_indicated;
 922         u16 cq_head;
 923         u16 cq_size;
 924         u16 cq_number;
 925         u8  cqes_pending;
 926 };
 927
 928 struct nes_hw_qp {
 929         struct nes_hw_qp_wqe *sq_vbase;         /* PCI memory for host rings */
 930         struct nes_hw_qp_wqe *rq_vbase;         /* PCI memory for host rings */
 931         void                 *q2_vbase;                 /* PCI memory for host rings */
 932         dma_addr_t sq_pbase;    /* PCI memory for host rings */
 933         dma_addr_t rq_pbase;    /* PCI memory for host rings */
 934         dma_addr_t q2_pbase;    /* PCI memory for host rings */
 935         u32 qp_id;
 936         u16 sq_head;
 937         u16 sq_tail;
 938         u16 sq_size;
 939         u16 rq_head;
 940         u16 rq_tail;
 941         u16 rq_size;
 942         u8  rq_encoded_size;
 943         u8  sq_encoded_size;
 944 };
 945
 946 struct nes_hw_cq {
 947         struct nes_hw_cqe *cq_vbase;    /* PCI memory for host rings */
 948         void (*ce_handler)(struct nes_device *nesdev, struct nes_hw_cq *cq);
 949         dma_addr_t cq_pbase;    /* PCI memory for host rings */
 950         u16 cq_head;
 951         u16 cq_size;
 952         u16 cq_number;
 953 };
 954
 955 struct nes_hw_ceq {
 956         struct nes_hw_ceqe volatile *ceq_vbase; /* PCI memory for host rings */
 957         dma_addr_t ceq_pbase;   /* PCI memory for host rings */
 958         u16 ceq_head;
 959         u16 ceq_size;
 960 };
 961
 962 struct nes_hw_aeq {
 963         struct nes_hw_aeqe volatile *aeq_vbase; /* PCI memory for host rings */
 964         dma_addr_t aeq_pbase;   /* PCI memory for host rings */
 965         u16 aeq_head;
 966         u16 aeq_size;
 967 };
 968
 969 struct nic_qp_map {
 970         u8 qpid;
 971         u8 nic_index;
 972         u8 logical_port;
 973         u8 is_hnic;
 974 };
 975
 976 #define NES_CQP_ARP_AEQ_INDEX_MASK  0x000f0000
 977 #define NES_CQP_ARP_AEQ_INDEX_SHIFT 16
 978
 979 #define NES_CQP_APBVT_ADD                       0x00008000
 980 #define NES_CQP_APBVT_NIC_SHIFT         16
 981
 982 #define NES_ARP_ADD     1
 983 #define NES_ARP_DELETE  2
 984 #define NES_ARP_RESOLVE 3
 985
 986 #define NES_MAC_SW_IDLE      0
 987 #define NES_MAC_SW_INTERRUPT 1
 988 #define NES_MAC_SW_MH        2
 989
 990 struct nes_arp_entry {
 991         u32 ip_addr;
 992         u8  mac_addr[ETH_ALEN];
 993 };
 994
 995 #define NES_NIC_FAST_TIMER          96
 996 #define NES_NIC_FAST_TIMER_LOW      40
 997 #define NES_NIC_FAST_TIMER_HIGH     1000
 998 #define DEFAULT_NES_QL_HIGH         256
 999 #define DEFAULT_NES_QL_LOW          16
1000 #define DEFAULT_NES_QL_TARGET       64
1001 #define DEFAULT_JUMBO_NES_QL_LOW    12
1002 #define DEFAULT_JUMBO_NES_QL_TARGET 40
1003 #define DEFAULT_JUMBO_NES_QL_HIGH   128
1004 #define NES_NIC_CQ_DOWNWARD_TREND   16
1005 #define NES_PFT_SIZE                48
1006
1007 struct nes_hw_tune_timer {
1008     /* u16 cq_count; */
1009     u16 threshold_low;
1010     u16 threshold_target;
1011     u16 threshold_high;
1012     u16 timer_in_use;
1013     u16 timer_in_use_old;
1014     u16 timer_in_use_min;
1015     u16 timer_in_use_max;
1016     u8  timer_direction_upward;
1017     u8  timer_direction_downward;
1018     u16 cq_count_old;
1019     u8  cq_direction_downward;
1020 };
1021
1022 #define NES_TIMER_INT_LIMIT         2
1023 #define NES_TIMER_INT_LIMIT_DYNAMIC 10
1024 #define NES_TIMER_ENABLE_LIMIT      4
1025 #define NES_MAX_LINK_INTERRUPTS     128
1026 #define NES_MAX_LINK_CHECK          200
1027 #define NES_MAX_LRO_DESCRIPTORS     32
1028 #define NES_LRO_MAX_AGGR            64
1029
1030 struct nes_adapter {
1031         u64              fw_ver;
1032         unsigned long    *allocated_qps;
1033         unsigned long    *allocated_cqs;
1034         unsigned long    *allocated_mrs;
1035         unsigned long    *allocated_pds;
1036         unsigned long    *allocated_arps;
1037         struct nes_qp    **qp_table;
1038         struct workqueue_struct *work_q;
1039
1040         struct list_head list;
1041         struct list_head active_listeners;
1042         /* list of the netdev's associated with each logical port */
1043         struct list_head nesvnic_list[4];
1044
1045         struct timer_list  mh_timer;
1046         struct timer_list  lc_timer;
1047         struct work_struct work;
1048         spinlock_t         resource_lock;
1049         spinlock_t         phy_lock;
1050         spinlock_t         pbl_lock;
1051         spinlock_t         periodic_timer_lock;
1052
1053         struct nes_arp_entry arp_table[NES_MAX_ARP_TABLE_SIZE];
1054
1055         /* Adapter CEQ and AEQs */
1056         struct nes_hw_ceq ceq[16];
1057         struct nes_hw_aeq aeq[8];
1058
1059         struct nes_hw_tune_timer tune_timer;
1060
1061         unsigned long doorbell_start;
1062
1063         u32 hw_rev;
1064         u32 vendor_id;
1065         u32 vendor_part_id;
1066         u32 device_cap_flags;
1067         u32 tick_delta;
1068         u32 timer_int_req;
1069         u32 arp_table_size;
1070         u32 next_arp_index;
1071
1072         u32 max_mr;
1073         u32 max_256pbl;
1074         u32 max_4kpbl;
1075         u32 free_256pbl;
1076         u32 free_4kpbl;
1077         u32 max_mr_size;
1078         u32 max_qp;
1079         u32 next_qp;
1080         u32 max_irrq;
1081         u32 max_qp_wr;
1082         u32 max_sge;
1083         u32 max_cq;
1084         u32 next_cq;
1085         u32 max_cqe;
1086         u32 max_pd;
1087         u32 base_pd;
1088         u32 next_pd;
1089         u32 hte_index_mask;
1090
1091         /* EEPROM information */
1092         u32 rx_pool_size;
1093         u32 tx_pool_size;
1094         u32 rx_threshold;
1095         u32 tcp_timer_core_clk_divisor;
1096         u32 iwarp_config;
1097         u32 cm_config;
1098         u32 sws_timer_config;
1099         u32 tcp_config1;
1100         u32 wqm_wat;
1101         u32 core_clock;
1102         u32 firmware_version;
1103         u32 eeprom_version;
1104
1105         u32 nic_rx_eth_route_err;
1106
1107         u32 et_rx_coalesce_usecs;
1108         u32 et_rx_max_coalesced_frames;
1109         u32 et_rx_coalesce_usecs_irq;
1110         u32 et_rx_max_coalesced_frames_irq;
1111         u32 et_pkt_rate_low;
1112         u32 et_rx_coalesce_usecs_low;
1113         u32 et_rx_max_coalesced_frames_low;
1114         u32 et_pkt_rate_high;
1115         u32 et_rx_coalesce_usecs_high;
1116         u32 et_rx_max_coalesced_frames_high;
1117         u32 et_rate_sample_interval;
1118         u32 timer_int_limit;
1119         u32 wqm_quanta;
1120
1121         /* Adapter base MAC address */
1122         u32 mac_addr_low;
1123         u16 mac_addr_high;
1124
1125         u16 firmware_eeprom_offset;
1126         u16 software_eeprom_offset;
1127
1128         u16 max_irrq_wr;
1129
1130         /* pd config for each port */
1131         u16 pd_config_size[4];
1132         u16 pd_config_base[4];
1133
1134         u16 link_interrupt_count[4];
1135         u8 crit_error_count[32];
1136
1137         /* the phy index for each port */
1138         u8  phy_index[4];
1139         u8  mac_sw_state[4];
1140         u8  mac_link_down[4];
1141         u8  phy_type[4];
1142         u8  log_port;
1143
1144         /* PCI information */
1145         unsigned int  devfn;
1146         unsigned char bus_number;
1147         unsigned char OneG_Mode;
1148
1149         unsigned char ref_count;
1150         u8            netdev_count;
1151         u8            netdev_max;       /* from host nic address count in EEPROM */
1152         u8            port_count;
1153         u8            virtwq;
1154         u8            send_term_ok;
1155         u8            et_use_adaptive_rx_coalesce;
1156         u8            adapter_fcn_count;
1157         u8 pft_mcast_map[NES_PFT_SIZE];
1158 };
1159
1160 struct nes_pbl {
1161         u64              *pbl_vbase;
1162         dma_addr_t       pbl_pbase;
1163         struct page      *page;
1164         unsigned long    user_base;
1165         u32              pbl_size;
1166         struct list_head list;
1167         /* TODO: need to add list for two level tables */
1168 };
1169
1170 #define NES_4K_PBL_CHUNK_SIZE   4096
1171
1172 struct nes_fast_mr_wqe_pbl {
1173         u64             *kva;
1174         dma_addr_t      paddr;
1175 };
1176
1177 struct nes_ib_fast_reg_page_list {
1178         struct ib_fast_reg_page_list    ibfrpl;
1179         struct nes_fast_mr_wqe_pbl      nes_wqe_pbl;
1180         u64                             pbl;
1181 };
1182
1183 struct nes_listener {
1184         struct work_struct      work;
1185         struct workqueue_struct *wq;
1186         struct nes_vnic         *nesvnic;
1187         struct iw_cm_id         *cm_id;
1188         struct list_head        list;
1189         unsigned long           socket;
1190         u8                      accept_failed;
1191 };
1192
1193 struct nes_ib_device;
1194
1195 struct nes_vnic {
1196         struct nes_ib_device *nesibdev;
1197         u64 sq_full;
1198         u64 tso_requests;
1199         u64 segmented_tso_requests;
1200         u64 linearized_skbs;
1201         u64 tx_sw_dropped;
1202         u64 endnode_nstat_rx_discard;
1203         u64 endnode_nstat_rx_octets;
1204         u64 endnode_nstat_rx_frames;
1205         u64 endnode_nstat_tx_octets;
1206         u64 endnode_nstat_tx_frames;
1207         u64 endnode_ipv4_tcp_retransmits;
1208         /* void *mem; */
1209         struct nes_device *nesdev;
1210         struct net_device *netdev;
1211         struct vlan_group *vlan_grp;
1212         atomic_t          rx_skbs_needed;
1213         atomic_t          rx_skb_timer_running;
1214         int               budget;
1215         u32               msg_enable;
1216         /* u32 tx_avail; */
1217         __be32            local_ipaddr;
1218         struct napi_struct   napi;
1219         spinlock_t           tx_lock;   /* could use netdev tx lock? */
1220         struct timer_list    rq_wqes_timer;
1221         u32                  nic_mem_size;
1222         void                 *nic_vbase;
1223         dma_addr_t           nic_pbase;
1224         struct nes_hw_nic    nic;
1225         struct nes_hw_nic_cq nic_cq;
1226         u32    mcrq_qp_id;
1227         struct nes_ucontext *mcrq_ucontext;
1228         struct nes_cqp_request* (*get_cqp_request)(struct nes_device *nesdev);
1229         void (*post_cqp_request)(struct nes_device*, struct nes_cqp_request *);
1230         int (*mcrq_mcast_filter)( struct nes_vnic* nesvnic, __u8* dmi_addr );
1231         struct net_device_stats netstats;
1232         /* used to put the netdev on the adapters logical port list */
1233         struct list_head list;
1234         u16 max_frame_size;
1235         u8  netdev_open;
1236         u8  linkup;
1237         u8  logical_port;
1238         u8  netdev_index;  /* might not be needed, indexes nesdev->netdev */
1239         u8  perfect_filter_index;
1240         u8  nic_index;
1241         u8  qp_nic_index[4];
1242         u8  next_qp_nic_index;
1243         u8  of_device_registered;
1244         u8  rdma_enabled;
1245         u8  rx_checksum_disabled;
1246         u32 lro_max_aggr;
1247         struct net_lro_mgr lro_mgr;
1248         struct net_lro_desc lro_desc[NES_MAX_LRO_DESCRIPTORS];
1249 };
1250
1251 struct nes_ib_device {
1252         struct ib_device ibdev;
1253         struct nes_vnic *nesvnic;
1254
1255         /* Virtual RNIC Limits */
1256         u32 max_mr;
1257         u32 max_qp;
1258         u32 max_cq;
1259         u32 max_pd;
1260         u32 num_mr;
1261         u32 num_qp;
1262         u32 num_cq;
1263         u32 num_pd;
1264 };
1265
1266 enum nes_hdrct_flags {
1267         DDP_LEN_FLAG                    = 0x80,
1268         DDP_HDR_FLAG                    = 0x40,
1269         RDMA_HDR_FLAG                   = 0x20
1270 };
1271
1272 enum nes_term_layers {
1273         LAYER_RDMA                      = 0,
1274         LAYER_DDP                       = 1,
1275         LAYER_MPA                       = 2
1276 };
1277
1278 enum nes_term_error_types {
1279         RDMAP_CATASTROPHIC              = 0,
1280         RDMAP_REMOTE_PROT               = 1,
1281         RDMAP_REMOTE_OP                 = 2,
1282         DDP_CATASTROPHIC                = 0,
1283         DDP_TAGGED_BUFFER               = 1,
1284         DDP_UNTAGGED_BUFFER             = 2,
1285         DDP_LLP                         = 3
1286 };
1287
1288 enum nes_term_rdma_errors {
1289         RDMAP_INV_STAG                  = 0x00,
1290         RDMAP_INV_BOUNDS                = 0x01,
1291         RDMAP_ACCESS                    = 0x02,
1292         RDMAP_UNASSOC_STAG              = 0x03,
1293         RDMAP_TO_WRAP                   = 0x04,
1294         RDMAP_INV_RDMAP_VER             = 0x05,
1295         RDMAP_UNEXPECTED_OP             = 0x06,
1296         RDMAP_CATASTROPHIC_LOCAL        = 0x07,
1297         RDMAP_CATASTROPHIC_GLOBAL       = 0x08,
1298         RDMAP_CANT_INV_STAG             = 0x09,
1299         RDMAP_UNSPECIFIED               = 0xff
1300 };
1301
1302 enum nes_term_ddp_errors {
1303         DDP_CATASTROPHIC_LOCAL          = 0x00,
1304         DDP_TAGGED_INV_STAG             = 0x00,
1305         DDP_TAGGED_BOUNDS               = 0x01,
1306         DDP_TAGGED_UNASSOC_STAG         = 0x02,
1307         DDP_TAGGED_TO_WRAP              = 0x03,
1308         DDP_TAGGED_INV_DDP_VER          = 0x04,
1309         DDP_UNTAGGED_INV_QN             = 0x01,
1310         DDP_UNTAGGED_INV_MSN_NO_BUF     = 0x02,
1311         DDP_UNTAGGED_INV_MSN_RANGE      = 0x03,
1312         DDP_UNTAGGED_INV_MO             = 0x04,
1313         DDP_UNTAGGED_INV_TOO_LONG       = 0x05,
1314         DDP_UNTAGGED_INV_DDP_VER        = 0x06
1315 };
1316
1317 enum nes_term_mpa_errors {
1318         MPA_CLOSED                      = 0x01,
1319         MPA_CRC                         = 0x02,
1320         MPA_MARKER                      = 0x03,
1321         MPA_REQ_RSP                     = 0x04,
1322 };
1323
1324 struct nes_terminate_hdr {
1325         u8 layer_etype;
1326         u8 error_code;
1327         u8 hdrct;
1328         u8 rsvd;
1329 };
1330
1331 /* Used to determine how to fill in terminate error codes */
1332 #define IWARP_OPCODE_WRITE              0
1333 #define IWARP_OPCODE_READREQ            1
1334 #define IWARP_OPCODE_READRSP            2
1335 #define IWARP_OPCODE_SEND               3
1336 #define IWARP_OPCODE_SEND_INV           4
1337 #define IWARP_OPCODE_SEND_SE            5
1338 #define IWARP_OPCODE_SEND_SE_INV        6
1339 #define IWARP_OPCODE_TERM               7
1340
1341 /* These values are used only during terminate processing */
1342 #define TERM_DDP_LEN_TAGGED     14
1343 #define TERM_DDP_LEN_UNTAGGED   18
1344 #define TERM_RDMA_LEN           28
1345 #define RDMA_OPCODE_MASK        0x0f
1346 #define RDMA_READ_REQ_OPCODE    1
1347 #define BAD_FRAME_OFFSET        64
1348 #define CQE_MAJOR_DRV           0x8000
1349
1350 #define nes_vlan_rx vlan_hwaccel_receive_skb
1351 #define nes_netif_rx netif_receive_skb
1352
1353 #endif          /* __NES_HW_H */