drivers/infiniband/hw/mthca/mthca_qp.c

   1 /*
   2  * Copyright (c) 2004 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Cisco Systems. All rights reserved.
   4  * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
   5  * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * OpenIB.org BSD license below:
  12  *
  13  *     Redistribution and use in source and binary forms, with or
  14  *     without modification, are permitted provided that the following
  15  *     conditions are met:
  16  *
  17  *      - Redistributions of source code must retain the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer.
  20  *
  21  *      - Redistributions in binary form must reproduce the above
  22  *        copyright notice, this list of conditions and the following
  23  *        disclaimer in the documentation and/or other materials
  24  *        provided with the distribution.
  25  *
  26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33  * SOFTWARE.
  34  *
  35  * $Id: mthca_qp.c 1355 2004-12-17 15:23:43Z roland $
  36  */
  37
  38 #include <linux/init.h>
  39 #include <linux/string.h>
  40 #include <linux/slab.h>
  41
  42 #include <asm/io.h>
  43
  44 #include <rdma/ib_verbs.h>
  45 #include <rdma/ib_cache.h>
  46 #include <rdma/ib_pack.h>
  47
  48 #include "mthca_dev.h"
  49 #include "mthca_cmd.h"
  50 #include "mthca_memfree.h"
  51 #include "mthca_wqe.h"
  52
  53 enum {
  54         MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE,
  55         MTHCA_ACK_REQ_FREQ       = 10,
  56         MTHCA_FLIGHT_LIMIT       = 9,
  57         MTHCA_UD_HEADER_SIZE     = 72, /* largest UD header possible */
  58         MTHCA_INLINE_HEADER_SIZE = 4,  /* data segment overhead for inline */
  59         MTHCA_INLINE_CHUNK_SIZE  = 16  /* inline data segment chunk */
  60 };
  61
  62 enum {
  63         MTHCA_QP_STATE_RST  = 0,
  64         MTHCA_QP_STATE_INIT = 1,
  65         MTHCA_QP_STATE_RTR  = 2,
  66         MTHCA_QP_STATE_RTS  = 3,
  67         MTHCA_QP_STATE_SQE  = 4,
  68         MTHCA_QP_STATE_SQD  = 5,
  69         MTHCA_QP_STATE_ERR  = 6,
  70         MTHCA_QP_STATE_DRAINING = 7
  71 };
  72
  73 enum {
  74         MTHCA_QP_ST_RC  = 0x0,
  75         MTHCA_QP_ST_UC  = 0x1,
  76         MTHCA_QP_ST_RD  = 0x2,
  77         MTHCA_QP_ST_UD  = 0x3,
  78         MTHCA_QP_ST_MLX = 0x7
  79 };
  80
  81 enum {
  82         MTHCA_QP_PM_MIGRATED = 0x3,
  83         MTHCA_QP_PM_ARMED    = 0x0,
  84         MTHCA_QP_PM_REARM    = 0x1
  85 };
  86
  87 enum {
  88         /* qp_context flags */
  89         MTHCA_QP_BIT_DE  = 1 <<  8,
  90         /* params1 */
  91         MTHCA_QP_BIT_SRE = 1 << 15,
  92         MTHCA_QP_BIT_SWE = 1 << 14,
  93         MTHCA_QP_BIT_SAE = 1 << 13,
  94         MTHCA_QP_BIT_SIC = 1 <<  4,
  95         MTHCA_QP_BIT_SSC = 1 <<  3,
  96         /* params2 */
  97         MTHCA_QP_BIT_RRE = 1 << 15,
  98         MTHCA_QP_BIT_RWE = 1 << 14,
  99         MTHCA_QP_BIT_RAE = 1 << 13,
 100         MTHCA_QP_BIT_RIC = 1 <<  4,
 101         MTHCA_QP_BIT_RSC = 1 <<  3
 102 };
 103
 104 enum {
 105         MTHCA_SEND_DOORBELL_FENCE = 1 << 5
 106 };
 107
 108 struct mthca_qp_path {
 109         __be32 port_pkey;
 110         u8     rnr_retry;
 111         u8     g_mylmc;
 112         __be16 rlid;
 113         u8     ackto;
 114         u8     mgid_index;
 115         u8     static_rate;
 116         u8     hop_limit;
 117         __be32 sl_tclass_flowlabel;
 118         u8     rgid[16];
 119 } __attribute__((packed));
 120
 121 struct mthca_qp_context {
 122         __be32 flags;
 123         __be32 tavor_sched_queue; /* Reserved on Arbel */
 124         u8     mtu_msgmax;
 125         u8     rq_size_stride;  /* Reserved on Tavor */
 126         u8     sq_size_stride;  /* Reserved on Tavor */
 127         u8     rlkey_arbel_sched_queue; /* Reserved on Tavor */
 128         __be32 usr_page;
 129         __be32 local_qpn;
 130         __be32 remote_qpn;
 131         u32    reserved1[2];
 132         struct mthca_qp_path pri_path;
 133         struct mthca_qp_path alt_path;
 134         __be32 rdd;
 135         __be32 pd;
 136         __be32 wqe_base;
 137         __be32 wqe_lkey;
 138         __be32 params1;
 139         __be32 reserved2;
 140         __be32 next_send_psn;
 141         __be32 cqn_snd;
 142         __be32 snd_wqe_base_l;  /* Next send WQE on Tavor */
 143         __be32 snd_db_index;    /* (debugging only entries) */
 144         __be32 last_acked_psn;
 145         __be32 ssn;
 146         __be32 params2;
 147         __be32 rnr_nextrecvpsn;
 148         __be32 ra_buff_indx;
 149         __be32 cqn_rcv;
 150         __be32 rcv_wqe_base_l;  /* Next recv WQE on Tavor */
 151         __be32 rcv_db_index;    /* (debugging only entries) */
 152         __be32 qkey;
 153         __be32 srqn;
 154         __be32 rmsn;
 155         __be16 rq_wqe_counter;  /* reserved on Tavor */
 156         __be16 sq_wqe_counter;  /* reserved on Tavor */
 157         u32    reserved3[18];
 158 } __attribute__((packed));
 159
 160 struct mthca_qp_param {
 161         __be32 opt_param_mask;
 162         u32    reserved1;
 163         struct mthca_qp_context context;
 164         u32    reserved2[62];
 165 } __attribute__((packed));
 166
 167 enum {
 168         MTHCA_QP_OPTPAR_ALT_ADDR_PATH     = 1 << 0,
 169         MTHCA_QP_OPTPAR_RRE               = 1 << 1,
 170         MTHCA_QP_OPTPAR_RAE               = 1 << 2,
 171         MTHCA_QP_OPTPAR_RWE               = 1 << 3,
 172         MTHCA_QP_OPTPAR_PKEY_INDEX        = 1 << 4,
 173         MTHCA_QP_OPTPAR_Q_KEY             = 1 << 5,
 174         MTHCA_QP_OPTPAR_RNR_TIMEOUT       = 1 << 6,
 175         MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
 176         MTHCA_QP_OPTPAR_SRA_MAX           = 1 << 8,
 177         MTHCA_QP_OPTPAR_RRA_MAX           = 1 << 9,
 178         MTHCA_QP_OPTPAR_PM_STATE          = 1 << 10,
 179         MTHCA_QP_OPTPAR_PORT_NUM          = 1 << 11,
 180         MTHCA_QP_OPTPAR_RETRY_COUNT       = 1 << 12,
 181         MTHCA_QP_OPTPAR_ALT_RNR_RETRY     = 1 << 13,
 182         MTHCA_QP_OPTPAR_ACK_TIMEOUT       = 1 << 14,
 183         MTHCA_QP_OPTPAR_RNR_RETRY         = 1 << 15,
 184         MTHCA_QP_OPTPAR_SCHED_QUEUE       = 1 << 16
 185 };
 186
 187 static const u8 mthca_opcode[] = {
 188         [IB_WR_SEND]                 = MTHCA_OPCODE_SEND,
 189         [IB_WR_SEND_WITH_IMM]        = MTHCA_OPCODE_SEND_IMM,
 190         [IB_WR_RDMA_WRITE]           = MTHCA_OPCODE_RDMA_WRITE,
 191         [IB_WR_RDMA_WRITE_WITH_IMM]  = MTHCA_OPCODE_RDMA_WRITE_IMM,
 192         [IB_WR_RDMA_READ]            = MTHCA_OPCODE_RDMA_READ,
 193         [IB_WR_ATOMIC_CMP_AND_SWP]   = MTHCA_OPCODE_ATOMIC_CS,
 194         [IB_WR_ATOMIC_FETCH_AND_ADD] = MTHCA_OPCODE_ATOMIC_FA,
 195 };
 196
 197 static int is_sqp(struct mthca_dev *dev, struct mthca_qp *qp)
 198 {
 199         return qp->qpn >= dev->qp_table.sqp_start &&
 200                 qp->qpn <= dev->qp_table.sqp_start + 3;
 201 }
 202
 203 static int is_qp0(struct mthca_dev *dev, struct mthca_qp *qp)
 204 {
 205         return qp->qpn >= dev->qp_table.sqp_start &&
 206                 qp->qpn <= dev->qp_table.sqp_start + 1;
 207 }
 208
 209 static void *get_recv_wqe(struct mthca_qp *qp, int n)
 210 {
 211         if (qp->is_direct)
 212                 return qp->queue.direct.buf + (n << qp->rq.wqe_shift);
 213         else
 214                 return qp->queue.page_list[(n << qp->rq.wqe_shift) >> PAGE_SHIFT].buf +
 215                         ((n << qp->rq.wqe_shift) & (PAGE_SIZE - 1));
 216 }
 217
 218 static void *get_send_wqe(struct mthca_qp *qp, int n)
 219 {
 220         if (qp->is_direct)
 221                 return qp->queue.direct.buf + qp->send_wqe_offset +
 222                         (n << qp->sq.wqe_shift);
 223         else
 224                 return qp->queue.page_list[(qp->send_wqe_offset +
 225                                             (n << qp->sq.wqe_shift)) >>
 226                                            PAGE_SHIFT].buf +
 227                         ((qp->send_wqe_offset + (n << qp->sq.wqe_shift)) &
 228                          (PAGE_SIZE - 1));
 229 }
 230
 231 static void mthca_wq_reset(struct mthca_wq *wq)
 232 {
 233         wq->next_ind  = 0;
 234         wq->last_comp = wq->max - 1;
 235         wq->head      = 0;
 236         wq->tail      = 0;
 237 }
 238
 239 void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
 240                     enum ib_event_type event_type)
 241 {
 242         struct mthca_qp *qp;
 243         struct ib_event event;
 244
 245         spin_lock(&dev->qp_table.lock);
 246         qp = mthca_array_get(&dev->qp_table.qp, qpn & (dev->limits.num_qps - 1));
 247         if (qp)
 248                 ++qp->refcount;
 249         spin_unlock(&dev->qp_table.lock);
 250
 251         if (!qp) {
 252                 mthca_warn(dev, "Async event for bogus QP %08x\n", qpn);
 253                 return;
 254         }
 255
 256         if (event_type == IB_EVENT_PATH_MIG)
 257                 qp->port = qp->alt_port;
 258
 259         event.device      = &dev->ib_dev;
 260         event.event       = event_type;
 261         event.element.qp  = &qp->ibqp;
 262         if (qp->ibqp.event_handler)
 263                 qp->ibqp.event_handler(&event, qp->ibqp.qp_context);
 264
 265         spin_lock(&dev->qp_table.lock);
 266         if (!--qp->refcount)
 267                 wake_up(&qp->wait);
 268         spin_unlock(&dev->qp_table.lock);
 269 }
 270
 271 static int to_mthca_state(enum ib_qp_state ib_state)
 272 {
 273         switch (ib_state) {
 274         case IB_QPS_RESET: return MTHCA_QP_STATE_RST;
 275         case IB_QPS_INIT:  return MTHCA_QP_STATE_INIT;
 276         case IB_QPS_RTR:   return MTHCA_QP_STATE_RTR;
 277         case IB_QPS_RTS:   return MTHCA_QP_STATE_RTS;
 278         case IB_QPS_SQD:   return MTHCA_QP_STATE_SQD;
 279         case IB_QPS_SQE:   return MTHCA_QP_STATE_SQE;
 280         case IB_QPS_ERR:   return MTHCA_QP_STATE_ERR;
 281         default:                return -1;
 282         }
 283 }
 284
 285 enum { RC, UC, UD, RD, RDEE, MLX, NUM_TRANS };
 286
 287 static int to_mthca_st(int transport)
 288 {
 289         switch (transport) {
 290         case RC:  return MTHCA_QP_ST_RC;
 291         case UC:  return MTHCA_QP_ST_UC;
 292         case UD:  return MTHCA_QP_ST_UD;
 293         case RD:  return MTHCA_QP_ST_RD;
 294         case MLX: return MTHCA_QP_ST_MLX;
 295         default:  return -1;
 296         }
 297 }
 298
 299 static void store_attrs(struct mthca_sqp *sqp, struct ib_qp_attr *attr,
 300                         int attr_mask)
 301 {
 302         if (attr_mask & IB_QP_PKEY_INDEX)
 303                 sqp->pkey_index = attr->pkey_index;
 304         if (attr_mask & IB_QP_QKEY)
 305                 sqp->qkey = attr->qkey;
 306         if (attr_mask & IB_QP_SQ_PSN)
 307                 sqp->send_psn = attr->sq_psn;
 308 }
 309
 310 static void init_port(struct mthca_dev *dev, int port)
 311 {
 312         int err;
 313         u8 status;
 314         struct mthca_init_ib_param param;
 315
 316         memset(&param, 0, sizeof param);
 317
 318         param.port_width = dev->limits.port_width_cap;
 319         param.vl_cap     = dev->limits.vl_cap;
 320         param.mtu_cap    = dev->limits.mtu_cap;
 321         param.gid_cap    = dev->limits.gid_table_len;
 322         param.pkey_cap   = dev->limits.pkey_table_len;
 323
 324         err = mthca_INIT_IB(dev, &param, port, &status);
 325         if (err)
 326                 mthca_warn(dev, "INIT_IB failed, return code %d.\n", err);
 327         if (status)
 328                 mthca_warn(dev, "INIT_IB returned status %02x.\n", status);
 329 }
 330
 331 static __be32 get_hw_access_flags(struct mthca_qp *qp, struct ib_qp_attr *attr,
 332                                   int attr_mask)
 333 {
 334         u8 dest_rd_atomic;
 335         u32 access_flags;
 336         u32 hw_access_flags = 0;
 337
 338         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
 339                 dest_rd_atomic = attr->max_dest_rd_atomic;
 340         else
 341                 dest_rd_atomic = qp->resp_depth;
 342
 343         if (attr_mask & IB_QP_ACCESS_FLAGS)
 344                 access_flags = attr->qp_access_flags;
 345         else
 346                 access_flags = qp->atomic_rd_en;
 347
 348         if (!dest_rd_atomic)
 349                 access_flags &= IB_ACCESS_REMOTE_WRITE;
 350
 351         if (access_flags & IB_ACCESS_REMOTE_READ)
 352                 hw_access_flags |= MTHCA_QP_BIT_RRE;
 353         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
 354                 hw_access_flags |= MTHCA_QP_BIT_RAE;
 355         if (access_flags & IB_ACCESS_REMOTE_WRITE)
 356                 hw_access_flags |= MTHCA_QP_BIT_RWE;
 357
 358         return cpu_to_be32(hw_access_flags);
 359 }
 360
 361 static inline enum ib_qp_state to_ib_qp_state(int mthca_state)
 362 {
 363         switch (mthca_state) {
 364         case MTHCA_QP_STATE_RST:      return IB_QPS_RESET;
 365         case MTHCA_QP_STATE_INIT:     return IB_QPS_INIT;
 366         case MTHCA_QP_STATE_RTR:      return IB_QPS_RTR;
 367         case MTHCA_QP_STATE_RTS:      return IB_QPS_RTS;
 368         case MTHCA_QP_STATE_DRAINING:
 369         case MTHCA_QP_STATE_SQD:      return IB_QPS_SQD;
 370         case MTHCA_QP_STATE_SQE:      return IB_QPS_SQE;
 371         case MTHCA_QP_STATE_ERR:      return IB_QPS_ERR;
 372         default:                      return -1;
 373         }
 374 }
 375
 376 static inline enum ib_mig_state to_ib_mig_state(int mthca_mig_state)
 377 {
 378         switch (mthca_mig_state) {
 379         case 0:  return IB_MIG_ARMED;
 380         case 1:  return IB_MIG_REARM;
 381         case 3:  return IB_MIG_MIGRATED;
 382         default: return -1;
 383         }
 384 }
 385
 386 static int to_ib_qp_access_flags(int mthca_flags)
 387 {
 388         int ib_flags = 0;
 389
 390         if (mthca_flags & MTHCA_QP_BIT_RRE)
 391                 ib_flags |= IB_ACCESS_REMOTE_READ;
 392         if (mthca_flags & MTHCA_QP_BIT_RWE)
 393                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
 394         if (mthca_flags & MTHCA_QP_BIT_RAE)
 395                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
 396
 397         return ib_flags;
 398 }
 399
 400 static void to_ib_ah_attr(struct mthca_dev *dev, struct ib_ah_attr *ib_ah_attr,
 401                                 struct mthca_qp_path *path)
 402 {
 403         memset(ib_ah_attr, 0, sizeof *path);
 404         ib_ah_attr->port_num      = (be32_to_cpu(path->port_pkey) >> 24) & 0x3;
 405
 406         if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->limits.num_ports)
 407                 return;
 408
 409         ib_ah_attr->dlid          = be16_to_cpu(path->rlid);
 410         ib_ah_attr->sl            = be32_to_cpu(path->sl_tclass_flowlabel) >> 28;
 411         ib_ah_attr->src_path_bits = path->g_mylmc & 0x7f;
 412         ib_ah_attr->static_rate   = mthca_rate_to_ib(dev,
 413                                                      path->static_rate & 0xf,
 414                                                      ib_ah_attr->port_num);
 415         ib_ah_attr->ah_flags      = (path->g_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
 416         if (ib_ah_attr->ah_flags) {
 417                 ib_ah_attr->grh.sgid_index = path->mgid_index & (dev->limits.gid_table_len - 1);
 418                 ib_ah_attr->grh.hop_limit  = path->hop_limit;
 419                 ib_ah_attr->grh.traffic_class =
 420                         (be32_to_cpu(path->sl_tclass_flowlabel) >> 20) & 0xff;
 421                 ib_ah_attr->grh.flow_label =
 422                         be32_to_cpu(path->sl_tclass_flowlabel) & 0xfffff;
 423                 memcpy(ib_ah_attr->grh.dgid.raw,
 424                         path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
 425         }
 426 }
 427
 428 int mthca_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
 429                    struct ib_qp_init_attr *qp_init_attr)
 430 {
 431         struct mthca_dev *dev = to_mdev(ibqp->device);
 432         struct mthca_qp *qp = to_mqp(ibqp);
 433         int err;
 434         struct mthca_mailbox *mailbox;
 435         struct mthca_qp_param *qp_param;
 436         struct mthca_qp_context *context;
 437         int mthca_state;
 438         u8 status;
 439
 440         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 441         if (IS_ERR(mailbox))
 442                 return PTR_ERR(mailbox);
 443
 444         err = mthca_QUERY_QP(dev, qp->qpn, 0, mailbox, &status);
 445         if (err)
 446                 goto out;
 447         if (status) {
 448                 mthca_warn(dev, "QUERY_QP returned status %02x\n", status);
 449                 err = -EINVAL;
 450                 goto out;
 451         }
 452
 453         qp_param    = mailbox->buf;
 454         context     = &qp_param->context;
 455         mthca_state = be32_to_cpu(context->flags) >> 28;
 456
 457         qp_attr->qp_state            = to_ib_qp_state(mthca_state);
 458         qp_attr->cur_qp_state        = qp_attr->qp_state;
 459         qp_attr->path_mtu            = context->mtu_msgmax >> 5;
 460         qp_attr->path_mig_state      =
 461                 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
 462         qp_attr->qkey                = be32_to_cpu(context->qkey);
 463         qp_attr->rq_psn              = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
 464         qp_attr->sq_psn              = be32_to_cpu(context->next_send_psn) & 0xffffff;
 465         qp_attr->dest_qp_num         = be32_to_cpu(context->remote_qpn) & 0xffffff;
 466         qp_attr->qp_access_flags     =
 467                 to_ib_qp_access_flags(be32_to_cpu(context->params2));
 468         qp_attr->cap.max_send_wr     = qp->sq.max;
 469         qp_attr->cap.max_recv_wr     = qp->rq.max;
 470         qp_attr->cap.max_send_sge    = qp->sq.max_gs;
 471         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
 472         qp_attr->cap.max_inline_data = qp->max_inline_data;
 473
 474         if (qp->transport == RC || qp->transport == UC) {
 475                 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
 476                 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
 477                 qp_attr->alt_pkey_index =
 478                         be32_to_cpu(context->alt_path.port_pkey) & 0x7f;
 479                 qp_attr->alt_port_num   = qp_attr->alt_ah_attr.port_num;
 480         }
 481
 482         qp_attr->pkey_index = be32_to_cpu(context->pri_path.port_pkey) & 0x7f;
 483         qp_attr->port_num   =
 484                 (be32_to_cpu(context->pri_path.port_pkey) >> 24) & 0x3;
 485
 486         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
 487         qp_attr->sq_draining = mthca_state == MTHCA_QP_STATE_DRAINING;
 488
 489         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
 490
 491         qp_attr->max_dest_rd_atomic =
 492                 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
 493         qp_attr->min_rnr_timer      =
 494                 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
 495         qp_attr->timeout            = context->pri_path.ackto >> 3;
 496         qp_attr->retry_cnt          = (be32_to_cpu(context->params1) >> 16) & 0x7;
 497         qp_attr->rnr_retry          = context->pri_path.rnr_retry >> 5;
 498         qp_attr->alt_timeout        = context->alt_path.ackto >> 3;
 499         qp_init_attr->cap           = qp_attr->cap;
 500
 501 out:
 502         mthca_free_mailbox(dev, mailbox);
 503         return err;
 504 }
 505
 506 static int mthca_path_set(struct mthca_dev *dev, struct ib_ah_attr *ah,
 507                           struct mthca_qp_path *path, u8 port)
 508 {
 509         path->g_mylmc     = ah->src_path_bits & 0x7f;
 510         path->rlid        = cpu_to_be16(ah->dlid);
 511         path->static_rate = mthca_get_rate(dev, ah->static_rate, port);
 512
 513         if (ah->ah_flags & IB_AH_GRH) {
 514                 if (ah->grh.sgid_index >= dev->limits.gid_table_len) {
 515                         mthca_dbg(dev, "sgid_index (%u) too large. max is %d\n",
 516                                   ah->grh.sgid_index, dev->limits.gid_table_len-1);
 517                         return -1;
 518                 }
 519
 520                 path->g_mylmc   |= 1 << 7;
 521                 path->mgid_index = ah->grh.sgid_index;
 522                 path->hop_limit  = ah->grh.hop_limit;
 523                 path->sl_tclass_flowlabel =
 524                         cpu_to_be32((ah->sl << 28)                |
 525                                     (ah->grh.traffic_class << 20) |
 526                                     (ah->grh.flow_label));
 527                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
 528         } else
 529                 path->sl_tclass_flowlabel = cpu_to_be32(ah->sl << 28);
 530
 531         return 0;
 532 }
 533
 534 int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask,
 535                     struct ib_udata *udata)
 536 {
 537         struct mthca_dev *dev = to_mdev(ibqp->device);
 538         struct mthca_qp *qp = to_mqp(ibqp);
 539         enum ib_qp_state cur_state, new_state;
 540         struct mthca_mailbox *mailbox;
 541         struct mthca_qp_param *qp_param;
 542         struct mthca_qp_context *qp_context;
 543         u32 sqd_event = 0;
 544         u8 status;
 545         int err = -EINVAL;
 546
 547         mutex_lock(&qp->mutex);
 548
 549         if (attr_mask & IB_QP_CUR_STATE) {
 550                 cur_state = attr->cur_qp_state;
 551         } else {
 552                 spin_lock_irq(&qp->sq.lock);
 553                 spin_lock(&qp->rq.lock);
 554                 cur_state = qp->state;
 555                 spin_unlock(&qp->rq.lock);
 556                 spin_unlock_irq(&qp->sq.lock);
 557         }
 558
 559         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
 560
 561         if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask)) {
 562                 mthca_dbg(dev, "Bad QP transition (transport %d) "
 563                           "%d->%d with attr 0x%08x\n",
 564                           qp->transport, cur_state, new_state,
 565                           attr_mask);
 566                 goto out;
 567         }
 568
 569         if ((attr_mask & IB_QP_PKEY_INDEX) &&
 570              attr->pkey_index >= dev->limits.pkey_table_len) {
 571                 mthca_dbg(dev, "P_Key index (%u) too large. max is %d\n",
 572                           attr->pkey_index, dev->limits.pkey_table_len-1);
 573                 goto out;
 574         }
 575
 576         if ((attr_mask & IB_QP_PORT) &&
 577             (attr->port_num == 0 || attr->port_num > dev->limits.num_ports)) {
 578                 mthca_dbg(dev, "Port number (%u) is invalid\n", attr->port_num);
 579                 goto out;
 580         }
 581
 582         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
 583             attr->max_rd_atomic > dev->limits.max_qp_init_rdma) {
 584                 mthca_dbg(dev, "Max rdma_atomic as initiator %u too large (max is %d)\n",
 585                           attr->max_rd_atomic, dev->limits.max_qp_init_rdma);
 586                 goto out;
 587         }
 588
 589         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
 590             attr->max_dest_rd_atomic > 1 << dev->qp_table.rdb_shift) {
 591                 mthca_dbg(dev, "Max rdma_atomic as responder %u too large (max %d)\n",
 592                           attr->max_dest_rd_atomic, 1 << dev->qp_table.rdb_shift);
 593                 goto out;
 594         }
 595
 596         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 597         if (IS_ERR(mailbox)) {
 598                 err = PTR_ERR(mailbox);
 599                 goto out;
 600         }
 601         qp_param = mailbox->buf;
 602         qp_context = &qp_param->context;
 603         memset(qp_param, 0, sizeof *qp_param);
 604
 605         qp_context->flags      = cpu_to_be32((to_mthca_state(new_state) << 28) |
 606                                              (to_mthca_st(qp->transport) << 16));
 607         qp_context->flags     |= cpu_to_be32(MTHCA_QP_BIT_DE);
 608         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
 609                 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 610         else {
 611                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE);
 612                 switch (attr->path_mig_state) {
 613                 case IB_MIG_MIGRATED:
 614                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 615                         break;
 616                 case IB_MIG_REARM:
 617                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_REARM << 11);
 618                         break;
 619                 case IB_MIG_ARMED:
 620                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_ARMED << 11);
 621                         break;
 622                 }
 623         }
 624
 625         /* leave tavor_sched_queue as 0 */
 626
 627         if (qp->transport == MLX || qp->transport == UD)
 628                 qp_context->mtu_msgmax = (IB_MTU_2048 << 5) | 11;
 629         else if (attr_mask & IB_QP_PATH_MTU) {
 630                 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_2048) {
 631                         mthca_dbg(dev, "path MTU (%u) is invalid\n",
 632                                   attr->path_mtu);
 633                         goto out_mailbox;
 634                 }
 635                 qp_context->mtu_msgmax = (attr->path_mtu << 5) | 31;
 636         }
 637
 638         if (mthca_is_memfree(dev)) {
 639                 if (qp->rq.max)
 640                         qp_context->rq_size_stride = long_log2(qp->rq.max) << 3;
 641                 qp_context->rq_size_stride |= qp->rq.wqe_shift - 4;
 642
 643                 if (qp->sq.max)
 644                         qp_context->sq_size_stride = long_log2(qp->sq.max) << 3;
 645                 qp_context->sq_size_stride |= qp->sq.wqe_shift - 4;
 646         }
 647
 648         /* leave arbel_sched_queue as 0 */
 649
 650         if (qp->ibqp.uobject)
 651                 qp_context->usr_page =
 652                         cpu_to_be32(to_mucontext(qp->ibqp.uobject->context)->uar.index);
 653         else
 654                 qp_context->usr_page = cpu_to_be32(dev->driver_uar.index);
 655         qp_context->local_qpn  = cpu_to_be32(qp->qpn);
 656         if (attr_mask & IB_QP_DEST_QPN) {
 657                 qp_context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
 658         }
 659
 660         if (qp->transport == MLX)
 661                 qp_context->pri_path.port_pkey |=
 662                         cpu_to_be32(qp->port << 24);
 663         else {
 664                 if (attr_mask & IB_QP_PORT) {
 665                         qp_context->pri_path.port_pkey |=
 666                                 cpu_to_be32(attr->port_num << 24);
 667                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM);
 668                 }
 669         }
 670
 671         if (attr_mask & IB_QP_PKEY_INDEX) {
 672                 qp_context->pri_path.port_pkey |=
 673                         cpu_to_be32(attr->pkey_index);
 674                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX);
 675         }
 676
 677         if (attr_mask & IB_QP_RNR_RETRY) {
 678                 qp_context->alt_path.rnr_retry = qp_context->pri_path.rnr_retry =
 679                         attr->rnr_retry << 5;
 680                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY |
 681                                                         MTHCA_QP_OPTPAR_ALT_RNR_RETRY);
 682         }
 683
 684         if (attr_mask & IB_QP_AV) {
 685                 if (mthca_path_set(dev, &attr->ah_attr, &qp_context->pri_path,
 686                                    attr_mask & IB_QP_PORT ? attr->port_num : qp->port))
 687                         goto out_mailbox;
 688
 689                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH);
 690         }
 691
 692         if (attr_mask & IB_QP_TIMEOUT) {
 693                 qp_context->pri_path.ackto = attr->timeout << 3;
 694                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT);
 695         }
 696
 697         if (attr_mask & IB_QP_ALT_PATH) {
 698                 if (attr->alt_pkey_index >= dev->limits.pkey_table_len) {
 699                         mthca_dbg(dev, "Alternate P_Key index (%u) too large. max is %d\n",
 700                                   attr->alt_pkey_index, dev->limits.pkey_table_len-1);
 701                         goto out_mailbox;
 702                 }
 703
 704                 if (attr->alt_port_num == 0 || attr->alt_port_num > dev->limits.num_ports) {
 705                         mthca_dbg(dev, "Alternate port number (%u) is invalid\n",
 706                                 attr->alt_port_num);
 707                         goto out_mailbox;
 708                 }
 709
 710                 if (mthca_path_set(dev, &attr->alt_ah_attr, &qp_context->alt_path,
 711                                    attr->alt_ah_attr.port_num))
 712                         goto out_mailbox;
 713
 714                 qp_context->alt_path.port_pkey |= cpu_to_be32(attr->alt_pkey_index |
 715                                                               attr->alt_port_num << 24);
 716                 qp_context->alt_path.ackto = attr->alt_timeout << 3;
 717                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ALT_ADDR_PATH);
 718         }
 719
 720         /* leave rdd as 0 */
 721         qp_context->pd         = cpu_to_be32(to_mpd(ibqp->pd)->pd_num);
 722         /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */
 723         qp_context->wqe_lkey   = cpu_to_be32(qp->mr.ibmr.lkey);
 724         qp_context->params1    = cpu_to_be32((MTHCA_ACK_REQ_FREQ << 28) |
 725                                              (MTHCA_FLIGHT_LIMIT << 24) |
 726                                              MTHCA_QP_BIT_SWE);
 727         if (qp->sq_policy == IB_SIGNAL_ALL_WR)
 728                 qp_context->params1 |= cpu_to_be32(MTHCA_QP_BIT_SSC);
 729         if (attr_mask & IB_QP_RETRY_CNT) {
 730                 qp_context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
 731                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT);
 732         }
 733
 734         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
 735                 if (attr->max_rd_atomic) {
 736                         qp_context->params1 |=
 737                                 cpu_to_be32(MTHCA_QP_BIT_SRE |
 738                                             MTHCA_QP_BIT_SAE);
 739                         qp_context->params1 |=
 740                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
 741                 }
 742                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX);
 743         }
 744
 745         if (attr_mask & IB_QP_SQ_PSN)
 746                 qp_context->next_send_psn = cpu_to_be32(attr->sq_psn);
 747         qp_context->cqn_snd = cpu_to_be32(to_mcq(ibqp->send_cq)->cqn);
 748
 749         if (mthca_is_memfree(dev)) {
 750                 qp_context->snd_wqe_base_l = cpu_to_be32(qp->send_wqe_offset);
 751                 qp_context->snd_db_index   = cpu_to_be32(qp->sq.db_index);
 752         }
 753
 754         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
 755                 if (attr->max_dest_rd_atomic)
 756                         qp_context->params2 |=
 757                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
 758
 759                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX);
 760         }
 761
 762         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
 763                 qp_context->params2      |= get_hw_access_flags(qp, attr, attr_mask);
 764                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
 765                                                         MTHCA_QP_OPTPAR_RRE |
 766                                                         MTHCA_QP_OPTPAR_RAE);
 767         }
 768
 769         qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC);
 770
 771         if (ibqp->srq)
 772                 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RIC);
 773
 774         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
 775                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
 776                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT);
 777         }
 778         if (attr_mask & IB_QP_RQ_PSN)
 779                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
 780
 781         qp_context->ra_buff_indx =
 782                 cpu_to_be32(dev->qp_table.rdb_base +
 783                             ((qp->qpn & (dev->limits.num_qps - 1)) * MTHCA_RDB_ENTRY_SIZE <<
 784                              dev->qp_table.rdb_shift));
 785
 786         qp_context->cqn_rcv = cpu_to_be32(to_mcq(ibqp->recv_cq)->cqn);
 787
 788         if (mthca_is_memfree(dev))
 789                 qp_context->rcv_db_index   = cpu_to_be32(qp->rq.db_index);
 790
 791         if (attr_mask & IB_QP_QKEY) {
 792                 qp_context->qkey = cpu_to_be32(attr->qkey);
 793                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY);
 794         }
 795
 796         if (ibqp->srq)
 797                 qp_context->srqn = cpu_to_be32(1 << 24 |
 798                                                to_msrq(ibqp->srq)->srqn);
 799
 800         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
 801             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY               &&
 802             attr->en_sqd_async_notify)
 803                 sqd_event = 1 << 31;
 804
 805         err = mthca_MODIFY_QP(dev, cur_state, new_state, qp->qpn, 0,
 806                               mailbox, sqd_event, &status);
 807         if (err)
 808                 goto out_mailbox;
 809         if (status) {
 810                 mthca_warn(dev, "modify QP %d->%d returned status %02x.\n",
 811                            cur_state, new_state, status);
 812                 err = -EINVAL;
 813                 goto out_mailbox;
 814         }
 815
 816         qp->state = new_state;
 817         if (attr_mask & IB_QP_ACCESS_FLAGS)
 818                 qp->atomic_rd_en = attr->qp_access_flags;
 819         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
 820                 qp->resp_depth = attr->max_dest_rd_atomic;
 821         if (attr_mask & IB_QP_PORT)
 822                 qp->port = attr->port_num;
 823         if (attr_mask & IB_QP_ALT_PATH)
 824                 qp->alt_port = attr->alt_port_num;
 825
 826         if (is_sqp(dev, qp))
 827                 store_attrs(to_msqp(qp), attr, attr_mask);
 828
 829         /*
 830          * If we moved QP0 to RTR, bring the IB link up; if we moved
 831          * QP0 to RESET or ERROR, bring the link back down.
 832          */
 833         if (is_qp0(dev, qp)) {
 834                 if (cur_state != IB_QPS_RTR &&
 835                     new_state == IB_QPS_RTR)
 836                         init_port(dev, qp->port);
 837
 838                 if (cur_state != IB_QPS_RESET &&
 839                     cur_state != IB_QPS_ERR &&
 840                     (new_state == IB_QPS_RESET ||
 841                      new_state == IB_QPS_ERR))
 842                         mthca_CLOSE_IB(dev, qp->port, &status);
 843         }
 844
 845         /*
 846          * If we moved a kernel QP to RESET, clean up all old CQ
 847          * entries and reinitialize the QP.
 848          */
 849         if (new_state == IB_QPS_RESET && !qp->ibqp.uobject) {
 850                 mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq), qp->qpn,
 851                                qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
 852                 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
 853                         mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq), qp->qpn, NULL);
 854
 855                 mthca_wq_reset(&qp->sq);
 856                 qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
 857
 858                 mthca_wq_reset(&qp->rq);
 859                 qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
 860
 861                 if (mthca_is_memfree(dev)) {
 862                         *qp->sq.db = 0;
 863                         *qp->rq.db = 0;
 864                 }
 865         }
 866
 867 out_mailbox:
 868         mthca_free_mailbox(dev, mailbox);
 869
 870 out:
 871         mutex_unlock(&qp->mutex);
 872         return err;
 873 }
 874
 875 static int mthca_max_data_size(struct mthca_dev *dev, struct mthca_qp *qp, int desc_sz)
 876 {
 877         /*
 878          * Calculate the maximum size of WQE s/g segments, excluding
 879          * the next segment and other non-data segments.
 880          */
 881         int max_data_size = desc_sz - sizeof (struct mthca_next_seg);
 882
 883         switch (qp->transport) {
 884         case MLX:
 885                 max_data_size -= 2 * sizeof (struct mthca_data_seg);
 886                 break;
 887
 888         case UD:
 889                 if (mthca_is_memfree(dev))
 890                         max_data_size -= sizeof (struct mthca_arbel_ud_seg);
 891                 else
 892                         max_data_size -= sizeof (struct mthca_tavor_ud_seg);
 893                 break;
 894
 895         default:
 896                 max_data_size -= sizeof (struct mthca_raddr_seg);
 897                 break;
 898         }
 899
 900         return max_data_size;
 901 }
 902
 903 static inline int mthca_max_inline_data(struct mthca_pd *pd, int max_data_size)
 904 {
 905         /* We don't support inline data for kernel QPs (yet). */
 906         return pd->ibpd.uobject ? max_data_size - MTHCA_INLINE_HEADER_SIZE : 0;
 907 }
 908
 909 static void mthca_adjust_qp_caps(struct mthca_dev *dev,
 910                                  struct mthca_pd *pd,
 911                                  struct mthca_qp *qp)
 912 {
 913         int max_data_size = mthca_max_data_size(dev, qp,
 914                                                 min(dev->limits.max_desc_sz,
 915                                                     1 << qp->sq.wqe_shift));
 916
 917         qp->max_inline_data = mthca_max_inline_data(pd, max_data_size);
 918
 919         qp->sq.max_gs = min_t(int, dev->limits.max_sg,
 920                               max_data_size / sizeof (struct mthca_data_seg));
 921         qp->rq.max_gs = min_t(int, dev->limits.max_sg,
 922                                (min(dev->limits.max_desc_sz, 1 << qp->rq.wqe_shift) -
 923                                 sizeof (struct mthca_next_seg)) /
 924                                sizeof (struct mthca_data_seg));
 925 }
 926
 927 /*
 928  * Allocate and register buffer for WQEs.  qp->rq.max, sq.max,
 929  * rq.max_gs and sq.max_gs must all be assigned.
 930  * mthca_alloc_wqe_buf will calculate rq.wqe_shift and
 931  * sq.wqe_shift (as well as send_wqe_offset, is_direct, and
 932  * queue)
 933  */
 934 static int mthca_alloc_wqe_buf(struct mthca_dev *dev,
 935                                struct mthca_pd *pd,
 936                                struct mthca_qp *qp)
 937 {
 938         int size;
 939         int err = -ENOMEM;
 940
 941         size = sizeof (struct mthca_next_seg) +
 942                 qp->rq.max_gs * sizeof (struct mthca_data_seg);
 943
 944         if (size > dev->limits.max_desc_sz)
 945                 return -EINVAL;
 946
 947         for (qp->rq.wqe_shift = 6; 1 << qp->rq.wqe_shift < size;
 948              qp->rq.wqe_shift++)
 949                 ; /* nothing */
 950
 951         size = qp->sq.max_gs * sizeof (struct mthca_data_seg);
 952         switch (qp->transport) {
 953         case MLX:
 954                 size += 2 * sizeof (struct mthca_data_seg);
 955                 break;
 956
 957         case UD:
 958                 size += mthca_is_memfree(dev) ?
 959                         sizeof (struct mthca_arbel_ud_seg) :
 960                         sizeof (struct mthca_tavor_ud_seg);
 961                 break;
 962
 963         case UC:
 964                 size += sizeof (struct mthca_raddr_seg);
 965                 break;
 966
 967         case RC:
 968                 size += sizeof (struct mthca_raddr_seg);
 969                 /*
 970                  * An atomic op will require an atomic segment, a
 971                  * remote address segment and one scatter entry.
 972                  */
 973                 size = max_t(int, size,
 974                              sizeof (struct mthca_atomic_seg) +
 975                              sizeof (struct mthca_raddr_seg) +
 976                              sizeof (struct mthca_data_seg));
 977                 break;
 978
 979         default:
 980                 break;
 981         }
 982
 983         /* Make sure that we have enough space for a bind request */
 984         size = max_t(int, size, sizeof (struct mthca_bind_seg));
 985
 986         size += sizeof (struct mthca_next_seg);
 987
 988         if (size > dev->limits.max_desc_sz)
 989                 return -EINVAL;
 990
 991         for (qp->sq.wqe_shift = 6; 1 << qp->sq.wqe_shift < size;
 992              qp->sq.wqe_shift++)
 993                 ; /* nothing */
 994
 995         qp->send_wqe_offset = ALIGN(qp->rq.max << qp->rq.wqe_shift,
 996                                     1 << qp->sq.wqe_shift);
 997
 998         /*
 999          * If this is a userspace QP, we don't actually have to
1000          * allocate anything.  All we need is to calculate the WQE
1001          * sizes and the send_wqe_offset, so we're done now.
1002          */
1003         if (pd->ibpd.uobject)
1004                 return 0;
1005
1006         size = PAGE_ALIGN(qp->send_wqe_offset +
1007                           (qp->sq.max << qp->sq.wqe_shift));
1008
1009         qp->wrid = kmalloc((qp->rq.max + qp->sq.max) * sizeof (u64),
1010                            GFP_KERNEL);
1011         if (!qp->wrid)
1012                 goto err_out;
1013
1014         err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_QP_SIZE,
1015                               &qp->queue, &qp->is_direct, pd, 0, &qp->mr);
1016         if (err)
1017                 goto err_out;
1018
1019         return 0;
1020
1021 err_out:
1022         kfree(qp->wrid);
1023         return err;
1024 }
1025
1026 static void mthca_free_wqe_buf(struct mthca_dev *dev,
1027                                struct mthca_qp *qp)
1028 {
1029         mthca_buf_free(dev, PAGE_ALIGN(qp->send_wqe_offset +
1030                                        (qp->sq.max << qp->sq.wqe_shift)),
1031                        &qp->queue, qp->is_direct, &qp->mr);
1032         kfree(qp->wrid);
1033 }
1034
1035 static int mthca_map_memfree(struct mthca_dev *dev,
1036                              struct mthca_qp *qp)
1037 {
1038         int ret;
1039
1040         if (mthca_is_memfree(dev)) {
1041                 ret = mthca_table_get(dev, dev->qp_table.qp_table, qp->qpn);
1042                 if (ret)
1043                         return ret;
1044
1045                 ret = mthca_table_get(dev, dev->qp_table.eqp_table, qp->qpn);
1046                 if (ret)
1047                         goto err_qpc;
1048
1049                 ret = mthca_table_get(dev, dev->qp_table.rdb_table,
1050                                       qp->qpn << dev->qp_table.rdb_shift);
1051                 if (ret)
1052                         goto err_eqpc;
1053
1054         }
1055
1056         return 0;
1057
1058 err_eqpc:
1059         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1060
1061 err_qpc:
1062         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1063
1064         return ret;
1065 }
1066
1067 static void mthca_unmap_memfree(struct mthca_dev *dev,
1068                                 struct mthca_qp *qp)
1069 {
1070         mthca_table_put(dev, dev->qp_table.rdb_table,
1071                         qp->qpn << dev->qp_table.rdb_shift);
1072         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1073         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1074 }
1075
1076 static int mthca_alloc_memfree(struct mthca_dev *dev,
1077                                struct mthca_qp *qp)
1078 {
1079         int ret = 0;
1080
1081         if (mthca_is_memfree(dev)) {
1082                 qp->rq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_RQ,
1083                                                  qp->qpn, &qp->rq.db);
1084                 if (qp->rq.db_index < 0)
1085                         return ret;
1086
1087                 qp->sq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SQ,
1088                                                  qp->qpn, &qp->sq.db);
1089                 if (qp->sq.db_index < 0)
1090                         mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1091         }
1092
1093         return ret;
1094 }
1095
1096 static void mthca_free_memfree(struct mthca_dev *dev,
1097                                struct mthca_qp *qp)
1098 {
1099         if (mthca_is_memfree(dev)) {
1100                 mthca_free_db(dev, MTHCA_DB_TYPE_SQ, qp->sq.db_index);
1101                 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1102         }
1103 }
1104
1105 static int mthca_alloc_qp_common(struct mthca_dev *dev,
1106                                  struct mthca_pd *pd,
1107                                  struct mthca_cq *send_cq,
1108                                  struct mthca_cq *recv_cq,
1109                                  enum ib_sig_type send_policy,
1110                                  struct mthca_qp *qp)
1111 {
1112         int ret;
1113         int i;
1114
1115         qp->refcount = 1;
1116         init_waitqueue_head(&qp->wait);
1117         mutex_init(&qp->mutex);
1118         qp->state        = IB_QPS_RESET;
1119         qp->atomic_rd_en = 0;
1120         qp->resp_depth   = 0;
1121         qp->sq_policy    = send_policy;
1122         mthca_wq_reset(&qp->sq);
1123         mthca_wq_reset(&qp->rq);
1124
1125         spin_lock_init(&qp->sq.lock);
1126         spin_lock_init(&qp->rq.lock);
1127
1128         ret = mthca_map_memfree(dev, qp);
1129         if (ret)
1130                 return ret;
1131
1132         ret = mthca_alloc_wqe_buf(dev, pd, qp);
1133         if (ret) {
1134                 mthca_unmap_memfree(dev, qp);
1135                 return ret;
1136         }
1137
1138         mthca_adjust_qp_caps(dev, pd, qp);
1139
1140         /*
1141          * If this is a userspace QP, we're done now.  The doorbells
1142          * will be allocated and buffers will be initialized in
1143          * userspace.
1144          */
1145         if (pd->ibpd.uobject)
1146                 return 0;
1147
1148         ret = mthca_alloc_memfree(dev, qp);
1149         if (ret) {
1150                 mthca_free_wqe_buf(dev, qp);
1151                 mthca_unmap_memfree(dev, qp);
1152                 return ret;
1153         }
1154
1155         if (mthca_is_memfree(dev)) {
1156                 struct mthca_next_seg *next;
1157                 struct mthca_data_seg *scatter;
1158                 int size = (sizeof (struct mthca_next_seg) +
1159                             qp->rq.max_gs * sizeof (struct mthca_data_seg)) / 16;
1160
1161                 for (i = 0; i < qp->rq.max; ++i) {
1162                         next = get_recv_wqe(qp, i);
1163                         next->nda_op = cpu_to_be32(((i + 1) & (qp->rq.max - 1)) <<
1164                                                    qp->rq.wqe_shift);
1165                         next->ee_nds = cpu_to_be32(size);
1166
1167                         for (scatter = (void *) (next + 1);
1168                              (void *) scatter < (void *) next + (1 << qp->rq.wqe_shift);
1169                              ++scatter)
1170                                 scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
1171                 }
1172
1173                 for (i = 0; i < qp->sq.max; ++i) {
1174                         next = get_send_wqe(qp, i);
1175                         next->nda_op = cpu_to_be32((((i + 1) & (qp->sq.max - 1)) <<
1176                                                     qp->sq.wqe_shift) +
1177                                                    qp->send_wqe_offset);
1178                 }
1179         }
1180
1181         qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
1182         qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
1183
1184         return 0;
1185 }
1186
1187 static int mthca_set_qp_size(struct mthca_dev *dev, struct ib_qp_cap *cap,
1188                              struct mthca_pd *pd, struct mthca_qp *qp)
1189 {
1190         int max_data_size = mthca_max_data_size(dev, qp, dev->limits.max_desc_sz);
1191
1192         /* Sanity check QP size before proceeding */
1193         if (cap->max_send_wr     > dev->limits.max_wqes ||
1194             cap->max_recv_wr     > dev->limits.max_wqes ||
1195             cap->max_send_sge    > dev->limits.max_sg   ||
1196             cap->max_recv_sge    > dev->limits.max_sg   ||
1197             cap->max_inline_data > mthca_max_inline_data(pd, max_data_size))
1198                 return -EINVAL;
1199
1200         /*
1201          * For MLX transport we need 2 extra S/G entries:
1202          * one for the header and one for the checksum at the end
1203          */
1204         if (qp->transport == MLX && cap->max_recv_sge + 2 > dev->limits.max_sg)
1205                 return -EINVAL;
1206
1207         if (mthca_is_memfree(dev)) {
1208                 qp->rq.max = cap->max_recv_wr ?
1209                         roundup_pow_of_two(cap->max_recv_wr) : 0;
1210                 qp->sq.max = cap->max_send_wr ?
1211                         roundup_pow_of_two(cap->max_send_wr) : 0;
1212         } else {
1213                 qp->rq.max = cap->max_recv_wr;
1214                 qp->sq.max = cap->max_send_wr;
1215         }
1216
1217         qp->rq.max_gs = cap->max_recv_sge;
1218         qp->sq.max_gs = max_t(int, cap->max_send_sge,
1219                               ALIGN(cap->max_inline_data + MTHCA_INLINE_HEADER_SIZE,
1220                                     MTHCA_INLINE_CHUNK_SIZE) /
1221                               sizeof (struct mthca_data_seg));
1222
1223         return 0;
1224 }
1225
1226 int mthca_alloc_qp(struct mthca_dev *dev,
1227                    struct mthca_pd *pd,
1228                    struct mthca_cq *send_cq,
1229                    struct mthca_cq *recv_cq,
1230                    enum ib_qp_type type,
1231                    enum ib_sig_type send_policy,
1232                    struct ib_qp_cap *cap,
1233                    struct mthca_qp *qp)
1234 {
1235         int err;
1236
1237         switch (type) {
1238         case IB_QPT_RC: qp->transport = RC; break;
1239         case IB_QPT_UC: qp->transport = UC; break;
1240         case IB_QPT_UD: qp->transport = UD; break;
1241         default: return -EINVAL;
1242         }
1243
1244         err = mthca_set_qp_size(dev, cap, pd, qp);
1245         if (err)
1246                 return err;
1247
1248         qp->qpn = mthca_alloc(&dev->qp_table.alloc);
1249         if (qp->qpn == -1)
1250                 return -ENOMEM;
1251
1252         /* initialize port to zero for error-catching. */
1253         qp->port = 0;
1254
1255         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1256                                     send_policy, qp);
1257         if (err) {
1258                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1259                 return err;
1260         }
1261
1262         spin_lock_irq(&dev->qp_table.lock);
1263         mthca_array_set(&dev->qp_table.qp,
1264                         qp->qpn & (dev->limits.num_qps - 1), qp);
1265         spin_unlock_irq(&dev->qp_table.lock);
1266
1267         return 0;
1268 }
1269
1270 static void mthca_lock_cqs(struct mthca_cq *send_cq, struct mthca_cq *recv_cq)
1271 {
1272         if (send_cq == recv_cq)
1273                 spin_lock_irq(&send_cq->lock);
1274         else if (send_cq->cqn < recv_cq->cqn) {
1275                 spin_lock_irq(&send_cq->lock);
1276                 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
1277         } else {
1278                 spin_lock_irq(&recv_cq->lock);
1279                 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
1280         }
1281 }
1282
1283 static void mthca_unlock_cqs(struct mthca_cq *send_cq, struct mthca_cq *recv_cq)
1284 {
1285         if (send_cq == recv_cq)
1286                 spin_unlock_irq(&send_cq->lock);
1287         else if (send_cq->cqn < recv_cq->cqn) {
1288                 spin_unlock(&recv_cq->lock);
1289                 spin_unlock_irq(&send_cq->lock);
1290         } else {
1291                 spin_unlock(&send_cq->lock);
1292                 spin_unlock_irq(&recv_cq->lock);
1293         }
1294 }
1295
1296 int mthca_alloc_sqp(struct mthca_dev *dev,
1297                     struct mthca_pd *pd,
1298                     struct mthca_cq *send_cq,
1299                     struct mthca_cq *recv_cq,
1300                     enum ib_sig_type send_policy,
1301                     struct ib_qp_cap *cap,
1302                     int qpn,
1303                     int port,
1304                     struct mthca_sqp *sqp)
1305 {
1306         u32 mqpn = qpn * 2 + dev->qp_table.sqp_start + port - 1;
1307         int err;
1308
1309         sqp->qp.transport = MLX;
1310         err = mthca_set_qp_size(dev, cap, pd, &sqp->qp);
1311         if (err)
1312                 return err;
1313
1314         sqp->header_buf_size = sqp->qp.sq.max * MTHCA_UD_HEADER_SIZE;
1315         sqp->header_buf = dma_alloc_coherent(&dev->pdev->dev, sqp->header_buf_size,
1316                                              &sqp->header_dma, GFP_KERNEL);
1317         if (!sqp->header_buf)
1318                 return -ENOMEM;
1319
1320         spin_lock_irq(&dev->qp_table.lock);
1321         if (mthca_array_get(&dev->qp_table.qp, mqpn))
1322                 err = -EBUSY;
1323         else
1324                 mthca_array_set(&dev->qp_table.qp, mqpn, sqp);
1325         spin_unlock_irq(&dev->qp_table.lock);
1326
1327         if (err)
1328                 goto err_out;
1329
1330         sqp->qp.port      = port;
1331         sqp->qp.qpn       = mqpn;
1332         sqp->qp.transport = MLX;
1333
1334         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1335                                     send_policy, &sqp->qp);
1336         if (err)
1337                 goto err_out_free;
1338
1339         atomic_inc(&pd->sqp_count);
1340
1341         return 0;
1342
1343  err_out_free:
1344         /*
1345          * Lock CQs here, so that CQ polling code can do QP lookup
1346          * without taking a lock.
1347          */
1348         mthca_lock_cqs(send_cq, recv_cq);
1349
1350         spin_lock(&dev->qp_table.lock);
1351         mthca_array_clear(&dev->qp_table.qp, mqpn);
1352         spin_unlock(&dev->qp_table.lock);
1353
1354         mthca_unlock_cqs(send_cq, recv_cq);
1355
1356  err_out:
1357         dma_free_coherent(&dev->pdev->dev, sqp->header_buf_size,
1358                           sqp->header_buf, sqp->header_dma);
1359
1360         return err;
1361 }
1362
1363 static inline int get_qp_refcount(struct mthca_dev *dev, struct mthca_qp *qp)
1364 {
1365         int c;
1366
1367         spin_lock_irq(&dev->qp_table.lock);
1368         c = qp->refcount;
1369         spin_unlock_irq(&dev->qp_table.lock);
1370
1371         return c;
1372 }
1373
1374 void mthca_free_qp(struct mthca_dev *dev,
1375                    struct mthca_qp *qp)
1376 {
1377         u8 status;
1378         struct mthca_cq *send_cq;
1379         struct mthca_cq *recv_cq;
1380
1381         send_cq = to_mcq(qp->ibqp.send_cq);
1382         recv_cq = to_mcq(qp->ibqp.recv_cq);
1383
1384         /*
1385          * Lock CQs here, so that CQ polling code can do QP lookup
1386          * without taking a lock.
1387          */
1388         mthca_lock_cqs(send_cq, recv_cq);
1389
1390         spin_lock(&dev->qp_table.lock);
1391         mthca_array_clear(&dev->qp_table.qp,
1392                           qp->qpn & (dev->limits.num_qps - 1));
1393         --qp->refcount;
1394         spin_unlock(&dev->qp_table.lock);
1395
1396         mthca_unlock_cqs(send_cq, recv_cq);
1397
1398         wait_event(qp->wait, !get_qp_refcount(dev, qp));
1399
1400         if (qp->state != IB_QPS_RESET)
1401                 mthca_MODIFY_QP(dev, qp->state, IB_QPS_RESET, qp->qpn, 0,
1402                                 NULL, 0, &status);
1403
1404         /*
1405          * If this is a userspace QP, the buffers, MR, CQs and so on
1406          * will be cleaned up in userspace, so all we have to do is
1407          * unref the mem-free tables and free the QPN in our table.
1408          */
1409         if (!qp->ibqp.uobject) {
1410                 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq), qp->qpn,
1411                                qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1412                 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
1413                         mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq), qp->qpn,
1414                                        qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1415
1416                 mthca_free_memfree(dev, qp);
1417                 mthca_free_wqe_buf(dev, qp);
1418         }
1419
1420         mthca_unmap_memfree(dev, qp);
1421
1422         if (is_sqp(dev, qp)) {
1423                 atomic_dec(&(to_mpd(qp->ibqp.pd)->sqp_count));
1424                 dma_free_coherent(&dev->pdev->dev,
1425                                   to_msqp(qp)->header_buf_size,
1426                                   to_msqp(qp)->header_buf,
1427                                   to_msqp(qp)->header_dma);
1428         } else
1429                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1430 }
1431
1432 /* Create UD header for an MLX send and build a data segment for it */
1433 static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp,
1434                             int ind, struct ib_send_wr *wr,
1435                             struct mthca_mlx_seg *mlx,
1436                             struct mthca_data_seg *data)
1437 {
1438         int header_size;
1439         int err;
1440         u16 pkey;
1441
1442         ib_ud_header_init(256, /* assume a MAD */
1443                           mthca_ah_grh_present(to_mah(wr->wr.ud.ah)),
1444                           &sqp->ud_header);
1445
1446         err = mthca_read_ah(dev, to_mah(wr->wr.ud.ah), &sqp->ud_header);
1447         if (err)
1448                 return err;
1449         mlx->flags &= ~cpu_to_be32(MTHCA_NEXT_SOLICIT | 1);
1450         mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MTHCA_MLX_VL15 : 0) |
1451                                   (sqp->ud_header.lrh.destination_lid ==
1452                                    IB_LID_PERMISSIVE ? MTHCA_MLX_SLR : 0) |
1453                                   (sqp->ud_header.lrh.service_level << 8));
1454         mlx->rlid = sqp->ud_header.lrh.destination_lid;
1455         mlx->vcrc = 0;
1456
1457         switch (wr->opcode) {
1458         case IB_WR_SEND:
1459                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1460                 sqp->ud_header.immediate_present = 0;
1461                 break;
1462         case IB_WR_SEND_WITH_IMM:
1463                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1464                 sqp->ud_header.immediate_present = 1;
1465                 sqp->ud_header.immediate_data = wr->imm_data;
1466                 break;
1467         default:
1468                 return -EINVAL;
1469         }
1470
1471         sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
1472         if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1473                 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1474         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1475         if (!sqp->qp.ibqp.qp_num)
1476                 ib_get_cached_pkey(&dev->ib_dev, sqp->qp.port,
1477                                    sqp->pkey_index, &pkey);
1478         else
1479                 ib_get_cached_pkey(&dev->ib_dev, sqp->qp.port,
1480                                    wr->wr.ud.pkey_index, &pkey);
1481         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1482         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1483         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1484         sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1485                                                sqp->qkey : wr->wr.ud.remote_qkey);
1486         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1487
1488         header_size = ib_ud_header_pack(&sqp->ud_header,
1489                                         sqp->header_buf +
1490                                         ind * MTHCA_UD_HEADER_SIZE);
1491
1492         data->byte_count = cpu_to_be32(header_size);
1493         data->lkey       = cpu_to_be32(to_mpd(sqp->qp.ibqp.pd)->ntmr.ibmr.lkey);
1494         data->addr       = cpu_to_be64(sqp->header_dma +
1495                                        ind * MTHCA_UD_HEADER_SIZE);
1496
1497         return 0;
1498 }
1499
1500 static inline int mthca_wq_overflow(struct mthca_wq *wq, int nreq,
1501                                     struct ib_cq *ib_cq)
1502 {
1503         unsigned cur;
1504         struct mthca_cq *cq;
1505
1506         cur = wq->head - wq->tail;
1507         if (likely(cur + nreq < wq->max))
1508                 return 0;
1509
1510         cq = to_mcq(ib_cq);
1511         spin_lock(&cq->lock);
1512         cur = wq->head - wq->tail;
1513         spin_unlock(&cq->lock);
1514
1515         return cur + nreq >= wq->max;
1516 }
1517
1518 int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1519                           struct ib_send_wr **bad_wr)
1520 {
1521         struct mthca_dev *dev = to_mdev(ibqp->device);
1522         struct mthca_qp *qp = to_mqp(ibqp);
1523         void *wqe;
1524         void *prev_wqe;
1525         unsigned long flags;
1526         int err = 0;
1527         int nreq;
1528         int i;
1529         int size;
1530         int size0 = 0;
1531         u32 f0;
1532         int ind;
1533         u8 op0 = 0;
1534
1535         spin_lock_irqsave(&qp->sq.lock, flags);
1536
1537         /* XXX check that state is OK to post send */
1538
1539         ind = qp->sq.next_ind;
1540
1541         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1542                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1543                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1544                                         " %d max, %d nreq)\n", qp->qpn,
1545                                         qp->sq.head, qp->sq.tail,
1546                                         qp->sq.max, nreq);
1547                         err = -ENOMEM;
1548                         *bad_wr = wr;
1549                         goto out;
1550                 }
1551
1552                 wqe = get_send_wqe(qp, ind);
1553                 prev_wqe = qp->sq.last;
1554                 qp->sq.last = wqe;
1555
1556                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1557                 ((struct mthca_next_seg *) wqe)->ee_nds = 0;
1558                 ((struct mthca_next_seg *) wqe)->flags =
1559                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1560                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1561                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1562                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1563                         cpu_to_be32(1);
1564                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1565                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1566                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1567
1568                 wqe += sizeof (struct mthca_next_seg);
1569                 size = sizeof (struct mthca_next_seg) / 16;
1570
1571                 switch (qp->transport) {
1572                 case RC:
1573                         switch (wr->opcode) {
1574                         case IB_WR_ATOMIC_CMP_AND_SWP:
1575                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1576                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1577                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1578                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1579                                         cpu_to_be32(wr->wr.atomic.rkey);
1580                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1581
1582                                 wqe += sizeof (struct mthca_raddr_seg);
1583
1584                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1585                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1586                                                 cpu_to_be64(wr->wr.atomic.swap);
1587                                         ((struct mthca_atomic_seg *) wqe)->compare =
1588                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1589                                 } else {
1590                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1591                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1592                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1593                                 }
1594
1595                                 wqe += sizeof (struct mthca_atomic_seg);
1596                                 size += (sizeof (struct mthca_raddr_seg) +
1597                                          sizeof (struct mthca_atomic_seg)) / 16;
1598                                 break;
1599
1600                         case IB_WR_RDMA_WRITE:
1601                         case IB_WR_RDMA_WRITE_WITH_IMM:
1602                         case IB_WR_RDMA_READ:
1603                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1604                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1605                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1606                                         cpu_to_be32(wr->wr.rdma.rkey);
1607                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1608                                 wqe += sizeof (struct mthca_raddr_seg);
1609                                 size += sizeof (struct mthca_raddr_seg) / 16;
1610                                 break;
1611
1612                         default:
1613                                 /* No extra segments required for sends */
1614                                 break;
1615                         }
1616
1617                         break;
1618
1619                 case UC:
1620                         switch (wr->opcode) {
1621                         case IB_WR_RDMA_WRITE:
1622                         case IB_WR_RDMA_WRITE_WITH_IMM:
1623                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1624                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1625                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1626                                         cpu_to_be32(wr->wr.rdma.rkey);
1627                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1628                                 wqe += sizeof (struct mthca_raddr_seg);
1629                                 size += sizeof (struct mthca_raddr_seg) / 16;
1630                                 break;
1631
1632                         default:
1633                                 /* No extra segments required for sends */
1634                                 break;
1635                         }
1636
1637                         break;
1638
1639                 case UD:
1640                         ((struct mthca_tavor_ud_seg *) wqe)->lkey =
1641                                 cpu_to_be32(to_mah(wr->wr.ud.ah)->key);
1642                         ((struct mthca_tavor_ud_seg *) wqe)->av_addr =
1643                                 cpu_to_be64(to_mah(wr->wr.ud.ah)->avdma);
1644                         ((struct mthca_tavor_ud_seg *) wqe)->dqpn =
1645                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1646                         ((struct mthca_tavor_ud_seg *) wqe)->qkey =
1647                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1648
1649                         wqe += sizeof (struct mthca_tavor_ud_seg);
1650                         size += sizeof (struct mthca_tavor_ud_seg) / 16;
1651                         break;
1652
1653                 case MLX:
1654                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1655                                                wqe - sizeof (struct mthca_next_seg),
1656                                                wqe);
1657                         if (err) {
1658                                 *bad_wr = wr;
1659                                 goto out;
1660                         }
1661                         wqe += sizeof (struct mthca_data_seg);
1662                         size += sizeof (struct mthca_data_seg) / 16;
1663                         break;
1664                 }
1665
1666                 if (wr->num_sge > qp->sq.max_gs) {
1667                         mthca_err(dev, "too many gathers\n");
1668                         err = -EINVAL;
1669                         *bad_wr = wr;
1670                         goto out;
1671                 }
1672
1673                 for (i = 0; i < wr->num_sge; ++i) {
1674                         ((struct mthca_data_seg *) wqe)->byte_count =
1675                                 cpu_to_be32(wr->sg_list[i].length);
1676                         ((struct mthca_data_seg *) wqe)->lkey =
1677                                 cpu_to_be32(wr->sg_list[i].lkey);
1678                         ((struct mthca_data_seg *) wqe)->addr =
1679                                 cpu_to_be64(wr->sg_list[i].addr);
1680                         wqe += sizeof (struct mthca_data_seg);
1681                         size += sizeof (struct mthca_data_seg) / 16;
1682                 }
1683
1684                 /* Add one more inline data segment for ICRC */
1685                 if (qp->transport == MLX) {
1686                         ((struct mthca_data_seg *) wqe)->byte_count =
1687                                 cpu_to_be32((1 << 31) | 4);
1688                         ((u32 *) wqe)[1] = 0;
1689                         wqe += sizeof (struct mthca_data_seg);
1690                         size += sizeof (struct mthca_data_seg) / 16;
1691                 }
1692
1693                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1694
1695                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1696                         mthca_err(dev, "opcode invalid\n");
1697                         err = -EINVAL;
1698                         *bad_wr = wr;
1699                         goto out;
1700                 }
1701
1702                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1703                         cpu_to_be32(((ind << qp->sq.wqe_shift) +
1704                                      qp->send_wqe_offset) |
1705                                     mthca_opcode[wr->opcode]);
1706                 wmb();
1707                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1708                         cpu_to_be32((size0 ? 0 : MTHCA_NEXT_DBD) | size |
1709                                     ((wr->send_flags & IB_SEND_FENCE) ?
1710                                     MTHCA_NEXT_FENCE : 0));
1711
1712                 if (!size0) {
1713                         size0 = size;
1714                         op0   = mthca_opcode[wr->opcode];
1715                         f0    = wr->send_flags & IB_SEND_FENCE ?
1716                                 MTHCA_SEND_DOORBELL_FENCE : 0;
1717                 }
1718
1719                 ++ind;
1720                 if (unlikely(ind >= qp->sq.max))
1721                         ind -= qp->sq.max;
1722         }
1723
1724 out:
1725         if (likely(nreq)) {
1726                 __be32 doorbell[2];
1727
1728                 doorbell[0] = cpu_to_be32(((qp->sq.next_ind << qp->sq.wqe_shift) +
1729                                            qp->send_wqe_offset) | f0 | op0);
1730                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1731
1732                 wmb();
1733
1734                 mthca_write64(doorbell,
1735                               dev->kar + MTHCA_SEND_DOORBELL,
1736                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1737                 /*
1738                  * Make sure doorbells don't leak out of SQ spinlock
1739                  * and reach the HCA out of order:
1740                  */
1741                 mmiowb();
1742         }
1743
1744         qp->sq.next_ind = ind;
1745         qp->sq.head    += nreq;
1746
1747         spin_unlock_irqrestore(&qp->sq.lock, flags);
1748         return err;
1749 }
1750
1751 int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1752                              struct ib_recv_wr **bad_wr)
1753 {
1754         struct mthca_dev *dev = to_mdev(ibqp->device);
1755         struct mthca_qp *qp = to_mqp(ibqp);
1756         __be32 doorbell[2];
1757         unsigned long flags;
1758         int err = 0;
1759         int nreq;
1760         int i;
1761         int size;
1762         int size0 = 0;
1763         int ind;
1764         void *wqe;
1765         void *prev_wqe;
1766
1767         spin_lock_irqsave(&qp->rq.lock, flags);
1768
1769         /* XXX check that state is OK to post receive */
1770
1771         ind = qp->rq.next_ind;
1772
1773         for (nreq = 0; wr; wr = wr->next) {
1774                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1775                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
1776                                         " %d max, %d nreq)\n", qp->qpn,
1777                                         qp->rq.head, qp->rq.tail,
1778                                         qp->rq.max, nreq);
1779                         err = -ENOMEM;
1780                         *bad_wr = wr;
1781                         goto out;
1782                 }
1783
1784                 wqe = get_recv_wqe(qp, ind);
1785                 prev_wqe = qp->rq.last;
1786                 qp->rq.last = wqe;
1787
1788                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1789                 ((struct mthca_next_seg *) wqe)->ee_nds =
1790                         cpu_to_be32(MTHCA_NEXT_DBD);
1791                 ((struct mthca_next_seg *) wqe)->flags = 0;
1792
1793                 wqe += sizeof (struct mthca_next_seg);
1794                 size = sizeof (struct mthca_next_seg) / 16;
1795
1796                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1797                         err = -EINVAL;
1798                         *bad_wr = wr;
1799                         goto out;
1800                 }
1801
1802                 for (i = 0; i < wr->num_sge; ++i) {
1803                         ((struct mthca_data_seg *) wqe)->byte_count =
1804                                 cpu_to_be32(wr->sg_list[i].length);
1805                         ((struct mthca_data_seg *) wqe)->lkey =
1806                                 cpu_to_be32(wr->sg_list[i].lkey);
1807                         ((struct mthca_data_seg *) wqe)->addr =
1808                                 cpu_to_be64(wr->sg_list[i].addr);
1809                         wqe += sizeof (struct mthca_data_seg);
1810                         size += sizeof (struct mthca_data_seg) / 16;
1811                 }
1812
1813                 qp->wrid[ind] = wr->wr_id;
1814
1815                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1816                         cpu_to_be32((ind << qp->rq.wqe_shift) | 1);
1817                 wmb();
1818                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1819                         cpu_to_be32(MTHCA_NEXT_DBD | size);
1820
1821                 if (!size0)
1822                         size0 = size;
1823
1824                 ++ind;
1825                 if (unlikely(ind >= qp->rq.max))
1826                         ind -= qp->rq.max;
1827
1828                 ++nreq;
1829                 if (unlikely(nreq == MTHCA_TAVOR_MAX_WQES_PER_RECV_DB)) {
1830                         nreq = 0;
1831
1832                         doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1833                         doorbell[1] = cpu_to_be32(qp->qpn << 8);
1834
1835                         wmb();
1836
1837                         mthca_write64(doorbell,
1838                                       dev->kar + MTHCA_RECEIVE_DOORBELL,
1839                                       MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1840
1841                         qp->rq.head += MTHCA_TAVOR_MAX_WQES_PER_RECV_DB;
1842                         size0 = 0;
1843                 }
1844         }
1845
1846 out:
1847         if (likely(nreq)) {
1848                 doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1849                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | nreq);
1850
1851                 wmb();
1852
1853                 mthca_write64(doorbell,
1854                               dev->kar + MTHCA_RECEIVE_DOORBELL,
1855                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1856         }
1857
1858         qp->rq.next_ind = ind;
1859         qp->rq.head    += nreq;
1860
1861         /*
1862          * Make sure doorbells don't leak out of RQ spinlock and reach
1863          * the HCA out of order:
1864          */
1865         mmiowb();
1866
1867         spin_unlock_irqrestore(&qp->rq.lock, flags);
1868         return err;
1869 }
1870
1871 int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1872                           struct ib_send_wr **bad_wr)
1873 {
1874         struct mthca_dev *dev = to_mdev(ibqp->device);
1875         struct mthca_qp *qp = to_mqp(ibqp);
1876         __be32 doorbell[2];
1877         void *wqe;
1878         void *prev_wqe;
1879         unsigned long flags;
1880         int err = 0;
1881         int nreq;
1882         int i;
1883         int size;
1884         int size0 = 0;
1885         u32 f0;
1886         int ind;
1887         u8 op0 = 0;
1888
1889         spin_lock_irqsave(&qp->sq.lock, flags);
1890
1891         /* XXX check that state is OK to post send */
1892
1893         ind = qp->sq.head & (qp->sq.max - 1);
1894
1895         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1896                 if (unlikely(nreq == MTHCA_ARBEL_MAX_WQES_PER_SEND_DB)) {
1897                         nreq = 0;
1898
1899                         doorbell[0] = cpu_to_be32((MTHCA_ARBEL_MAX_WQES_PER_SEND_DB << 24) |
1900                                                   ((qp->sq.head & 0xffff) << 8) |
1901                                                   f0 | op0);
1902                         doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1903
1904                         qp->sq.head += MTHCA_ARBEL_MAX_WQES_PER_SEND_DB;
1905                         size0 = 0;
1906
1907                         /*
1908                          * Make sure that descriptors are written before
1909                          * doorbell record.
1910                          */
1911                         wmb();
1912                         *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
1913
1914                         /*
1915                          * Make sure doorbell record is written before we
1916                          * write MMIO send doorbell.
1917                          */
1918                         wmb();
1919                         mthca_write64(doorbell,
1920                                       dev->kar + MTHCA_SEND_DOORBELL,
1921                                       MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1922                 }
1923
1924                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1925                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1926                                         " %d max, %d nreq)\n", qp->qpn,
1927                                         qp->sq.head, qp->sq.tail,
1928                                         qp->sq.max, nreq);
1929                         err = -ENOMEM;
1930                         *bad_wr = wr;
1931                         goto out;
1932                 }
1933
1934                 wqe = get_send_wqe(qp, ind);
1935                 prev_wqe = qp->sq.last;
1936                 qp->sq.last = wqe;
1937
1938                 ((struct mthca_next_seg *) wqe)->flags =
1939                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1940                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1941                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1942                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1943                         cpu_to_be32(1);
1944                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1945                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1946                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1947
1948                 wqe += sizeof (struct mthca_next_seg);
1949                 size = sizeof (struct mthca_next_seg) / 16;
1950
1951                 switch (qp->transport) {
1952                 case RC:
1953                         switch (wr->opcode) {
1954                         case IB_WR_ATOMIC_CMP_AND_SWP:
1955                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1956                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1957                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1958                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1959                                         cpu_to_be32(wr->wr.atomic.rkey);
1960                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1961
1962                                 wqe += sizeof (struct mthca_raddr_seg);
1963
1964                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1965                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1966                                                 cpu_to_be64(wr->wr.atomic.swap);
1967                                         ((struct mthca_atomic_seg *) wqe)->compare =
1968                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1969                                 } else {
1970                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1971                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1972                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1973                                 }
1974
1975                                 wqe += sizeof (struct mthca_atomic_seg);
1976                                 size += (sizeof (struct mthca_raddr_seg) +
1977                                          sizeof (struct mthca_atomic_seg)) / 16;
1978                                 break;
1979
1980                         case IB_WR_RDMA_READ:
1981                         case IB_WR_RDMA_WRITE:
1982                         case IB_WR_RDMA_WRITE_WITH_IMM:
1983                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1984                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1985                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1986                                         cpu_to_be32(wr->wr.rdma.rkey);
1987                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1988                                 wqe += sizeof (struct mthca_raddr_seg);
1989                                 size += sizeof (struct mthca_raddr_seg) / 16;
1990                                 break;
1991
1992                         default:
1993                                 /* No extra segments required for sends */
1994                                 break;
1995                         }
1996
1997                         break;
1998
1999                 case UC:
2000                         switch (wr->opcode) {
2001                         case IB_WR_RDMA_WRITE:
2002                         case IB_WR_RDMA_WRITE_WITH_IMM:
2003                                 ((struct mthca_raddr_seg *) wqe)->raddr =
2004                                         cpu_to_be64(wr->wr.rdma.remote_addr);
2005                                 ((struct mthca_raddr_seg *) wqe)->rkey =
2006                                         cpu_to_be32(wr->wr.rdma.rkey);
2007                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
2008                                 wqe += sizeof (struct mthca_raddr_seg);
2009                                 size += sizeof (struct mthca_raddr_seg) / 16;
2010                                 break;
2011
2012                         default:
2013                                 /* No extra segments required for sends */
2014                                 break;
2015                         }
2016
2017                         break;
2018
2019                 case UD:
2020                         memcpy(((struct mthca_arbel_ud_seg *) wqe)->av,
2021                                to_mah(wr->wr.ud.ah)->av, MTHCA_AV_SIZE);
2022                         ((struct mthca_arbel_ud_seg *) wqe)->dqpn =
2023                                 cpu_to_be32(wr->wr.ud.remote_qpn);
2024                         ((struct mthca_arbel_ud_seg *) wqe)->qkey =
2025                                 cpu_to_be32(wr->wr.ud.remote_qkey);
2026
2027                         wqe += sizeof (struct mthca_arbel_ud_seg);
2028                         size += sizeof (struct mthca_arbel_ud_seg) / 16;
2029                         break;
2030
2031                 case MLX:
2032                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
2033                                                wqe - sizeof (struct mthca_next_seg),
2034                                                wqe);
2035                         if (err) {
2036                                 *bad_wr = wr;
2037                                 goto out;
2038                         }
2039                         wqe += sizeof (struct mthca_data_seg);
2040                         size += sizeof (struct mthca_data_seg) / 16;
2041                         break;
2042                 }
2043
2044                 if (wr->num_sge > qp->sq.max_gs) {
2045                         mthca_err(dev, "too many gathers\n");
2046                         err = -EINVAL;
2047                         *bad_wr = wr;
2048                         goto out;
2049                 }
2050
2051                 for (i = 0; i < wr->num_sge; ++i) {
2052                         ((struct mthca_data_seg *) wqe)->byte_count =
2053                                 cpu_to_be32(wr->sg_list[i].length);
2054                         ((struct mthca_data_seg *) wqe)->lkey =
2055                                 cpu_to_be32(wr->sg_list[i].lkey);
2056                         ((struct mthca_data_seg *) wqe)->addr =
2057                                 cpu_to_be64(wr->sg_list[i].addr);
2058                         wqe += sizeof (struct mthca_data_seg);
2059                         size += sizeof (struct mthca_data_seg) / 16;
2060                 }
2061
2062                 /* Add one more inline data segment for ICRC */
2063                 if (qp->transport == MLX) {
2064                         ((struct mthca_data_seg *) wqe)->byte_count =
2065                                 cpu_to_be32((1 << 31) | 4);
2066                         ((u32 *) wqe)[1] = 0;
2067                         wqe += sizeof (struct mthca_data_seg);
2068                         size += sizeof (struct mthca_data_seg) / 16;
2069                 }
2070
2071                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
2072
2073                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
2074                         mthca_err(dev, "opcode invalid\n");
2075                         err = -EINVAL;
2076                         *bad_wr = wr;
2077                         goto out;
2078                 }
2079
2080                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
2081                         cpu_to_be32(((ind << qp->sq.wqe_shift) +
2082                                      qp->send_wqe_offset) |
2083                                     mthca_opcode[wr->opcode]);
2084                 wmb();
2085                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
2086                         cpu_to_be32(MTHCA_NEXT_DBD | size |
2087                                     ((wr->send_flags & IB_SEND_FENCE) ?
2088                                      MTHCA_NEXT_FENCE : 0));
2089
2090                 if (!size0) {
2091                         size0 = size;
2092                         op0   = mthca_opcode[wr->opcode];
2093                         f0    = wr->send_flags & IB_SEND_FENCE ?
2094                                 MTHCA_SEND_DOORBELL_FENCE : 0;
2095                 }
2096
2097                 ++ind;
2098                 if (unlikely(ind >= qp->sq.max))
2099                         ind -= qp->sq.max;
2100         }
2101
2102 out:
2103         if (likely(nreq)) {
2104                 doorbell[0] = cpu_to_be32((nreq << 24)                  |
2105                                           ((qp->sq.head & 0xffff) << 8) |
2106                                           f0 | op0);
2107                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
2108
2109                 qp->sq.head += nreq;
2110
2111                 /*
2112                  * Make sure that descriptors are written before
2113                  * doorbell record.
2114                  */
2115                 wmb();
2116                 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
2117
2118                 /*
2119                  * Make sure doorbell record is written before we
2120                  * write MMIO send doorbell.
2121                  */
2122                 wmb();
2123                 mthca_write64(doorbell,
2124                               dev->kar + MTHCA_SEND_DOORBELL,
2125                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
2126         }
2127
2128         /*
2129          * Make sure doorbells don't leak out of SQ spinlock and reach
2130          * the HCA out of order:
2131          */
2132         mmiowb();
2133
2134         spin_unlock_irqrestore(&qp->sq.lock, flags);
2135         return err;
2136 }
2137
2138 int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2139                              struct ib_recv_wr **bad_wr)
2140 {
2141         struct mthca_dev *dev = to_mdev(ibqp->device);
2142         struct mthca_qp *qp = to_mqp(ibqp);
2143         unsigned long flags;
2144         int err = 0;
2145         int nreq;
2146         int ind;
2147         int i;
2148         void *wqe;
2149
2150         spin_lock_irqsave(&qp->rq.lock, flags);
2151
2152         /* XXX check that state is OK to post receive */
2153
2154         ind = qp->rq.head & (qp->rq.max - 1);
2155
2156         for (nreq = 0; wr; ++nreq, wr = wr->next) {
2157                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2158                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
2159                                         " %d max, %d nreq)\n", qp->qpn,
2160                                         qp->rq.head, qp->rq.tail,
2161                                         qp->rq.max, nreq);
2162                         err = -ENOMEM;
2163                         *bad_wr = wr;
2164                         goto out;
2165                 }
2166
2167                 wqe = get_recv_wqe(qp, ind);
2168
2169                 ((struct mthca_next_seg *) wqe)->flags = 0;
2170
2171                 wqe += sizeof (struct mthca_next_seg);
2172
2173                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2174                         err = -EINVAL;
2175                         *bad_wr = wr;
2176                         goto out;
2177                 }
2178
2179                 for (i = 0; i < wr->num_sge; ++i) {
2180                         ((struct mthca_data_seg *) wqe)->byte_count =
2181                                 cpu_to_be32(wr->sg_list[i].length);
2182                         ((struct mthca_data_seg *) wqe)->lkey =
2183                                 cpu_to_be32(wr->sg_list[i].lkey);
2184                         ((struct mthca_data_seg *) wqe)->addr =
2185                                 cpu_to_be64(wr->sg_list[i].addr);
2186                         wqe += sizeof (struct mthca_data_seg);
2187                 }
2188
2189                 if (i < qp->rq.max_gs) {
2190                         ((struct mthca_data_seg *) wqe)->byte_count = 0;
2191                         ((struct mthca_data_seg *) wqe)->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
2192                         ((struct mthca_data_seg *) wqe)->addr = 0;
2193                 }
2194
2195                 qp->wrid[ind] = wr->wr_id;
2196
2197                 ++ind;
2198                 if (unlikely(ind >= qp->rq.max))
2199                         ind -= qp->rq.max;
2200         }
2201 out:
2202         if (likely(nreq)) {
2203                 qp->rq.head += nreq;
2204
2205                 /*
2206                  * Make sure that descriptors are written before
2207                  * doorbell record.
2208                  */
2209                 wmb();
2210                 *qp->rq.db = cpu_to_be32(qp->rq.head & 0xffff);
2211         }
2212
2213         spin_unlock_irqrestore(&qp->rq.lock, flags);
2214         return err;
2215 }
2216
2217 void mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
2218                         int index, int *dbd, __be32 *new_wqe)
2219 {
2220         struct mthca_next_seg *next;
2221
2222         /*
2223          * For SRQs, all WQEs generate a CQE, so we're always at the
2224          * end of the doorbell chain.
2225          */
2226         if (qp->ibqp.srq) {
2227                 *new_wqe = 0;
2228                 return;
2229         }
2230
2231         if (is_send)
2232                 next = get_send_wqe(qp, index);
2233         else
2234                 next = get_recv_wqe(qp, index);
2235
2236         *dbd = !!(next->ee_nds & cpu_to_be32(MTHCA_NEXT_DBD));
2237         if (next->ee_nds & cpu_to_be32(0x3f))
2238                 *new_wqe = (next->nda_op & cpu_to_be32(~0x3f)) |
2239                         (next->ee_nds & cpu_to_be32(0x3f));
2240         else
2241                 *new_wqe = 0;
2242 }
2243
2244 int __devinit mthca_init_qp_table(struct mthca_dev *dev)
2245 {
2246         int err;
2247         u8 status;
2248         int i;
2249
2250         spin_lock_init(&dev->qp_table.lock);
2251
2252         /*
2253          * We reserve 2 extra QPs per port for the special QPs.  The
2254          * special QP for port 1 has to be even, so round up.
2255          */
2256         dev->qp_table.sqp_start = (dev->limits.reserved_qps + 1) & ~1UL;
2257         err = mthca_alloc_init(&dev->qp_table.alloc,
2258                                dev->limits.num_qps,
2259                                (1 << 24) - 1,
2260                                dev->qp_table.sqp_start +
2261                                MTHCA_MAX_PORTS * 2);
2262         if (err)
2263                 return err;
2264
2265         err = mthca_array_init(&dev->qp_table.qp,
2266                                dev->limits.num_qps);
2267         if (err) {
2268                 mthca_alloc_cleanup(&dev->qp_table.alloc);
2269                 return err;
2270         }
2271
2272         for (i = 0; i < 2; ++i) {
2273                 err = mthca_CONF_SPECIAL_QP(dev, i ? IB_QPT_GSI : IB_QPT_SMI,
2274                                             dev->qp_table.sqp_start + i * 2,
2275                                             &status);
2276                 if (err)
2277                         goto err_out;
2278                 if (status) {
2279                         mthca_warn(dev, "CONF_SPECIAL_QP returned "
2280                                    "status %02x, aborting.\n",
2281                                    status);
2282                         err = -EINVAL;
2283                         goto err_out;
2284                 }
2285         }
2286         return 0;
2287
2288  err_out:
2289         for (i = 0; i < 2; ++i)
2290                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2291
2292         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2293         mthca_alloc_cleanup(&dev->qp_table.alloc);
2294
2295         return err;
2296 }
2297
2298 void mthca_cleanup_qp_table(struct mthca_dev *dev)
2299 {
2300         int i;
2301         u8 status;
2302
2303         for (i = 0; i < 2; ++i)
2304                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2305
2306         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2307         mthca_alloc_cleanup(&dev->qp_table.alloc);
2308 }