drivers/infiniband/hw/mthca/mthca_qp.c

   1 /*
   2  * Copyright (c) 2004 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Cisco Systems. All rights reserved.
   4  * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
   5  * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * OpenIB.org BSD license below:
  12  *
  13  *     Redistribution and use in source and binary forms, with or
  14  *     without modification, are permitted provided that the following
  15  *     conditions are met:
  16  *
  17  *      - Redistributions of source code must retain the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer.
  20  *
  21  *      - Redistributions in binary form must reproduce the above
  22  *        copyright notice, this list of conditions and the following
  23  *        disclaimer in the documentation and/or other materials
  24  *        provided with the distribution.
  25  *
  26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33  * SOFTWARE.
  34  *
  35  * $Id: mthca_qp.c 1355 2004-12-17 15:23:43Z roland $
  36  */
  37
  38 #include <linux/init.h>
  39 #include <linux/string.h>
  40 #include <linux/slab.h>
  41
  42 #include <rdma/ib_verbs.h>
  43 #include <rdma/ib_cache.h>
  44 #include <rdma/ib_pack.h>
  45
  46 #include "mthca_dev.h"
  47 #include "mthca_cmd.h"
  48 #include "mthca_memfree.h"
  49 #include "mthca_wqe.h"
  50
  51 enum {
  52         MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE,
  53         MTHCA_ACK_REQ_FREQ       = 10,
  54         MTHCA_FLIGHT_LIMIT       = 9,
  55         MTHCA_UD_HEADER_SIZE     = 72, /* largest UD header possible */
  56         MTHCA_INLINE_HEADER_SIZE = 4,  /* data segment overhead for inline */
  57         MTHCA_INLINE_CHUNK_SIZE  = 16  /* inline data segment chunk */
  58 };
  59
  60 enum {
  61         MTHCA_QP_STATE_RST  = 0,
  62         MTHCA_QP_STATE_INIT = 1,
  63         MTHCA_QP_STATE_RTR  = 2,
  64         MTHCA_QP_STATE_RTS  = 3,
  65         MTHCA_QP_STATE_SQE  = 4,
  66         MTHCA_QP_STATE_SQD  = 5,
  67         MTHCA_QP_STATE_ERR  = 6,
  68         MTHCA_QP_STATE_DRAINING = 7
  69 };
  70
  71 enum {
  72         MTHCA_QP_ST_RC  = 0x0,
  73         MTHCA_QP_ST_UC  = 0x1,
  74         MTHCA_QP_ST_RD  = 0x2,
  75         MTHCA_QP_ST_UD  = 0x3,
  76         MTHCA_QP_ST_MLX = 0x7
  77 };
  78
  79 enum {
  80         MTHCA_QP_PM_MIGRATED = 0x3,
  81         MTHCA_QP_PM_ARMED    = 0x0,
  82         MTHCA_QP_PM_REARM    = 0x1
  83 };
  84
  85 enum {
  86         /* qp_context flags */
  87         MTHCA_QP_BIT_DE  = 1 <<  8,
  88         /* params1 */
  89         MTHCA_QP_BIT_SRE = 1 << 15,
  90         MTHCA_QP_BIT_SWE = 1 << 14,
  91         MTHCA_QP_BIT_SAE = 1 << 13,
  92         MTHCA_QP_BIT_SIC = 1 <<  4,
  93         MTHCA_QP_BIT_SSC = 1 <<  3,
  94         /* params2 */
  95         MTHCA_QP_BIT_RRE = 1 << 15,
  96         MTHCA_QP_BIT_RWE = 1 << 14,
  97         MTHCA_QP_BIT_RAE = 1 << 13,
  98         MTHCA_QP_BIT_RIC = 1 <<  4,
  99         MTHCA_QP_BIT_RSC = 1 <<  3
 100 };
 101
 102 struct mthca_qp_path {
 103         __be32 port_pkey;
 104         u8     rnr_retry;
 105         u8     g_mylmc;
 106         __be16 rlid;
 107         u8     ackto;
 108         u8     mgid_index;
 109         u8     static_rate;
 110         u8     hop_limit;
 111         __be32 sl_tclass_flowlabel;
 112         u8     rgid[16];
 113 } __attribute__((packed));
 114
 115 struct mthca_qp_context {
 116         __be32 flags;
 117         __be32 tavor_sched_queue; /* Reserved on Arbel */
 118         u8     mtu_msgmax;
 119         u8     rq_size_stride;  /* Reserved on Tavor */
 120         u8     sq_size_stride;  /* Reserved on Tavor */
 121         u8     rlkey_arbel_sched_queue; /* Reserved on Tavor */
 122         __be32 usr_page;
 123         __be32 local_qpn;
 124         __be32 remote_qpn;
 125         u32    reserved1[2];
 126         struct mthca_qp_path pri_path;
 127         struct mthca_qp_path alt_path;
 128         __be32 rdd;
 129         __be32 pd;
 130         __be32 wqe_base;
 131         __be32 wqe_lkey;
 132         __be32 params1;
 133         __be32 reserved2;
 134         __be32 next_send_psn;
 135         __be32 cqn_snd;
 136         __be32 snd_wqe_base_l;  /* Next send WQE on Tavor */
 137         __be32 snd_db_index;    /* (debugging only entries) */
 138         __be32 last_acked_psn;
 139         __be32 ssn;
 140         __be32 params2;
 141         __be32 rnr_nextrecvpsn;
 142         __be32 ra_buff_indx;
 143         __be32 cqn_rcv;
 144         __be32 rcv_wqe_base_l;  /* Next recv WQE on Tavor */
 145         __be32 rcv_db_index;    /* (debugging only entries) */
 146         __be32 qkey;
 147         __be32 srqn;
 148         __be32 rmsn;
 149         __be16 rq_wqe_counter;  /* reserved on Tavor */
 150         __be16 sq_wqe_counter;  /* reserved on Tavor */
 151         u32    reserved3[18];
 152 } __attribute__((packed));
 153
 154 struct mthca_qp_param {
 155         __be32 opt_param_mask;
 156         u32    reserved1;
 157         struct mthca_qp_context context;
 158         u32    reserved2[62];
 159 } __attribute__((packed));
 160
 161 enum {
 162         MTHCA_QP_OPTPAR_ALT_ADDR_PATH     = 1 << 0,
 163         MTHCA_QP_OPTPAR_RRE               = 1 << 1,
 164         MTHCA_QP_OPTPAR_RAE               = 1 << 2,
 165         MTHCA_QP_OPTPAR_RWE               = 1 << 3,
 166         MTHCA_QP_OPTPAR_PKEY_INDEX        = 1 << 4,
 167         MTHCA_QP_OPTPAR_Q_KEY             = 1 << 5,
 168         MTHCA_QP_OPTPAR_RNR_TIMEOUT       = 1 << 6,
 169         MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
 170         MTHCA_QP_OPTPAR_SRA_MAX           = 1 << 8,
 171         MTHCA_QP_OPTPAR_RRA_MAX           = 1 << 9,
 172         MTHCA_QP_OPTPAR_PM_STATE          = 1 << 10,
 173         MTHCA_QP_OPTPAR_PORT_NUM          = 1 << 11,
 174         MTHCA_QP_OPTPAR_RETRY_COUNT       = 1 << 12,
 175         MTHCA_QP_OPTPAR_ALT_RNR_RETRY     = 1 << 13,
 176         MTHCA_QP_OPTPAR_ACK_TIMEOUT       = 1 << 14,
 177         MTHCA_QP_OPTPAR_RNR_RETRY         = 1 << 15,
 178         MTHCA_QP_OPTPAR_SCHED_QUEUE       = 1 << 16
 179 };
 180
 181 static const u8 mthca_opcode[] = {
 182         [IB_WR_SEND]                 = MTHCA_OPCODE_SEND,
 183         [IB_WR_SEND_WITH_IMM]        = MTHCA_OPCODE_SEND_IMM,
 184         [IB_WR_RDMA_WRITE]           = MTHCA_OPCODE_RDMA_WRITE,
 185         [IB_WR_RDMA_WRITE_WITH_IMM]  = MTHCA_OPCODE_RDMA_WRITE_IMM,
 186         [IB_WR_RDMA_READ]            = MTHCA_OPCODE_RDMA_READ,
 187         [IB_WR_ATOMIC_CMP_AND_SWP]   = MTHCA_OPCODE_ATOMIC_CS,
 188         [IB_WR_ATOMIC_FETCH_AND_ADD] = MTHCA_OPCODE_ATOMIC_FA,
 189 };
 190
 191 static int is_sqp(struct mthca_dev *dev, struct mthca_qp *qp)
 192 {
 193         return qp->qpn >= dev->qp_table.sqp_start &&
 194                 qp->qpn <= dev->qp_table.sqp_start + 3;
 195 }
 196
 197 static int is_qp0(struct mthca_dev *dev, struct mthca_qp *qp)
 198 {
 199         return qp->qpn >= dev->qp_table.sqp_start &&
 200                 qp->qpn <= dev->qp_table.sqp_start + 1;
 201 }
 202
 203 static void *get_recv_wqe(struct mthca_qp *qp, int n)
 204 {
 205         if (qp->is_direct)
 206                 return qp->queue.direct.buf + (n << qp->rq.wqe_shift);
 207         else
 208                 return qp->queue.page_list[(n << qp->rq.wqe_shift) >> PAGE_SHIFT].buf +
 209                         ((n << qp->rq.wqe_shift) & (PAGE_SIZE - 1));
 210 }
 211
 212 static void *get_send_wqe(struct mthca_qp *qp, int n)
 213 {
 214         if (qp->is_direct)
 215                 return qp->queue.direct.buf + qp->send_wqe_offset +
 216                         (n << qp->sq.wqe_shift);
 217         else
 218                 return qp->queue.page_list[(qp->send_wqe_offset +
 219                                             (n << qp->sq.wqe_shift)) >>
 220                                            PAGE_SHIFT].buf +
 221                         ((qp->send_wqe_offset + (n << qp->sq.wqe_shift)) &
 222                          (PAGE_SIZE - 1));
 223 }
 224
 225 static void mthca_wq_init(struct mthca_wq *wq)
 226 {
 227         spin_lock_init(&wq->lock);
 228         wq->next_ind  = 0;
 229         wq->last_comp = wq->max - 1;
 230         wq->head      = 0;
 231         wq->tail      = 0;
 232 }
 233
 234 void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
 235                     enum ib_event_type event_type)
 236 {
 237         struct mthca_qp *qp;
 238         struct ib_event event;
 239
 240         spin_lock(&dev->qp_table.lock);
 241         qp = mthca_array_get(&dev->qp_table.qp, qpn & (dev->limits.num_qps - 1));
 242         if (qp)
 243                 atomic_inc(&qp->refcount);
 244         spin_unlock(&dev->qp_table.lock);
 245
 246         if (!qp) {
 247                 mthca_warn(dev, "Async event for bogus QP %08x\n", qpn);
 248                 return;
 249         }
 250
 251         event.device      = &dev->ib_dev;
 252         event.event       = event_type;
 253         event.element.qp  = &qp->ibqp;
 254         if (qp->ibqp.event_handler)
 255                 qp->ibqp.event_handler(&event, qp->ibqp.qp_context);
 256
 257         if (atomic_dec_and_test(&qp->refcount))
 258                 wake_up(&qp->wait);
 259 }
 260
 261 static int to_mthca_state(enum ib_qp_state ib_state)
 262 {
 263         switch (ib_state) {
 264         case IB_QPS_RESET: return MTHCA_QP_STATE_RST;
 265         case IB_QPS_INIT:  return MTHCA_QP_STATE_INIT;
 266         case IB_QPS_RTR:   return MTHCA_QP_STATE_RTR;
 267         case IB_QPS_RTS:   return MTHCA_QP_STATE_RTS;
 268         case IB_QPS_SQD:   return MTHCA_QP_STATE_SQD;
 269         case IB_QPS_SQE:   return MTHCA_QP_STATE_SQE;
 270         case IB_QPS_ERR:   return MTHCA_QP_STATE_ERR;
 271         default:                return -1;
 272         }
 273 }
 274
 275 enum { RC, UC, UD, RD, RDEE, MLX, NUM_TRANS };
 276
 277 static int to_mthca_st(int transport)
 278 {
 279         switch (transport) {
 280         case RC:  return MTHCA_QP_ST_RC;
 281         case UC:  return MTHCA_QP_ST_UC;
 282         case UD:  return MTHCA_QP_ST_UD;
 283         case RD:  return MTHCA_QP_ST_RD;
 284         case MLX: return MTHCA_QP_ST_MLX;
 285         default:  return -1;
 286         }
 287 }
 288
 289 static void store_attrs(struct mthca_sqp *sqp, struct ib_qp_attr *attr,
 290                         int attr_mask)
 291 {
 292         if (attr_mask & IB_QP_PKEY_INDEX)
 293                 sqp->pkey_index = attr->pkey_index;
 294         if (attr_mask & IB_QP_QKEY)
 295                 sqp->qkey = attr->qkey;
 296         if (attr_mask & IB_QP_SQ_PSN)
 297                 sqp->send_psn = attr->sq_psn;
 298 }
 299
 300 static void init_port(struct mthca_dev *dev, int port)
 301 {
 302         int err;
 303         u8 status;
 304         struct mthca_init_ib_param param;
 305
 306         memset(&param, 0, sizeof param);
 307
 308         param.port_width = dev->limits.port_width_cap;
 309         param.vl_cap     = dev->limits.vl_cap;
 310         param.mtu_cap    = dev->limits.mtu_cap;
 311         param.gid_cap    = dev->limits.gid_table_len;
 312         param.pkey_cap   = dev->limits.pkey_table_len;
 313
 314         err = mthca_INIT_IB(dev, &param, port, &status);
 315         if (err)
 316                 mthca_warn(dev, "INIT_IB failed, return code %d.\n", err);
 317         if (status)
 318                 mthca_warn(dev, "INIT_IB returned status %02x.\n", status);
 319 }
 320
 321 static __be32 get_hw_access_flags(struct mthca_qp *qp, struct ib_qp_attr *attr,
 322                                   int attr_mask)
 323 {
 324         u8 dest_rd_atomic;
 325         u32 access_flags;
 326         u32 hw_access_flags = 0;
 327
 328         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
 329                 dest_rd_atomic = attr->max_dest_rd_atomic;
 330         else
 331                 dest_rd_atomic = qp->resp_depth;
 332
 333         if (attr_mask & IB_QP_ACCESS_FLAGS)
 334                 access_flags = attr->qp_access_flags;
 335         else
 336                 access_flags = qp->atomic_rd_en;
 337
 338         if (!dest_rd_atomic)
 339                 access_flags &= IB_ACCESS_REMOTE_WRITE;
 340
 341         if (access_flags & IB_ACCESS_REMOTE_READ)
 342                 hw_access_flags |= MTHCA_QP_BIT_RRE;
 343         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
 344                 hw_access_flags |= MTHCA_QP_BIT_RAE;
 345         if (access_flags & IB_ACCESS_REMOTE_WRITE)
 346                 hw_access_flags |= MTHCA_QP_BIT_RWE;
 347
 348         return cpu_to_be32(hw_access_flags);
 349 }
 350
 351 static inline enum ib_qp_state to_ib_qp_state(int mthca_state)
 352 {
 353         switch (mthca_state) {
 354         case MTHCA_QP_STATE_RST:      return IB_QPS_RESET;
 355         case MTHCA_QP_STATE_INIT:     return IB_QPS_INIT;
 356         case MTHCA_QP_STATE_RTR:      return IB_QPS_RTR;
 357         case MTHCA_QP_STATE_RTS:      return IB_QPS_RTS;
 358         case MTHCA_QP_STATE_DRAINING:
 359         case MTHCA_QP_STATE_SQD:      return IB_QPS_SQD;
 360         case MTHCA_QP_STATE_SQE:      return IB_QPS_SQE;
 361         case MTHCA_QP_STATE_ERR:      return IB_QPS_ERR;
 362         default:                      return -1;
 363         }
 364 }
 365
 366 static inline enum ib_mig_state to_ib_mig_state(int mthca_mig_state)
 367 {
 368         switch (mthca_mig_state) {
 369         case 0:  return IB_MIG_ARMED;
 370         case 1:  return IB_MIG_REARM;
 371         case 3:  return IB_MIG_MIGRATED;
 372         default: return -1;
 373         }
 374 }
 375
 376 static int to_ib_qp_access_flags(int mthca_flags)
 377 {
 378         int ib_flags = 0;
 379
 380         if (mthca_flags & MTHCA_QP_BIT_RRE)
 381                 ib_flags |= IB_ACCESS_REMOTE_READ;
 382         if (mthca_flags & MTHCA_QP_BIT_RWE)
 383                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
 384         if (mthca_flags & MTHCA_QP_BIT_RAE)
 385                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
 386
 387         return ib_flags;
 388 }
 389
 390 static void to_ib_ah_attr(struct mthca_dev *dev, struct ib_ah_attr *ib_ah_attr,
 391                                 struct mthca_qp_path *path)
 392 {
 393         memset(ib_ah_attr, 0, sizeof *path);
 394         ib_ah_attr->port_num      = (be32_to_cpu(path->port_pkey) >> 24) & 0x3;
 395         ib_ah_attr->dlid          = be16_to_cpu(path->rlid);
 396         ib_ah_attr->sl            = be32_to_cpu(path->sl_tclass_flowlabel) >> 28;
 397         ib_ah_attr->src_path_bits = path->g_mylmc & 0x7f;
 398         ib_ah_attr->static_rate   = path->static_rate & 0x7;
 399         ib_ah_attr->ah_flags      = (path->g_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
 400         if (ib_ah_attr->ah_flags) {
 401                 ib_ah_attr->grh.sgid_index = path->mgid_index & (dev->limits.gid_table_len - 1);
 402                 ib_ah_attr->grh.hop_limit  = path->hop_limit;
 403                 ib_ah_attr->grh.traffic_class =
 404                         (be32_to_cpu(path->sl_tclass_flowlabel) >> 20) & 0xff;
 405                 ib_ah_attr->grh.flow_label =
 406                         be32_to_cpu(path->sl_tclass_flowlabel) & 0xfffff;
 407                 memcpy(ib_ah_attr->grh.dgid.raw,
 408                         path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
 409         }
 410 }
 411
 412 int mthca_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
 413                    struct ib_qp_init_attr *qp_init_attr)
 414 {
 415         struct mthca_dev *dev = to_mdev(ibqp->device);
 416         struct mthca_qp *qp = to_mqp(ibqp);
 417         int err;
 418         struct mthca_mailbox *mailbox;
 419         struct mthca_qp_param *qp_param;
 420         struct mthca_qp_context *context;
 421         int mthca_state;
 422         u8 status;
 423
 424         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 425         if (IS_ERR(mailbox))
 426                 return PTR_ERR(mailbox);
 427
 428         err = mthca_QUERY_QP(dev, qp->qpn, 0, mailbox, &status);
 429         if (err)
 430                 goto out;
 431         if (status) {
 432                 mthca_warn(dev, "QUERY_QP returned status %02x\n", status);
 433                 err = -EINVAL;
 434                 goto out;
 435         }
 436
 437         qp_param    = mailbox->buf;
 438         context     = &qp_param->context;
 439         mthca_state = be32_to_cpu(context->flags) >> 28;
 440
 441         qp_attr->qp_state            = to_ib_qp_state(mthca_state);
 442         qp_attr->cur_qp_state        = qp_attr->qp_state;
 443         qp_attr->path_mtu            = context->mtu_msgmax >> 5;
 444         qp_attr->path_mig_state      =
 445                 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
 446         qp_attr->qkey                = be32_to_cpu(context->qkey);
 447         qp_attr->rq_psn              = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
 448         qp_attr->sq_psn              = be32_to_cpu(context->next_send_psn) & 0xffffff;
 449         qp_attr->dest_qp_num         = be32_to_cpu(context->remote_qpn) & 0xffffff;
 450         qp_attr->qp_access_flags     =
 451                 to_ib_qp_access_flags(be32_to_cpu(context->params2));
 452         qp_attr->cap.max_send_wr     = qp->sq.max;
 453         qp_attr->cap.max_recv_wr     = qp->rq.max;
 454         qp_attr->cap.max_send_sge    = qp->sq.max_gs;
 455         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
 456         qp_attr->cap.max_inline_data = qp->max_inline_data;
 457
 458         to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
 459         to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
 460
 461         qp_attr->pkey_index     = be32_to_cpu(context->pri_path.port_pkey) & 0x7f;
 462         qp_attr->alt_pkey_index = be32_to_cpu(context->alt_path.port_pkey) & 0x7f;
 463
 464         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
 465         qp_attr->sq_draining = mthca_state == MTHCA_QP_STATE_DRAINING;
 466
 467         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
 468
 469         qp_attr->max_dest_rd_atomic =
 470                 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
 471         qp_attr->min_rnr_timer      =
 472                 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
 473         qp_attr->port_num           = qp_attr->ah_attr.port_num;
 474         qp_attr->timeout            = context->pri_path.ackto >> 3;
 475         qp_attr->retry_cnt          = (be32_to_cpu(context->params1) >> 16) & 0x7;
 476         qp_attr->rnr_retry          = context->pri_path.rnr_retry >> 5;
 477         qp_attr->alt_port_num       = qp_attr->alt_ah_attr.port_num;
 478         qp_attr->alt_timeout        = context->alt_path.ackto >> 3;
 479         qp_init_attr->cap           = qp_attr->cap;
 480
 481 out:
 482         mthca_free_mailbox(dev, mailbox);
 483         return err;
 484 }
 485
 486 static void mthca_path_set(struct ib_ah_attr *ah, struct mthca_qp_path *path)
 487 {
 488         path->g_mylmc     = ah->src_path_bits & 0x7f;
 489         path->rlid        = cpu_to_be16(ah->dlid);
 490         path->static_rate = !!ah->static_rate;
 491
 492         if (ah->ah_flags & IB_AH_GRH) {
 493                 path->g_mylmc   |= 1 << 7;
 494                 path->mgid_index = ah->grh.sgid_index;
 495                 path->hop_limit  = ah->grh.hop_limit;
 496                 path->sl_tclass_flowlabel =
 497                         cpu_to_be32((ah->sl << 28)                |
 498                                     (ah->grh.traffic_class << 20) |
 499                                     (ah->grh.flow_label));
 500                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
 501         } else
 502                 path->sl_tclass_flowlabel = cpu_to_be32(ah->sl << 28);
 503 }
 504
 505 int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask)
 506 {
 507         struct mthca_dev *dev = to_mdev(ibqp->device);
 508         struct mthca_qp *qp = to_mqp(ibqp);
 509         enum ib_qp_state cur_state, new_state;
 510         struct mthca_mailbox *mailbox;
 511         struct mthca_qp_param *qp_param;
 512         struct mthca_qp_context *qp_context;
 513         u32 sqd_event = 0;
 514         u8 status;
 515         int err;
 516
 517         if (attr_mask & IB_QP_CUR_STATE) {
 518                 cur_state = attr->cur_qp_state;
 519         } else {
 520                 spin_lock_irq(&qp->sq.lock);
 521                 spin_lock(&qp->rq.lock);
 522                 cur_state = qp->state;
 523                 spin_unlock(&qp->rq.lock);
 524                 spin_unlock_irq(&qp->sq.lock);
 525         }
 526
 527         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
 528
 529         if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask)) {
 530                 mthca_dbg(dev, "Bad QP transition (transport %d) "
 531                           "%d->%d with attr 0x%08x\n",
 532                           qp->transport, cur_state, new_state,
 533                           attr_mask);
 534                 return -EINVAL;
 535         }
 536
 537         if ((attr_mask & IB_QP_PKEY_INDEX) &&
 538              attr->pkey_index >= dev->limits.pkey_table_len) {
 539                 mthca_dbg(dev, "PKey index (%u) too large. max is %d\n",
 540                           attr->pkey_index,dev->limits.pkey_table_len-1);
 541                 return -EINVAL;
 542         }
 543
 544         if ((attr_mask & IB_QP_PORT) &&
 545             (attr->port_num == 0 || attr->port_num > dev->limits.num_ports)) {
 546                 mthca_dbg(dev, "Port number (%u) is invalid\n", attr->port_num);
 547                 return -EINVAL;
 548         }
 549
 550         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
 551             attr->max_rd_atomic > dev->limits.max_qp_init_rdma) {
 552                 mthca_dbg(dev, "Max rdma_atomic as initiator %u too large (max is %d)\n",
 553                           attr->max_rd_atomic, dev->limits.max_qp_init_rdma);
 554                 return -EINVAL;
 555         }
 556
 557         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
 558             attr->max_dest_rd_atomic > 1 << dev->qp_table.rdb_shift) {
 559                 mthca_dbg(dev, "Max rdma_atomic as responder %u too large (max %d)\n",
 560                           attr->max_dest_rd_atomic, 1 << dev->qp_table.rdb_shift);
 561                 return -EINVAL;
 562         }
 563
 564         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 565         if (IS_ERR(mailbox))
 566                 return PTR_ERR(mailbox);
 567         qp_param = mailbox->buf;
 568         qp_context = &qp_param->context;
 569         memset(qp_param, 0, sizeof *qp_param);
 570
 571         qp_context->flags      = cpu_to_be32((to_mthca_state(new_state) << 28) |
 572                                              (to_mthca_st(qp->transport) << 16));
 573         qp_context->flags     |= cpu_to_be32(MTHCA_QP_BIT_DE);
 574         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
 575                 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 576         else {
 577                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE);
 578                 switch (attr->path_mig_state) {
 579                 case IB_MIG_MIGRATED:
 580                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 581                         break;
 582                 case IB_MIG_REARM:
 583                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_REARM << 11);
 584                         break;
 585                 case IB_MIG_ARMED:
 586                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_ARMED << 11);
 587                         break;
 588                 }
 589         }
 590
 591         /* leave tavor_sched_queue as 0 */
 592
 593         if (qp->transport == MLX || qp->transport == UD)
 594                 qp_context->mtu_msgmax = (IB_MTU_2048 << 5) | 11;
 595         else if (attr_mask & IB_QP_PATH_MTU)
 596                 qp_context->mtu_msgmax = (attr->path_mtu << 5) | 31;
 597
 598         if (mthca_is_memfree(dev)) {
 599                 if (qp->rq.max)
 600                         qp_context->rq_size_stride = long_log2(qp->rq.max) << 3;
 601                 qp_context->rq_size_stride |= qp->rq.wqe_shift - 4;
 602
 603                 if (qp->sq.max)
 604                         qp_context->sq_size_stride = long_log2(qp->sq.max) << 3;
 605                 qp_context->sq_size_stride |= qp->sq.wqe_shift - 4;
 606         }
 607
 608         /* leave arbel_sched_queue as 0 */
 609
 610         if (qp->ibqp.uobject)
 611                 qp_context->usr_page =
 612                         cpu_to_be32(to_mucontext(qp->ibqp.uobject->context)->uar.index);
 613         else
 614                 qp_context->usr_page = cpu_to_be32(dev->driver_uar.index);
 615         qp_context->local_qpn  = cpu_to_be32(qp->qpn);
 616         if (attr_mask & IB_QP_DEST_QPN) {
 617                 qp_context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
 618         }
 619
 620         if (qp->transport == MLX)
 621                 qp_context->pri_path.port_pkey |=
 622                         cpu_to_be32(to_msqp(qp)->port << 24);
 623         else {
 624                 if (attr_mask & IB_QP_PORT) {
 625                         qp_context->pri_path.port_pkey |=
 626                                 cpu_to_be32(attr->port_num << 24);
 627                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM);
 628                 }
 629         }
 630
 631         if (attr_mask & IB_QP_PKEY_INDEX) {
 632                 qp_context->pri_path.port_pkey |=
 633                         cpu_to_be32(attr->pkey_index);
 634                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX);
 635         }
 636
 637         if (attr_mask & IB_QP_RNR_RETRY) {
 638                 qp_context->alt_path.rnr_retry = qp_context->pri_path.rnr_retry =
 639                         attr->rnr_retry << 5;
 640                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY |
 641                                                         MTHCA_QP_OPTPAR_ALT_RNR_RETRY);
 642         }
 643
 644         if (attr_mask & IB_QP_AV) {
 645                 mthca_path_set(&attr->ah_attr, &qp_context->pri_path);
 646                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH);
 647         }
 648
 649         if (attr_mask & IB_QP_TIMEOUT) {
 650                 qp_context->pri_path.ackto = attr->timeout << 3;
 651                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT);
 652         }
 653
 654         if (attr_mask & IB_QP_ALT_PATH) {
 655                 if (attr->alt_port_num == 0 || attr->alt_port_num > dev->limits.num_ports) {
 656                         mthca_dbg(dev, "Alternate port number (%u) is invalid\n",
 657                                 attr->alt_port_num);
 658                         return -EINVAL;
 659                 }
 660
 661                 mthca_path_set(&attr->alt_ah_attr, &qp_context->alt_path);
 662                 qp_context->alt_path.port_pkey |= cpu_to_be32(attr->alt_pkey_index |
 663                                                               attr->alt_port_num << 24);
 664                 qp_context->alt_path.ackto = attr->alt_timeout << 3;
 665                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ALT_ADDR_PATH);
 666         }
 667
 668         /* leave rdd as 0 */
 669         qp_context->pd         = cpu_to_be32(to_mpd(ibqp->pd)->pd_num);
 670         /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */
 671         qp_context->wqe_lkey   = cpu_to_be32(qp->mr.ibmr.lkey);
 672         qp_context->params1    = cpu_to_be32((MTHCA_ACK_REQ_FREQ << 28) |
 673                                              (MTHCA_FLIGHT_LIMIT << 24) |
 674                                              MTHCA_QP_BIT_SWE);
 675         if (qp->sq_policy == IB_SIGNAL_ALL_WR)
 676                 qp_context->params1 |= cpu_to_be32(MTHCA_QP_BIT_SSC);
 677         if (attr_mask & IB_QP_RETRY_CNT) {
 678                 qp_context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
 679                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT);
 680         }
 681
 682         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
 683                 if (attr->max_rd_atomic) {
 684                         qp_context->params1 |=
 685                                 cpu_to_be32(MTHCA_QP_BIT_SRE |
 686                                             MTHCA_QP_BIT_SAE);
 687                         qp_context->params1 |=
 688                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
 689                 }
 690                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX);
 691         }
 692
 693         if (attr_mask & IB_QP_SQ_PSN)
 694                 qp_context->next_send_psn = cpu_to_be32(attr->sq_psn);
 695         qp_context->cqn_snd = cpu_to_be32(to_mcq(ibqp->send_cq)->cqn);
 696
 697         if (mthca_is_memfree(dev)) {
 698                 qp_context->snd_wqe_base_l = cpu_to_be32(qp->send_wqe_offset);
 699                 qp_context->snd_db_index   = cpu_to_be32(qp->sq.db_index);
 700         }
 701
 702         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
 703                 if (attr->max_dest_rd_atomic)
 704                         qp_context->params2 |=
 705                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
 706
 707                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX);
 708         }
 709
 710         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
 711                 qp_context->params2      |= get_hw_access_flags(qp, attr, attr_mask);
 712                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
 713                                                         MTHCA_QP_OPTPAR_RRE |
 714                                                         MTHCA_QP_OPTPAR_RAE);
 715         }
 716
 717         qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC);
 718
 719         if (ibqp->srq)
 720                 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RIC);
 721
 722         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
 723                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
 724                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT);
 725         }
 726         if (attr_mask & IB_QP_RQ_PSN)
 727                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
 728
 729         qp_context->ra_buff_indx =
 730                 cpu_to_be32(dev->qp_table.rdb_base +
 731                             ((qp->qpn & (dev->limits.num_qps - 1)) * MTHCA_RDB_ENTRY_SIZE <<
 732                              dev->qp_table.rdb_shift));
 733
 734         qp_context->cqn_rcv = cpu_to_be32(to_mcq(ibqp->recv_cq)->cqn);
 735
 736         if (mthca_is_memfree(dev))
 737                 qp_context->rcv_db_index   = cpu_to_be32(qp->rq.db_index);
 738
 739         if (attr_mask & IB_QP_QKEY) {
 740                 qp_context->qkey = cpu_to_be32(attr->qkey);
 741                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY);
 742         }
 743
 744         if (ibqp->srq)
 745                 qp_context->srqn = cpu_to_be32(1 << 24 |
 746                                                to_msrq(ibqp->srq)->srqn);
 747
 748         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
 749             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY               &&
 750             attr->en_sqd_async_notify)
 751                 sqd_event = 1 << 31;
 752
 753         err = mthca_MODIFY_QP(dev, cur_state, new_state, qp->qpn, 0,
 754                               mailbox, sqd_event, &status);
 755         if (status) {
 756                 mthca_warn(dev, "modify QP %d->%d returned status %02x.\n",
 757                            cur_state, new_state, status);
 758                 err = -EINVAL;
 759         }
 760
 761         if (!err) {
 762                 qp->state = new_state;
 763                 if (attr_mask & IB_QP_ACCESS_FLAGS)
 764                         qp->atomic_rd_en = attr->qp_access_flags;
 765                 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
 766                         qp->resp_depth = attr->max_dest_rd_atomic;
 767         }
 768
 769         mthca_free_mailbox(dev, mailbox);
 770
 771         if (is_sqp(dev, qp))
 772                 store_attrs(to_msqp(qp), attr, attr_mask);
 773
 774         /*
 775          * If we moved QP0 to RTR, bring the IB link up; if we moved
 776          * QP0 to RESET or ERROR, bring the link back down.
 777          */
 778         if (is_qp0(dev, qp)) {
 779                 if (cur_state != IB_QPS_RTR &&
 780                     new_state == IB_QPS_RTR)
 781                         init_port(dev, to_msqp(qp)->port);
 782
 783                 if (cur_state != IB_QPS_RESET &&
 784                     cur_state != IB_QPS_ERR &&
 785                     (new_state == IB_QPS_RESET ||
 786                      new_state == IB_QPS_ERR))
 787                         mthca_CLOSE_IB(dev, to_msqp(qp)->port, &status);
 788         }
 789
 790         /*
 791          * If we moved a kernel QP to RESET, clean up all old CQ
 792          * entries and reinitialize the QP.
 793          */
 794         if (!err && new_state == IB_QPS_RESET && !qp->ibqp.uobject) {
 795                 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq)->cqn, qp->qpn,
 796                                qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
 797                 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
 798                         mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq)->cqn, qp->qpn,
 799                                        qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
 800
 801                 mthca_wq_init(&qp->sq);
 802                 qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
 803
 804                 mthca_wq_init(&qp->rq);
 805                 qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
 806
 807                 if (mthca_is_memfree(dev)) {
 808                         *qp->sq.db = 0;
 809                         *qp->rq.db = 0;
 810                 }
 811         }
 812
 813         return err;
 814 }
 815
 816 static int mthca_max_data_size(struct mthca_dev *dev, struct mthca_qp *qp, int desc_sz)
 817 {
 818         /*
 819          * Calculate the maximum size of WQE s/g segments, excluding
 820          * the next segment and other non-data segments.
 821          */
 822         int max_data_size = desc_sz - sizeof (struct mthca_next_seg);
 823
 824         switch (qp->transport) {
 825         case MLX:
 826                 max_data_size -= 2 * sizeof (struct mthca_data_seg);
 827                 break;
 828
 829         case UD:
 830                 if (mthca_is_memfree(dev))
 831                         max_data_size -= sizeof (struct mthca_arbel_ud_seg);
 832                 else
 833                         max_data_size -= sizeof (struct mthca_tavor_ud_seg);
 834                 break;
 835
 836         default:
 837                 max_data_size -= sizeof (struct mthca_raddr_seg);
 838                 break;
 839         }
 840
 841         return max_data_size;
 842 }
 843
 844 static inline int mthca_max_inline_data(struct mthca_pd *pd, int max_data_size)
 845 {
 846         /* We don't support inline data for kernel QPs (yet). */
 847         return pd->ibpd.uobject ? max_data_size - MTHCA_INLINE_HEADER_SIZE : 0;
 848 }
 849
 850 static void mthca_adjust_qp_caps(struct mthca_dev *dev,
 851                                  struct mthca_pd *pd,
 852                                  struct mthca_qp *qp)
 853 {
 854         int max_data_size = mthca_max_data_size(dev, qp,
 855                                                 min(dev->limits.max_desc_sz,
 856                                                     1 << qp->sq.wqe_shift));
 857
 858         qp->max_inline_data = mthca_max_inline_data(pd, max_data_size);
 859
 860         qp->sq.max_gs = min_t(int, dev->limits.max_sg,
 861                               max_data_size / sizeof (struct mthca_data_seg));
 862         qp->rq.max_gs = min_t(int, dev->limits.max_sg,
 863                                (min(dev->limits.max_desc_sz, 1 << qp->rq.wqe_shift) -
 864                                 sizeof (struct mthca_next_seg)) /
 865                                sizeof (struct mthca_data_seg));
 866 }
 867
 868 /*
 869  * Allocate and register buffer for WQEs.  qp->rq.max, sq.max,
 870  * rq.max_gs and sq.max_gs must all be assigned.
 871  * mthca_alloc_wqe_buf will calculate rq.wqe_shift and
 872  * sq.wqe_shift (as well as send_wqe_offset, is_direct, and
 873  * queue)
 874  */
 875 static int mthca_alloc_wqe_buf(struct mthca_dev *dev,
 876                                struct mthca_pd *pd,
 877                                struct mthca_qp *qp)
 878 {
 879         int size;
 880         int err = -ENOMEM;
 881
 882         size = sizeof (struct mthca_next_seg) +
 883                 qp->rq.max_gs * sizeof (struct mthca_data_seg);
 884
 885         if (size > dev->limits.max_desc_sz)
 886                 return -EINVAL;
 887
 888         for (qp->rq.wqe_shift = 6; 1 << qp->rq.wqe_shift < size;
 889              qp->rq.wqe_shift++)
 890                 ; /* nothing */
 891
 892         size = qp->sq.max_gs * sizeof (struct mthca_data_seg);
 893         switch (qp->transport) {
 894         case MLX:
 895                 size += 2 * sizeof (struct mthca_data_seg);
 896                 break;
 897
 898         case UD:
 899                 size += mthca_is_memfree(dev) ?
 900                         sizeof (struct mthca_arbel_ud_seg) :
 901                         sizeof (struct mthca_tavor_ud_seg);
 902                 break;
 903
 904         case UC:
 905                 size += sizeof (struct mthca_raddr_seg);
 906                 break;
 907
 908         case RC:
 909                 size += sizeof (struct mthca_raddr_seg);
 910                 /*
 911                  * An atomic op will require an atomic segment, a
 912                  * remote address segment and one scatter entry.
 913                  */
 914                 size = max_t(int, size,
 915                              sizeof (struct mthca_atomic_seg) +
 916                              sizeof (struct mthca_raddr_seg) +
 917                              sizeof (struct mthca_data_seg));
 918                 break;
 919
 920         default:
 921                 break;
 922         }
 923
 924         /* Make sure that we have enough space for a bind request */
 925         size = max_t(int, size, sizeof (struct mthca_bind_seg));
 926
 927         size += sizeof (struct mthca_next_seg);
 928
 929         if (size > dev->limits.max_desc_sz)
 930                 return -EINVAL;
 931
 932         for (qp->sq.wqe_shift = 6; 1 << qp->sq.wqe_shift < size;
 933              qp->sq.wqe_shift++)
 934                 ; /* nothing */
 935
 936         qp->send_wqe_offset = ALIGN(qp->rq.max << qp->rq.wqe_shift,
 937                                     1 << qp->sq.wqe_shift);
 938
 939         /*
 940          * If this is a userspace QP, we don't actually have to
 941          * allocate anything.  All we need is to calculate the WQE
 942          * sizes and the send_wqe_offset, so we're done now.
 943          */
 944         if (pd->ibpd.uobject)
 945                 return 0;
 946
 947         size = PAGE_ALIGN(qp->send_wqe_offset +
 948                           (qp->sq.max << qp->sq.wqe_shift));
 949
 950         qp->wrid = kmalloc((qp->rq.max + qp->sq.max) * sizeof (u64),
 951                            GFP_KERNEL);
 952         if (!qp->wrid)
 953                 goto err_out;
 954
 955         err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_QP_SIZE,
 956                               &qp->queue, &qp->is_direct, pd, 0, &qp->mr);
 957         if (err)
 958                 goto err_out;
 959
 960         return 0;
 961
 962 err_out:
 963         kfree(qp->wrid);
 964         return err;
 965 }
 966
 967 static void mthca_free_wqe_buf(struct mthca_dev *dev,
 968                                struct mthca_qp *qp)
 969 {
 970         mthca_buf_free(dev, PAGE_ALIGN(qp->send_wqe_offset +
 971                                        (qp->sq.max << qp->sq.wqe_shift)),
 972                        &qp->queue, qp->is_direct, &qp->mr);
 973         kfree(qp->wrid);
 974 }
 975
 976 static int mthca_map_memfree(struct mthca_dev *dev,
 977                              struct mthca_qp *qp)
 978 {
 979         int ret;
 980
 981         if (mthca_is_memfree(dev)) {
 982                 ret = mthca_table_get(dev, dev->qp_table.qp_table, qp->qpn);
 983                 if (ret)
 984                         return ret;
 985
 986                 ret = mthca_table_get(dev, dev->qp_table.eqp_table, qp->qpn);
 987                 if (ret)
 988                         goto err_qpc;
 989
 990                 ret = mthca_table_get(dev, dev->qp_table.rdb_table,
 991                                       qp->qpn << dev->qp_table.rdb_shift);
 992                 if (ret)
 993                         goto err_eqpc;
 994
 995         }
 996
 997         return 0;
 998
 999 err_eqpc:
1000         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1001
1002 err_qpc:
1003         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1004
1005         return ret;
1006 }
1007
1008 static void mthca_unmap_memfree(struct mthca_dev *dev,
1009                                 struct mthca_qp *qp)
1010 {
1011         mthca_table_put(dev, dev->qp_table.rdb_table,
1012                         qp->qpn << dev->qp_table.rdb_shift);
1013         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1014         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1015 }
1016
1017 static int mthca_alloc_memfree(struct mthca_dev *dev,
1018                                struct mthca_qp *qp)
1019 {
1020         int ret = 0;
1021
1022         if (mthca_is_memfree(dev)) {
1023                 qp->rq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_RQ,
1024                                                  qp->qpn, &qp->rq.db);
1025                 if (qp->rq.db_index < 0)
1026                         return ret;
1027
1028                 qp->sq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SQ,
1029                                                  qp->qpn, &qp->sq.db);
1030                 if (qp->sq.db_index < 0)
1031                         mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1032         }
1033
1034         return ret;
1035 }
1036
1037 static void mthca_free_memfree(struct mthca_dev *dev,
1038                                struct mthca_qp *qp)
1039 {
1040         if (mthca_is_memfree(dev)) {
1041                 mthca_free_db(dev, MTHCA_DB_TYPE_SQ, qp->sq.db_index);
1042                 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1043         }
1044 }
1045
1046 static int mthca_alloc_qp_common(struct mthca_dev *dev,
1047                                  struct mthca_pd *pd,
1048                                  struct mthca_cq *send_cq,
1049                                  struct mthca_cq *recv_cq,
1050                                  enum ib_sig_type send_policy,
1051                                  struct mthca_qp *qp)
1052 {
1053         int ret;
1054         int i;
1055
1056         atomic_set(&qp->refcount, 1);
1057         init_waitqueue_head(&qp->wait);
1058         qp->state        = IB_QPS_RESET;
1059         qp->atomic_rd_en = 0;
1060         qp->resp_depth   = 0;
1061         qp->sq_policy    = send_policy;
1062         mthca_wq_init(&qp->sq);
1063         mthca_wq_init(&qp->rq);
1064
1065         ret = mthca_map_memfree(dev, qp);
1066         if (ret)
1067                 return ret;
1068
1069         ret = mthca_alloc_wqe_buf(dev, pd, qp);
1070         if (ret) {
1071                 mthca_unmap_memfree(dev, qp);
1072                 return ret;
1073         }
1074
1075         mthca_adjust_qp_caps(dev, pd, qp);
1076
1077         /*
1078          * If this is a userspace QP, we're done now.  The doorbells
1079          * will be allocated and buffers will be initialized in
1080          * userspace.
1081          */
1082         if (pd->ibpd.uobject)
1083                 return 0;
1084
1085         ret = mthca_alloc_memfree(dev, qp);
1086         if (ret) {
1087                 mthca_free_wqe_buf(dev, qp);
1088                 mthca_unmap_memfree(dev, qp);
1089                 return ret;
1090         }
1091
1092         if (mthca_is_memfree(dev)) {
1093                 struct mthca_next_seg *next;
1094                 struct mthca_data_seg *scatter;
1095                 int size = (sizeof (struct mthca_next_seg) +
1096                             qp->rq.max_gs * sizeof (struct mthca_data_seg)) / 16;
1097
1098                 for (i = 0; i < qp->rq.max; ++i) {
1099                         next = get_recv_wqe(qp, i);
1100                         next->nda_op = cpu_to_be32(((i + 1) & (qp->rq.max - 1)) <<
1101                                                    qp->rq.wqe_shift);
1102                         next->ee_nds = cpu_to_be32(size);
1103
1104                         for (scatter = (void *) (next + 1);
1105                              (void *) scatter < (void *) next + (1 << qp->rq.wqe_shift);
1106                              ++scatter)
1107                                 scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
1108                 }
1109
1110                 for (i = 0; i < qp->sq.max; ++i) {
1111                         next = get_send_wqe(qp, i);
1112                         next->nda_op = cpu_to_be32((((i + 1) & (qp->sq.max - 1)) <<
1113                                                     qp->sq.wqe_shift) +
1114                                                    qp->send_wqe_offset);
1115                 }
1116         }
1117
1118         qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
1119         qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
1120
1121         return 0;
1122 }
1123
1124 static int mthca_set_qp_size(struct mthca_dev *dev, struct ib_qp_cap *cap,
1125                              struct mthca_pd *pd, struct mthca_qp *qp)
1126 {
1127         int max_data_size = mthca_max_data_size(dev, qp, dev->limits.max_desc_sz);
1128
1129         /* Sanity check QP size before proceeding */
1130         if (cap->max_send_wr     > dev->limits.max_wqes ||
1131             cap->max_recv_wr     > dev->limits.max_wqes ||
1132             cap->max_send_sge    > dev->limits.max_sg   ||
1133             cap->max_recv_sge    > dev->limits.max_sg   ||
1134             cap->max_inline_data > mthca_max_inline_data(pd, max_data_size))
1135                 return -EINVAL;
1136
1137         /*
1138          * For MLX transport we need 2 extra S/G entries:
1139          * one for the header and one for the checksum at the end
1140          */
1141         if (qp->transport == MLX && cap->max_recv_sge + 2 > dev->limits.max_sg)
1142                 return -EINVAL;
1143
1144         if (mthca_is_memfree(dev)) {
1145                 qp->rq.max = cap->max_recv_wr ?
1146                         roundup_pow_of_two(cap->max_recv_wr) : 0;
1147                 qp->sq.max = cap->max_send_wr ?
1148                         roundup_pow_of_two(cap->max_send_wr) : 0;
1149         } else {
1150                 qp->rq.max = cap->max_recv_wr;
1151                 qp->sq.max = cap->max_send_wr;
1152         }
1153
1154         qp->rq.max_gs = cap->max_recv_sge;
1155         qp->sq.max_gs = max_t(int, cap->max_send_sge,
1156                               ALIGN(cap->max_inline_data + MTHCA_INLINE_HEADER_SIZE,
1157                                     MTHCA_INLINE_CHUNK_SIZE) /
1158                               sizeof (struct mthca_data_seg));
1159
1160         return 0;
1161 }
1162
1163 int mthca_alloc_qp(struct mthca_dev *dev,
1164                    struct mthca_pd *pd,
1165                    struct mthca_cq *send_cq,
1166                    struct mthca_cq *recv_cq,
1167                    enum ib_qp_type type,
1168                    enum ib_sig_type send_policy,
1169                    struct ib_qp_cap *cap,
1170                    struct mthca_qp *qp)
1171 {
1172         int err;
1173
1174         err = mthca_set_qp_size(dev, cap, pd, qp);
1175         if (err)
1176                 return err;
1177
1178         switch (type) {
1179         case IB_QPT_RC: qp->transport = RC; break;
1180         case IB_QPT_UC: qp->transport = UC; break;
1181         case IB_QPT_UD: qp->transport = UD; break;
1182         default: return -EINVAL;
1183         }
1184
1185         qp->qpn = mthca_alloc(&dev->qp_table.alloc);
1186         if (qp->qpn == -1)
1187                 return -ENOMEM;
1188
1189         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1190                                     send_policy, qp);
1191         if (err) {
1192                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1193                 return err;
1194         }
1195
1196         spin_lock_irq(&dev->qp_table.lock);
1197         mthca_array_set(&dev->qp_table.qp,
1198                         qp->qpn & (dev->limits.num_qps - 1), qp);
1199         spin_unlock_irq(&dev->qp_table.lock);
1200
1201         return 0;
1202 }
1203
1204 int mthca_alloc_sqp(struct mthca_dev *dev,
1205                     struct mthca_pd *pd,
1206                     struct mthca_cq *send_cq,
1207                     struct mthca_cq *recv_cq,
1208                     enum ib_sig_type send_policy,
1209                     struct ib_qp_cap *cap,
1210                     int qpn,
1211                     int port,
1212                     struct mthca_sqp *sqp)
1213 {
1214         u32 mqpn = qpn * 2 + dev->qp_table.sqp_start + port - 1;
1215         int err;
1216
1217         err = mthca_set_qp_size(dev, cap, pd, &sqp->qp);
1218         if (err)
1219                 return err;
1220
1221         sqp->header_buf_size = sqp->qp.sq.max * MTHCA_UD_HEADER_SIZE;
1222         sqp->header_buf = dma_alloc_coherent(&dev->pdev->dev, sqp->header_buf_size,
1223                                              &sqp->header_dma, GFP_KERNEL);
1224         if (!sqp->header_buf)
1225                 return -ENOMEM;
1226
1227         spin_lock_irq(&dev->qp_table.lock);
1228         if (mthca_array_get(&dev->qp_table.qp, mqpn))
1229                 err = -EBUSY;
1230         else
1231                 mthca_array_set(&dev->qp_table.qp, mqpn, sqp);
1232         spin_unlock_irq(&dev->qp_table.lock);
1233
1234         if (err)
1235                 goto err_out;
1236
1237         sqp->port = port;
1238         sqp->qp.qpn       = mqpn;
1239         sqp->qp.transport = MLX;
1240
1241         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1242                                     send_policy, &sqp->qp);
1243         if (err)
1244                 goto err_out_free;
1245
1246         atomic_inc(&pd->sqp_count);
1247
1248         return 0;
1249
1250  err_out_free:
1251         /*
1252          * Lock CQs here, so that CQ polling code can do QP lookup
1253          * without taking a lock.
1254          */
1255         spin_lock_irq(&send_cq->lock);
1256         if (send_cq != recv_cq)
1257                 spin_lock(&recv_cq->lock);
1258
1259         spin_lock(&dev->qp_table.lock);
1260         mthca_array_clear(&dev->qp_table.qp, mqpn);
1261         spin_unlock(&dev->qp_table.lock);
1262
1263         if (send_cq != recv_cq)
1264                 spin_unlock(&recv_cq->lock);
1265         spin_unlock_irq(&send_cq->lock);
1266
1267  err_out:
1268         dma_free_coherent(&dev->pdev->dev, sqp->header_buf_size,
1269                           sqp->header_buf, sqp->header_dma);
1270
1271         return err;
1272 }
1273
1274 void mthca_free_qp(struct mthca_dev *dev,
1275                    struct mthca_qp *qp)
1276 {
1277         u8 status;
1278         struct mthca_cq *send_cq;
1279         struct mthca_cq *recv_cq;
1280
1281         send_cq = to_mcq(qp->ibqp.send_cq);
1282         recv_cq = to_mcq(qp->ibqp.recv_cq);
1283
1284         /*
1285          * Lock CQs here, so that CQ polling code can do QP lookup
1286          * without taking a lock.
1287          */
1288         spin_lock_irq(&send_cq->lock);
1289         if (send_cq != recv_cq)
1290                 spin_lock(&recv_cq->lock);
1291
1292         spin_lock(&dev->qp_table.lock);
1293         mthca_array_clear(&dev->qp_table.qp,
1294                           qp->qpn & (dev->limits.num_qps - 1));
1295         spin_unlock(&dev->qp_table.lock);
1296
1297         if (send_cq != recv_cq)
1298                 spin_unlock(&recv_cq->lock);
1299         spin_unlock_irq(&send_cq->lock);
1300
1301         atomic_dec(&qp->refcount);
1302         wait_event(qp->wait, !atomic_read(&qp->refcount));
1303
1304         if (qp->state != IB_QPS_RESET)
1305                 mthca_MODIFY_QP(dev, qp->state, IB_QPS_RESET, qp->qpn, 0,
1306                                 NULL, 0, &status);
1307
1308         /*
1309          * If this is a userspace QP, the buffers, MR, CQs and so on
1310          * will be cleaned up in userspace, so all we have to do is
1311          * unref the mem-free tables and free the QPN in our table.
1312          */
1313         if (!qp->ibqp.uobject) {
1314                 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq)->cqn, qp->qpn,
1315                                qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1316                 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
1317                         mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq)->cqn, qp->qpn,
1318                                        qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1319
1320                 mthca_free_memfree(dev, qp);
1321                 mthca_free_wqe_buf(dev, qp);
1322         }
1323
1324         mthca_unmap_memfree(dev, qp);
1325
1326         if (is_sqp(dev, qp)) {
1327                 atomic_dec(&(to_mpd(qp->ibqp.pd)->sqp_count));
1328                 dma_free_coherent(&dev->pdev->dev,
1329                                   to_msqp(qp)->header_buf_size,
1330                                   to_msqp(qp)->header_buf,
1331                                   to_msqp(qp)->header_dma);
1332         } else
1333                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1334 }
1335
1336 /* Create UD header for an MLX send and build a data segment for it */
1337 static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp,
1338                             int ind, struct ib_send_wr *wr,
1339                             struct mthca_mlx_seg *mlx,
1340                             struct mthca_data_seg *data)
1341 {
1342         int header_size;
1343         int err;
1344         u16 pkey;
1345
1346         ib_ud_header_init(256, /* assume a MAD */
1347                           mthca_ah_grh_present(to_mah(wr->wr.ud.ah)),
1348                           &sqp->ud_header);
1349
1350         err = mthca_read_ah(dev, to_mah(wr->wr.ud.ah), &sqp->ud_header);
1351         if (err)
1352                 return err;
1353         mlx->flags &= ~cpu_to_be32(MTHCA_NEXT_SOLICIT | 1);
1354         mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MTHCA_MLX_VL15 : 0) |
1355                                   (sqp->ud_header.lrh.destination_lid ==
1356                                    IB_LID_PERMISSIVE ? MTHCA_MLX_SLR : 0) |
1357                                   (sqp->ud_header.lrh.service_level << 8));
1358         mlx->rlid = sqp->ud_header.lrh.destination_lid;
1359         mlx->vcrc = 0;
1360
1361         switch (wr->opcode) {
1362         case IB_WR_SEND:
1363                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1364                 sqp->ud_header.immediate_present = 0;
1365                 break;
1366         case IB_WR_SEND_WITH_IMM:
1367                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1368                 sqp->ud_header.immediate_present = 1;
1369                 sqp->ud_header.immediate_data = wr->imm_data;
1370                 break;
1371         default:
1372                 return -EINVAL;
1373         }
1374
1375         sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
1376         if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1377                 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1378         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1379         if (!sqp->qp.ibqp.qp_num)
1380                 ib_get_cached_pkey(&dev->ib_dev, sqp->port,
1381                                    sqp->pkey_index, &pkey);
1382         else
1383                 ib_get_cached_pkey(&dev->ib_dev, sqp->port,
1384                                    wr->wr.ud.pkey_index, &pkey);
1385         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1386         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1387         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1388         sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1389                                                sqp->qkey : wr->wr.ud.remote_qkey);
1390         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1391
1392         header_size = ib_ud_header_pack(&sqp->ud_header,
1393                                         sqp->header_buf +
1394                                         ind * MTHCA_UD_HEADER_SIZE);
1395
1396         data->byte_count = cpu_to_be32(header_size);
1397         data->lkey       = cpu_to_be32(to_mpd(sqp->qp.ibqp.pd)->ntmr.ibmr.lkey);
1398         data->addr       = cpu_to_be64(sqp->header_dma +
1399                                        ind * MTHCA_UD_HEADER_SIZE);
1400
1401         return 0;
1402 }
1403
1404 static inline int mthca_wq_overflow(struct mthca_wq *wq, int nreq,
1405                                     struct ib_cq *ib_cq)
1406 {
1407         unsigned cur;
1408         struct mthca_cq *cq;
1409
1410         cur = wq->head - wq->tail;
1411         if (likely(cur + nreq < wq->max))
1412                 return 0;
1413
1414         cq = to_mcq(ib_cq);
1415         spin_lock(&cq->lock);
1416         cur = wq->head - wq->tail;
1417         spin_unlock(&cq->lock);
1418
1419         return cur + nreq >= wq->max;
1420 }
1421
1422 int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1423                           struct ib_send_wr **bad_wr)
1424 {
1425         struct mthca_dev *dev = to_mdev(ibqp->device);
1426         struct mthca_qp *qp = to_mqp(ibqp);
1427         void *wqe;
1428         void *prev_wqe;
1429         unsigned long flags;
1430         int err = 0;
1431         int nreq;
1432         int i;
1433         int size;
1434         int size0 = 0;
1435         u32 f0 = 0;
1436         int ind;
1437         u8 op0 = 0;
1438
1439         spin_lock_irqsave(&qp->sq.lock, flags);
1440
1441         /* XXX check that state is OK to post send */
1442
1443         ind = qp->sq.next_ind;
1444
1445         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1446                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1447                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1448                                         " %d max, %d nreq)\n", qp->qpn,
1449                                         qp->sq.head, qp->sq.tail,
1450                                         qp->sq.max, nreq);
1451                         err = -ENOMEM;
1452                         *bad_wr = wr;
1453                         goto out;
1454                 }
1455
1456                 wqe = get_send_wqe(qp, ind);
1457                 prev_wqe = qp->sq.last;
1458                 qp->sq.last = wqe;
1459
1460                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1461                 ((struct mthca_next_seg *) wqe)->ee_nds = 0;
1462                 ((struct mthca_next_seg *) wqe)->flags =
1463                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1464                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1465                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1466                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1467                         cpu_to_be32(1);
1468                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1469                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1470                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1471
1472                 wqe += sizeof (struct mthca_next_seg);
1473                 size = sizeof (struct mthca_next_seg) / 16;
1474
1475                 switch (qp->transport) {
1476                 case RC:
1477                         switch (wr->opcode) {
1478                         case IB_WR_ATOMIC_CMP_AND_SWP:
1479                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1480                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1481                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1482                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1483                                         cpu_to_be32(wr->wr.atomic.rkey);
1484                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1485
1486                                 wqe += sizeof (struct mthca_raddr_seg);
1487
1488                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1489                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1490                                                 cpu_to_be64(wr->wr.atomic.swap);
1491                                         ((struct mthca_atomic_seg *) wqe)->compare =
1492                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1493                                 } else {
1494                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1495                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1496                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1497                                 }
1498
1499                                 wqe += sizeof (struct mthca_atomic_seg);
1500                                 size += (sizeof (struct mthca_raddr_seg) +
1501                                          sizeof (struct mthca_atomic_seg)) / 16;
1502                                 break;
1503
1504                         case IB_WR_RDMA_WRITE:
1505                         case IB_WR_RDMA_WRITE_WITH_IMM:
1506                         case IB_WR_RDMA_READ:
1507                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1508                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1509                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1510                                         cpu_to_be32(wr->wr.rdma.rkey);
1511                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1512                                 wqe += sizeof (struct mthca_raddr_seg);
1513                                 size += sizeof (struct mthca_raddr_seg) / 16;
1514                                 break;
1515
1516                         default:
1517                                 /* No extra segments required for sends */
1518                                 break;
1519                         }
1520
1521                         break;
1522
1523                 case UC:
1524                         switch (wr->opcode) {
1525                         case IB_WR_RDMA_WRITE:
1526                         case IB_WR_RDMA_WRITE_WITH_IMM:
1527                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1528                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1529                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1530                                         cpu_to_be32(wr->wr.rdma.rkey);
1531                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1532                                 wqe += sizeof (struct mthca_raddr_seg);
1533                                 size += sizeof (struct mthca_raddr_seg) / 16;
1534                                 break;
1535
1536                         default:
1537                                 /* No extra segments required for sends */
1538                                 break;
1539                         }
1540
1541                         break;
1542
1543                 case UD:
1544                         ((struct mthca_tavor_ud_seg *) wqe)->lkey =
1545                                 cpu_to_be32(to_mah(wr->wr.ud.ah)->key);
1546                         ((struct mthca_tavor_ud_seg *) wqe)->av_addr =
1547                                 cpu_to_be64(to_mah(wr->wr.ud.ah)->avdma);
1548                         ((struct mthca_tavor_ud_seg *) wqe)->dqpn =
1549                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1550                         ((struct mthca_tavor_ud_seg *) wqe)->qkey =
1551                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1552
1553                         wqe += sizeof (struct mthca_tavor_ud_seg);
1554                         size += sizeof (struct mthca_tavor_ud_seg) / 16;
1555                         break;
1556
1557                 case MLX:
1558                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1559                                                wqe - sizeof (struct mthca_next_seg),
1560                                                wqe);
1561                         if (err) {
1562                                 *bad_wr = wr;
1563                                 goto out;
1564                         }
1565                         wqe += sizeof (struct mthca_data_seg);
1566                         size += sizeof (struct mthca_data_seg) / 16;
1567                         break;
1568                 }
1569
1570                 if (wr->num_sge > qp->sq.max_gs) {
1571                         mthca_err(dev, "too many gathers\n");
1572                         err = -EINVAL;
1573                         *bad_wr = wr;
1574                         goto out;
1575                 }
1576
1577                 for (i = 0; i < wr->num_sge; ++i) {
1578                         ((struct mthca_data_seg *) wqe)->byte_count =
1579                                 cpu_to_be32(wr->sg_list[i].length);
1580                         ((struct mthca_data_seg *) wqe)->lkey =
1581                                 cpu_to_be32(wr->sg_list[i].lkey);
1582                         ((struct mthca_data_seg *) wqe)->addr =
1583                                 cpu_to_be64(wr->sg_list[i].addr);
1584                         wqe += sizeof (struct mthca_data_seg);
1585                         size += sizeof (struct mthca_data_seg) / 16;
1586                 }
1587
1588                 /* Add one more inline data segment for ICRC */
1589                 if (qp->transport == MLX) {
1590                         ((struct mthca_data_seg *) wqe)->byte_count =
1591                                 cpu_to_be32((1 << 31) | 4);
1592                         ((u32 *) wqe)[1] = 0;
1593                         wqe += sizeof (struct mthca_data_seg);
1594                         size += sizeof (struct mthca_data_seg) / 16;
1595                 }
1596
1597                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1598
1599                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1600                         mthca_err(dev, "opcode invalid\n");
1601                         err = -EINVAL;
1602                         *bad_wr = wr;
1603                         goto out;
1604                 }
1605
1606                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1607                         cpu_to_be32(((ind << qp->sq.wqe_shift) +
1608                                      qp->send_wqe_offset) |
1609                                     mthca_opcode[wr->opcode]);
1610                 wmb();
1611                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1612                         cpu_to_be32((size0 ? 0 : MTHCA_NEXT_DBD) | size |
1613                                     ((wr->send_flags & IB_SEND_FENCE) ?
1614                                     MTHCA_NEXT_FENCE : 0));
1615
1616                 if (!size0) {
1617                         size0 = size;
1618                         op0   = mthca_opcode[wr->opcode];
1619                 }
1620
1621                 ++ind;
1622                 if (unlikely(ind >= qp->sq.max))
1623                         ind -= qp->sq.max;
1624         }
1625
1626 out:
1627         if (likely(nreq)) {
1628                 __be32 doorbell[2];
1629
1630                 doorbell[0] = cpu_to_be32(((qp->sq.next_ind << qp->sq.wqe_shift) +
1631                                            qp->send_wqe_offset) | f0 | op0);
1632                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1633
1634                 wmb();
1635
1636                 mthca_write64(doorbell,
1637                               dev->kar + MTHCA_SEND_DOORBELL,
1638                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1639         }
1640
1641         qp->sq.next_ind = ind;
1642         qp->sq.head    += nreq;
1643
1644         spin_unlock_irqrestore(&qp->sq.lock, flags);
1645         return err;
1646 }
1647
1648 int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1649                              struct ib_recv_wr **bad_wr)
1650 {
1651         struct mthca_dev *dev = to_mdev(ibqp->device);
1652         struct mthca_qp *qp = to_mqp(ibqp);
1653         __be32 doorbell[2];
1654         unsigned long flags;
1655         int err = 0;
1656         int nreq;
1657         int i;
1658         int size;
1659         int size0 = 0;
1660         int ind;
1661         void *wqe;
1662         void *prev_wqe;
1663
1664         spin_lock_irqsave(&qp->rq.lock, flags);
1665
1666         /* XXX check that state is OK to post receive */
1667
1668         ind = qp->rq.next_ind;
1669
1670         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1671                 if (unlikely(nreq == MTHCA_TAVOR_MAX_WQES_PER_RECV_DB)) {
1672                         nreq = 0;
1673
1674                         doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1675                         doorbell[1] = cpu_to_be32(qp->qpn << 8);
1676
1677                         wmb();
1678
1679                         mthca_write64(doorbell,
1680                                       dev->kar + MTHCA_RECEIVE_DOORBELL,
1681                                       MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1682
1683                         qp->rq.head += MTHCA_TAVOR_MAX_WQES_PER_RECV_DB;
1684                         size0 = 0;
1685                 }
1686
1687                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1688                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
1689                                         " %d max, %d nreq)\n", qp->qpn,
1690                                         qp->rq.head, qp->rq.tail,
1691                                         qp->rq.max, nreq);
1692                         err = -ENOMEM;
1693                         *bad_wr = wr;
1694                         goto out;
1695                 }
1696
1697                 wqe = get_recv_wqe(qp, ind);
1698                 prev_wqe = qp->rq.last;
1699                 qp->rq.last = wqe;
1700
1701                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1702                 ((struct mthca_next_seg *) wqe)->ee_nds =
1703                         cpu_to_be32(MTHCA_NEXT_DBD);
1704                 ((struct mthca_next_seg *) wqe)->flags = 0;
1705
1706                 wqe += sizeof (struct mthca_next_seg);
1707                 size = sizeof (struct mthca_next_seg) / 16;
1708
1709                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1710                         err = -EINVAL;
1711                         *bad_wr = wr;
1712                         goto out;
1713                 }
1714
1715                 for (i = 0; i < wr->num_sge; ++i) {
1716                         ((struct mthca_data_seg *) wqe)->byte_count =
1717                                 cpu_to_be32(wr->sg_list[i].length);
1718                         ((struct mthca_data_seg *) wqe)->lkey =
1719                                 cpu_to_be32(wr->sg_list[i].lkey);
1720                         ((struct mthca_data_seg *) wqe)->addr =
1721                                 cpu_to_be64(wr->sg_list[i].addr);
1722                         wqe += sizeof (struct mthca_data_seg);
1723                         size += sizeof (struct mthca_data_seg) / 16;
1724                 }
1725
1726                 qp->wrid[ind] = wr->wr_id;
1727
1728                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1729                         cpu_to_be32((ind << qp->rq.wqe_shift) | 1);
1730                 wmb();
1731                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1732                         cpu_to_be32(MTHCA_NEXT_DBD | size);
1733
1734                 if (!size0)
1735                         size0 = size;
1736
1737                 ++ind;
1738                 if (unlikely(ind >= qp->rq.max))
1739                         ind -= qp->rq.max;
1740         }
1741
1742 out:
1743         if (likely(nreq)) {
1744                 doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1745                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | nreq);
1746
1747                 wmb();
1748
1749                 mthca_write64(doorbell,
1750                               dev->kar + MTHCA_RECEIVE_DOORBELL,
1751                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1752         }
1753
1754         qp->rq.next_ind = ind;
1755         qp->rq.head    += nreq;
1756
1757         spin_unlock_irqrestore(&qp->rq.lock, flags);
1758         return err;
1759 }
1760
1761 int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1762                           struct ib_send_wr **bad_wr)
1763 {
1764         struct mthca_dev *dev = to_mdev(ibqp->device);
1765         struct mthca_qp *qp = to_mqp(ibqp);
1766         __be32 doorbell[2];
1767         void *wqe;
1768         void *prev_wqe;
1769         unsigned long flags;
1770         int err = 0;
1771         int nreq;
1772         int i;
1773         int size;
1774         int size0 = 0;
1775         u32 f0 = 0;
1776         int ind;
1777         u8 op0 = 0;
1778
1779         spin_lock_irqsave(&qp->sq.lock, flags);
1780
1781         /* XXX check that state is OK to post send */
1782
1783         ind = qp->sq.head & (qp->sq.max - 1);
1784
1785         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1786                 if (unlikely(nreq == MTHCA_ARBEL_MAX_WQES_PER_SEND_DB)) {
1787                         nreq = 0;
1788
1789                         doorbell[0] = cpu_to_be32((MTHCA_ARBEL_MAX_WQES_PER_SEND_DB << 24) |
1790                                                   ((qp->sq.head & 0xffff) << 8) |
1791                                                   f0 | op0);
1792                         doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1793
1794                         qp->sq.head += MTHCA_ARBEL_MAX_WQES_PER_SEND_DB;
1795                         size0 = 0;
1796
1797                         /*
1798                          * Make sure that descriptors are written before
1799                          * doorbell record.
1800                          */
1801                         wmb();
1802                         *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
1803
1804                         /*
1805                          * Make sure doorbell record is written before we
1806                          * write MMIO send doorbell.
1807                          */
1808                         wmb();
1809                         mthca_write64(doorbell,
1810                                       dev->kar + MTHCA_SEND_DOORBELL,
1811                                       MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1812                 }
1813
1814                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1815                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1816                                         " %d max, %d nreq)\n", qp->qpn,
1817                                         qp->sq.head, qp->sq.tail,
1818                                         qp->sq.max, nreq);
1819                         err = -ENOMEM;
1820                         *bad_wr = wr;
1821                         goto out;
1822                 }
1823
1824                 wqe = get_send_wqe(qp, ind);
1825                 prev_wqe = qp->sq.last;
1826                 qp->sq.last = wqe;
1827
1828                 ((struct mthca_next_seg *) wqe)->flags =
1829                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1830                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1831                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1832                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1833                         cpu_to_be32(1);
1834                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1835                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1836                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1837
1838                 wqe += sizeof (struct mthca_next_seg);
1839                 size = sizeof (struct mthca_next_seg) / 16;
1840
1841                 switch (qp->transport) {
1842                 case RC:
1843                         switch (wr->opcode) {
1844                         case IB_WR_ATOMIC_CMP_AND_SWP:
1845                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1846                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1847                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1848                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1849                                         cpu_to_be32(wr->wr.atomic.rkey);
1850                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1851
1852                                 wqe += sizeof (struct mthca_raddr_seg);
1853
1854                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1855                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1856                                                 cpu_to_be64(wr->wr.atomic.swap);
1857                                         ((struct mthca_atomic_seg *) wqe)->compare =
1858                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1859                                 } else {
1860                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1861                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1862                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1863                                 }
1864
1865                                 wqe += sizeof (struct mthca_atomic_seg);
1866                                 size += (sizeof (struct mthca_raddr_seg) +
1867                                          sizeof (struct mthca_atomic_seg)) / 16;
1868                                 break;
1869
1870                         case IB_WR_RDMA_READ:
1871                         case IB_WR_RDMA_WRITE:
1872                         case IB_WR_RDMA_WRITE_WITH_IMM:
1873                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1874                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1875                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1876                                         cpu_to_be32(wr->wr.rdma.rkey);
1877                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1878                                 wqe += sizeof (struct mthca_raddr_seg);
1879                                 size += sizeof (struct mthca_raddr_seg) / 16;
1880                                 break;
1881
1882                         default:
1883                                 /* No extra segments required for sends */
1884                                 break;
1885                         }
1886
1887                         break;
1888
1889                 case UC:
1890                         switch (wr->opcode) {
1891                         case IB_WR_RDMA_WRITE:
1892                         case IB_WR_RDMA_WRITE_WITH_IMM:
1893                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1894                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1895                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1896                                         cpu_to_be32(wr->wr.rdma.rkey);
1897                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1898                                 wqe += sizeof (struct mthca_raddr_seg);
1899                                 size += sizeof (struct mthca_raddr_seg) / 16;
1900                                 break;
1901
1902                         default:
1903                                 /* No extra segments required for sends */
1904                                 break;
1905                         }
1906
1907                         break;
1908
1909                 case UD:
1910                         memcpy(((struct mthca_arbel_ud_seg *) wqe)->av,
1911                                to_mah(wr->wr.ud.ah)->av, MTHCA_AV_SIZE);
1912                         ((struct mthca_arbel_ud_seg *) wqe)->dqpn =
1913                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1914                         ((struct mthca_arbel_ud_seg *) wqe)->qkey =
1915                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1916
1917                         wqe += sizeof (struct mthca_arbel_ud_seg);
1918                         size += sizeof (struct mthca_arbel_ud_seg) / 16;
1919                         break;
1920
1921                 case MLX:
1922                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1923                                                wqe - sizeof (struct mthca_next_seg),
1924                                                wqe);
1925                         if (err) {
1926                                 *bad_wr = wr;
1927                                 goto out;
1928                         }
1929                         wqe += sizeof (struct mthca_data_seg);
1930                         size += sizeof (struct mthca_data_seg) / 16;
1931                         break;
1932                 }
1933
1934                 if (wr->num_sge > qp->sq.max_gs) {
1935                         mthca_err(dev, "too many gathers\n");
1936                         err = -EINVAL;
1937                         *bad_wr = wr;
1938                         goto out;
1939                 }
1940
1941                 for (i = 0; i < wr->num_sge; ++i) {
1942                         ((struct mthca_data_seg *) wqe)->byte_count =
1943                                 cpu_to_be32(wr->sg_list[i].length);
1944                         ((struct mthca_data_seg *) wqe)->lkey =
1945                                 cpu_to_be32(wr->sg_list[i].lkey);
1946                         ((struct mthca_data_seg *) wqe)->addr =
1947                                 cpu_to_be64(wr->sg_list[i].addr);
1948                         wqe += sizeof (struct mthca_data_seg);
1949                         size += sizeof (struct mthca_data_seg) / 16;
1950                 }
1951
1952                 /* Add one more inline data segment for ICRC */
1953                 if (qp->transport == MLX) {
1954                         ((struct mthca_data_seg *) wqe)->byte_count =
1955                                 cpu_to_be32((1 << 31) | 4);
1956                         ((u32 *) wqe)[1] = 0;
1957                         wqe += sizeof (struct mthca_data_seg);
1958                         size += sizeof (struct mthca_data_seg) / 16;
1959                 }
1960
1961                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1962
1963                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1964                         mthca_err(dev, "opcode invalid\n");
1965                         err = -EINVAL;
1966                         *bad_wr = wr;
1967                         goto out;
1968                 }
1969
1970                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1971                         cpu_to_be32(((ind << qp->sq.wqe_shift) +
1972                                      qp->send_wqe_offset) |
1973                                     mthca_opcode[wr->opcode]);
1974                 wmb();
1975                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1976                         cpu_to_be32(MTHCA_NEXT_DBD | size |
1977                                     ((wr->send_flags & IB_SEND_FENCE) ?
1978                                     MTHCA_NEXT_FENCE : 0));
1979
1980                 if (!size0) {
1981                         size0 = size;
1982                         op0   = mthca_opcode[wr->opcode];
1983                 }
1984
1985                 ++ind;
1986                 if (unlikely(ind >= qp->sq.max))
1987                         ind -= qp->sq.max;
1988         }
1989
1990 out:
1991         if (likely(nreq)) {
1992                 doorbell[0] = cpu_to_be32((nreq << 24)                  |
1993                                           ((qp->sq.head & 0xffff) << 8) |
1994                                           f0 | op0);
1995                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1996
1997                 qp->sq.head += nreq;
1998
1999                 /*
2000                  * Make sure that descriptors are written before
2001                  * doorbell record.
2002                  */
2003                 wmb();
2004                 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
2005
2006                 /*
2007                  * Make sure doorbell record is written before we
2008                  * write MMIO send doorbell.
2009                  */
2010                 wmb();
2011                 mthca_write64(doorbell,
2012                               dev->kar + MTHCA_SEND_DOORBELL,
2013                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
2014         }
2015
2016         spin_unlock_irqrestore(&qp->sq.lock, flags);
2017         return err;
2018 }
2019
2020 int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2021                              struct ib_recv_wr **bad_wr)
2022 {
2023         struct mthca_dev *dev = to_mdev(ibqp->device);
2024         struct mthca_qp *qp = to_mqp(ibqp);
2025         unsigned long flags;
2026         int err = 0;
2027         int nreq;
2028         int ind;
2029         int i;
2030         void *wqe;
2031
2032         spin_lock_irqsave(&qp->rq.lock, flags);
2033
2034         /* XXX check that state is OK to post receive */
2035
2036         ind = qp->rq.head & (qp->rq.max - 1);
2037
2038         for (nreq = 0; wr; ++nreq, wr = wr->next) {
2039                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2040                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
2041                                         " %d max, %d nreq)\n", qp->qpn,
2042                                         qp->rq.head, qp->rq.tail,
2043                                         qp->rq.max, nreq);
2044                         err = -ENOMEM;
2045                         *bad_wr = wr;
2046                         goto out;
2047                 }
2048
2049                 wqe = get_recv_wqe(qp, ind);
2050
2051                 ((struct mthca_next_seg *) wqe)->flags = 0;
2052
2053                 wqe += sizeof (struct mthca_next_seg);
2054
2055                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2056                         err = -EINVAL;
2057                         *bad_wr = wr;
2058                         goto out;
2059                 }
2060
2061                 for (i = 0; i < wr->num_sge; ++i) {
2062                         ((struct mthca_data_seg *) wqe)->byte_count =
2063                                 cpu_to_be32(wr->sg_list[i].length);
2064                         ((struct mthca_data_seg *) wqe)->lkey =
2065                                 cpu_to_be32(wr->sg_list[i].lkey);
2066                         ((struct mthca_data_seg *) wqe)->addr =
2067                                 cpu_to_be64(wr->sg_list[i].addr);
2068                         wqe += sizeof (struct mthca_data_seg);
2069                 }
2070
2071                 if (i < qp->rq.max_gs) {
2072                         ((struct mthca_data_seg *) wqe)->byte_count = 0;
2073                         ((struct mthca_data_seg *) wqe)->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
2074                         ((struct mthca_data_seg *) wqe)->addr = 0;
2075                 }
2076
2077                 qp->wrid[ind] = wr->wr_id;
2078
2079                 ++ind;
2080                 if (unlikely(ind >= qp->rq.max))
2081                         ind -= qp->rq.max;
2082         }
2083 out:
2084         if (likely(nreq)) {
2085                 qp->rq.head += nreq;
2086
2087                 /*
2088                  * Make sure that descriptors are written before
2089                  * doorbell record.
2090                  */
2091                 wmb();
2092                 *qp->rq.db = cpu_to_be32(qp->rq.head & 0xffff);
2093         }
2094
2095         spin_unlock_irqrestore(&qp->rq.lock, flags);
2096         return err;
2097 }
2098
2099 void mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
2100                         int index, int *dbd, __be32 *new_wqe)
2101 {
2102         struct mthca_next_seg *next;
2103
2104         /*
2105          * For SRQs, all WQEs generate a CQE, so we're always at the
2106          * end of the doorbell chain.
2107          */
2108         if (qp->ibqp.srq) {
2109                 *new_wqe = 0;
2110                 return;
2111         }
2112
2113         if (is_send)
2114                 next = get_send_wqe(qp, index);
2115         else
2116                 next = get_recv_wqe(qp, index);
2117
2118         *dbd = !!(next->ee_nds & cpu_to_be32(MTHCA_NEXT_DBD));
2119         if (next->ee_nds & cpu_to_be32(0x3f))
2120                 *new_wqe = (next->nda_op & cpu_to_be32(~0x3f)) |
2121                         (next->ee_nds & cpu_to_be32(0x3f));
2122         else
2123                 *new_wqe = 0;
2124 }
2125
2126 int __devinit mthca_init_qp_table(struct mthca_dev *dev)
2127 {
2128         int err;
2129         u8 status;
2130         int i;
2131
2132         spin_lock_init(&dev->qp_table.lock);
2133
2134         /*
2135          * We reserve 2 extra QPs per port for the special QPs.  The
2136          * special QP for port 1 has to be even, so round up.
2137          */
2138         dev->qp_table.sqp_start = (dev->limits.reserved_qps + 1) & ~1UL;
2139         err = mthca_alloc_init(&dev->qp_table.alloc,
2140                                dev->limits.num_qps,
2141                                (1 << 24) - 1,
2142                                dev->qp_table.sqp_start +
2143                                MTHCA_MAX_PORTS * 2);
2144         if (err)
2145                 return err;
2146
2147         err = mthca_array_init(&dev->qp_table.qp,
2148                                dev->limits.num_qps);
2149         if (err) {
2150                 mthca_alloc_cleanup(&dev->qp_table.alloc);
2151                 return err;
2152         }
2153
2154         for (i = 0; i < 2; ++i) {
2155                 err = mthca_CONF_SPECIAL_QP(dev, i ? IB_QPT_GSI : IB_QPT_SMI,
2156                                             dev->qp_table.sqp_start + i * 2,
2157                                             &status);
2158                 if (err)
2159                         goto err_out;
2160                 if (status) {
2161                         mthca_warn(dev, "CONF_SPECIAL_QP returned "
2162                                    "status %02x, aborting.\n",
2163                                    status);
2164                         err = -EINVAL;
2165                         goto err_out;
2166                 }
2167         }
2168         return 0;
2169
2170  err_out:
2171         for (i = 0; i < 2; ++i)
2172                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2173
2174         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2175         mthca_alloc_cleanup(&dev->qp_table.alloc);
2176
2177         return err;
2178 }
2179
2180 void __devexit mthca_cleanup_qp_table(struct mthca_dev *dev)
2181 {
2182         int i;
2183         u8 status;
2184
2185         for (i = 0; i < 2; ++i)
2186                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2187
2188         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2189         mthca_alloc_cleanup(&dev->qp_table.alloc);
2190 }