drivers/infiniband/hw/mthca/mthca_qp.c

   1 /*
   2  * Copyright (c) 2004 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Cisco Systems. All rights reserved.
   4  * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
   5  * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * OpenIB.org BSD license below:
  12  *
  13  *     Redistribution and use in source and binary forms, with or
  14  *     without modification, are permitted provided that the following
  15  *     conditions are met:
  16  *
  17  *      - Redistributions of source code must retain the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer.
  20  *
  21  *      - Redistributions in binary form must reproduce the above
  22  *        copyright notice, this list of conditions and the following
  23  *        disclaimer in the documentation and/or other materials
  24  *        provided with the distribution.
  25  *
  26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33  * SOFTWARE.
  34  *
  35  * $Id: mthca_qp.c 1355 2004-12-17 15:23:43Z roland $
  36  */
  37
  38 #include <linux/init.h>
  39 #include <linux/string.h>
  40 #include <linux/slab.h>
  41
  42 #include <rdma/ib_verbs.h>
  43 #include <rdma/ib_cache.h>
  44 #include <rdma/ib_pack.h>
  45
  46 #include "mthca_dev.h"
  47 #include "mthca_cmd.h"
  48 #include "mthca_memfree.h"
  49 #include "mthca_wqe.h"
  50
  51 enum {
  52         MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE,
  53         MTHCA_ACK_REQ_FREQ       = 10,
  54         MTHCA_FLIGHT_LIMIT       = 9,
  55         MTHCA_UD_HEADER_SIZE     = 72, /* largest UD header possible */
  56         MTHCA_INLINE_HEADER_SIZE = 4,  /* data segment overhead for inline */
  57         MTHCA_INLINE_CHUNK_SIZE  = 16  /* inline data segment chunk */
  58 };
  59
  60 enum {
  61         MTHCA_QP_STATE_RST  = 0,
  62         MTHCA_QP_STATE_INIT = 1,
  63         MTHCA_QP_STATE_RTR  = 2,
  64         MTHCA_QP_STATE_RTS  = 3,
  65         MTHCA_QP_STATE_SQE  = 4,
  66         MTHCA_QP_STATE_SQD  = 5,
  67         MTHCA_QP_STATE_ERR  = 6,
  68         MTHCA_QP_STATE_DRAINING = 7
  69 };
  70
  71 enum {
  72         MTHCA_QP_ST_RC  = 0x0,
  73         MTHCA_QP_ST_UC  = 0x1,
  74         MTHCA_QP_ST_RD  = 0x2,
  75         MTHCA_QP_ST_UD  = 0x3,
  76         MTHCA_QP_ST_MLX = 0x7
  77 };
  78
  79 enum {
  80         MTHCA_QP_PM_MIGRATED = 0x3,
  81         MTHCA_QP_PM_ARMED    = 0x0,
  82         MTHCA_QP_PM_REARM    = 0x1
  83 };
  84
  85 enum {
  86         /* qp_context flags */
  87         MTHCA_QP_BIT_DE  = 1 <<  8,
  88         /* params1 */
  89         MTHCA_QP_BIT_SRE = 1 << 15,
  90         MTHCA_QP_BIT_SWE = 1 << 14,
  91         MTHCA_QP_BIT_SAE = 1 << 13,
  92         MTHCA_QP_BIT_SIC = 1 <<  4,
  93         MTHCA_QP_BIT_SSC = 1 <<  3,
  94         /* params2 */
  95         MTHCA_QP_BIT_RRE = 1 << 15,
  96         MTHCA_QP_BIT_RWE = 1 << 14,
  97         MTHCA_QP_BIT_RAE = 1 << 13,
  98         MTHCA_QP_BIT_RIC = 1 <<  4,
  99         MTHCA_QP_BIT_RSC = 1 <<  3
 100 };
 101
 102 struct mthca_qp_path {
 103         __be32 port_pkey;
 104         u8     rnr_retry;
 105         u8     g_mylmc;
 106         __be16 rlid;
 107         u8     ackto;
 108         u8     mgid_index;
 109         u8     static_rate;
 110         u8     hop_limit;
 111         __be32 sl_tclass_flowlabel;
 112         u8     rgid[16];
 113 } __attribute__((packed));
 114
 115 struct mthca_qp_context {
 116         __be32 flags;
 117         __be32 tavor_sched_queue; /* Reserved on Arbel */
 118         u8     mtu_msgmax;
 119         u8     rq_size_stride;  /* Reserved on Tavor */
 120         u8     sq_size_stride;  /* Reserved on Tavor */
 121         u8     rlkey_arbel_sched_queue; /* Reserved on Tavor */
 122         __be32 usr_page;
 123         __be32 local_qpn;
 124         __be32 remote_qpn;
 125         u32    reserved1[2];
 126         struct mthca_qp_path pri_path;
 127         struct mthca_qp_path alt_path;
 128         __be32 rdd;
 129         __be32 pd;
 130         __be32 wqe_base;
 131         __be32 wqe_lkey;
 132         __be32 params1;
 133         __be32 reserved2;
 134         __be32 next_send_psn;
 135         __be32 cqn_snd;
 136         __be32 snd_wqe_base_l;  /* Next send WQE on Tavor */
 137         __be32 snd_db_index;    /* (debugging only entries) */
 138         __be32 last_acked_psn;
 139         __be32 ssn;
 140         __be32 params2;
 141         __be32 rnr_nextrecvpsn;
 142         __be32 ra_buff_indx;
 143         __be32 cqn_rcv;
 144         __be32 rcv_wqe_base_l;  /* Next recv WQE on Tavor */
 145         __be32 rcv_db_index;    /* (debugging only entries) */
 146         __be32 qkey;
 147         __be32 srqn;
 148         __be32 rmsn;
 149         __be16 rq_wqe_counter;  /* reserved on Tavor */
 150         __be16 sq_wqe_counter;  /* reserved on Tavor */
 151         u32    reserved3[18];
 152 } __attribute__((packed));
 153
 154 struct mthca_qp_param {
 155         __be32 opt_param_mask;
 156         u32    reserved1;
 157         struct mthca_qp_context context;
 158         u32    reserved2[62];
 159 } __attribute__((packed));
 160
 161 enum {
 162         MTHCA_QP_OPTPAR_ALT_ADDR_PATH     = 1 << 0,
 163         MTHCA_QP_OPTPAR_RRE               = 1 << 1,
 164         MTHCA_QP_OPTPAR_RAE               = 1 << 2,
 165         MTHCA_QP_OPTPAR_RWE               = 1 << 3,
 166         MTHCA_QP_OPTPAR_PKEY_INDEX        = 1 << 4,
 167         MTHCA_QP_OPTPAR_Q_KEY             = 1 << 5,
 168         MTHCA_QP_OPTPAR_RNR_TIMEOUT       = 1 << 6,
 169         MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
 170         MTHCA_QP_OPTPAR_SRA_MAX           = 1 << 8,
 171         MTHCA_QP_OPTPAR_RRA_MAX           = 1 << 9,
 172         MTHCA_QP_OPTPAR_PM_STATE          = 1 << 10,
 173         MTHCA_QP_OPTPAR_PORT_NUM          = 1 << 11,
 174         MTHCA_QP_OPTPAR_RETRY_COUNT       = 1 << 12,
 175         MTHCA_QP_OPTPAR_ALT_RNR_RETRY     = 1 << 13,
 176         MTHCA_QP_OPTPAR_ACK_TIMEOUT       = 1 << 14,
 177         MTHCA_QP_OPTPAR_RNR_RETRY         = 1 << 15,
 178         MTHCA_QP_OPTPAR_SCHED_QUEUE       = 1 << 16
 179 };
 180
 181 static const u8 mthca_opcode[] = {
 182         [IB_WR_SEND]                 = MTHCA_OPCODE_SEND,
 183         [IB_WR_SEND_WITH_IMM]        = MTHCA_OPCODE_SEND_IMM,
 184         [IB_WR_RDMA_WRITE]           = MTHCA_OPCODE_RDMA_WRITE,
 185         [IB_WR_RDMA_WRITE_WITH_IMM]  = MTHCA_OPCODE_RDMA_WRITE_IMM,
 186         [IB_WR_RDMA_READ]            = MTHCA_OPCODE_RDMA_READ,
 187         [IB_WR_ATOMIC_CMP_AND_SWP]   = MTHCA_OPCODE_ATOMIC_CS,
 188         [IB_WR_ATOMIC_FETCH_AND_ADD] = MTHCA_OPCODE_ATOMIC_FA,
 189 };
 190
 191 static int is_sqp(struct mthca_dev *dev, struct mthca_qp *qp)
 192 {
 193         return qp->qpn >= dev->qp_table.sqp_start &&
 194                 qp->qpn <= dev->qp_table.sqp_start + 3;
 195 }
 196
 197 static int is_qp0(struct mthca_dev *dev, struct mthca_qp *qp)
 198 {
 199         return qp->qpn >= dev->qp_table.sqp_start &&
 200                 qp->qpn <= dev->qp_table.sqp_start + 1;
 201 }
 202
 203 static void *get_recv_wqe(struct mthca_qp *qp, int n)
 204 {
 205         if (qp->is_direct)
 206                 return qp->queue.direct.buf + (n << qp->rq.wqe_shift);
 207         else
 208                 return qp->queue.page_list[(n << qp->rq.wqe_shift) >> PAGE_SHIFT].buf +
 209                         ((n << qp->rq.wqe_shift) & (PAGE_SIZE - 1));
 210 }
 211
 212 static void *get_send_wqe(struct mthca_qp *qp, int n)
 213 {
 214         if (qp->is_direct)
 215                 return qp->queue.direct.buf + qp->send_wqe_offset +
 216                         (n << qp->sq.wqe_shift);
 217         else
 218                 return qp->queue.page_list[(qp->send_wqe_offset +
 219                                             (n << qp->sq.wqe_shift)) >>
 220                                            PAGE_SHIFT].buf +
 221                         ((qp->send_wqe_offset + (n << qp->sq.wqe_shift)) &
 222                          (PAGE_SIZE - 1));
 223 }
 224
 225 static void mthca_wq_init(struct mthca_wq *wq)
 226 {
 227         spin_lock_init(&wq->lock);
 228         wq->next_ind  = 0;
 229         wq->last_comp = wq->max - 1;
 230         wq->head      = 0;
 231         wq->tail      = 0;
 232 }
 233
 234 void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
 235                     enum ib_event_type event_type)
 236 {
 237         struct mthca_qp *qp;
 238         struct ib_event event;
 239
 240         spin_lock(&dev->qp_table.lock);
 241         qp = mthca_array_get(&dev->qp_table.qp, qpn & (dev->limits.num_qps - 1));
 242         if (qp)
 243                 atomic_inc(&qp->refcount);
 244         spin_unlock(&dev->qp_table.lock);
 245
 246         if (!qp) {
 247                 mthca_warn(dev, "Async event for bogus QP %08x\n", qpn);
 248                 return;
 249         }
 250
 251         event.device      = &dev->ib_dev;
 252         event.event       = event_type;
 253         event.element.qp  = &qp->ibqp;
 254         if (qp->ibqp.event_handler)
 255                 qp->ibqp.event_handler(&event, qp->ibqp.qp_context);
 256
 257         if (atomic_dec_and_test(&qp->refcount))
 258                 wake_up(&qp->wait);
 259 }
 260
 261 static int to_mthca_state(enum ib_qp_state ib_state)
 262 {
 263         switch (ib_state) {
 264         case IB_QPS_RESET: return MTHCA_QP_STATE_RST;
 265         case IB_QPS_INIT:  return MTHCA_QP_STATE_INIT;
 266         case IB_QPS_RTR:   return MTHCA_QP_STATE_RTR;
 267         case IB_QPS_RTS:   return MTHCA_QP_STATE_RTS;
 268         case IB_QPS_SQD:   return MTHCA_QP_STATE_SQD;
 269         case IB_QPS_SQE:   return MTHCA_QP_STATE_SQE;
 270         case IB_QPS_ERR:   return MTHCA_QP_STATE_ERR;
 271         default:                return -1;
 272         }
 273 }
 274
 275 enum { RC, UC, UD, RD, RDEE, MLX, NUM_TRANS };
 276
 277 static int to_mthca_st(int transport)
 278 {
 279         switch (transport) {
 280         case RC:  return MTHCA_QP_ST_RC;
 281         case UC:  return MTHCA_QP_ST_UC;
 282         case UD:  return MTHCA_QP_ST_UD;
 283         case RD:  return MTHCA_QP_ST_RD;
 284         case MLX: return MTHCA_QP_ST_MLX;
 285         default:  return -1;
 286         }
 287 }
 288
 289 static const struct {
 290         int trans;
 291         u32 req_param[NUM_TRANS];
 292         u32 opt_param[NUM_TRANS];
 293 } state_table[IB_QPS_ERR + 1][IB_QPS_ERR + 1] = {
 294         [IB_QPS_RESET] = {
 295                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 296                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 297                 [IB_QPS_INIT]  = {
 298                         .trans = MTHCA_TRANS_RST2INIT,
 299                         .req_param = {
 300                                 [UD]  = (IB_QP_PKEY_INDEX |
 301                                          IB_QP_PORT       |
 302                                          IB_QP_QKEY),
 303                                 [UC]  = (IB_QP_PKEY_INDEX |
 304                                          IB_QP_PORT       |
 305                                          IB_QP_ACCESS_FLAGS),
 306                                 [RC]  = (IB_QP_PKEY_INDEX |
 307                                          IB_QP_PORT       |
 308                                          IB_QP_ACCESS_FLAGS),
 309                                 [MLX] = (IB_QP_PKEY_INDEX |
 310                                          IB_QP_QKEY),
 311                         },
 312                         /* bug-for-bug compatibility with VAPI: */
 313                         .opt_param = {
 314                                 [MLX] = IB_QP_PORT
 315                         }
 316                 },
 317         },
 318         [IB_QPS_INIT]  = {
 319                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 320                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 321                 [IB_QPS_INIT]  = {
 322                         .trans = MTHCA_TRANS_INIT2INIT,
 323                         .opt_param = {
 324                                 [UD]  = (IB_QP_PKEY_INDEX |
 325                                          IB_QP_PORT       |
 326                                          IB_QP_QKEY),
 327                                 [UC]  = (IB_QP_PKEY_INDEX |
 328                                          IB_QP_PORT       |
 329                                          IB_QP_ACCESS_FLAGS),
 330                                 [RC]  = (IB_QP_PKEY_INDEX |
 331                                          IB_QP_PORT       |
 332                                          IB_QP_ACCESS_FLAGS),
 333                                 [MLX] = (IB_QP_PKEY_INDEX |
 334                                          IB_QP_QKEY),
 335                         }
 336                 },
 337                 [IB_QPS_RTR]   = {
 338                         .trans = MTHCA_TRANS_INIT2RTR,
 339                         .req_param = {
 340                                 [UC]  = (IB_QP_AV                  |
 341                                          IB_QP_PATH_MTU            |
 342                                          IB_QP_DEST_QPN            |
 343                                          IB_QP_RQ_PSN),
 344                                 [RC]  = (IB_QP_AV                  |
 345                                          IB_QP_PATH_MTU            |
 346                                          IB_QP_DEST_QPN            |
 347                                          IB_QP_RQ_PSN              |
 348                                          IB_QP_MAX_DEST_RD_ATOMIC  |
 349                                          IB_QP_MIN_RNR_TIMER),
 350                         },
 351                         .opt_param = {
 352                                 [UD]  = (IB_QP_PKEY_INDEX |
 353                                          IB_QP_QKEY),
 354                                 [UC]  = (IB_QP_ALT_PATH     |
 355                                          IB_QP_ACCESS_FLAGS |
 356                                          IB_QP_PKEY_INDEX),
 357                                 [RC]  = (IB_QP_ALT_PATH     |
 358                                          IB_QP_ACCESS_FLAGS |
 359                                          IB_QP_PKEY_INDEX),
 360                                 [MLX] = (IB_QP_PKEY_INDEX |
 361                                          IB_QP_QKEY),
 362                         }
 363                 }
 364         },
 365         [IB_QPS_RTR]   = {
 366                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 367                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 368                 [IB_QPS_RTS]   = {
 369                         .trans = MTHCA_TRANS_RTR2RTS,
 370                         .req_param = {
 371                                 [UD]  = IB_QP_SQ_PSN,
 372                                 [UC]  = IB_QP_SQ_PSN,
 373                                 [RC]  = (IB_QP_TIMEOUT           |
 374                                          IB_QP_RETRY_CNT         |
 375                                          IB_QP_RNR_RETRY         |
 376                                          IB_QP_SQ_PSN            |
 377                                          IB_QP_MAX_QP_RD_ATOMIC),
 378                                 [MLX] = IB_QP_SQ_PSN,
 379                         },
 380                         .opt_param = {
 381                                 [UD]  = (IB_QP_CUR_STATE             |
 382                                          IB_QP_QKEY),
 383                                 [UC]  = (IB_QP_CUR_STATE             |
 384                                          IB_QP_ALT_PATH              |
 385                                          IB_QP_ACCESS_FLAGS          |
 386                                          IB_QP_PATH_MIG_STATE),
 387                                 [RC]  = (IB_QP_CUR_STATE             |
 388                                          IB_QP_ALT_PATH              |
 389                                          IB_QP_ACCESS_FLAGS          |
 390                                          IB_QP_MIN_RNR_TIMER         |
 391                                          IB_QP_PATH_MIG_STATE),
 392                                 [MLX] = (IB_QP_CUR_STATE             |
 393                                          IB_QP_QKEY),
 394                         }
 395                 }
 396         },
 397         [IB_QPS_RTS]   = {
 398                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 399                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 400                 [IB_QPS_RTS]   = {
 401                         .trans = MTHCA_TRANS_RTS2RTS,
 402                         .opt_param = {
 403                                 [UD]  = (IB_QP_CUR_STATE             |
 404                                          IB_QP_QKEY),
 405                                 [UC]  = (IB_QP_ACCESS_FLAGS          |
 406                                          IB_QP_ALT_PATH              |
 407                                          IB_QP_PATH_MIG_STATE),
 408                                 [RC]  = (IB_QP_ACCESS_FLAGS          |
 409                                          IB_QP_ALT_PATH              |
 410                                          IB_QP_PATH_MIG_STATE        |
 411                                          IB_QP_MIN_RNR_TIMER),
 412                                 [MLX] = (IB_QP_CUR_STATE             |
 413                                          IB_QP_QKEY),
 414                         }
 415                 },
 416                 [IB_QPS_SQD]   = {
 417                         .trans = MTHCA_TRANS_RTS2SQD,
 418                 },
 419         },
 420         [IB_QPS_SQD]   = {
 421                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 422                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 423                 [IB_QPS_RTS]   = {
 424                         .trans = MTHCA_TRANS_SQD2RTS,
 425                         .opt_param = {
 426                                 [UD]  = (IB_QP_CUR_STATE             |
 427                                          IB_QP_QKEY),
 428                                 [UC]  = (IB_QP_CUR_STATE             |
 429                                          IB_QP_ALT_PATH              |
 430                                          IB_QP_ACCESS_FLAGS          |
 431                                          IB_QP_PATH_MIG_STATE),
 432                                 [RC]  = (IB_QP_CUR_STATE             |
 433                                          IB_QP_ALT_PATH              |
 434                                          IB_QP_ACCESS_FLAGS          |
 435                                          IB_QP_MIN_RNR_TIMER         |
 436                                          IB_QP_PATH_MIG_STATE),
 437                                 [MLX] = (IB_QP_CUR_STATE             |
 438                                          IB_QP_QKEY),
 439                         }
 440                 },
 441                 [IB_QPS_SQD]   = {
 442                         .trans = MTHCA_TRANS_SQD2SQD,
 443                         .opt_param = {
 444                                 [UD]  = (IB_QP_PKEY_INDEX            |
 445                                          IB_QP_QKEY),
 446                                 [UC]  = (IB_QP_AV                    |
 447                                          IB_QP_CUR_STATE             |
 448                                          IB_QP_ALT_PATH              |
 449                                          IB_QP_ACCESS_FLAGS          |
 450                                          IB_QP_PKEY_INDEX            |
 451                                          IB_QP_PATH_MIG_STATE),
 452                                 [RC]  = (IB_QP_AV                    |
 453                                          IB_QP_TIMEOUT               |
 454                                          IB_QP_RETRY_CNT             |
 455                                          IB_QP_RNR_RETRY             |
 456                                          IB_QP_MAX_QP_RD_ATOMIC      |
 457                                          IB_QP_MAX_DEST_RD_ATOMIC    |
 458                                          IB_QP_CUR_STATE             |
 459                                          IB_QP_ALT_PATH              |
 460                                          IB_QP_ACCESS_FLAGS          |
 461                                          IB_QP_PKEY_INDEX            |
 462                                          IB_QP_MIN_RNR_TIMER         |
 463                                          IB_QP_PATH_MIG_STATE),
 464                                 [MLX] = (IB_QP_PKEY_INDEX            |
 465                                          IB_QP_QKEY),
 466                         }
 467                 }
 468         },
 469         [IB_QPS_SQE]   = {
 470                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 471                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 472                 [IB_QPS_RTS]   = {
 473                         .trans = MTHCA_TRANS_SQERR2RTS,
 474                         .opt_param = {
 475                                 [UD]  = (IB_QP_CUR_STATE             |
 476                                          IB_QP_QKEY),
 477                                 [UC]  = (IB_QP_CUR_STATE             |
 478                                          IB_QP_ACCESS_FLAGS),
 479                                 [MLX] = (IB_QP_CUR_STATE             |
 480                                          IB_QP_QKEY),
 481                         }
 482                 }
 483         },
 484         [IB_QPS_ERR] = {
 485                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 486                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR }
 487         }
 488 };
 489
 490 static void store_attrs(struct mthca_sqp *sqp, struct ib_qp_attr *attr,
 491                         int attr_mask)
 492 {
 493         if (attr_mask & IB_QP_PKEY_INDEX)
 494                 sqp->pkey_index = attr->pkey_index;
 495         if (attr_mask & IB_QP_QKEY)
 496                 sqp->qkey = attr->qkey;
 497         if (attr_mask & IB_QP_SQ_PSN)
 498                 sqp->send_psn = attr->sq_psn;
 499 }
 500
 501 static void init_port(struct mthca_dev *dev, int port)
 502 {
 503         int err;
 504         u8 status;
 505         struct mthca_init_ib_param param;
 506
 507         memset(&param, 0, sizeof param);
 508
 509         param.port_width = dev->limits.port_width_cap;
 510         param.vl_cap     = dev->limits.vl_cap;
 511         param.mtu_cap    = dev->limits.mtu_cap;
 512         param.gid_cap    = dev->limits.gid_table_len;
 513         param.pkey_cap   = dev->limits.pkey_table_len;
 514
 515         err = mthca_INIT_IB(dev, &param, port, &status);
 516         if (err)
 517                 mthca_warn(dev, "INIT_IB failed, return code %d.\n", err);
 518         if (status)
 519                 mthca_warn(dev, "INIT_IB returned status %02x.\n", status);
 520 }
 521
 522 static __be32 get_hw_access_flags(struct mthca_qp *qp, struct ib_qp_attr *attr,
 523                                   int attr_mask)
 524 {
 525         u8 dest_rd_atomic;
 526         u32 access_flags;
 527         u32 hw_access_flags = 0;
 528
 529         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
 530                 dest_rd_atomic = attr->max_dest_rd_atomic;
 531         else
 532                 dest_rd_atomic = qp->resp_depth;
 533
 534         if (attr_mask & IB_QP_ACCESS_FLAGS)
 535                 access_flags = attr->qp_access_flags;
 536         else
 537                 access_flags = qp->atomic_rd_en;
 538
 539         if (!dest_rd_atomic)
 540                 access_flags &= IB_ACCESS_REMOTE_WRITE;
 541
 542         if (access_flags & IB_ACCESS_REMOTE_READ)
 543                 hw_access_flags |= MTHCA_QP_BIT_RRE;
 544         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
 545                 hw_access_flags |= MTHCA_QP_BIT_RAE;
 546         if (access_flags & IB_ACCESS_REMOTE_WRITE)
 547                 hw_access_flags |= MTHCA_QP_BIT_RWE;
 548
 549         return cpu_to_be32(hw_access_flags);
 550 }
 551
 552 int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask)
 553 {
 554         struct mthca_dev *dev = to_mdev(ibqp->device);
 555         struct mthca_qp *qp = to_mqp(ibqp);
 556         enum ib_qp_state cur_state, new_state;
 557         struct mthca_mailbox *mailbox;
 558         struct mthca_qp_param *qp_param;
 559         struct mthca_qp_context *qp_context;
 560         u32 req_param, opt_param;
 561         u8 status;
 562         int err;
 563
 564         if (attr_mask & IB_QP_CUR_STATE) {
 565                 if (attr->cur_qp_state != IB_QPS_RTR &&
 566                     attr->cur_qp_state != IB_QPS_RTS &&
 567                     attr->cur_qp_state != IB_QPS_SQD &&
 568                     attr->cur_qp_state != IB_QPS_SQE)
 569                         return -EINVAL;
 570                 else
 571                         cur_state = attr->cur_qp_state;
 572         } else {
 573                 spin_lock_irq(&qp->sq.lock);
 574                 spin_lock(&qp->rq.lock);
 575                 cur_state = qp->state;
 576                 spin_unlock(&qp->rq.lock);
 577                 spin_unlock_irq(&qp->sq.lock);
 578         }
 579
 580         if (attr_mask & IB_QP_STATE) {
 581                if (attr->qp_state < 0 || attr->qp_state > IB_QPS_ERR)
 582                         return -EINVAL;
 583                 new_state = attr->qp_state;
 584         } else
 585                 new_state = cur_state;
 586
 587         if (state_table[cur_state][new_state].trans == MTHCA_TRANS_INVALID) {
 588                 mthca_dbg(dev, "Illegal QP transition "
 589                           "%d->%d\n", cur_state, new_state);
 590                 return -EINVAL;
 591         }
 592
 593         req_param = state_table[cur_state][new_state].req_param[qp->transport];
 594         opt_param = state_table[cur_state][new_state].opt_param[qp->transport];
 595
 596         if ((req_param & attr_mask) != req_param) {
 597                 mthca_dbg(dev, "QP transition "
 598                           "%d->%d missing req attr 0x%08x\n",
 599                           cur_state, new_state,
 600                           req_param & ~attr_mask);
 601                 return -EINVAL;
 602         }
 603
 604         if (attr_mask & ~(req_param | opt_param | IB_QP_STATE)) {
 605                 mthca_dbg(dev, "QP transition (transport %d) "
 606                           "%d->%d has extra attr 0x%08x\n",
 607                           qp->transport,
 608                           cur_state, new_state,
 609                           attr_mask & ~(req_param | opt_param |
 610                                                  IB_QP_STATE));
 611                 return -EINVAL;
 612         }
 613
 614         if ((attr_mask & IB_QP_PKEY_INDEX) &&
 615              attr->pkey_index >= dev->limits.pkey_table_len) {
 616                 mthca_dbg(dev, "PKey index (%u) too large. max is %d\n",
 617                           attr->pkey_index,dev->limits.pkey_table_len-1);
 618                 return -EINVAL;
 619         }
 620
 621         if ((attr_mask & IB_QP_PORT) &&
 622             (attr->port_num == 0 || attr->port_num > dev->limits.num_ports)) {
 623                 mthca_dbg(dev, "Port number (%u) is invalid\n", attr->port_num);
 624                 return -EINVAL;
 625         }
 626
 627         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
 628             attr->max_rd_atomic > dev->limits.max_qp_init_rdma) {
 629                 mthca_dbg(dev, "Max rdma_atomic as initiator %u too large (max is %d)\n",
 630                           attr->max_rd_atomic, dev->limits.max_qp_init_rdma);
 631                 return -EINVAL;
 632         }
 633
 634         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
 635             attr->max_dest_rd_atomic > 1 << dev->qp_table.rdb_shift) {
 636                 mthca_dbg(dev, "Max rdma_atomic as responder %u too large (max %d)\n",
 637                           attr->max_dest_rd_atomic, 1 << dev->qp_table.rdb_shift);
 638                 return -EINVAL;
 639         }
 640
 641         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 642         if (IS_ERR(mailbox))
 643                 return PTR_ERR(mailbox);
 644         qp_param = mailbox->buf;
 645         qp_context = &qp_param->context;
 646         memset(qp_param, 0, sizeof *qp_param);
 647
 648         qp_context->flags      = cpu_to_be32((to_mthca_state(new_state) << 28) |
 649                                              (to_mthca_st(qp->transport) << 16));
 650         qp_context->flags     |= cpu_to_be32(MTHCA_QP_BIT_DE);
 651         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
 652                 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 653         else {
 654                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE);
 655                 switch (attr->path_mig_state) {
 656                 case IB_MIG_MIGRATED:
 657                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 658                         break;
 659                 case IB_MIG_REARM:
 660                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_REARM << 11);
 661                         break;
 662                 case IB_MIG_ARMED:
 663                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_ARMED << 11);
 664                         break;
 665                 }
 666         }
 667
 668         /* leave tavor_sched_queue as 0 */
 669
 670         if (qp->transport == MLX || qp->transport == UD)
 671                 qp_context->mtu_msgmax = (IB_MTU_2048 << 5) | 11;
 672         else if (attr_mask & IB_QP_PATH_MTU)
 673                 qp_context->mtu_msgmax = (attr->path_mtu << 5) | 31;
 674
 675         if (mthca_is_memfree(dev)) {
 676                 if (qp->rq.max)
 677                         qp_context->rq_size_stride = long_log2(qp->rq.max) << 3;
 678                 qp_context->rq_size_stride |= qp->rq.wqe_shift - 4;
 679
 680                 if (qp->sq.max)
 681                         qp_context->sq_size_stride = long_log2(qp->sq.max) << 3;
 682                 qp_context->sq_size_stride |= qp->sq.wqe_shift - 4;
 683         }
 684
 685         /* leave arbel_sched_queue as 0 */
 686
 687         if (qp->ibqp.uobject)
 688                 qp_context->usr_page =
 689                         cpu_to_be32(to_mucontext(qp->ibqp.uobject->context)->uar.index);
 690         else
 691                 qp_context->usr_page = cpu_to_be32(dev->driver_uar.index);
 692         qp_context->local_qpn  = cpu_to_be32(qp->qpn);
 693         if (attr_mask & IB_QP_DEST_QPN) {
 694                 qp_context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
 695         }
 696
 697         if (qp->transport == MLX)
 698                 qp_context->pri_path.port_pkey |=
 699                         cpu_to_be32(to_msqp(qp)->port << 24);
 700         else {
 701                 if (attr_mask & IB_QP_PORT) {
 702                         qp_context->pri_path.port_pkey |=
 703                                 cpu_to_be32(attr->port_num << 24);
 704                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM);
 705                 }
 706         }
 707
 708         if (attr_mask & IB_QP_PKEY_INDEX) {
 709                 qp_context->pri_path.port_pkey |=
 710                         cpu_to_be32(attr->pkey_index);
 711                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX);
 712         }
 713
 714         if (attr_mask & IB_QP_RNR_RETRY) {
 715                 qp_context->pri_path.rnr_retry = attr->rnr_retry << 5;
 716                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY);
 717         }
 718
 719         if (attr_mask & IB_QP_AV) {
 720                 qp_context->pri_path.g_mylmc     = attr->ah_attr.src_path_bits & 0x7f;
 721                 qp_context->pri_path.rlid        = cpu_to_be16(attr->ah_attr.dlid);
 722                 qp_context->pri_path.static_rate = !!attr->ah_attr.static_rate;
 723                 if (attr->ah_attr.ah_flags & IB_AH_GRH) {
 724                         qp_context->pri_path.g_mylmc |= 1 << 7;
 725                         qp_context->pri_path.mgid_index = attr->ah_attr.grh.sgid_index;
 726                         qp_context->pri_path.hop_limit = attr->ah_attr.grh.hop_limit;
 727                         qp_context->pri_path.sl_tclass_flowlabel =
 728                                 cpu_to_be32((attr->ah_attr.sl << 28)                |
 729                                             (attr->ah_attr.grh.traffic_class << 20) |
 730                                             (attr->ah_attr.grh.flow_label));
 731                         memcpy(qp_context->pri_path.rgid,
 732                                attr->ah_attr.grh.dgid.raw, 16);
 733                 } else {
 734                         qp_context->pri_path.sl_tclass_flowlabel =
 735                                 cpu_to_be32(attr->ah_attr.sl << 28);
 736                 }
 737                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH);
 738         }
 739
 740         if (attr_mask & IB_QP_TIMEOUT) {
 741                 qp_context->pri_path.ackto = attr->timeout << 3;
 742                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT);
 743         }
 744
 745         /* XXX alt_path */
 746
 747         /* leave rdd as 0 */
 748         qp_context->pd         = cpu_to_be32(to_mpd(ibqp->pd)->pd_num);
 749         /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */
 750         qp_context->wqe_lkey   = cpu_to_be32(qp->mr.ibmr.lkey);
 751         qp_context->params1    = cpu_to_be32((MTHCA_ACK_REQ_FREQ << 28) |
 752                                              (MTHCA_FLIGHT_LIMIT << 24) |
 753                                              MTHCA_QP_BIT_SWE);
 754         if (qp->sq_policy == IB_SIGNAL_ALL_WR)
 755                 qp_context->params1 |= cpu_to_be32(MTHCA_QP_BIT_SSC);
 756         if (attr_mask & IB_QP_RETRY_CNT) {
 757                 qp_context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
 758                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT);
 759         }
 760
 761         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
 762                 if (attr->max_rd_atomic) {
 763                         qp_context->params1 |=
 764                                 cpu_to_be32(MTHCA_QP_BIT_SRE |
 765                                             MTHCA_QP_BIT_SAE);
 766                         qp_context->params1 |=
 767                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
 768                 }
 769                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX);
 770         }
 771
 772         if (attr_mask & IB_QP_SQ_PSN)
 773                 qp_context->next_send_psn = cpu_to_be32(attr->sq_psn);
 774         qp_context->cqn_snd = cpu_to_be32(to_mcq(ibqp->send_cq)->cqn);
 775
 776         if (mthca_is_memfree(dev)) {
 777                 qp_context->snd_wqe_base_l = cpu_to_be32(qp->send_wqe_offset);
 778                 qp_context->snd_db_index   = cpu_to_be32(qp->sq.db_index);
 779         }
 780
 781         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
 782                 if (attr->max_dest_rd_atomic)
 783                         qp_context->params2 |=
 784                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
 785
 786                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX);
 787         }
 788
 789         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
 790                 qp_context->params2      |= get_hw_access_flags(qp, attr, attr_mask);
 791                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
 792                                                         MTHCA_QP_OPTPAR_RRE |
 793                                                         MTHCA_QP_OPTPAR_RAE);
 794         }
 795
 796         qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC);
 797
 798         if (ibqp->srq)
 799                 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RIC);
 800
 801         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
 802                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
 803                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT);
 804         }
 805         if (attr_mask & IB_QP_RQ_PSN)
 806                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
 807
 808         qp_context->ra_buff_indx =
 809                 cpu_to_be32(dev->qp_table.rdb_base +
 810                             ((qp->qpn & (dev->limits.num_qps - 1)) * MTHCA_RDB_ENTRY_SIZE <<
 811                              dev->qp_table.rdb_shift));
 812
 813         qp_context->cqn_rcv = cpu_to_be32(to_mcq(ibqp->recv_cq)->cqn);
 814
 815         if (mthca_is_memfree(dev))
 816                 qp_context->rcv_db_index   = cpu_to_be32(qp->rq.db_index);
 817
 818         if (attr_mask & IB_QP_QKEY) {
 819                 qp_context->qkey = cpu_to_be32(attr->qkey);
 820                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY);
 821         }
 822
 823         if (ibqp->srq)
 824                 qp_context->srqn = cpu_to_be32(1 << 24 |
 825                                                to_msrq(ibqp->srq)->srqn);
 826
 827         err = mthca_MODIFY_QP(dev, state_table[cur_state][new_state].trans,
 828                               qp->qpn, 0, mailbox, 0, &status);
 829         if (status) {
 830                 mthca_warn(dev, "modify QP %d returned status %02x.\n",
 831                            state_table[cur_state][new_state].trans, status);
 832                 err = -EINVAL;
 833         }
 834
 835         if (!err) {
 836                 qp->state = new_state;
 837                 if (attr_mask & IB_QP_ACCESS_FLAGS)
 838                         qp->atomic_rd_en = attr->qp_access_flags;
 839                 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
 840                         qp->resp_depth = attr->max_dest_rd_atomic;
 841         }
 842
 843         mthca_free_mailbox(dev, mailbox);
 844
 845         if (is_sqp(dev, qp))
 846                 store_attrs(to_msqp(qp), attr, attr_mask);
 847
 848         /*
 849          * If we moved QP0 to RTR, bring the IB link up; if we moved
 850          * QP0 to RESET or ERROR, bring the link back down.
 851          */
 852         if (is_qp0(dev, qp)) {
 853                 if (cur_state != IB_QPS_RTR &&
 854                     new_state == IB_QPS_RTR)
 855                         init_port(dev, to_msqp(qp)->port);
 856
 857                 if (cur_state != IB_QPS_RESET &&
 858                     cur_state != IB_QPS_ERR &&
 859                     (new_state == IB_QPS_RESET ||
 860                      new_state == IB_QPS_ERR))
 861                         mthca_CLOSE_IB(dev, to_msqp(qp)->port, &status);
 862         }
 863
 864         /*
 865          * If we moved a kernel QP to RESET, clean up all old CQ
 866          * entries and reinitialize the QP.
 867          */
 868         if (!err && new_state == IB_QPS_RESET && !qp->ibqp.uobject) {
 869                 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq)->cqn, qp->qpn,
 870                                qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
 871                 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
 872                         mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq)->cqn, qp->qpn,
 873                                        qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
 874
 875                 mthca_wq_init(&qp->sq);
 876                 qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
 877
 878                 mthca_wq_init(&qp->rq);
 879                 qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
 880
 881                 if (mthca_is_memfree(dev)) {
 882                         *qp->sq.db = 0;
 883                         *qp->rq.db = 0;
 884                 }
 885         }
 886
 887         return err;
 888 }
 889
 890 static int mthca_max_data_size(struct mthca_dev *dev, struct mthca_qp *qp, int desc_sz)
 891 {
 892         /*
 893          * Calculate the maximum size of WQE s/g segments, excluding
 894          * the next segment and other non-data segments.
 895          */
 896         int max_data_size = desc_sz - sizeof (struct mthca_next_seg);
 897
 898         switch (qp->transport) {
 899         case MLX:
 900                 max_data_size -= 2 * sizeof (struct mthca_data_seg);
 901                 break;
 902
 903         case UD:
 904                 if (mthca_is_memfree(dev))
 905                         max_data_size -= sizeof (struct mthca_arbel_ud_seg);
 906                 else
 907                         max_data_size -= sizeof (struct mthca_tavor_ud_seg);
 908                 break;
 909
 910         default:
 911                 max_data_size -= sizeof (struct mthca_raddr_seg);
 912                 break;
 913         }
 914
 915         return max_data_size;
 916 }
 917
 918 static inline int mthca_max_inline_data(struct mthca_pd *pd, int max_data_size)
 919 {
 920         /* We don't support inline data for kernel QPs (yet). */
 921         return pd->ibpd.uobject ? max_data_size - MTHCA_INLINE_HEADER_SIZE : 0;
 922 }
 923
 924 static void mthca_adjust_qp_caps(struct mthca_dev *dev,
 925                                  struct mthca_pd *pd,
 926                                  struct mthca_qp *qp)
 927 {
 928         int max_data_size = mthca_max_data_size(dev, qp,
 929                                                 min(dev->limits.max_desc_sz,
 930                                                     1 << qp->sq.wqe_shift));
 931
 932         qp->max_inline_data = mthca_max_inline_data(pd, max_data_size);
 933
 934         qp->sq.max_gs = min_t(int, dev->limits.max_sg,
 935                               max_data_size / sizeof (struct mthca_data_seg));
 936         qp->rq.max_gs = min_t(int, dev->limits.max_sg,
 937                                (min(dev->limits.max_desc_sz, 1 << qp->rq.wqe_shift) -
 938                                 sizeof (struct mthca_next_seg)) /
 939                                sizeof (struct mthca_data_seg));
 940 }
 941
 942 /*
 943  * Allocate and register buffer for WQEs.  qp->rq.max, sq.max,
 944  * rq.max_gs and sq.max_gs must all be assigned.
 945  * mthca_alloc_wqe_buf will calculate rq.wqe_shift and
 946  * sq.wqe_shift (as well as send_wqe_offset, is_direct, and
 947  * queue)
 948  */
 949 static int mthca_alloc_wqe_buf(struct mthca_dev *dev,
 950                                struct mthca_pd *pd,
 951                                struct mthca_qp *qp)
 952 {
 953         int size;
 954         int err = -ENOMEM;
 955
 956         size = sizeof (struct mthca_next_seg) +
 957                 qp->rq.max_gs * sizeof (struct mthca_data_seg);
 958
 959         if (size > dev->limits.max_desc_sz)
 960                 return -EINVAL;
 961
 962         for (qp->rq.wqe_shift = 6; 1 << qp->rq.wqe_shift < size;
 963              qp->rq.wqe_shift++)
 964                 ; /* nothing */
 965
 966         size = qp->sq.max_gs * sizeof (struct mthca_data_seg);
 967         switch (qp->transport) {
 968         case MLX:
 969                 size += 2 * sizeof (struct mthca_data_seg);
 970                 break;
 971
 972         case UD:
 973                 size += mthca_is_memfree(dev) ?
 974                         sizeof (struct mthca_arbel_ud_seg) :
 975                         sizeof (struct mthca_tavor_ud_seg);
 976                 break;
 977
 978         case UC:
 979                 size += sizeof (struct mthca_raddr_seg);
 980                 break;
 981
 982         case RC:
 983                 size += sizeof (struct mthca_raddr_seg);
 984                 /*
 985                  * An atomic op will require an atomic segment, a
 986                  * remote address segment and one scatter entry.
 987                  */
 988                 size = max_t(int, size,
 989                              sizeof (struct mthca_atomic_seg) +
 990                              sizeof (struct mthca_raddr_seg) +
 991                              sizeof (struct mthca_data_seg));
 992                 break;
 993
 994         default:
 995                 break;
 996         }
 997
 998         /* Make sure that we have enough space for a bind request */
 999         size = max_t(int, size, sizeof (struct mthca_bind_seg));
1000
1001         size += sizeof (struct mthca_next_seg);
1002
1003         if (size > dev->limits.max_desc_sz)
1004                 return -EINVAL;
1005
1006         for (qp->sq.wqe_shift = 6; 1 << qp->sq.wqe_shift < size;
1007              qp->sq.wqe_shift++)
1008                 ; /* nothing */
1009
1010         qp->send_wqe_offset = ALIGN(qp->rq.max << qp->rq.wqe_shift,
1011                                     1 << qp->sq.wqe_shift);
1012
1013         /*
1014          * If this is a userspace QP, we don't actually have to
1015          * allocate anything.  All we need is to calculate the WQE
1016          * sizes and the send_wqe_offset, so we're done now.
1017          */
1018         if (pd->ibpd.uobject)
1019                 return 0;
1020
1021         size = PAGE_ALIGN(qp->send_wqe_offset +
1022                           (qp->sq.max << qp->sq.wqe_shift));
1023
1024         qp->wrid = kmalloc((qp->rq.max + qp->sq.max) * sizeof (u64),
1025                            GFP_KERNEL);
1026         if (!qp->wrid)
1027                 goto err_out;
1028
1029         err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_QP_SIZE,
1030                               &qp->queue, &qp->is_direct, pd, 0, &qp->mr);
1031         if (err)
1032                 goto err_out;
1033
1034         return 0;
1035
1036 err_out:
1037         kfree(qp->wrid);
1038         return err;
1039 }
1040
1041 static void mthca_free_wqe_buf(struct mthca_dev *dev,
1042                                struct mthca_qp *qp)
1043 {
1044         mthca_buf_free(dev, PAGE_ALIGN(qp->send_wqe_offset +
1045                                        (qp->sq.max << qp->sq.wqe_shift)),
1046                        &qp->queue, qp->is_direct, &qp->mr);
1047         kfree(qp->wrid);
1048 }
1049
1050 static int mthca_map_memfree(struct mthca_dev *dev,
1051                              struct mthca_qp *qp)
1052 {
1053         int ret;
1054
1055         if (mthca_is_memfree(dev)) {
1056                 ret = mthca_table_get(dev, dev->qp_table.qp_table, qp->qpn);
1057                 if (ret)
1058                         return ret;
1059
1060                 ret = mthca_table_get(dev, dev->qp_table.eqp_table, qp->qpn);
1061                 if (ret)
1062                         goto err_qpc;
1063
1064                 ret = mthca_table_get(dev, dev->qp_table.rdb_table,
1065                                       qp->qpn << dev->qp_table.rdb_shift);
1066                 if (ret)
1067                         goto err_eqpc;
1068
1069         }
1070
1071         return 0;
1072
1073 err_eqpc:
1074         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1075
1076 err_qpc:
1077         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1078
1079         return ret;
1080 }
1081
1082 static void mthca_unmap_memfree(struct mthca_dev *dev,
1083                                 struct mthca_qp *qp)
1084 {
1085         mthca_table_put(dev, dev->qp_table.rdb_table,
1086                         qp->qpn << dev->qp_table.rdb_shift);
1087         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1088         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1089 }
1090
1091 static int mthca_alloc_memfree(struct mthca_dev *dev,
1092                                struct mthca_qp *qp)
1093 {
1094         int ret = 0;
1095
1096         if (mthca_is_memfree(dev)) {
1097                 qp->rq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_RQ,
1098                                                  qp->qpn, &qp->rq.db);
1099                 if (qp->rq.db_index < 0)
1100                         return ret;
1101
1102                 qp->sq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SQ,
1103                                                  qp->qpn, &qp->sq.db);
1104                 if (qp->sq.db_index < 0)
1105                         mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1106         }
1107
1108         return ret;
1109 }
1110
1111 static void mthca_free_memfree(struct mthca_dev *dev,
1112                                struct mthca_qp *qp)
1113 {
1114         if (mthca_is_memfree(dev)) {
1115                 mthca_free_db(dev, MTHCA_DB_TYPE_SQ, qp->sq.db_index);
1116                 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1117         }
1118 }
1119
1120 static int mthca_alloc_qp_common(struct mthca_dev *dev,
1121                                  struct mthca_pd *pd,
1122                                  struct mthca_cq *send_cq,
1123                                  struct mthca_cq *recv_cq,
1124                                  enum ib_sig_type send_policy,
1125                                  struct mthca_qp *qp)
1126 {
1127         int ret;
1128         int i;
1129
1130         atomic_set(&qp->refcount, 1);
1131         init_waitqueue_head(&qp->wait);
1132         qp->state        = IB_QPS_RESET;
1133         qp->atomic_rd_en = 0;
1134         qp->resp_depth   = 0;
1135         qp->sq_policy    = send_policy;
1136         mthca_wq_init(&qp->sq);
1137         mthca_wq_init(&qp->rq);
1138
1139         ret = mthca_map_memfree(dev, qp);
1140         if (ret)
1141                 return ret;
1142
1143         ret = mthca_alloc_wqe_buf(dev, pd, qp);
1144         if (ret) {
1145                 mthca_unmap_memfree(dev, qp);
1146                 return ret;
1147         }
1148
1149         mthca_adjust_qp_caps(dev, pd, qp);
1150
1151         /*
1152          * If this is a userspace QP, we're done now.  The doorbells
1153          * will be allocated and buffers will be initialized in
1154          * userspace.
1155          */
1156         if (pd->ibpd.uobject)
1157                 return 0;
1158
1159         ret = mthca_alloc_memfree(dev, qp);
1160         if (ret) {
1161                 mthca_free_wqe_buf(dev, qp);
1162                 mthca_unmap_memfree(dev, qp);
1163                 return ret;
1164         }
1165
1166         if (mthca_is_memfree(dev)) {
1167                 struct mthca_next_seg *next;
1168                 struct mthca_data_seg *scatter;
1169                 int size = (sizeof (struct mthca_next_seg) +
1170                             qp->rq.max_gs * sizeof (struct mthca_data_seg)) / 16;
1171
1172                 for (i = 0; i < qp->rq.max; ++i) {
1173                         next = get_recv_wqe(qp, i);
1174                         next->nda_op = cpu_to_be32(((i + 1) & (qp->rq.max - 1)) <<
1175                                                    qp->rq.wqe_shift);
1176                         next->ee_nds = cpu_to_be32(size);
1177
1178                         for (scatter = (void *) (next + 1);
1179                              (void *) scatter < (void *) next + (1 << qp->rq.wqe_shift);
1180                              ++scatter)
1181                                 scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
1182                 }
1183
1184                 for (i = 0; i < qp->sq.max; ++i) {
1185                         next = get_send_wqe(qp, i);
1186                         next->nda_op = cpu_to_be32((((i + 1) & (qp->sq.max - 1)) <<
1187                                                     qp->sq.wqe_shift) +
1188                                                    qp->send_wqe_offset);
1189                 }
1190         }
1191
1192         qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
1193         qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
1194
1195         return 0;
1196 }
1197
1198 static int mthca_set_qp_size(struct mthca_dev *dev, struct ib_qp_cap *cap,
1199                              struct mthca_pd *pd, struct mthca_qp *qp)
1200 {
1201         int max_data_size = mthca_max_data_size(dev, qp, dev->limits.max_desc_sz);
1202
1203         /* Sanity check QP size before proceeding */
1204         if (cap->max_send_wr     > dev->limits.max_wqes ||
1205             cap->max_recv_wr     > dev->limits.max_wqes ||
1206             cap->max_send_sge    > dev->limits.max_sg   ||
1207             cap->max_recv_sge    > dev->limits.max_sg   ||
1208             cap->max_inline_data > mthca_max_inline_data(pd, max_data_size))
1209                 return -EINVAL;
1210
1211         /*
1212          * For MLX transport we need 2 extra S/G entries:
1213          * one for the header and one for the checksum at the end
1214          */
1215         if (qp->transport == MLX && cap->max_recv_sge + 2 > dev->limits.max_sg)
1216                 return -EINVAL;
1217
1218         if (mthca_is_memfree(dev)) {
1219                 qp->rq.max = cap->max_recv_wr ?
1220                         roundup_pow_of_two(cap->max_recv_wr) : 0;
1221                 qp->sq.max = cap->max_send_wr ?
1222                         roundup_pow_of_two(cap->max_send_wr) : 0;
1223         } else {
1224                 qp->rq.max = cap->max_recv_wr;
1225                 qp->sq.max = cap->max_send_wr;
1226         }
1227
1228         qp->rq.max_gs = cap->max_recv_sge;
1229         qp->sq.max_gs = max_t(int, cap->max_send_sge,
1230                               ALIGN(cap->max_inline_data + MTHCA_INLINE_HEADER_SIZE,
1231                                     MTHCA_INLINE_CHUNK_SIZE) /
1232                               sizeof (struct mthca_data_seg));
1233
1234         return 0;
1235 }
1236
1237 int mthca_alloc_qp(struct mthca_dev *dev,
1238                    struct mthca_pd *pd,
1239                    struct mthca_cq *send_cq,
1240                    struct mthca_cq *recv_cq,
1241                    enum ib_qp_type type,
1242                    enum ib_sig_type send_policy,
1243                    struct ib_qp_cap *cap,
1244                    struct mthca_qp *qp)
1245 {
1246         int err;
1247
1248         err = mthca_set_qp_size(dev, cap, pd, qp);
1249         if (err)
1250                 return err;
1251
1252         switch (type) {
1253         case IB_QPT_RC: qp->transport = RC; break;
1254         case IB_QPT_UC: qp->transport = UC; break;
1255         case IB_QPT_UD: qp->transport = UD; break;
1256         default: return -EINVAL;
1257         }
1258
1259         qp->qpn = mthca_alloc(&dev->qp_table.alloc);
1260         if (qp->qpn == -1)
1261                 return -ENOMEM;
1262
1263         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1264                                     send_policy, qp);
1265         if (err) {
1266                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1267                 return err;
1268         }
1269
1270         spin_lock_irq(&dev->qp_table.lock);
1271         mthca_array_set(&dev->qp_table.qp,
1272                         qp->qpn & (dev->limits.num_qps - 1), qp);
1273         spin_unlock_irq(&dev->qp_table.lock);
1274
1275         return 0;
1276 }
1277
1278 int mthca_alloc_sqp(struct mthca_dev *dev,
1279                     struct mthca_pd *pd,
1280                     struct mthca_cq *send_cq,
1281                     struct mthca_cq *recv_cq,
1282                     enum ib_sig_type send_policy,
1283                     struct ib_qp_cap *cap,
1284                     int qpn,
1285                     int port,
1286                     struct mthca_sqp *sqp)
1287 {
1288         u32 mqpn = qpn * 2 + dev->qp_table.sqp_start + port - 1;
1289         int err;
1290
1291         err = mthca_set_qp_size(dev, cap, pd, &sqp->qp);
1292         if (err)
1293                 return err;
1294
1295         sqp->header_buf_size = sqp->qp.sq.max * MTHCA_UD_HEADER_SIZE;
1296         sqp->header_buf = dma_alloc_coherent(&dev->pdev->dev, sqp->header_buf_size,
1297                                              &sqp->header_dma, GFP_KERNEL);
1298         if (!sqp->header_buf)
1299                 return -ENOMEM;
1300
1301         spin_lock_irq(&dev->qp_table.lock);
1302         if (mthca_array_get(&dev->qp_table.qp, mqpn))
1303                 err = -EBUSY;
1304         else
1305                 mthca_array_set(&dev->qp_table.qp, mqpn, sqp);
1306         spin_unlock_irq(&dev->qp_table.lock);
1307
1308         if (err)
1309                 goto err_out;
1310
1311         sqp->port = port;
1312         sqp->qp.qpn       = mqpn;
1313         sqp->qp.transport = MLX;
1314
1315         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1316                                     send_policy, &sqp->qp);
1317         if (err)
1318                 goto err_out_free;
1319
1320         atomic_inc(&pd->sqp_count);
1321
1322         return 0;
1323
1324  err_out_free:
1325         /*
1326          * Lock CQs here, so that CQ polling code can do QP lookup
1327          * without taking a lock.
1328          */
1329         spin_lock_irq(&send_cq->lock);
1330         if (send_cq != recv_cq)
1331                 spin_lock(&recv_cq->lock);
1332
1333         spin_lock(&dev->qp_table.lock);
1334         mthca_array_clear(&dev->qp_table.qp, mqpn);
1335         spin_unlock(&dev->qp_table.lock);
1336
1337         if (send_cq != recv_cq)
1338                 spin_unlock(&recv_cq->lock);
1339         spin_unlock_irq(&send_cq->lock);
1340
1341  err_out:
1342         dma_free_coherent(&dev->pdev->dev, sqp->header_buf_size,
1343                           sqp->header_buf, sqp->header_dma);
1344
1345         return err;
1346 }
1347
1348 void mthca_free_qp(struct mthca_dev *dev,
1349                    struct mthca_qp *qp)
1350 {
1351         u8 status;
1352         struct mthca_cq *send_cq;
1353         struct mthca_cq *recv_cq;
1354
1355         send_cq = to_mcq(qp->ibqp.send_cq);
1356         recv_cq = to_mcq(qp->ibqp.recv_cq);
1357
1358         /*
1359          * Lock CQs here, so that CQ polling code can do QP lookup
1360          * without taking a lock.
1361          */
1362         spin_lock_irq(&send_cq->lock);
1363         if (send_cq != recv_cq)
1364                 spin_lock(&recv_cq->lock);
1365
1366         spin_lock(&dev->qp_table.lock);
1367         mthca_array_clear(&dev->qp_table.qp,
1368                           qp->qpn & (dev->limits.num_qps - 1));
1369         spin_unlock(&dev->qp_table.lock);
1370
1371         if (send_cq != recv_cq)
1372                 spin_unlock(&recv_cq->lock);
1373         spin_unlock_irq(&send_cq->lock);
1374
1375         atomic_dec(&qp->refcount);
1376         wait_event(qp->wait, !atomic_read(&qp->refcount));
1377
1378         if (qp->state != IB_QPS_RESET)
1379                 mthca_MODIFY_QP(dev, MTHCA_TRANS_ANY2RST, qp->qpn, 0, NULL, 0, &status);
1380
1381         /*
1382          * If this is a userspace QP, the buffers, MR, CQs and so on
1383          * will be cleaned up in userspace, so all we have to do is
1384          * unref the mem-free tables and free the QPN in our table.
1385          */
1386         if (!qp->ibqp.uobject) {
1387                 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq)->cqn, qp->qpn,
1388                                qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1389                 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
1390                         mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq)->cqn, qp->qpn,
1391                                        qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1392
1393                 mthca_free_memfree(dev, qp);
1394                 mthca_free_wqe_buf(dev, qp);
1395         }
1396
1397         mthca_unmap_memfree(dev, qp);
1398
1399         if (is_sqp(dev, qp)) {
1400                 atomic_dec(&(to_mpd(qp->ibqp.pd)->sqp_count));
1401                 dma_free_coherent(&dev->pdev->dev,
1402                                   to_msqp(qp)->header_buf_size,
1403                                   to_msqp(qp)->header_buf,
1404                                   to_msqp(qp)->header_dma);
1405         } else
1406                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1407 }
1408
1409 /* Create UD header for an MLX send and build a data segment for it */
1410 static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp,
1411                             int ind, struct ib_send_wr *wr,
1412                             struct mthca_mlx_seg *mlx,
1413                             struct mthca_data_seg *data)
1414 {
1415         int header_size;
1416         int err;
1417         u16 pkey;
1418
1419         ib_ud_header_init(256, /* assume a MAD */
1420                           sqp->ud_header.grh_present,
1421                           &sqp->ud_header);
1422
1423         err = mthca_read_ah(dev, to_mah(wr->wr.ud.ah), &sqp->ud_header);
1424         if (err)
1425                 return err;
1426         mlx->flags &= ~cpu_to_be32(MTHCA_NEXT_SOLICIT | 1);
1427         mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MTHCA_MLX_VL15 : 0) |
1428                                   (sqp->ud_header.lrh.destination_lid ==
1429                                    IB_LID_PERMISSIVE ? MTHCA_MLX_SLR : 0) |
1430                                   (sqp->ud_header.lrh.service_level << 8));
1431         mlx->rlid = sqp->ud_header.lrh.destination_lid;
1432         mlx->vcrc = 0;
1433
1434         switch (wr->opcode) {
1435         case IB_WR_SEND:
1436                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1437                 sqp->ud_header.immediate_present = 0;
1438                 break;
1439         case IB_WR_SEND_WITH_IMM:
1440                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1441                 sqp->ud_header.immediate_present = 1;
1442                 sqp->ud_header.immediate_data = wr->imm_data;
1443                 break;
1444         default:
1445                 return -EINVAL;
1446         }
1447
1448         sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
1449         if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1450                 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1451         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1452         if (!sqp->qp.ibqp.qp_num)
1453                 ib_get_cached_pkey(&dev->ib_dev, sqp->port,
1454                                    sqp->pkey_index, &pkey);
1455         else
1456                 ib_get_cached_pkey(&dev->ib_dev, sqp->port,
1457                                    wr->wr.ud.pkey_index, &pkey);
1458         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1459         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1460         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1461         sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1462                                                sqp->qkey : wr->wr.ud.remote_qkey);
1463         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1464
1465         header_size = ib_ud_header_pack(&sqp->ud_header,
1466                                         sqp->header_buf +
1467                                         ind * MTHCA_UD_HEADER_SIZE);
1468
1469         data->byte_count = cpu_to_be32(header_size);
1470         data->lkey       = cpu_to_be32(to_mpd(sqp->qp.ibqp.pd)->ntmr.ibmr.lkey);
1471         data->addr       = cpu_to_be64(sqp->header_dma +
1472                                        ind * MTHCA_UD_HEADER_SIZE);
1473
1474         return 0;
1475 }
1476
1477 static inline int mthca_wq_overflow(struct mthca_wq *wq, int nreq,
1478                                     struct ib_cq *ib_cq)
1479 {
1480         unsigned cur;
1481         struct mthca_cq *cq;
1482
1483         cur = wq->head - wq->tail;
1484         if (likely(cur + nreq < wq->max))
1485                 return 0;
1486
1487         cq = to_mcq(ib_cq);
1488         spin_lock(&cq->lock);
1489         cur = wq->head - wq->tail;
1490         spin_unlock(&cq->lock);
1491
1492         return cur + nreq >= wq->max;
1493 }
1494
1495 int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1496                           struct ib_send_wr **bad_wr)
1497 {
1498         struct mthca_dev *dev = to_mdev(ibqp->device);
1499         struct mthca_qp *qp = to_mqp(ibqp);
1500         void *wqe;
1501         void *prev_wqe;
1502         unsigned long flags;
1503         int err = 0;
1504         int nreq;
1505         int i;
1506         int size;
1507         int size0 = 0;
1508         u32 f0 = 0;
1509         int ind;
1510         u8 op0 = 0;
1511
1512         spin_lock_irqsave(&qp->sq.lock, flags);
1513
1514         /* XXX check that state is OK to post send */
1515
1516         ind = qp->sq.next_ind;
1517
1518         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1519                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1520                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1521                                         " %d max, %d nreq)\n", qp->qpn,
1522                                         qp->sq.head, qp->sq.tail,
1523                                         qp->sq.max, nreq);
1524                         err = -ENOMEM;
1525                         *bad_wr = wr;
1526                         goto out;
1527                 }
1528
1529                 wqe = get_send_wqe(qp, ind);
1530                 prev_wqe = qp->sq.last;
1531                 qp->sq.last = wqe;
1532
1533                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1534                 ((struct mthca_next_seg *) wqe)->ee_nds = 0;
1535                 ((struct mthca_next_seg *) wqe)->flags =
1536                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1537                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1538                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1539                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1540                         cpu_to_be32(1);
1541                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1542                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1543                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1544
1545                 wqe += sizeof (struct mthca_next_seg);
1546                 size = sizeof (struct mthca_next_seg) / 16;
1547
1548                 switch (qp->transport) {
1549                 case RC:
1550                         switch (wr->opcode) {
1551                         case IB_WR_ATOMIC_CMP_AND_SWP:
1552                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1553                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1554                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1555                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1556                                         cpu_to_be32(wr->wr.atomic.rkey);
1557                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1558
1559                                 wqe += sizeof (struct mthca_raddr_seg);
1560
1561                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1562                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1563                                                 cpu_to_be64(wr->wr.atomic.swap);
1564                                         ((struct mthca_atomic_seg *) wqe)->compare =
1565                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1566                                 } else {
1567                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1568                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1569                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1570                                 }
1571
1572                                 wqe += sizeof (struct mthca_atomic_seg);
1573                                 size += (sizeof (struct mthca_raddr_seg) +
1574                                          sizeof (struct mthca_atomic_seg)) / 16;
1575                                 break;
1576
1577                         case IB_WR_RDMA_WRITE:
1578                         case IB_WR_RDMA_WRITE_WITH_IMM:
1579                         case IB_WR_RDMA_READ:
1580                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1581                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1582                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1583                                         cpu_to_be32(wr->wr.rdma.rkey);
1584                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1585                                 wqe += sizeof (struct mthca_raddr_seg);
1586                                 size += sizeof (struct mthca_raddr_seg) / 16;
1587                                 break;
1588
1589                         default:
1590                                 /* No extra segments required for sends */
1591                                 break;
1592                         }
1593
1594                         break;
1595
1596                 case UC:
1597                         switch (wr->opcode) {
1598                         case IB_WR_RDMA_WRITE:
1599                         case IB_WR_RDMA_WRITE_WITH_IMM:
1600                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1601                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1602                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1603                                         cpu_to_be32(wr->wr.rdma.rkey);
1604                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1605                                 wqe += sizeof (struct mthca_raddr_seg);
1606                                 size += sizeof (struct mthca_raddr_seg) / 16;
1607                                 break;
1608
1609                         default:
1610                                 /* No extra segments required for sends */
1611                                 break;
1612                         }
1613
1614                         break;
1615
1616                 case UD:
1617                         ((struct mthca_tavor_ud_seg *) wqe)->lkey =
1618                                 cpu_to_be32(to_mah(wr->wr.ud.ah)->key);
1619                         ((struct mthca_tavor_ud_seg *) wqe)->av_addr =
1620                                 cpu_to_be64(to_mah(wr->wr.ud.ah)->avdma);
1621                         ((struct mthca_tavor_ud_seg *) wqe)->dqpn =
1622                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1623                         ((struct mthca_tavor_ud_seg *) wqe)->qkey =
1624                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1625
1626                         wqe += sizeof (struct mthca_tavor_ud_seg);
1627                         size += sizeof (struct mthca_tavor_ud_seg) / 16;
1628                         break;
1629
1630                 case MLX:
1631                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1632                                                wqe - sizeof (struct mthca_next_seg),
1633                                                wqe);
1634                         if (err) {
1635                                 *bad_wr = wr;
1636                                 goto out;
1637                         }
1638                         wqe += sizeof (struct mthca_data_seg);
1639                         size += sizeof (struct mthca_data_seg) / 16;
1640                         break;
1641                 }
1642
1643                 if (wr->num_sge > qp->sq.max_gs) {
1644                         mthca_err(dev, "too many gathers\n");
1645                         err = -EINVAL;
1646                         *bad_wr = wr;
1647                         goto out;
1648                 }
1649
1650                 for (i = 0; i < wr->num_sge; ++i) {
1651                         ((struct mthca_data_seg *) wqe)->byte_count =
1652                                 cpu_to_be32(wr->sg_list[i].length);
1653                         ((struct mthca_data_seg *) wqe)->lkey =
1654                                 cpu_to_be32(wr->sg_list[i].lkey);
1655                         ((struct mthca_data_seg *) wqe)->addr =
1656                                 cpu_to_be64(wr->sg_list[i].addr);
1657                         wqe += sizeof (struct mthca_data_seg);
1658                         size += sizeof (struct mthca_data_seg) / 16;
1659                 }
1660
1661                 /* Add one more inline data segment for ICRC */
1662                 if (qp->transport == MLX) {
1663                         ((struct mthca_data_seg *) wqe)->byte_count =
1664                                 cpu_to_be32((1 << 31) | 4);
1665                         ((u32 *) wqe)[1] = 0;
1666                         wqe += sizeof (struct mthca_data_seg);
1667                         size += sizeof (struct mthca_data_seg) / 16;
1668                 }
1669
1670                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1671
1672                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1673                         mthca_err(dev, "opcode invalid\n");
1674                         err = -EINVAL;
1675                         *bad_wr = wr;
1676                         goto out;
1677                 }
1678
1679                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1680                         cpu_to_be32(((ind << qp->sq.wqe_shift) +
1681                                      qp->send_wqe_offset) |
1682                                     mthca_opcode[wr->opcode]);
1683                 wmb();
1684                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1685                         cpu_to_be32((size0 ? 0 : MTHCA_NEXT_DBD) | size);
1686
1687                 if (!size0) {
1688                         size0 = size;
1689                         op0   = mthca_opcode[wr->opcode];
1690                 }
1691
1692                 ++ind;
1693                 if (unlikely(ind >= qp->sq.max))
1694                         ind -= qp->sq.max;
1695         }
1696
1697 out:
1698         if (likely(nreq)) {
1699                 __be32 doorbell[2];
1700
1701                 doorbell[0] = cpu_to_be32(((qp->sq.next_ind << qp->sq.wqe_shift) +
1702                                            qp->send_wqe_offset) | f0 | op0);
1703                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1704
1705                 wmb();
1706
1707                 mthca_write64(doorbell,
1708                               dev->kar + MTHCA_SEND_DOORBELL,
1709                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1710         }
1711
1712         qp->sq.next_ind = ind;
1713         qp->sq.head    += nreq;
1714
1715         spin_unlock_irqrestore(&qp->sq.lock, flags);
1716         return err;
1717 }
1718
1719 int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1720                              struct ib_recv_wr **bad_wr)
1721 {
1722         struct mthca_dev *dev = to_mdev(ibqp->device);
1723         struct mthca_qp *qp = to_mqp(ibqp);
1724         __be32 doorbell[2];
1725         unsigned long flags;
1726         int err = 0;
1727         int nreq;
1728         int i;
1729         int size;
1730         int size0 = 0;
1731         int ind;
1732         void *wqe;
1733         void *prev_wqe;
1734
1735         spin_lock_irqsave(&qp->rq.lock, flags);
1736
1737         /* XXX check that state is OK to post receive */
1738
1739         ind = qp->rq.next_ind;
1740
1741         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1742                 if (unlikely(nreq == MTHCA_TAVOR_MAX_WQES_PER_RECV_DB)) {
1743                         nreq = 0;
1744
1745                         doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1746                         doorbell[1] = cpu_to_be32(qp->qpn << 8);
1747
1748                         wmb();
1749
1750                         mthca_write64(doorbell,
1751                                       dev->kar + MTHCA_RECEIVE_DOORBELL,
1752                                       MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1753
1754                         qp->rq.head += MTHCA_TAVOR_MAX_WQES_PER_RECV_DB;
1755                         size0 = 0;
1756                 }
1757
1758                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1759                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
1760                                         " %d max, %d nreq)\n", qp->qpn,
1761                                         qp->rq.head, qp->rq.tail,
1762                                         qp->rq.max, nreq);
1763                         err = -ENOMEM;
1764                         *bad_wr = wr;
1765                         goto out;
1766                 }
1767
1768                 wqe = get_recv_wqe(qp, ind);
1769                 prev_wqe = qp->rq.last;
1770                 qp->rq.last = wqe;
1771
1772                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1773                 ((struct mthca_next_seg *) wqe)->ee_nds =
1774                         cpu_to_be32(MTHCA_NEXT_DBD);
1775                 ((struct mthca_next_seg *) wqe)->flags = 0;
1776
1777                 wqe += sizeof (struct mthca_next_seg);
1778                 size = sizeof (struct mthca_next_seg) / 16;
1779
1780                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1781                         err = -EINVAL;
1782                         *bad_wr = wr;
1783                         goto out;
1784                 }
1785
1786                 for (i = 0; i < wr->num_sge; ++i) {
1787                         ((struct mthca_data_seg *) wqe)->byte_count =
1788                                 cpu_to_be32(wr->sg_list[i].length);
1789                         ((struct mthca_data_seg *) wqe)->lkey =
1790                                 cpu_to_be32(wr->sg_list[i].lkey);
1791                         ((struct mthca_data_seg *) wqe)->addr =
1792                                 cpu_to_be64(wr->sg_list[i].addr);
1793                         wqe += sizeof (struct mthca_data_seg);
1794                         size += sizeof (struct mthca_data_seg) / 16;
1795                 }
1796
1797                 qp->wrid[ind] = wr->wr_id;
1798
1799                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1800                         cpu_to_be32((ind << qp->rq.wqe_shift) | 1);
1801                 wmb();
1802                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1803                         cpu_to_be32(MTHCA_NEXT_DBD | size);
1804
1805                 if (!size0)
1806                         size0 = size;
1807
1808                 ++ind;
1809                 if (unlikely(ind >= qp->rq.max))
1810                         ind -= qp->rq.max;
1811         }
1812
1813 out:
1814         if (likely(nreq)) {
1815                 doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1816                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | nreq);
1817
1818                 wmb();
1819
1820                 mthca_write64(doorbell,
1821                               dev->kar + MTHCA_RECEIVE_DOORBELL,
1822                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1823         }
1824
1825         qp->rq.next_ind = ind;
1826         qp->rq.head    += nreq;
1827
1828         spin_unlock_irqrestore(&qp->rq.lock, flags);
1829         return err;
1830 }
1831
1832 int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1833                           struct ib_send_wr **bad_wr)
1834 {
1835         struct mthca_dev *dev = to_mdev(ibqp->device);
1836         struct mthca_qp *qp = to_mqp(ibqp);
1837         __be32 doorbell[2];
1838         void *wqe;
1839         void *prev_wqe;
1840         unsigned long flags;
1841         int err = 0;
1842         int nreq;
1843         int i;
1844         int size;
1845         int size0 = 0;
1846         u32 f0 = 0;
1847         int ind;
1848         u8 op0 = 0;
1849
1850         spin_lock_irqsave(&qp->sq.lock, flags);
1851
1852         /* XXX check that state is OK to post send */
1853
1854         ind = qp->sq.head & (qp->sq.max - 1);
1855
1856         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1857                 if (unlikely(nreq == MTHCA_ARBEL_MAX_WQES_PER_SEND_DB)) {
1858                         nreq = 0;
1859
1860                         doorbell[0] = cpu_to_be32((MTHCA_ARBEL_MAX_WQES_PER_SEND_DB << 24) |
1861                                                   ((qp->sq.head & 0xffff) << 8) |
1862                                                   f0 | op0);
1863                         doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1864
1865                         qp->sq.head += MTHCA_ARBEL_MAX_WQES_PER_SEND_DB;
1866                         size0 = 0;
1867
1868                         /*
1869                          * Make sure that descriptors are written before
1870                          * doorbell record.
1871                          */
1872                         wmb();
1873                         *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
1874
1875                         /*
1876                          * Make sure doorbell record is written before we
1877                          * write MMIO send doorbell.
1878                          */
1879                         wmb();
1880                         mthca_write64(doorbell,
1881                                       dev->kar + MTHCA_SEND_DOORBELL,
1882                                       MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1883                 }
1884
1885                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1886                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1887                                         " %d max, %d nreq)\n", qp->qpn,
1888                                         qp->sq.head, qp->sq.tail,
1889                                         qp->sq.max, nreq);
1890                         err = -ENOMEM;
1891                         *bad_wr = wr;
1892                         goto out;
1893                 }
1894
1895                 wqe = get_send_wqe(qp, ind);
1896                 prev_wqe = qp->sq.last;
1897                 qp->sq.last = wqe;
1898
1899                 ((struct mthca_next_seg *) wqe)->flags =
1900                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1901                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1902                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1903                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1904                         cpu_to_be32(1);
1905                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1906                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1907                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1908
1909                 wqe += sizeof (struct mthca_next_seg);
1910                 size = sizeof (struct mthca_next_seg) / 16;
1911
1912                 switch (qp->transport) {
1913                 case RC:
1914                         switch (wr->opcode) {
1915                         case IB_WR_ATOMIC_CMP_AND_SWP:
1916                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1917                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1918                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1919                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1920                                         cpu_to_be32(wr->wr.atomic.rkey);
1921                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1922
1923                                 wqe += sizeof (struct mthca_raddr_seg);
1924
1925                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1926                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1927                                                 cpu_to_be64(wr->wr.atomic.swap);
1928                                         ((struct mthca_atomic_seg *) wqe)->compare =
1929                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1930                                 } else {
1931                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1932                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1933                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1934                                 }
1935
1936                                 wqe += sizeof (struct mthca_atomic_seg);
1937                                 size += (sizeof (struct mthca_raddr_seg) +
1938                                          sizeof (struct mthca_atomic_seg)) / 16;
1939                                 break;
1940
1941                         case IB_WR_RDMA_READ:
1942                         case IB_WR_RDMA_WRITE:
1943                         case IB_WR_RDMA_WRITE_WITH_IMM:
1944                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1945                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1946                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1947                                         cpu_to_be32(wr->wr.rdma.rkey);
1948                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1949                                 wqe += sizeof (struct mthca_raddr_seg);
1950                                 size += sizeof (struct mthca_raddr_seg) / 16;
1951                                 break;
1952
1953                         default:
1954                                 /* No extra segments required for sends */
1955                                 break;
1956                         }
1957
1958                         break;
1959
1960                 case UC:
1961                         switch (wr->opcode) {
1962                         case IB_WR_RDMA_WRITE:
1963                         case IB_WR_RDMA_WRITE_WITH_IMM:
1964                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1965                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1966                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1967                                         cpu_to_be32(wr->wr.rdma.rkey);
1968                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1969                                 wqe += sizeof (struct mthca_raddr_seg);
1970                                 size += sizeof (struct mthca_raddr_seg) / 16;
1971                                 break;
1972
1973                         default:
1974                                 /* No extra segments required for sends */
1975                                 break;
1976                         }
1977
1978                         break;
1979
1980                 case UD:
1981                         memcpy(((struct mthca_arbel_ud_seg *) wqe)->av,
1982                                to_mah(wr->wr.ud.ah)->av, MTHCA_AV_SIZE);
1983                         ((struct mthca_arbel_ud_seg *) wqe)->dqpn =
1984                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1985                         ((struct mthca_arbel_ud_seg *) wqe)->qkey =
1986                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1987
1988                         wqe += sizeof (struct mthca_arbel_ud_seg);
1989                         size += sizeof (struct mthca_arbel_ud_seg) / 16;
1990                         break;
1991
1992                 case MLX:
1993                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1994                                                wqe - sizeof (struct mthca_next_seg),
1995                                                wqe);
1996                         if (err) {
1997                                 *bad_wr = wr;
1998                                 goto out;
1999                         }
2000                         wqe += sizeof (struct mthca_data_seg);
2001                         size += sizeof (struct mthca_data_seg) / 16;
2002                         break;
2003                 }
2004
2005                 if (wr->num_sge > qp->sq.max_gs) {
2006                         mthca_err(dev, "too many gathers\n");
2007                         err = -EINVAL;
2008                         *bad_wr = wr;
2009                         goto out;
2010                 }
2011
2012                 for (i = 0; i < wr->num_sge; ++i) {
2013                         ((struct mthca_data_seg *) wqe)->byte_count =
2014                                 cpu_to_be32(wr->sg_list[i].length);
2015                         ((struct mthca_data_seg *) wqe)->lkey =
2016                                 cpu_to_be32(wr->sg_list[i].lkey);
2017                         ((struct mthca_data_seg *) wqe)->addr =
2018                                 cpu_to_be64(wr->sg_list[i].addr);
2019                         wqe += sizeof (struct mthca_data_seg);
2020                         size += sizeof (struct mthca_data_seg) / 16;
2021                 }
2022
2023                 /* Add one more inline data segment for ICRC */
2024                 if (qp->transport == MLX) {
2025                         ((struct mthca_data_seg *) wqe)->byte_count =
2026                                 cpu_to_be32((1 << 31) | 4);
2027                         ((u32 *) wqe)[1] = 0;
2028                         wqe += sizeof (struct mthca_data_seg);
2029                         size += sizeof (struct mthca_data_seg) / 16;
2030                 }
2031
2032                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
2033
2034                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
2035                         mthca_err(dev, "opcode invalid\n");
2036                         err = -EINVAL;
2037                         *bad_wr = wr;
2038                         goto out;
2039                 }
2040
2041                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
2042                         cpu_to_be32(((ind << qp->sq.wqe_shift) +
2043                                      qp->send_wqe_offset) |
2044                                     mthca_opcode[wr->opcode]);
2045                 wmb();
2046                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
2047                         cpu_to_be32(MTHCA_NEXT_DBD | size);
2048
2049                 if (!size0) {
2050                         size0 = size;
2051                         op0   = mthca_opcode[wr->opcode];
2052                 }
2053
2054                 ++ind;
2055                 if (unlikely(ind >= qp->sq.max))
2056                         ind -= qp->sq.max;
2057         }
2058
2059 out:
2060         if (likely(nreq)) {
2061                 doorbell[0] = cpu_to_be32((nreq << 24)                  |
2062                                           ((qp->sq.head & 0xffff) << 8) |
2063                                           f0 | op0);
2064                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
2065
2066                 qp->sq.head += nreq;
2067
2068                 /*
2069                  * Make sure that descriptors are written before
2070                  * doorbell record.
2071                  */
2072                 wmb();
2073                 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
2074
2075                 /*
2076                  * Make sure doorbell record is written before we
2077                  * write MMIO send doorbell.
2078                  */
2079                 wmb();
2080                 mthca_write64(doorbell,
2081                               dev->kar + MTHCA_SEND_DOORBELL,
2082                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
2083         }
2084
2085         spin_unlock_irqrestore(&qp->sq.lock, flags);
2086         return err;
2087 }
2088
2089 int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2090                              struct ib_recv_wr **bad_wr)
2091 {
2092         struct mthca_dev *dev = to_mdev(ibqp->device);
2093         struct mthca_qp *qp = to_mqp(ibqp);
2094         unsigned long flags;
2095         int err = 0;
2096         int nreq;
2097         int ind;
2098         int i;
2099         void *wqe;
2100
2101         spin_lock_irqsave(&qp->rq.lock, flags);
2102
2103         /* XXX check that state is OK to post receive */
2104
2105         ind = qp->rq.head & (qp->rq.max - 1);
2106
2107         for (nreq = 0; wr; ++nreq, wr = wr->next) {
2108                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2109                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
2110                                         " %d max, %d nreq)\n", qp->qpn,
2111                                         qp->rq.head, qp->rq.tail,
2112                                         qp->rq.max, nreq);
2113                         err = -ENOMEM;
2114                         *bad_wr = wr;
2115                         goto out;
2116                 }
2117
2118                 wqe = get_recv_wqe(qp, ind);
2119
2120                 ((struct mthca_next_seg *) wqe)->flags = 0;
2121
2122                 wqe += sizeof (struct mthca_next_seg);
2123
2124                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2125                         err = -EINVAL;
2126                         *bad_wr = wr;
2127                         goto out;
2128                 }
2129
2130                 for (i = 0; i < wr->num_sge; ++i) {
2131                         ((struct mthca_data_seg *) wqe)->byte_count =
2132                                 cpu_to_be32(wr->sg_list[i].length);
2133                         ((struct mthca_data_seg *) wqe)->lkey =
2134                                 cpu_to_be32(wr->sg_list[i].lkey);
2135                         ((struct mthca_data_seg *) wqe)->addr =
2136                                 cpu_to_be64(wr->sg_list[i].addr);
2137                         wqe += sizeof (struct mthca_data_seg);
2138                 }
2139
2140                 if (i < qp->rq.max_gs) {
2141                         ((struct mthca_data_seg *) wqe)->byte_count = 0;
2142                         ((struct mthca_data_seg *) wqe)->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
2143                         ((struct mthca_data_seg *) wqe)->addr = 0;
2144                 }
2145
2146                 qp->wrid[ind] = wr->wr_id;
2147
2148                 ++ind;
2149                 if (unlikely(ind >= qp->rq.max))
2150                         ind -= qp->rq.max;
2151         }
2152 out:
2153         if (likely(nreq)) {
2154                 qp->rq.head += nreq;
2155
2156                 /*
2157                  * Make sure that descriptors are written before
2158                  * doorbell record.
2159                  */
2160                 wmb();
2161                 *qp->rq.db = cpu_to_be32(qp->rq.head & 0xffff);
2162         }
2163
2164         spin_unlock_irqrestore(&qp->rq.lock, flags);
2165         return err;
2166 }
2167
2168 int mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
2169                        int index, int *dbd, __be32 *new_wqe)
2170 {
2171         struct mthca_next_seg *next;
2172
2173         /*
2174          * For SRQs, all WQEs generate a CQE, so we're always at the
2175          * end of the doorbell chain.
2176          */
2177         if (qp->ibqp.srq) {
2178                 *new_wqe = 0;
2179                 return 0;
2180         }
2181
2182         if (is_send)
2183                 next = get_send_wqe(qp, index);
2184         else
2185                 next = get_recv_wqe(qp, index);
2186
2187         *dbd = !!(next->ee_nds & cpu_to_be32(MTHCA_NEXT_DBD));
2188         if (next->ee_nds & cpu_to_be32(0x3f))
2189                 *new_wqe = (next->nda_op & cpu_to_be32(~0x3f)) |
2190                         (next->ee_nds & cpu_to_be32(0x3f));
2191         else
2192                 *new_wqe = 0;
2193
2194         return 0;
2195 }
2196
2197 int __devinit mthca_init_qp_table(struct mthca_dev *dev)
2198 {
2199         int err;
2200         u8 status;
2201         int i;
2202
2203         spin_lock_init(&dev->qp_table.lock);
2204
2205         /*
2206          * We reserve 2 extra QPs per port for the special QPs.  The
2207          * special QP for port 1 has to be even, so round up.
2208          */
2209         dev->qp_table.sqp_start = (dev->limits.reserved_qps + 1) & ~1UL;
2210         err = mthca_alloc_init(&dev->qp_table.alloc,
2211                                dev->limits.num_qps,
2212                                (1 << 24) - 1,
2213                                dev->qp_table.sqp_start +
2214                                MTHCA_MAX_PORTS * 2);
2215         if (err)
2216                 return err;
2217
2218         err = mthca_array_init(&dev->qp_table.qp,
2219                                dev->limits.num_qps);
2220         if (err) {
2221                 mthca_alloc_cleanup(&dev->qp_table.alloc);
2222                 return err;
2223         }
2224
2225         for (i = 0; i < 2; ++i) {
2226                 err = mthca_CONF_SPECIAL_QP(dev, i ? IB_QPT_GSI : IB_QPT_SMI,
2227                                             dev->qp_table.sqp_start + i * 2,
2228                                             &status);
2229                 if (err)
2230                         goto err_out;
2231                 if (status) {
2232                         mthca_warn(dev, "CONF_SPECIAL_QP returned "
2233                                    "status %02x, aborting.\n",
2234                                    status);
2235                         err = -EINVAL;
2236                         goto err_out;
2237                 }
2238         }
2239         return 0;
2240
2241  err_out:
2242         for (i = 0; i < 2; ++i)
2243                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2244
2245         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2246         mthca_alloc_cleanup(&dev->qp_table.alloc);
2247
2248         return err;
2249 }
2250
2251 void __devexit mthca_cleanup_qp_table(struct mthca_dev *dev)
2252 {
2253         int i;
2254         u8 status;
2255
2256         for (i = 0; i < 2; ++i)
2257                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2258
2259         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2260         mthca_alloc_cleanup(&dev->qp_table.alloc);
2261 }