drivers/infiniband/hw/mlx4/qp.c

   1 /*
   2  * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
   3  * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 #include <linux/log2.h>
  35 #include <linux/slab.h>
  36 #include <linux/netdevice.h>
  37
  38 #include <rdma/ib_cache.h>
  39 #include <rdma/ib_pack.h>
  40
  41 #include <linux/mlx4/qp.h>
  42
  43 #include "mlx4_ib.h"
  44 #include "user.h"
  45
  46 enum {
  47         MLX4_IB_ACK_REQ_FREQ    = 8,
  48 };
  49
  50 enum {
  51         MLX4_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  52         MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  53         MLX4_IB_LINK_TYPE_IB            = 0,
  54         MLX4_IB_LINK_TYPE_ETH           = 1
  55 };
  56
  57 enum {
  58         /*
  59          * Largest possible UD header: send with GRH and immediate
  60          * data plus 14 bytes for an Ethernet header.  (LRH would only
  61          * use 8 bytes, so Ethernet is the biggest case)
  62          */
  63         MLX4_IB_UD_HEADER_SIZE          = 78,
  64         MLX4_IB_LSO_HEADER_SPARE        = 128,
  65 };
  66
  67 enum {
  68         MLX4_IB_IBOE_ETHERTYPE          = 0x8915
  69 };
  70
  71 struct mlx4_ib_sqp {
  72         struct mlx4_ib_qp       qp;
  73         int                     pkey_index;
  74         u32                     qkey;
  75         u32                     send_psn;
  76         struct ib_ud_header     ud_header;
  77         u8                      header_buf[MLX4_IB_UD_HEADER_SIZE];
  78 };
  79
  80 enum {
  81         MLX4_IB_MIN_SQ_STRIDE   = 6,
  82         MLX4_IB_CACHE_LINE_SIZE = 64,
  83 };
  84
  85 static const __be32 mlx4_ib_opcode[] = {
  86         [IB_WR_SEND]                            = cpu_to_be32(MLX4_OPCODE_SEND),
  87         [IB_WR_LSO]                             = cpu_to_be32(MLX4_OPCODE_LSO),
  88         [IB_WR_SEND_WITH_IMM]                   = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
  89         [IB_WR_RDMA_WRITE]                      = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
  90         [IB_WR_RDMA_WRITE_WITH_IMM]             = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
  91         [IB_WR_RDMA_READ]                       = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
  92         [IB_WR_ATOMIC_CMP_AND_SWP]              = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
  93         [IB_WR_ATOMIC_FETCH_AND_ADD]            = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
  94         [IB_WR_SEND_WITH_INV]                   = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
  95         [IB_WR_LOCAL_INV]                       = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
  96         [IB_WR_FAST_REG_MR]                     = cpu_to_be32(MLX4_OPCODE_FMR),
  97         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
  98         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
  99 };
 100
 101 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
 102 {
 103         return container_of(mqp, struct mlx4_ib_sqp, qp);
 104 }
 105
 106 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 107 {
 108         return qp->mqp.qpn >= dev->dev->caps.sqp_start &&
 109                 qp->mqp.qpn <= dev->dev->caps.sqp_start + 3;
 110 }
 111
 112 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 113 {
 114         return qp->mqp.qpn >= dev->dev->caps.sqp_start &&
 115                 qp->mqp.qpn <= dev->dev->caps.sqp_start + 1;
 116 }
 117
 118 static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
 119 {
 120         return mlx4_buf_offset(&qp->buf, offset);
 121 }
 122
 123 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
 124 {
 125         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
 126 }
 127
 128 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
 129 {
 130         return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
 131 }
 132
 133 /*
 134  * Stamp a SQ WQE so that it is invalid if prefetched by marking the
 135  * first four bytes of every 64 byte chunk with
 136  *     0x7FFFFFF | (invalid_ownership_value << 31).
 137  *
 138  * When the max work request size is less than or equal to the WQE
 139  * basic block size, as an optimization, we can stamp all WQEs with
 140  * 0xffffffff, and skip the very first chunk of each WQE.
 141  */
 142 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
 143 {
 144         __be32 *wqe;
 145         int i;
 146         int s;
 147         int ind;
 148         void *buf;
 149         __be32 stamp;
 150         struct mlx4_wqe_ctrl_seg *ctrl;
 151
 152         if (qp->sq_max_wqes_per_wr > 1) {
 153                 s = roundup(size, 1U << qp->sq.wqe_shift);
 154                 for (i = 0; i < s; i += 64) {
 155                         ind = (i >> qp->sq.wqe_shift) + n;
 156                         stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
 157                                                        cpu_to_be32(0xffffffff);
 158                         buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
 159                         wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
 160                         *wqe = stamp;
 161                 }
 162         } else {
 163                 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
 164                 s = (ctrl->fence_size & 0x3f) << 4;
 165                 for (i = 64; i < s; i += 64) {
 166                         wqe = buf + i;
 167                         *wqe = cpu_to_be32(0xffffffff);
 168                 }
 169         }
 170 }
 171
 172 static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
 173 {
 174         struct mlx4_wqe_ctrl_seg *ctrl;
 175         struct mlx4_wqe_inline_seg *inl;
 176         void *wqe;
 177         int s;
 178
 179         ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
 180         s = sizeof(struct mlx4_wqe_ctrl_seg);
 181
 182         if (qp->ibqp.qp_type == IB_QPT_UD) {
 183                 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
 184                 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
 185                 memset(dgram, 0, sizeof *dgram);
 186                 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
 187                 s += sizeof(struct mlx4_wqe_datagram_seg);
 188         }
 189
 190         /* Pad the remainder of the WQE with an inline data segment. */
 191         if (size > s) {
 192                 inl = wqe + s;
 193                 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
 194         }
 195         ctrl->srcrb_flags = 0;
 196         ctrl->fence_size = size / 16;
 197         /*
 198          * Make sure descriptor is fully written before setting ownership bit
 199          * (because HW can start executing as soon as we do).
 200          */
 201         wmb();
 202
 203         ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
 204                 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
 205
 206         stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
 207 }
 208
 209 /* Post NOP WQE to prevent wrap-around in the middle of WR */
 210 static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
 211 {
 212         unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
 213         if (unlikely(s < qp->sq_max_wqes_per_wr)) {
 214                 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
 215                 ind += s;
 216         }
 217         return ind;
 218 }
 219
 220 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
 221 {
 222         struct ib_event event;
 223         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 224
 225         if (type == MLX4_EVENT_TYPE_PATH_MIG)
 226                 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
 227
 228         if (ibqp->event_handler) {
 229                 event.device     = ibqp->device;
 230                 event.element.qp = ibqp;
 231                 switch (type) {
 232                 case MLX4_EVENT_TYPE_PATH_MIG:
 233                         event.event = IB_EVENT_PATH_MIG;
 234                         break;
 235                 case MLX4_EVENT_TYPE_COMM_EST:
 236                         event.event = IB_EVENT_COMM_EST;
 237                         break;
 238                 case MLX4_EVENT_TYPE_SQ_DRAINED:
 239                         event.event = IB_EVENT_SQ_DRAINED;
 240                         break;
 241                 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
 242                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 243                         break;
 244                 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
 245                         event.event = IB_EVENT_QP_FATAL;
 246                         break;
 247                 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
 248                         event.event = IB_EVENT_PATH_MIG_ERR;
 249                         break;
 250                 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 251                         event.event = IB_EVENT_QP_REQ_ERR;
 252                         break;
 253                 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
 254                         event.event = IB_EVENT_QP_ACCESS_ERR;
 255                         break;
 256                 default:
 257                         printk(KERN_WARNING "mlx4_ib: Unexpected event type %d "
 258                                "on QP %06x\n", type, qp->qpn);
 259                         return;
 260                 }
 261
 262                 ibqp->event_handler(&event, ibqp->qp_context);
 263         }
 264 }
 265
 266 static int send_wqe_overhead(enum ib_qp_type type, u32 flags)
 267 {
 268         /*
 269          * UD WQEs must have a datagram segment.
 270          * RC and UC WQEs might have a remote address segment.
 271          * MLX WQEs need two extra inline data segments (for the UD
 272          * header and space for the ICRC).
 273          */
 274         switch (type) {
 275         case IB_QPT_UD:
 276                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 277                         sizeof (struct mlx4_wqe_datagram_seg) +
 278                         ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
 279         case IB_QPT_UC:
 280                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 281                         sizeof (struct mlx4_wqe_raddr_seg);
 282         case IB_QPT_RC:
 283                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 284                         sizeof (struct mlx4_wqe_atomic_seg) +
 285                         sizeof (struct mlx4_wqe_raddr_seg);
 286         case IB_QPT_SMI:
 287         case IB_QPT_GSI:
 288                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 289                         ALIGN(MLX4_IB_UD_HEADER_SIZE +
 290                               DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
 291                                            MLX4_INLINE_ALIGN) *
 292                               sizeof (struct mlx4_wqe_inline_seg),
 293                               sizeof (struct mlx4_wqe_data_seg)) +
 294                         ALIGN(4 +
 295                               sizeof (struct mlx4_wqe_inline_seg),
 296                               sizeof (struct mlx4_wqe_data_seg));
 297         default:
 298                 return sizeof (struct mlx4_wqe_ctrl_seg);
 299         }
 300 }
 301
 302 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 303                        int is_user, int has_srq, struct mlx4_ib_qp *qp)
 304 {
 305         /* Sanity check RQ size before proceeding */
 306         if (cap->max_recv_wr  > dev->dev->caps.max_wqes  ||
 307             cap->max_recv_sge > dev->dev->caps.max_rq_sg)
 308                 return -EINVAL;
 309
 310         if (has_srq) {
 311                 /* QPs attached to an SRQ should have no RQ */
 312                 if (cap->max_recv_wr)
 313                         return -EINVAL;
 314
 315                 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
 316         } else {
 317                 /* HW requires >= 1 RQ entry with >= 1 gather entry */
 318                 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
 319                         return -EINVAL;
 320
 321                 qp->rq.wqe_cnt   = roundup_pow_of_two(max(1U, cap->max_recv_wr));
 322                 qp->rq.max_gs    = roundup_pow_of_two(max(1U, cap->max_recv_sge));
 323                 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
 324         }
 325
 326         cap->max_recv_wr  = qp->rq.max_post = qp->rq.wqe_cnt;
 327         cap->max_recv_sge = qp->rq.max_gs;
 328
 329         return 0;
 330 }
 331
 332 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 333                               enum ib_qp_type type, struct mlx4_ib_qp *qp)
 334 {
 335         int s;
 336
 337         /* Sanity check SQ size before proceeding */
 338         if (cap->max_send_wr     > dev->dev->caps.max_wqes  ||
 339             cap->max_send_sge    > dev->dev->caps.max_sq_sg ||
 340             cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
 341             sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
 342                 return -EINVAL;
 343
 344         /*
 345          * For MLX transport we need 2 extra S/G entries:
 346          * one for the header and one for the checksum at the end
 347          */
 348         if ((type == IB_QPT_SMI || type == IB_QPT_GSI) &&
 349             cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
 350                 return -EINVAL;
 351
 352         s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
 353                 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
 354                 send_wqe_overhead(type, qp->flags);
 355
 356         if (s > dev->dev->caps.max_sq_desc_sz)
 357                 return -EINVAL;
 358
 359         /*
 360          * Hermon supports shrinking WQEs, such that a single work
 361          * request can include multiple units of 1 << wqe_shift.  This
 362          * way, work requests can differ in size, and do not have to
 363          * be a power of 2 in size, saving memory and speeding up send
 364          * WR posting.  Unfortunately, if we do this then the
 365          * wqe_index field in CQEs can't be used to look up the WR ID
 366          * anymore, so we do this only if selective signaling is off.
 367          *
 368          * Further, on 32-bit platforms, we can't use vmap() to make
 369          * the QP buffer virtually contiguous.  Thus we have to use
 370          * constant-sized WRs to make sure a WR is always fully within
 371          * a single page-sized chunk.
 372          *
 373          * Finally, we use NOP work requests to pad the end of the
 374          * work queue, to avoid wrap-around in the middle of WR.  We
 375          * set NEC bit to avoid getting completions with error for
 376          * these NOP WRs, but since NEC is only supported starting
 377          * with firmware 2.2.232, we use constant-sized WRs for older
 378          * firmware.
 379          *
 380          * And, since MLX QPs only support SEND, we use constant-sized
 381          * WRs in this case.
 382          *
 383          * We look for the smallest value of wqe_shift such that the
 384          * resulting number of wqes does not exceed device
 385          * capabilities.
 386          *
 387          * We set WQE size to at least 64 bytes, this way stamping
 388          * invalidates each WQE.
 389          */
 390         if (dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
 391             qp->sq_signal_bits && BITS_PER_LONG == 64 &&
 392             type != IB_QPT_SMI && type != IB_QPT_GSI)
 393                 qp->sq.wqe_shift = ilog2(64);
 394         else
 395                 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
 396
 397         for (;;) {
 398                 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
 399
 400                 /*
 401                  * We need to leave 2 KB + 1 WR of headroom in the SQ to
 402                  * allow HW to prefetch.
 403                  */
 404                 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
 405                 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
 406                                                     qp->sq_max_wqes_per_wr +
 407                                                     qp->sq_spare_wqes);
 408
 409                 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
 410                         break;
 411
 412                 if (qp->sq_max_wqes_per_wr <= 1)
 413                         return -EINVAL;
 414
 415                 ++qp->sq.wqe_shift;
 416         }
 417
 418         qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
 419                              (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
 420                          send_wqe_overhead(type, qp->flags)) /
 421                 sizeof (struct mlx4_wqe_data_seg);
 422
 423         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 424                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 425         if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
 426                 qp->rq.offset = 0;
 427                 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 428         } else {
 429                 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
 430                 qp->sq.offset = 0;
 431         }
 432
 433         cap->max_send_wr  = qp->sq.max_post =
 434                 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
 435         cap->max_send_sge = min(qp->sq.max_gs,
 436                                 min(dev->dev->caps.max_sq_sg,
 437                                     dev->dev->caps.max_rq_sg));
 438         /* We don't support inline sends for kernel QPs (yet) */
 439         cap->max_inline_data = 0;
 440
 441         return 0;
 442 }
 443
 444 static int set_user_sq_size(struct mlx4_ib_dev *dev,
 445                             struct mlx4_ib_qp *qp,
 446                             struct mlx4_ib_create_qp *ucmd)
 447 {
 448         /* Sanity check SQ size before proceeding */
 449         if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes       ||
 450             ucmd->log_sq_stride >
 451                 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
 452             ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
 453                 return -EINVAL;
 454
 455         qp->sq.wqe_cnt   = 1 << ucmd->log_sq_bb_count;
 456         qp->sq.wqe_shift = ucmd->log_sq_stride;
 457
 458         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 459                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 460
 461         return 0;
 462 }
 463
 464 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
 465                             struct ib_qp_init_attr *init_attr,
 466                             struct ib_udata *udata, int sqpn, struct mlx4_ib_qp *qp)
 467 {
 468         int qpn;
 469         int err;
 470
 471         mutex_init(&qp->mutex);
 472         spin_lock_init(&qp->sq.lock);
 473         spin_lock_init(&qp->rq.lock);
 474         INIT_LIST_HEAD(&qp->gid_list);
 475
 476         qp->state        = IB_QPS_RESET;
 477         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
 478                 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
 479
 480         err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, !!init_attr->srq, qp);
 481         if (err)
 482                 goto err;
 483
 484         if (pd->uobject) {
 485                 struct mlx4_ib_create_qp ucmd;
 486
 487                 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
 488                         err = -EFAULT;
 489                         goto err;
 490                 }
 491
 492                 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
 493
 494                 err = set_user_sq_size(dev, qp, &ucmd);
 495                 if (err)
 496                         goto err;
 497
 498                 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
 499                                        qp->buf_size, 0, 0);
 500                 if (IS_ERR(qp->umem)) {
 501                         err = PTR_ERR(qp->umem);
 502                         goto err;
 503                 }
 504
 505                 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
 506                                     ilog2(qp->umem->page_size), &qp->mtt);
 507                 if (err)
 508                         goto err_buf;
 509
 510                 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
 511                 if (err)
 512                         goto err_mtt;
 513
 514                 if (!init_attr->srq) {
 515                         err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
 516                                                   ucmd.db_addr, &qp->db);
 517                         if (err)
 518                                 goto err_mtt;
 519                 }
 520         } else {
 521                 qp->sq_no_prefetch = 0;
 522
 523                 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
 524                         qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
 525
 526                 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
 527                         qp->flags |= MLX4_IB_QP_LSO;
 528
 529                 err = set_kernel_sq_size(dev, &init_attr->cap, init_attr->qp_type, qp);
 530                 if (err)
 531                         goto err;
 532
 533                 if (!init_attr->srq) {
 534                         err = mlx4_db_alloc(dev->dev, &qp->db, 0);
 535                         if (err)
 536                                 goto err;
 537
 538                         *qp->db.db = 0;
 539                 }
 540
 541                 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf)) {
 542                         err = -ENOMEM;
 543                         goto err_db;
 544                 }
 545
 546                 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
 547                                     &qp->mtt);
 548                 if (err)
 549                         goto err_buf;
 550
 551                 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
 552                 if (err)
 553                         goto err_mtt;
 554
 555                 qp->sq.wrid  = kmalloc(qp->sq.wqe_cnt * sizeof (u64), GFP_KERNEL);
 556                 qp->rq.wrid  = kmalloc(qp->rq.wqe_cnt * sizeof (u64), GFP_KERNEL);
 557
 558                 if (!qp->sq.wrid || !qp->rq.wrid) {
 559                         err = -ENOMEM;
 560                         goto err_wrid;
 561                 }
 562         }
 563
 564         if (sqpn) {
 565                 qpn = sqpn;
 566         } else {
 567                 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn);
 568                 if (err)
 569                         goto err_wrid;
 570         }
 571
 572         err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
 573         if (err)
 574                 goto err_qpn;
 575
 576         /*
 577          * Hardware wants QPN written in big-endian order (after
 578          * shifting) for send doorbell.  Precompute this value to save
 579          * a little bit when posting sends.
 580          */
 581         qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
 582
 583         qp->mqp.event = mlx4_ib_qp_event;
 584
 585         return 0;
 586
 587 err_qpn:
 588         if (!sqpn)
 589                 mlx4_qp_release_range(dev->dev, qpn, 1);
 590
 591 err_wrid:
 592         if (pd->uobject) {
 593                 if (!init_attr->srq)
 594                         mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context),
 595                                               &qp->db);
 596         } else {
 597                 kfree(qp->sq.wrid);
 598                 kfree(qp->rq.wrid);
 599         }
 600
 601 err_mtt:
 602         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
 603
 604 err_buf:
 605         if (pd->uobject)
 606                 ib_umem_release(qp->umem);
 607         else
 608                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
 609
 610 err_db:
 611         if (!pd->uobject && !init_attr->srq)
 612                 mlx4_db_free(dev->dev, &qp->db);
 613
 614 err:
 615         return err;
 616 }
 617
 618 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
 619 {
 620         switch (state) {
 621         case IB_QPS_RESET:      return MLX4_QP_STATE_RST;
 622         case IB_QPS_INIT:       return MLX4_QP_STATE_INIT;
 623         case IB_QPS_RTR:        return MLX4_QP_STATE_RTR;
 624         case IB_QPS_RTS:        return MLX4_QP_STATE_RTS;
 625         case IB_QPS_SQD:        return MLX4_QP_STATE_SQD;
 626         case IB_QPS_SQE:        return MLX4_QP_STATE_SQER;
 627         case IB_QPS_ERR:        return MLX4_QP_STATE_ERR;
 628         default:                return -1;
 629         }
 630 }
 631
 632 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
 633         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
 634 {
 635         if (send_cq == recv_cq) {
 636                 spin_lock_irq(&send_cq->lock);
 637                 __acquire(&recv_cq->lock);
 638         } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
 639                 spin_lock_irq(&send_cq->lock);
 640                 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
 641         } else {
 642                 spin_lock_irq(&recv_cq->lock);
 643                 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
 644         }
 645 }
 646
 647 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
 648         __releases(&send_cq->lock) __releases(&recv_cq->lock)
 649 {
 650         if (send_cq == recv_cq) {
 651                 __release(&recv_cq->lock);
 652                 spin_unlock_irq(&send_cq->lock);
 653         } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
 654                 spin_unlock(&recv_cq->lock);
 655                 spin_unlock_irq(&send_cq->lock);
 656         } else {
 657                 spin_unlock(&send_cq->lock);
 658                 spin_unlock_irq(&recv_cq->lock);
 659         }
 660 }
 661
 662 static void del_gid_entries(struct mlx4_ib_qp *qp)
 663 {
 664         struct mlx4_ib_gid_entry *ge, *tmp;
 665
 666         list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
 667                 list_del(&ge->list);
 668                 kfree(ge);
 669         }
 670 }
 671
 672 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
 673                               int is_user)
 674 {
 675         struct mlx4_ib_cq *send_cq, *recv_cq;
 676
 677         if (qp->state != IB_QPS_RESET)
 678                 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
 679                                    MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
 680                         printk(KERN_WARNING "mlx4_ib: modify QP %06x to RESET failed.\n",
 681                                qp->mqp.qpn);
 682
 683         send_cq = to_mcq(qp->ibqp.send_cq);
 684         recv_cq = to_mcq(qp->ibqp.recv_cq);
 685
 686         mlx4_ib_lock_cqs(send_cq, recv_cq);
 687
 688         if (!is_user) {
 689                 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
 690                                  qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
 691                 if (send_cq != recv_cq)
 692                         __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
 693         }
 694
 695         mlx4_qp_remove(dev->dev, &qp->mqp);
 696
 697         mlx4_ib_unlock_cqs(send_cq, recv_cq);
 698
 699         mlx4_qp_free(dev->dev, &qp->mqp);
 700
 701         if (!is_sqp(dev, qp))
 702                 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
 703
 704         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
 705
 706         if (is_user) {
 707                 if (!qp->ibqp.srq)
 708                         mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
 709                                               &qp->db);
 710                 ib_umem_release(qp->umem);
 711         } else {
 712                 kfree(qp->sq.wrid);
 713                 kfree(qp->rq.wrid);
 714                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
 715                 if (!qp->ibqp.srq)
 716                         mlx4_db_free(dev->dev, &qp->db);
 717         }
 718
 719         del_gid_entries(qp);
 720 }
 721
 722 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
 723                                 struct ib_qp_init_attr *init_attr,
 724                                 struct ib_udata *udata)
 725 {
 726         struct mlx4_ib_dev *dev = to_mdev(pd->device);
 727         struct mlx4_ib_sqp *sqp;
 728         struct mlx4_ib_qp *qp;
 729         int err;
 730
 731         /*
 732          * We only support LSO and multicast loopback blocking, and
 733          * only for kernel UD QPs.
 734          */
 735         if (init_attr->create_flags & ~(IB_QP_CREATE_IPOIB_UD_LSO |
 736                                         IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK))
 737                 return ERR_PTR(-EINVAL);
 738
 739         if (init_attr->create_flags &&
 740             (pd->uobject || init_attr->qp_type != IB_QPT_UD))
 741                 return ERR_PTR(-EINVAL);
 742
 743         switch (init_attr->qp_type) {
 744         case IB_QPT_RC:
 745         case IB_QPT_UC:
 746         case IB_QPT_UD:
 747         {
 748                 qp = kzalloc(sizeof *qp, GFP_KERNEL);
 749                 if (!qp)
 750                         return ERR_PTR(-ENOMEM);
 751
 752                 err = create_qp_common(dev, pd, init_attr, udata, 0, qp);
 753                 if (err) {
 754                         kfree(qp);
 755                         return ERR_PTR(err);
 756                 }
 757
 758                 qp->ibqp.qp_num = qp->mqp.qpn;
 759
 760                 break;
 761         }
 762         case IB_QPT_SMI:
 763         case IB_QPT_GSI:
 764         {
 765                 /* Userspace is not allowed to create special QPs: */
 766                 if (pd->uobject)
 767                         return ERR_PTR(-EINVAL);
 768
 769                 sqp = kzalloc(sizeof *sqp, GFP_KERNEL);
 770                 if (!sqp)
 771                         return ERR_PTR(-ENOMEM);
 772
 773                 qp = &sqp->qp;
 774
 775                 err = create_qp_common(dev, pd, init_attr, udata,
 776                                        dev->dev->caps.sqp_start +
 777                                        (init_attr->qp_type == IB_QPT_SMI ? 0 : 2) +
 778                                        init_attr->port_num - 1,
 779                                        qp);
 780                 if (err) {
 781                         kfree(sqp);
 782                         return ERR_PTR(err);
 783                 }
 784
 785                 qp->port        = init_attr->port_num;
 786                 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
 787
 788                 break;
 789         }
 790         default:
 791                 /* Don't support raw QPs */
 792                 return ERR_PTR(-EINVAL);
 793         }
 794
 795         return &qp->ibqp;
 796 }
 797
 798 int mlx4_ib_destroy_qp(struct ib_qp *qp)
 799 {
 800         struct mlx4_ib_dev *dev = to_mdev(qp->device);
 801         struct mlx4_ib_qp *mqp = to_mqp(qp);
 802
 803         if (is_qp0(dev, mqp))
 804                 mlx4_CLOSE_PORT(dev->dev, mqp->port);
 805
 806         destroy_qp_common(dev, mqp, !!qp->pd->uobject);
 807
 808         if (is_sqp(dev, mqp))
 809                 kfree(to_msqp(mqp));
 810         else
 811                 kfree(mqp);
 812
 813         return 0;
 814 }
 815
 816 static int to_mlx4_st(enum ib_qp_type type)
 817 {
 818         switch (type) {
 819         case IB_QPT_RC:         return MLX4_QP_ST_RC;
 820         case IB_QPT_UC:         return MLX4_QP_ST_UC;
 821         case IB_QPT_UD:         return MLX4_QP_ST_UD;
 822         case IB_QPT_SMI:
 823         case IB_QPT_GSI:        return MLX4_QP_ST_MLX;
 824         default:                return -1;
 825         }
 826 }
 827
 828 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
 829                                    int attr_mask)
 830 {
 831         u8 dest_rd_atomic;
 832         u32 access_flags;
 833         u32 hw_access_flags = 0;
 834
 835         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
 836                 dest_rd_atomic = attr->max_dest_rd_atomic;
 837         else
 838                 dest_rd_atomic = qp->resp_depth;
 839
 840         if (attr_mask & IB_QP_ACCESS_FLAGS)
 841                 access_flags = attr->qp_access_flags;
 842         else
 843                 access_flags = qp->atomic_rd_en;
 844
 845         if (!dest_rd_atomic)
 846                 access_flags &= IB_ACCESS_REMOTE_WRITE;
 847
 848         if (access_flags & IB_ACCESS_REMOTE_READ)
 849                 hw_access_flags |= MLX4_QP_BIT_RRE;
 850         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
 851                 hw_access_flags |= MLX4_QP_BIT_RAE;
 852         if (access_flags & IB_ACCESS_REMOTE_WRITE)
 853                 hw_access_flags |= MLX4_QP_BIT_RWE;
 854
 855         return cpu_to_be32(hw_access_flags);
 856 }
 857
 858 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
 859                             int attr_mask)
 860 {
 861         if (attr_mask & IB_QP_PKEY_INDEX)
 862                 sqp->pkey_index = attr->pkey_index;
 863         if (attr_mask & IB_QP_QKEY)
 864                 sqp->qkey = attr->qkey;
 865         if (attr_mask & IB_QP_SQ_PSN)
 866                 sqp->send_psn = attr->sq_psn;
 867 }
 868
 869 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
 870 {
 871         path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
 872 }
 873
 874 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
 875                          struct mlx4_qp_path *path, u8 port)
 876 {
 877         int err;
 878         int is_eth = rdma_port_get_link_layer(&dev->ib_dev, port) ==
 879                 IB_LINK_LAYER_ETHERNET;
 880         u8 mac[6];
 881         int is_mcast;
 882
 883         path->grh_mylmc     = ah->src_path_bits & 0x7f;
 884         path->rlid          = cpu_to_be16(ah->dlid);
 885         if (ah->static_rate) {
 886                 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
 887                 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
 888                        !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
 889                         --path->static_rate;
 890         } else
 891                 path->static_rate = 0;
 892         path->counter_index = 0xff;
 893
 894         if (ah->ah_flags & IB_AH_GRH) {
 895                 if (ah->grh.sgid_index >= dev->dev->caps.gid_table_len[port]) {
 896                         printk(KERN_ERR "sgid_index (%u) too large. max is %d\n",
 897                                ah->grh.sgid_index, dev->dev->caps.gid_table_len[port] - 1);
 898                         return -1;
 899                 }
 900
 901                 path->grh_mylmc |= 1 << 7;
 902                 path->mgid_index = ah->grh.sgid_index;
 903                 path->hop_limit  = ah->grh.hop_limit;
 904                 path->tclass_flowlabel =
 905                         cpu_to_be32((ah->grh.traffic_class << 20) |
 906                                     (ah->grh.flow_label));
 907                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
 908         }
 909
 910         path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
 911                 ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
 912
 913         if (is_eth) {
 914                 if (!(ah->ah_flags & IB_AH_GRH))
 915                         return -1;
 916
 917                 err = mlx4_ib_resolve_grh(dev, ah, mac, &is_mcast, port);
 918                 if (err)
 919                         return err;
 920
 921                 memcpy(path->dmac, mac, 6);
 922                 path->ackto = MLX4_IB_LINK_TYPE_ETH;
 923                 /* use index 0 into MAC table for IBoE */
 924                 path->grh_mylmc &= 0x80;
 925         }
 926
 927         return 0;
 928 }
 929
 930 static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 931 {
 932         struct mlx4_ib_gid_entry *ge, *tmp;
 933
 934         list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
 935                 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
 936                         ge->added = 1;
 937                         ge->port = qp->port;
 938                 }
 939         }
 940 }
 941
 942 static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
 943                                const struct ib_qp_attr *attr, int attr_mask,
 944                                enum ib_qp_state cur_state, enum ib_qp_state new_state)
 945 {
 946         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
 947         struct mlx4_ib_qp *qp = to_mqp(ibqp);
 948         struct mlx4_qp_context *context;
 949         enum mlx4_qp_optpar optpar = 0;
 950         int sqd_event;
 951         int err = -EINVAL;
 952
 953         context = kzalloc(sizeof *context, GFP_KERNEL);
 954         if (!context)
 955                 return -ENOMEM;
 956
 957         context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
 958                                      (to_mlx4_st(ibqp->qp_type) << 16));
 959
 960         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
 961                 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
 962         else {
 963                 optpar |= MLX4_QP_OPTPAR_PM_STATE;
 964                 switch (attr->path_mig_state) {
 965                 case IB_MIG_MIGRATED:
 966                         context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
 967                         break;
 968                 case IB_MIG_REARM:
 969                         context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
 970                         break;
 971                 case IB_MIG_ARMED:
 972                         context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
 973                         break;
 974                 }
 975         }
 976
 977         if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
 978                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
 979         else if (ibqp->qp_type == IB_QPT_UD) {
 980                 if (qp->flags & MLX4_IB_QP_LSO)
 981                         context->mtu_msgmax = (IB_MTU_4096 << 5) |
 982                                               ilog2(dev->dev->caps.max_gso_sz);
 983                 else
 984                         context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
 985         } else if (attr_mask & IB_QP_PATH_MTU) {
 986                 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
 987                         printk(KERN_ERR "path MTU (%u) is invalid\n",
 988                                attr->path_mtu);
 989                         goto out;
 990                 }
 991                 context->mtu_msgmax = (attr->path_mtu << 5) |
 992                         ilog2(dev->dev->caps.max_msg_sz);
 993         }
 994
 995         if (qp->rq.wqe_cnt)
 996                 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
 997         context->rq_size_stride |= qp->rq.wqe_shift - 4;
 998
 999         if (qp->sq.wqe_cnt)
1000                 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
1001         context->sq_size_stride |= qp->sq.wqe_shift - 4;
1002
1003         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1004                 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
1005
1006         if (qp->ibqp.uobject)
1007                 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
1008         else
1009                 context->usr_page = cpu_to_be32(dev->priv_uar.index);
1010
1011         if (attr_mask & IB_QP_DEST_QPN)
1012                 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
1013
1014         if (attr_mask & IB_QP_PORT) {
1015                 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
1016                     !(attr_mask & IB_QP_AV)) {
1017                         mlx4_set_sched(&context->pri_path, attr->port_num);
1018                         optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
1019                 }
1020         }
1021
1022         if (attr_mask & IB_QP_PKEY_INDEX) {
1023                 context->pri_path.pkey_index = attr->pkey_index;
1024                 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
1025         }
1026
1027         if (attr_mask & IB_QP_AV) {
1028                 if (mlx4_set_path(dev, &attr->ah_attr, &context->pri_path,
1029                                   attr_mask & IB_QP_PORT ? attr->port_num : qp->port))
1030                         goto out;
1031
1032                 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
1033                            MLX4_QP_OPTPAR_SCHED_QUEUE);
1034         }
1035
1036         if (attr_mask & IB_QP_TIMEOUT) {
1037                 context->pri_path.ackto |= attr->timeout << 3;
1038                 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
1039         }
1040
1041         if (attr_mask & IB_QP_ALT_PATH) {
1042                 if (attr->alt_port_num == 0 ||
1043                     attr->alt_port_num > dev->dev->caps.num_ports)
1044                         goto out;
1045
1046                 if (attr->alt_pkey_index >=
1047                     dev->dev->caps.pkey_table_len[attr->alt_port_num])
1048                         goto out;
1049
1050                 if (mlx4_set_path(dev, &attr->alt_ah_attr, &context->alt_path,
1051                                   attr->alt_port_num))
1052                         goto out;
1053
1054                 context->alt_path.pkey_index = attr->alt_pkey_index;
1055                 context->alt_path.ackto = attr->alt_timeout << 3;
1056                 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
1057         }
1058
1059         context->pd         = cpu_to_be32(to_mpd(ibqp->pd)->pdn);
1060         context->params1    = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
1061
1062         /* Set "fast registration enabled" for all kernel QPs */
1063         if (!qp->ibqp.uobject)
1064                 context->params1 |= cpu_to_be32(1 << 11);
1065
1066         if (attr_mask & IB_QP_RNR_RETRY) {
1067                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1068                 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
1069         }
1070
1071         if (attr_mask & IB_QP_RETRY_CNT) {
1072                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1073                 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
1074         }
1075
1076         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1077                 if (attr->max_rd_atomic)
1078                         context->params1 |=
1079                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1080                 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
1081         }
1082
1083         if (attr_mask & IB_QP_SQ_PSN)
1084                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1085
1086         context->cqn_send = cpu_to_be32(to_mcq(ibqp->send_cq)->mcq.cqn);
1087
1088         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1089                 if (attr->max_dest_rd_atomic)
1090                         context->params2 |=
1091                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1092                 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
1093         }
1094
1095         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
1096                 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
1097                 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
1098         }
1099
1100         if (ibqp->srq)
1101                 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
1102
1103         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1104                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1105                 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
1106         }
1107         if (attr_mask & IB_QP_RQ_PSN)
1108                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1109
1110         context->cqn_recv = cpu_to_be32(to_mcq(ibqp->recv_cq)->mcq.cqn);
1111
1112         if (attr_mask & IB_QP_QKEY) {
1113                 context->qkey = cpu_to_be32(attr->qkey);
1114                 optpar |= MLX4_QP_OPTPAR_Q_KEY;
1115         }
1116
1117         if (ibqp->srq)
1118                 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
1119
1120         if (!ibqp->srq && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1121                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1122
1123         if (cur_state == IB_QPS_INIT &&
1124             new_state == IB_QPS_RTR  &&
1125             (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
1126              ibqp->qp_type == IB_QPT_UD)) {
1127                 context->pri_path.sched_queue = (qp->port - 1) << 6;
1128                 if (is_qp0(dev, qp))
1129                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1130                 else
1131                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1132         }
1133
1134         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
1135             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1136                 sqd_event = 1;
1137         else
1138                 sqd_event = 0;
1139
1140         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1141                 context->rlkey |= (1 << 4);
1142
1143         /*
1144          * Before passing a kernel QP to the HW, make sure that the
1145          * ownership bits of the send queue are set and the SQ
1146          * headroom is stamped so that the hardware doesn't start
1147          * processing stale work requests.
1148          */
1149         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1150                 struct mlx4_wqe_ctrl_seg *ctrl;
1151                 int i;
1152
1153                 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
1154                         ctrl = get_send_wqe(qp, i);
1155                         ctrl->owner_opcode = cpu_to_be32(1 << 31);
1156                         if (qp->sq_max_wqes_per_wr == 1)
1157                                 ctrl->fence_size = 1 << (qp->sq.wqe_shift - 4);
1158
1159                         stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
1160                 }
1161         }
1162
1163         err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
1164                              to_mlx4_state(new_state), context, optpar,
1165                              sqd_event, &qp->mqp);
1166         if (err)
1167                 goto out;
1168
1169         qp->state = new_state;
1170
1171         if (attr_mask & IB_QP_ACCESS_FLAGS)
1172                 qp->atomic_rd_en = attr->qp_access_flags;
1173         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1174                 qp->resp_depth = attr->max_dest_rd_atomic;
1175         if (attr_mask & IB_QP_PORT) {
1176                 qp->port = attr->port_num;
1177                 update_mcg_macs(dev, qp);
1178         }
1179         if (attr_mask & IB_QP_ALT_PATH)
1180                 qp->alt_port = attr->alt_port_num;
1181
1182         if (is_sqp(dev, qp))
1183                 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
1184
1185         /*
1186          * If we moved QP0 to RTR, bring the IB link up; if we moved
1187          * QP0 to RESET or ERROR, bring the link back down.
1188          */
1189         if (is_qp0(dev, qp)) {
1190                 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
1191                         if (mlx4_INIT_PORT(dev->dev, qp->port))
1192                                 printk(KERN_WARNING "INIT_PORT failed for port %d\n",
1193                                        qp->port);
1194
1195                 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
1196                     (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
1197                         mlx4_CLOSE_PORT(dev->dev, qp->port);
1198         }
1199
1200         /*
1201          * If we moved a kernel QP to RESET, clean up all old CQ
1202          * entries and reinitialize the QP.
1203          */
1204         if (new_state == IB_QPS_RESET && !ibqp->uobject) {
1205                 mlx4_ib_cq_clean(to_mcq(ibqp->recv_cq), qp->mqp.qpn,
1206                                  ibqp->srq ? to_msrq(ibqp->srq): NULL);
1207                 if (ibqp->send_cq != ibqp->recv_cq)
1208                         mlx4_ib_cq_clean(to_mcq(ibqp->send_cq), qp->mqp.qpn, NULL);
1209
1210                 qp->rq.head = 0;
1211                 qp->rq.tail = 0;
1212                 qp->sq.head = 0;
1213                 qp->sq.tail = 0;
1214                 qp->sq_next_wqe = 0;
1215                 if (!ibqp->srq)
1216                         *qp->db.db  = 0;
1217         }
1218
1219 out:
1220         kfree(context);
1221         return err;
1222 }
1223
1224 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1225                       int attr_mask, struct ib_udata *udata)
1226 {
1227         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1228         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1229         enum ib_qp_state cur_state, new_state;
1230         int err = -EINVAL;
1231
1232         mutex_lock(&qp->mutex);
1233
1234         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
1235         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1236
1237         if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask))
1238                 goto out;
1239
1240         if ((attr_mask & IB_QP_PORT) &&
1241             (attr->port_num == 0 || attr->port_num > dev->dev->caps.num_ports)) {
1242                 goto out;
1243         }
1244
1245         if (attr_mask & IB_QP_PKEY_INDEX) {
1246                 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1247                 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p])
1248                         goto out;
1249         }
1250
1251         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
1252             attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
1253                 goto out;
1254         }
1255
1256         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
1257             attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
1258                 goto out;
1259         }
1260
1261         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1262                 err = 0;
1263                 goto out;
1264         }
1265
1266         err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
1267
1268 out:
1269         mutex_unlock(&qp->mutex);
1270         return err;
1271 }
1272
1273 static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_send_wr *wr,
1274                             void *wqe, unsigned *mlx_seg_len)
1275 {
1276         struct ib_device *ib_dev = sqp->qp.ibqp.device;
1277         struct mlx4_wqe_mlx_seg *mlx = wqe;
1278         struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
1279         struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
1280         u16 pkey;
1281         int send_size;
1282         int header_size;
1283         int spc;
1284         int i;
1285         int is_eth;
1286         int is_grh;
1287
1288         send_size = 0;
1289         for (i = 0; i < wr->num_sge; ++i)
1290                 send_size += wr->sg_list[i].length;
1291
1292         is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
1293         is_grh = mlx4_ib_ah_grh_present(ah);
1294         ib_ud_header_init(send_size, !is_eth, is_eth, 0, is_grh, 0, &sqp->ud_header);
1295
1296         if (!is_eth) {
1297                 sqp->ud_header.lrh.service_level =
1298                         be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
1299                 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
1300                 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
1301         }
1302
1303         if (is_grh) {
1304                 sqp->ud_header.grh.traffic_class =
1305                         (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
1306                 sqp->ud_header.grh.flow_label    =
1307                         ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
1308                 sqp->ud_header.grh.hop_limit     = ah->av.ib.hop_limit;
1309                 ib_get_cached_gid(ib_dev, be32_to_cpu(ah->av.ib.port_pd) >> 24,
1310                                   ah->av.ib.gid_index, &sqp->ud_header.grh.source_gid);
1311                 memcpy(sqp->ud_header.grh.destination_gid.raw,
1312                        ah->av.ib.dgid, 16);
1313         }
1314
1315         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
1316
1317         if (!is_eth) {
1318                 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
1319                                           (sqp->ud_header.lrh.destination_lid ==
1320                                            IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
1321                                           (sqp->ud_header.lrh.service_level << 8));
1322                 mlx->rlid = sqp->ud_header.lrh.destination_lid;
1323         }
1324
1325         switch (wr->opcode) {
1326         case IB_WR_SEND:
1327                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
1328                 sqp->ud_header.immediate_present = 0;
1329                 break;
1330         case IB_WR_SEND_WITH_IMM:
1331                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1332                 sqp->ud_header.immediate_present = 1;
1333                 sqp->ud_header.immediate_data    = wr->ex.imm_data;
1334                 break;
1335         default:
1336                 return -EINVAL;
1337         }
1338
1339         if (is_eth) {
1340                 u8 *smac;
1341
1342                 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
1343                 /* FIXME: cache smac value? */
1344                 smac = to_mdev(sqp->qp.ibqp.device)->iboe.netdevs[sqp->qp.port - 1]->dev_addr;
1345                 memcpy(sqp->ud_header.eth.smac_h, smac, 6);
1346                 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
1347                         mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
1348                 sqp->ud_header.eth.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
1349         } else {
1350                 sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
1351                 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1352                         sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1353         }
1354         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1355         if (!sqp->qp.ibqp.qp_num)
1356                 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
1357         else
1358                 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->wr.ud.pkey_index, &pkey);
1359         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1360         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1361         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1362         sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1363                                                sqp->qkey : wr->wr.ud.remote_qkey);
1364         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1365
1366         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
1367
1368         if (0) {
1369                 printk(KERN_ERR "built UD header of size %d:\n", header_size);
1370                 for (i = 0; i < header_size / 4; ++i) {
1371                         if (i % 8 == 0)
1372                                 printk("  [%02x] ", i * 4);
1373                         printk(" %08x",
1374                                be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
1375                         if ((i + 1) % 8 == 0)
1376                                 printk("\n");
1377                 }
1378                 printk("\n");
1379         }
1380
1381         /*
1382          * Inline data segments may not cross a 64 byte boundary.  If
1383          * our UD header is bigger than the space available up to the
1384          * next 64 byte boundary in the WQE, use two inline data
1385          * segments to hold the UD header.
1386          */
1387         spc = MLX4_INLINE_ALIGN -
1388                 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
1389         if (header_size <= spc) {
1390                 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
1391                 memcpy(inl + 1, sqp->header_buf, header_size);
1392                 i = 1;
1393         } else {
1394                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
1395                 memcpy(inl + 1, sqp->header_buf, spc);
1396
1397                 inl = (void *) (inl + 1) + spc;
1398                 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
1399                 /*
1400                  * Need a barrier here to make sure all the data is
1401                  * visible before the byte_count field is set.
1402                  * Otherwise the HCA prefetcher could grab the 64-byte
1403                  * chunk with this inline segment and get a valid (!=
1404                  * 0xffffffff) byte count but stale data, and end up
1405                  * generating a packet with bad headers.
1406                  *
1407                  * The first inline segment's byte_count field doesn't
1408                  * need a barrier, because it comes after a
1409                  * control/MLX segment and therefore is at an offset
1410                  * of 16 mod 64.
1411                  */
1412                 wmb();
1413                 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
1414                 i = 2;
1415         }
1416
1417         *mlx_seg_len =
1418                 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
1419         return 0;
1420 }
1421
1422 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
1423 {
1424         unsigned cur;
1425         struct mlx4_ib_cq *cq;
1426
1427         cur = wq->head - wq->tail;
1428         if (likely(cur + nreq < wq->max_post))
1429                 return 0;
1430
1431         cq = to_mcq(ib_cq);
1432         spin_lock(&cq->lock);
1433         cur = wq->head - wq->tail;
1434         spin_unlock(&cq->lock);
1435
1436         return cur + nreq >= wq->max_post;
1437 }
1438
1439 static __be32 convert_access(int acc)
1440 {
1441         return (acc & IB_ACCESS_REMOTE_ATOMIC ? cpu_to_be32(MLX4_WQE_FMR_PERM_ATOMIC)       : 0) |
1442                (acc & IB_ACCESS_REMOTE_WRITE  ? cpu_to_be32(MLX4_WQE_FMR_PERM_REMOTE_WRITE) : 0) |
1443                (acc & IB_ACCESS_REMOTE_READ   ? cpu_to_be32(MLX4_WQE_FMR_PERM_REMOTE_READ)  : 0) |
1444                (acc & IB_ACCESS_LOCAL_WRITE   ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE)  : 0) |
1445                 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
1446 }
1447
1448 static void set_fmr_seg(struct mlx4_wqe_fmr_seg *fseg, struct ib_send_wr *wr)
1449 {
1450         struct mlx4_ib_fast_reg_page_list *mfrpl = to_mfrpl(wr->wr.fast_reg.page_list);
1451         int i;
1452
1453         for (i = 0; i < wr->wr.fast_reg.page_list_len; ++i)
1454                 mfrpl->mapped_page_list[i] =
1455                         cpu_to_be64(wr->wr.fast_reg.page_list->page_list[i] |
1456                                     MLX4_MTT_FLAG_PRESENT);
1457
1458         fseg->flags             = convert_access(wr->wr.fast_reg.access_flags);
1459         fseg->mem_key           = cpu_to_be32(wr->wr.fast_reg.rkey);
1460         fseg->buf_list          = cpu_to_be64(mfrpl->map);
1461         fseg->start_addr        = cpu_to_be64(wr->wr.fast_reg.iova_start);
1462         fseg->reg_len           = cpu_to_be64(wr->wr.fast_reg.length);
1463         fseg->offset            = 0; /* XXX -- is this just for ZBVA? */
1464         fseg->page_size         = cpu_to_be32(wr->wr.fast_reg.page_shift);
1465         fseg->reserved[0]       = 0;
1466         fseg->reserved[1]       = 0;
1467 }
1468
1469 static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
1470 {
1471         iseg->flags     = 0;
1472         iseg->mem_key   = cpu_to_be32(rkey);
1473         iseg->guest_id  = 0;
1474         iseg->pa        = 0;
1475 }
1476
1477 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
1478                                           u64 remote_addr, u32 rkey)
1479 {
1480         rseg->raddr    = cpu_to_be64(remote_addr);
1481         rseg->rkey     = cpu_to_be32(rkey);
1482         rseg->reserved = 0;
1483 }
1484
1485 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, struct ib_send_wr *wr)
1486 {
1487         if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1488                 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap);
1489                 aseg->compare  = cpu_to_be64(wr->wr.atomic.compare_add);
1490         } else if (wr->opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
1491                 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
1492                 aseg->compare  = cpu_to_be64(wr->wr.atomic.compare_add_mask);
1493         } else {
1494                 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
1495                 aseg->compare  = 0;
1496         }
1497
1498 }
1499
1500 static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
1501                                   struct ib_send_wr *wr)
1502 {
1503         aseg->swap_add          = cpu_to_be64(wr->wr.atomic.swap);
1504         aseg->swap_add_mask     = cpu_to_be64(wr->wr.atomic.swap_mask);
1505         aseg->compare           = cpu_to_be64(wr->wr.atomic.compare_add);
1506         aseg->compare_mask      = cpu_to_be64(wr->wr.atomic.compare_add_mask);
1507 }
1508
1509 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
1510                              struct ib_send_wr *wr)
1511 {
1512         memcpy(dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof (struct mlx4_av));
1513         dseg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1514         dseg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
1515         dseg->vlan = to_mah(wr->wr.ud.ah)->av.eth.vlan;
1516         memcpy(dseg->mac, to_mah(wr->wr.ud.ah)->av.eth.mac, 6);
1517 }
1518
1519 static void set_mlx_icrc_seg(void *dseg)
1520 {
1521         u32 *t = dseg;
1522         struct mlx4_wqe_inline_seg *iseg = dseg;
1523
1524         t[1] = 0;
1525
1526         /*
1527          * Need a barrier here before writing the byte_count field to
1528          * make sure that all the data is visible before the
1529          * byte_count field is set.  Otherwise, if the segment begins
1530          * a new cacheline, the HCA prefetcher could grab the 64-byte
1531          * chunk and get a valid (!= * 0xffffffff) byte count but
1532          * stale data, and end up sending the wrong data.
1533          */
1534         wmb();
1535
1536         iseg->byte_count = cpu_to_be32((1 << 31) | 4);
1537 }
1538
1539 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
1540 {
1541         dseg->lkey       = cpu_to_be32(sg->lkey);
1542         dseg->addr       = cpu_to_be64(sg->addr);
1543
1544         /*
1545          * Need a barrier here before writing the byte_count field to
1546          * make sure that all the data is visible before the
1547          * byte_count field is set.  Otherwise, if the segment begins
1548          * a new cacheline, the HCA prefetcher could grab the 64-byte
1549          * chunk and get a valid (!= * 0xffffffff) byte count but
1550          * stale data, and end up sending the wrong data.
1551          */
1552         wmb();
1553
1554         dseg->byte_count = cpu_to_be32(sg->length);
1555 }
1556
1557 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
1558 {
1559         dseg->byte_count = cpu_to_be32(sg->length);
1560         dseg->lkey       = cpu_to_be32(sg->lkey);
1561         dseg->addr       = cpu_to_be64(sg->addr);
1562 }
1563
1564 static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_send_wr *wr,
1565                          struct mlx4_ib_qp *qp, unsigned *lso_seg_len,
1566                          __be32 *lso_hdr_sz, __be32 *blh)
1567 {
1568         unsigned halign = ALIGN(sizeof *wqe + wr->wr.ud.hlen, 16);
1569
1570         if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
1571                 *blh = cpu_to_be32(1 << 6);
1572
1573         if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
1574                      wr->num_sge > qp->sq.max_gs - (halign >> 4)))
1575                 return -EINVAL;
1576
1577         memcpy(wqe->header, wr->wr.ud.header, wr->wr.ud.hlen);
1578
1579         *lso_hdr_sz  = cpu_to_be32((wr->wr.ud.mss - wr->wr.ud.hlen) << 16 |
1580                                    wr->wr.ud.hlen);
1581         *lso_seg_len = halign;
1582         return 0;
1583 }
1584
1585 static __be32 send_ieth(struct ib_send_wr *wr)
1586 {
1587         switch (wr->opcode) {
1588         case IB_WR_SEND_WITH_IMM:
1589         case IB_WR_RDMA_WRITE_WITH_IMM:
1590                 return wr->ex.imm_data;
1591
1592         case IB_WR_SEND_WITH_INV:
1593                 return cpu_to_be32(wr->ex.invalidate_rkey);
1594
1595         default:
1596                 return 0;
1597         }
1598 }
1599
1600 int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1601                       struct ib_send_wr **bad_wr)
1602 {
1603         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1604         void *wqe;
1605         struct mlx4_wqe_ctrl_seg *ctrl;
1606         struct mlx4_wqe_data_seg *dseg;
1607         unsigned long flags;
1608         int nreq;
1609         int err = 0;
1610         unsigned ind;
1611         int uninitialized_var(stamp);
1612         int uninitialized_var(size);
1613         unsigned uninitialized_var(seglen);
1614         __be32 dummy;
1615         __be32 *lso_wqe;
1616         __be32 uninitialized_var(lso_hdr_sz);
1617         __be32 blh;
1618         int i;
1619
1620         spin_lock_irqsave(&qp->sq.lock, flags);
1621
1622         ind = qp->sq_next_wqe;
1623
1624         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1625                 lso_wqe = &dummy;
1626                 blh = 0;
1627
1628                 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1629                         err = -ENOMEM;
1630                         *bad_wr = wr;
1631                         goto out;
1632                 }
1633
1634                 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
1635                         err = -EINVAL;
1636                         *bad_wr = wr;
1637                         goto out;
1638                 }
1639
1640                 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
1641                 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
1642
1643                 ctrl->srcrb_flags =
1644                         (wr->send_flags & IB_SEND_SIGNALED ?
1645                          cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
1646                         (wr->send_flags & IB_SEND_SOLICITED ?
1647                          cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
1648                         ((wr->send_flags & IB_SEND_IP_CSUM) ?
1649                          cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
1650                                      MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
1651                         qp->sq_signal_bits;
1652
1653                 ctrl->imm = send_ieth(wr);
1654
1655                 wqe += sizeof *ctrl;
1656                 size = sizeof *ctrl / 16;
1657
1658                 switch (ibqp->qp_type) {
1659                 case IB_QPT_RC:
1660                 case IB_QPT_UC:
1661                         switch (wr->opcode) {
1662                         case IB_WR_ATOMIC_CMP_AND_SWP:
1663                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1664                         case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
1665                                 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
1666                                               wr->wr.atomic.rkey);
1667                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
1668
1669                                 set_atomic_seg(wqe, wr);
1670                                 wqe  += sizeof (struct mlx4_wqe_atomic_seg);
1671
1672                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
1673                                          sizeof (struct mlx4_wqe_atomic_seg)) / 16;
1674
1675                                 break;
1676
1677                         case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
1678                                 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
1679                                               wr->wr.atomic.rkey);
1680                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
1681
1682                                 set_masked_atomic_seg(wqe, wr);
1683                                 wqe  += sizeof (struct mlx4_wqe_masked_atomic_seg);
1684
1685                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
1686                                          sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
1687
1688                                 break;
1689
1690                         case IB_WR_RDMA_READ:
1691                         case IB_WR_RDMA_WRITE:
1692                         case IB_WR_RDMA_WRITE_WITH_IMM:
1693                                 set_raddr_seg(wqe, wr->wr.rdma.remote_addr,
1694                                               wr->wr.rdma.rkey);
1695                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
1696                                 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
1697                                 break;
1698
1699                         case IB_WR_LOCAL_INV:
1700                                 ctrl->srcrb_flags |=
1701                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
1702                                 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
1703                                 wqe  += sizeof (struct mlx4_wqe_local_inval_seg);
1704                                 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
1705                                 break;
1706
1707                         case IB_WR_FAST_REG_MR:
1708                                 ctrl->srcrb_flags |=
1709                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
1710                                 set_fmr_seg(wqe, wr);
1711                                 wqe  += sizeof (struct mlx4_wqe_fmr_seg);
1712                                 size += sizeof (struct mlx4_wqe_fmr_seg) / 16;
1713                                 break;
1714
1715                         default:
1716                                 /* No extra segments required for sends */
1717                                 break;
1718                         }
1719                         break;
1720
1721                 case IB_QPT_UD:
1722                         set_datagram_seg(wqe, wr);
1723                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
1724                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
1725
1726                         if (wr->opcode == IB_WR_LSO) {
1727                                 err = build_lso_seg(wqe, wr, qp, &seglen, &lso_hdr_sz, &blh);
1728                                 if (unlikely(err)) {
1729                                         *bad_wr = wr;
1730                                         goto out;
1731                                 }
1732                                 lso_wqe = (__be32 *) wqe;
1733                                 wqe  += seglen;
1734                                 size += seglen / 16;
1735                         }
1736                         break;
1737
1738                 case IB_QPT_SMI:
1739                 case IB_QPT_GSI:
1740                         err = build_mlx_header(to_msqp(qp), wr, ctrl, &seglen);
1741                         if (unlikely(err)) {
1742                                 *bad_wr = wr;
1743                                 goto out;
1744                         }
1745                         wqe  += seglen;
1746                         size += seglen / 16;
1747                         break;
1748
1749                 default:
1750                         break;
1751                 }
1752
1753                 /*
1754                  * Write data segments in reverse order, so as to
1755                  * overwrite cacheline stamp last within each
1756                  * cacheline.  This avoids issues with WQE
1757                  * prefetching.
1758                  */
1759
1760                 dseg = wqe;
1761                 dseg += wr->num_sge - 1;
1762                 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
1763
1764                 /* Add one more inline data segment for ICRC for MLX sends */
1765                 if (unlikely(qp->ibqp.qp_type == IB_QPT_SMI ||
1766                              qp->ibqp.qp_type == IB_QPT_GSI)) {
1767                         set_mlx_icrc_seg(dseg + 1);
1768                         size += sizeof (struct mlx4_wqe_data_seg) / 16;
1769                 }
1770
1771                 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
1772                         set_data_seg(dseg, wr->sg_list + i);
1773
1774                 /*
1775                  * Possibly overwrite stamping in cacheline with LSO
1776                  * segment only after making sure all data segments
1777                  * are written.
1778                  */
1779                 wmb();
1780                 *lso_wqe = lso_hdr_sz;
1781
1782                 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
1783                                     MLX4_WQE_CTRL_FENCE : 0) | size;
1784
1785                 /*
1786                  * Make sure descriptor is fully written before
1787                  * setting ownership bit (because HW can start
1788                  * executing as soon as we do).
1789                  */
1790                 wmb();
1791
1792                 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
1793                         err = -EINVAL;
1794                         goto out;
1795                 }
1796
1797                 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
1798                         (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
1799
1800                 stamp = ind + qp->sq_spare_wqes;
1801                 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
1802
1803                 /*
1804                  * We can improve latency by not stamping the last
1805                  * send queue WQE until after ringing the doorbell, so
1806                  * only stamp here if there are still more WQEs to post.
1807                  *
1808                  * Same optimization applies to padding with NOP wqe
1809                  * in case of WQE shrinking (used to prevent wrap-around
1810                  * in the middle of WR).
1811                  */
1812                 if (wr->next) {
1813                         stamp_send_wqe(qp, stamp, size * 16);
1814                         ind = pad_wraparound(qp, ind);
1815                 }
1816         }
1817
1818 out:
1819         if (likely(nreq)) {
1820                 qp->sq.head += nreq;
1821
1822                 /*
1823                  * Make sure that descriptors are written before
1824                  * doorbell record.
1825                  */
1826                 wmb();
1827
1828                 writel(qp->doorbell_qpn,
1829                        to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
1830
1831                 /*
1832                  * Make sure doorbells don't leak out of SQ spinlock
1833                  * and reach the HCA out of order.
1834                  */
1835                 mmiowb();
1836
1837                 stamp_send_wqe(qp, stamp, size * 16);
1838
1839                 ind = pad_wraparound(qp, ind);
1840                 qp->sq_next_wqe = ind;
1841         }
1842
1843         spin_unlock_irqrestore(&qp->sq.lock, flags);
1844
1845         return err;
1846 }
1847
1848 int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1849                       struct ib_recv_wr **bad_wr)
1850 {
1851         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1852         struct mlx4_wqe_data_seg *scat;
1853         unsigned long flags;
1854         int err = 0;
1855         int nreq;
1856         int ind;
1857         int i;
1858
1859         spin_lock_irqsave(&qp->rq.lock, flags);
1860
1861         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
1862
1863         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1864                 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1865                         err = -ENOMEM;
1866                         *bad_wr = wr;
1867                         goto out;
1868                 }
1869
1870                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1871                         err = -EINVAL;
1872                         *bad_wr = wr;
1873                         goto out;
1874                 }
1875
1876                 scat = get_recv_wqe(qp, ind);
1877
1878                 for (i = 0; i < wr->num_sge; ++i)
1879                         __set_data_seg(scat + i, wr->sg_list + i);
1880
1881                 if (i < qp->rq.max_gs) {
1882                         scat[i].byte_count = 0;
1883                         scat[i].lkey       = cpu_to_be32(MLX4_INVALID_LKEY);
1884                         scat[i].addr       = 0;
1885                 }
1886
1887                 qp->rq.wrid[ind] = wr->wr_id;
1888
1889                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
1890         }
1891
1892 out:
1893         if (likely(nreq)) {
1894                 qp->rq.head += nreq;
1895
1896                 /*
1897                  * Make sure that descriptors are written before
1898                  * doorbell record.
1899                  */
1900                 wmb();
1901
1902                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
1903         }
1904
1905         spin_unlock_irqrestore(&qp->rq.lock, flags);
1906
1907         return err;
1908 }
1909
1910 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
1911 {
1912         switch (mlx4_state) {
1913         case MLX4_QP_STATE_RST:      return IB_QPS_RESET;
1914         case MLX4_QP_STATE_INIT:     return IB_QPS_INIT;
1915         case MLX4_QP_STATE_RTR:      return IB_QPS_RTR;
1916         case MLX4_QP_STATE_RTS:      return IB_QPS_RTS;
1917         case MLX4_QP_STATE_SQ_DRAINING:
1918         case MLX4_QP_STATE_SQD:      return IB_QPS_SQD;
1919         case MLX4_QP_STATE_SQER:     return IB_QPS_SQE;
1920         case MLX4_QP_STATE_ERR:      return IB_QPS_ERR;
1921         default:                     return -1;
1922         }
1923 }
1924
1925 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
1926 {
1927         switch (mlx4_mig_state) {
1928         case MLX4_QP_PM_ARMED:          return IB_MIG_ARMED;
1929         case MLX4_QP_PM_REARM:          return IB_MIG_REARM;
1930         case MLX4_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
1931         default: return -1;
1932         }
1933 }
1934
1935 static int to_ib_qp_access_flags(int mlx4_flags)
1936 {
1937         int ib_flags = 0;
1938
1939         if (mlx4_flags & MLX4_QP_BIT_RRE)
1940                 ib_flags |= IB_ACCESS_REMOTE_READ;
1941         if (mlx4_flags & MLX4_QP_BIT_RWE)
1942                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
1943         if (mlx4_flags & MLX4_QP_BIT_RAE)
1944                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
1945
1946         return ib_flags;
1947 }
1948
1949 static void to_ib_ah_attr(struct mlx4_dev *dev, struct ib_ah_attr *ib_ah_attr,
1950                                 struct mlx4_qp_path *path)
1951 {
1952         memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
1953         ib_ah_attr->port_num      = path->sched_queue & 0x40 ? 2 : 1;
1954
1955         if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
1956                 return;
1957
1958         ib_ah_attr->dlid          = be16_to_cpu(path->rlid);
1959         ib_ah_attr->sl            = (path->sched_queue >> 2) & 0xf;
1960         ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f;
1961         ib_ah_attr->static_rate   = path->static_rate ? path->static_rate - 5 : 0;
1962         ib_ah_attr->ah_flags      = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
1963         if (ib_ah_attr->ah_flags) {
1964                 ib_ah_attr->grh.sgid_index = path->mgid_index;
1965                 ib_ah_attr->grh.hop_limit  = path->hop_limit;
1966                 ib_ah_attr->grh.traffic_class =
1967                         (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
1968                 ib_ah_attr->grh.flow_label =
1969                         be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
1970                 memcpy(ib_ah_attr->grh.dgid.raw,
1971                         path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
1972         }
1973 }
1974
1975 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
1976                      struct ib_qp_init_attr *qp_init_attr)
1977 {
1978         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1979         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1980         struct mlx4_qp_context context;
1981         int mlx4_state;
1982         int err = 0;
1983
1984         mutex_lock(&qp->mutex);
1985
1986         if (qp->state == IB_QPS_RESET) {
1987                 qp_attr->qp_state = IB_QPS_RESET;
1988                 goto done;
1989         }
1990
1991         err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
1992         if (err) {
1993                 err = -EINVAL;
1994                 goto out;
1995         }
1996
1997         mlx4_state = be32_to_cpu(context.flags) >> 28;
1998
1999         qp->state                    = to_ib_qp_state(mlx4_state);
2000         qp_attr->qp_state            = qp->state;
2001         qp_attr->path_mtu            = context.mtu_msgmax >> 5;
2002         qp_attr->path_mig_state      =
2003                 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
2004         qp_attr->qkey                = be32_to_cpu(context.qkey);
2005         qp_attr->rq_psn              = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
2006         qp_attr->sq_psn              = be32_to_cpu(context.next_send_psn) & 0xffffff;
2007         qp_attr->dest_qp_num         = be32_to_cpu(context.remote_qpn) & 0xffffff;
2008         qp_attr->qp_access_flags     =
2009                 to_ib_qp_access_flags(be32_to_cpu(context.params2));
2010
2011         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
2012                 to_ib_ah_attr(dev->dev, &qp_attr->ah_attr, &context.pri_path);
2013                 to_ib_ah_attr(dev->dev, &qp_attr->alt_ah_attr, &context.alt_path);
2014                 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
2015                 qp_attr->alt_port_num   = qp_attr->alt_ah_attr.port_num;
2016         }
2017
2018         qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
2019         if (qp_attr->qp_state == IB_QPS_INIT)
2020                 qp_attr->port_num = qp->port;
2021         else
2022                 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
2023
2024         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
2025         qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
2026
2027         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
2028
2029         qp_attr->max_dest_rd_atomic =
2030                 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
2031         qp_attr->min_rnr_timer      =
2032                 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
2033         qp_attr->timeout            = context.pri_path.ackto >> 3;
2034         qp_attr->retry_cnt          = (be32_to_cpu(context.params1) >> 16) & 0x7;
2035         qp_attr->rnr_retry          = (be32_to_cpu(context.params1) >> 13) & 0x7;
2036         qp_attr->alt_timeout        = context.alt_path.ackto >> 3;
2037
2038 done:
2039         qp_attr->cur_qp_state        = qp_attr->qp_state;
2040         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
2041         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
2042
2043         if (!ibqp->uobject) {
2044                 qp_attr->cap.max_send_wr  = qp->sq.wqe_cnt;
2045                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
2046         } else {
2047                 qp_attr->cap.max_send_wr  = 0;
2048                 qp_attr->cap.max_send_sge = 0;
2049         }
2050
2051         /*
2052          * We don't support inline sends for kernel QPs (yet), and we
2053          * don't know what userspace's value should be.
2054          */
2055         qp_attr->cap.max_inline_data = 0;
2056
2057         qp_init_attr->cap            = qp_attr->cap;
2058
2059         qp_init_attr->create_flags = 0;
2060         if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
2061                 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
2062
2063         if (qp->flags & MLX4_IB_QP_LSO)
2064                 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
2065
2066 out:
2067         mutex_unlock(&qp->mutex);
2068         return err;
2069 }
2070