2 * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved.
3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/pci.h>
35 #include <linux/netdevice.h>
36 #include <linux/vmalloc.h>
38 #include "ipath_kernel.h"
39 #include "ipath_common.h"
42 * min buffers we want to have per port, after driver
44 #define IPATH_MIN_USER_PORT_BUFCNT 8
47 * Number of ports we are configured to use (to allow for more pio
48 * buffers per port, etc.) Zero means use chip value.
50 static ushort ipath_cfgports;
52 module_param_named(cfgports, ipath_cfgports, ushort, S_IRUGO);
53 MODULE_PARM_DESC(cfgports, "Set max number of ports to use");
56 * Number of buffers reserved for driver (verbs and layered drivers.)
57 * Reserved at end of buffer list. Initialized based on
58 * number of PIO buffers if not set via module interface.
59 * The problem with this is that it's global, but we'll use different
60 * numbers for different chip types. So the default value is not
61 * very useful. I've redefined it for the 1.3 release so that it's
62 * zero unless set by the user to something else, in which case we
65 static ushort ipath_kpiobufs;
67 static int ipath_set_kpiobufs(const char *val, struct kernel_param *kp);
69 module_param_call(kpiobufs, ipath_set_kpiobufs, param_get_ushort,
70 &ipath_kpiobufs, S_IWUSR | S_IRUGO);
71 MODULE_PARM_DESC(kpiobufs, "Set number of PIO buffers for driver");
74 * create_port0_egr - allocate the eager TID buffers
75 * @dd: the infinipath device
77 * This code is now quite different for user and kernel, because
78 * the kernel uses skb's, for the accelerated network performance.
79 * This is the kernel (port0) version.
81 * Allocate the eager TID buffers and program them into infinipath.
82 * We use the network layer alloc_skb() allocator to allocate the
83 * memory, and either use the buffers as is for things like verbs
84 * packets, or pass the buffers up to the ipath layered driver and
85 * thence the network layer, replacing them as we do so (see
88 static int create_port0_egr(struct ipath_devdata *dd)
91 struct ipath_skbinfo *skbinfo;
94 egrcnt = dd->ipath_p0_rcvegrcnt;
96 skbinfo = vmalloc(sizeof(*dd->ipath_port0_skbinfo) * egrcnt);
97 if (skbinfo == NULL) {
98 ipath_dev_err(dd, "allocation error for eager TID "
103 for (e = 0; e < egrcnt; e++) {
105 * This is a bit tricky in that we allocate extra
106 * space for 2 bytes of the 14 byte ethernet header.
107 * These two bytes are passed in the ipath header so
108 * the rest of the data is word aligned. We allocate
109 * 4 bytes so that the data buffer stays word aligned.
110 * See ipath_kreceive() for more details.
112 skbinfo[e].skb = ipath_alloc_skb(dd, GFP_KERNEL);
113 if (!skbinfo[e].skb) {
114 ipath_dev_err(dd, "SKB allocation error for "
115 "eager TID %u\n", e);
117 dev_kfree_skb(skbinfo[--e].skb);
124 * After loop above, so we can test non-NULL to see if ready
125 * to use at receive, etc.
127 dd->ipath_port0_skbinfo = skbinfo;
129 for (e = 0; e < egrcnt; e++) {
130 dd->ipath_port0_skbinfo[e].phys =
131 ipath_map_single(dd->pcidev,
132 dd->ipath_port0_skbinfo[e].skb->data,
133 dd->ipath_ibmaxlen, PCI_DMA_FROMDEVICE);
134 dd->ipath_f_put_tid(dd, e + (u64 __iomem *)
135 ((char __iomem *) dd->ipath_kregbase +
136 dd->ipath_rcvegrbase),
137 RCVHQ_RCV_TYPE_EAGER,
138 dd->ipath_port0_skbinfo[e].phys);
147 static int bringup_link(struct ipath_devdata *dd)
152 /* hold IBC in reset */
153 dd->ipath_control &= ~INFINIPATH_C_LINKENABLE;
154 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
158 * Note that prior to try 14 or 15 of IB, the credit scaling
159 * wasn't working, because it was swapped for writes with the
160 * 1 bit default linkstate field
163 /* ignore pbc and align word */
164 val = dd->ipath_piosize2k - 2 * sizeof(u32);
166 * for ICRC, which we only send in diag test pkt mode, and we
167 * don't need to worry about that for mtu
171 * Set the IBC maxpktlength to the size of our pio buffers the
172 * maxpktlength is in words. This is *not* the IB data MTU.
174 ibc = (val / sizeof(u32)) << INFINIPATH_IBCC_MAXPKTLEN_SHIFT;
176 ibc |= 0x5ULL << INFINIPATH_IBCC_FLOWCTRLWATERMARK_SHIFT;
178 * How often flowctrl sent. More or less in usecs; balance against
179 * watermark value, so that in theory senders always get a flow
180 * control update in time to not let the IB link go idle.
182 ibc |= 0x3ULL << INFINIPATH_IBCC_FLOWCTRLPERIOD_SHIFT;
183 /* max error tolerance */
184 ibc |= 0xfULL << INFINIPATH_IBCC_PHYERRTHRESHOLD_SHIFT;
185 /* use "real" buffer space for */
186 ibc |= 4ULL << INFINIPATH_IBCC_CREDITSCALE_SHIFT;
187 /* IB credit flow control. */
188 ibc |= 0xfULL << INFINIPATH_IBCC_OVERRUNTHRESHOLD_SHIFT;
189 /* initially come up waiting for TS1, without sending anything. */
190 dd->ipath_ibcctrl = ibc;
192 * Want to start out with both LINKCMD and LINKINITCMD in NOP
193 * (0 and 0). Don't put linkinitcmd in ipath_ibcctrl, want that
196 ibc |= INFINIPATH_IBCC_LINKINITCMD_DISABLE <<
197 INFINIPATH_IBCC_LINKINITCMD_SHIFT;
198 ipath_cdbg(VERBOSE, "Writing 0x%llx to ibcctrl\n",
199 (unsigned long long) ibc);
200 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl, ibc);
202 // be sure chip saw it
203 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
205 ret = dd->ipath_f_bringup_serdes(dd);
208 dev_info(&dd->pcidev->dev, "Could not initialize SerDes, "
212 dd->ipath_control |= INFINIPATH_C_LINKENABLE;
213 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
220 static struct ipath_portdata *create_portdata0(struct ipath_devdata *dd)
222 struct ipath_portdata *pd = NULL;
224 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
228 /* The port 0 pkey table is used by the layer interface. */
229 pd->port_pkeys[0] = IPATH_DEFAULT_P_KEY;
234 static int init_chip_first(struct ipath_devdata *dd,
235 struct ipath_portdata **pdp)
237 struct ipath_portdata *pd = NULL;
242 * skip cfgports stuff because we are not allocating memory,
243 * and we don't want problems if the portcnt changed due to
244 * cfgports. We do still check and report a difference, if
245 * not same (should be impossible).
247 dd->ipath_f_config_ports(dd, ipath_cfgports);
249 dd->ipath_cfgports = dd->ipath_portcnt;
250 else if (ipath_cfgports <= dd->ipath_portcnt) {
251 dd->ipath_cfgports = ipath_cfgports;
252 ipath_dbg("Configured to use %u ports out of %u in chip\n",
253 dd->ipath_cfgports, dd->ipath_portcnt);
255 dd->ipath_cfgports = dd->ipath_portcnt;
256 ipath_dbg("Tried to configured to use %u ports; chip "
257 "only supports %u\n", ipath_cfgports,
261 * Allocate full portcnt array, rather than just cfgports, because
262 * cleanup iterates across all possible ports.
264 dd->ipath_pd = kzalloc(sizeof(*dd->ipath_pd) * dd->ipath_portcnt,
268 ipath_dev_err(dd, "Unable to allocate portdata array, "
274 pd = create_portdata0(dd);
276 ipath_dev_err(dd, "Unable to allocate portdata for port "
281 dd->ipath_pd[0] = pd;
283 dd->ipath_rcvtidcnt =
284 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidcnt);
285 dd->ipath_rcvtidbase =
286 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidbase);
287 dd->ipath_rcvegrcnt =
288 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt);
289 dd->ipath_rcvegrbase =
290 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrbase);
292 ipath_read_kreg32(dd, dd->ipath_kregs->kr_pagealign);
293 dd->ipath_piobufbase =
294 ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiobufbase);
295 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiosize);
296 dd->ipath_piosize2k = val & ~0U;
297 dd->ipath_piosize4k = val >> 32;
299 * Note: the chips support a maximum MTU of 4096, but the driver
300 * hasn't implemented this feature yet, so set the initial value
303 dd->ipath_ibmtu = 2048;
304 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiobufcnt);
305 dd->ipath_piobcnt2k = val & ~0U;
306 dd->ipath_piobcnt4k = val >> 32;
307 dd->ipath_pio2kbase =
308 (u32 __iomem *) (((char __iomem *) dd->ipath_kregbase) +
309 (dd->ipath_piobufbase & 0xffffffff));
310 if (dd->ipath_piobcnt4k) {
311 dd->ipath_pio4kbase = (u32 __iomem *)
312 (((char __iomem *) dd->ipath_kregbase) +
313 (dd->ipath_piobufbase >> 32));
315 * 4K buffers take 2 pages; we use roundup just to be
316 * paranoid; we calculate it once here, rather than on
319 dd->ipath_4kalign = ALIGN(dd->ipath_piosize4k,
321 ipath_dbg("%u 2k(%x) piobufs @ %p, %u 4k(%x) @ %p "
323 dd->ipath_piobcnt2k, dd->ipath_piosize2k,
324 dd->ipath_pio2kbase, dd->ipath_piobcnt4k,
325 dd->ipath_piosize4k, dd->ipath_pio4kbase,
328 else ipath_dbg("%u 2k piobufs @ %p\n",
329 dd->ipath_piobcnt2k, dd->ipath_pio2kbase);
331 spin_lock_init(&dd->ipath_tid_lock);
332 spin_lock_init(&dd->ipath_sendctrl_lock);
333 spin_lock_init(&dd->ipath_gpio_lock);
334 spin_lock_init(&dd->ipath_eep_st_lock);
335 mutex_init(&dd->ipath_eep_lock);
343 * init_chip_reset - re-initialize after a reset, or enable
344 * @dd: the infinipath device
345 * @pdp: output for port data
347 * sanity check at least some of the values after reset, and
348 * ensure no receive or transmit (explictly, in case reset
351 static int init_chip_reset(struct ipath_devdata *dd,
352 struct ipath_portdata **pdp)
356 *pdp = dd->ipath_pd[0];
357 /* ensure chip does no sends or receives while we re-initialize */
358 dd->ipath_control = dd->ipath_sendctrl = dd->ipath_rcvctrl = 0U;
359 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl, dd->ipath_rcvctrl);
360 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
361 ipath_write_kreg(dd, dd->ipath_kregs->kr_control, dd->ipath_control);
363 rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_portcnt);
364 if (dd->ipath_portcnt != rtmp)
365 dev_info(&dd->pcidev->dev, "portcnt was %u before "
366 "reset, now %u, using original\n",
367 dd->ipath_portcnt, rtmp);
368 rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidcnt);
369 if (rtmp != dd->ipath_rcvtidcnt)
370 dev_info(&dd->pcidev->dev, "tidcnt was %u before "
371 "reset, now %u, using original\n",
372 dd->ipath_rcvtidcnt, rtmp);
373 rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidbase);
374 if (rtmp != dd->ipath_rcvtidbase)
375 dev_info(&dd->pcidev->dev, "tidbase was %u before "
376 "reset, now %u, using original\n",
377 dd->ipath_rcvtidbase, rtmp);
378 rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt);
379 if (rtmp != dd->ipath_rcvegrcnt)
380 dev_info(&dd->pcidev->dev, "egrcnt was %u before "
381 "reset, now %u, using original\n",
382 dd->ipath_rcvegrcnt, rtmp);
383 rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrbase);
384 if (rtmp != dd->ipath_rcvegrbase)
385 dev_info(&dd->pcidev->dev, "egrbase was %u before "
386 "reset, now %u, using original\n",
387 dd->ipath_rcvegrbase, rtmp);
392 static int init_pioavailregs(struct ipath_devdata *dd)
396 dd->ipath_pioavailregs_dma = dma_alloc_coherent(
397 &dd->pcidev->dev, PAGE_SIZE, &dd->ipath_pioavailregs_phys,
399 if (!dd->ipath_pioavailregs_dma) {
400 ipath_dev_err(dd, "failed to allocate PIOavail reg area "
407 * we really want L2 cache aligned, but for current CPUs of
408 * interest, they are the same.
410 dd->ipath_statusp = (u64 *)
411 ((char *)dd->ipath_pioavailregs_dma +
412 ((2 * L1_CACHE_BYTES +
413 dd->ipath_pioavregs * sizeof(u64)) & ~L1_CACHE_BYTES));
414 /* copy the current value now that it's really allocated */
415 *dd->ipath_statusp = dd->_ipath_status;
417 * setup buffer to hold freeze msg, accessible to apps,
420 dd->ipath_freezemsg = (char *)&dd->ipath_statusp[1];
422 dd->ipath_freezelen = L1_CACHE_BYTES - sizeof(dd->ipath_statusp[0]);
431 * init_shadow_tids - allocate the shadow TID array
432 * @dd: the infinipath device
434 * allocate the shadow TID array, so we can ipath_munlock previous
435 * entries. It may make more sense to move the pageshadow to the
436 * port data structure, so we only allocate memory for ports actually
437 * in use, since we at 8k per port, now.
439 static void init_shadow_tids(struct ipath_devdata *dd)
444 pages = vmalloc(dd->ipath_cfgports * dd->ipath_rcvtidcnt *
445 sizeof(struct page *));
447 ipath_dev_err(dd, "failed to allocate shadow page * "
448 "array, no expected sends!\n");
449 dd->ipath_pageshadow = NULL;
453 addrs = vmalloc(dd->ipath_cfgports * dd->ipath_rcvtidcnt *
456 ipath_dev_err(dd, "failed to allocate shadow dma handle "
457 "array, no expected sends!\n");
458 vfree(dd->ipath_pageshadow);
459 dd->ipath_pageshadow = NULL;
463 memset(pages, 0, dd->ipath_cfgports * dd->ipath_rcvtidcnt *
464 sizeof(struct page *));
466 dd->ipath_pageshadow = pages;
467 dd->ipath_physshadow = addrs;
470 static void enable_chip(struct ipath_devdata *dd,
471 struct ipath_portdata *pd, int reinit)
478 init_waitqueue_head(&ipath_state_wait);
480 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
483 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
484 /* Enable PIO send, and update of PIOavail regs to memory. */
485 dd->ipath_sendctrl = INFINIPATH_S_PIOENABLE |
486 INFINIPATH_S_PIOBUFAVAILUPD;
487 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
488 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
489 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
492 * enable port 0 receive, and receive interrupt. other ports
493 * done as user opens and inits them.
495 dd->ipath_rcvctrl = (1ULL << dd->ipath_r_tailupd_shift) |
496 (1ULL << dd->ipath_r_portenable_shift) |
497 (1ULL << dd->ipath_r_intravail_shift);
498 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
502 * now ready for use. this should be cleared whenever we
503 * detect a reset, or initiate one.
505 dd->ipath_flags |= IPATH_INITTED;
508 * init our shadow copies of head from tail values, and write
509 * head values to match.
511 val = ipath_read_ureg32(dd, ur_rcvegrindextail, 0);
512 (void)ipath_write_ureg(dd, ur_rcvegrindexhead, val, 0);
514 /* Initialize so we interrupt on next packet received */
515 (void)ipath_write_ureg(dd, ur_rcvhdrhead,
516 dd->ipath_rhdrhead_intr_off |
517 dd->ipath_pd[0]->port_head, 0);
520 * by now pioavail updates to memory should have occurred, so
521 * copy them into our working/shadow registers; this is in
522 * case something went wrong with abort, but mostly to get the
523 * initial values of the generation bit correct.
525 for (i = 0; i < dd->ipath_pioavregs; i++) {
529 * Chip Errata bug 6641; even and odd qwords>3 are swapped.
533 val = dd->ipath_pioavailregs_dma[i - 1];
535 val = dd->ipath_pioavailregs_dma[i + 1];
538 val = dd->ipath_pioavailregs_dma[i];
539 dd->ipath_pioavailshadow[i] = le64_to_cpu(val);
541 /* can get counters, stats, etc. */
542 dd->ipath_flags |= IPATH_PRESENT;
545 static int init_housekeeping(struct ipath_devdata *dd,
546 struct ipath_portdata **pdp, int reinit)
552 * have to clear shadow copies of registers at init that are
553 * not otherwise set here, or all kinds of bizarre things
554 * happen with driver on chip reset
556 dd->ipath_rcvhdrsize = 0;
559 * Don't clear ipath_flags as 8bit mode was set before
560 * entering this func. However, we do set the linkstate to
561 * unknown, so we can watch for a transition.
562 * PRESENT is set because we want register reads to work,
563 * and the kernel infrastructure saw it in config space;
564 * We clear it if we have failures.
566 dd->ipath_flags |= IPATH_LINKUNK | IPATH_PRESENT;
567 dd->ipath_flags &= ~(IPATH_LINKACTIVE | IPATH_LINKARMED |
568 IPATH_LINKDOWN | IPATH_LINKINIT);
570 ipath_cdbg(VERBOSE, "Try to read spc chip revision\n");
572 ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision);
575 * set up fundamental info we need to use the chip; we assume
576 * if the revision reg and these regs are OK, we don't need to
577 * special case the rest
580 ipath_read_kreg32(dd, dd->ipath_kregs->kr_sendregbase);
582 ipath_read_kreg32(dd, dd->ipath_kregs->kr_counterregbase);
584 ipath_read_kreg32(dd, dd->ipath_kregs->kr_userregbase);
585 ipath_cdbg(VERBOSE, "ipath_kregbase %p, sendbase %x usrbase %x, "
586 "cntrbase %x\n", dd->ipath_kregbase, dd->ipath_sregbase,
587 dd->ipath_uregbase, dd->ipath_cregbase);
588 if ((dd->ipath_revision & 0xffffffff) == 0xffffffff
589 || (dd->ipath_sregbase & 0xffffffff) == 0xffffffff
590 || (dd->ipath_cregbase & 0xffffffff) == 0xffffffff
591 || (dd->ipath_uregbase & 0xffffffff) == 0xffffffff) {
592 ipath_dev_err(dd, "Register read failures from chip, "
593 "giving up initialization\n");
594 dd->ipath_flags &= ~IPATH_PRESENT;
600 /* clear diagctrl register, in case diags were running and crashed */
601 ipath_write_kreg (dd, dd->ipath_kregs->kr_hwdiagctrl, 0);
603 /* clear the initial reset flag, in case first driver load */
604 ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear,
608 ret = init_chip_reset(dd, pdp);
610 ret = init_chip_first(dd, pdp);
615 ipath_cdbg(VERBOSE, "Revision %llx (PCI %x), %u ports, %u tids, "
616 "%u egrtids\n", (unsigned long long) dd->ipath_revision,
617 dd->ipath_pcirev, dd->ipath_portcnt, dd->ipath_rcvtidcnt,
618 dd->ipath_rcvegrcnt);
620 if (((dd->ipath_revision >> INFINIPATH_R_SOFTWARE_SHIFT) &
621 INFINIPATH_R_SOFTWARE_MASK) != IPATH_CHIP_SWVERSION) {
622 ipath_dev_err(dd, "Driver only handles version %d, "
623 "chip swversion is %d (%llx), failng\n",
624 IPATH_CHIP_SWVERSION,
625 (int)(dd->ipath_revision >>
626 INFINIPATH_R_SOFTWARE_SHIFT) &
627 INFINIPATH_R_SOFTWARE_MASK,
628 (unsigned long long) dd->ipath_revision);
632 dd->ipath_majrev = (u8) ((dd->ipath_revision >>
633 INFINIPATH_R_CHIPREVMAJOR_SHIFT) &
634 INFINIPATH_R_CHIPREVMAJOR_MASK);
635 dd->ipath_minrev = (u8) ((dd->ipath_revision >>
636 INFINIPATH_R_CHIPREVMINOR_SHIFT) &
637 INFINIPATH_R_CHIPREVMINOR_MASK);
638 dd->ipath_boardrev = (u8) ((dd->ipath_revision >>
639 INFINIPATH_R_BOARDID_SHIFT) &
640 INFINIPATH_R_BOARDID_MASK);
642 ret = dd->ipath_f_get_boardname(dd, boardn, sizeof boardn);
644 snprintf(dd->ipath_boardversion, sizeof(dd->ipath_boardversion),
645 "ChipABI %u.%u, %s, InfiniPath%u %u.%u, PCI %u, "
647 IPATH_CHIP_VERS_MAJ, IPATH_CHIP_VERS_MIN, boardn,
648 (unsigned)(dd->ipath_revision >> INFINIPATH_R_ARCH_SHIFT) &
649 INFINIPATH_R_ARCH_MASK,
650 dd->ipath_majrev, dd->ipath_minrev, dd->ipath_pcirev,
651 (unsigned)(dd->ipath_revision >>
652 INFINIPATH_R_SOFTWARE_SHIFT) &
653 INFINIPATH_R_SOFTWARE_MASK);
655 ipath_dbg("%s", dd->ipath_boardversion);
663 * ipath_init_chip - do the actual initialization sequence on the chip
664 * @dd: the infinipath device
665 * @reinit: reinitializing, so don't allocate new memory
667 * Do the actual initialization sequence on the chip. This is done
668 * both from the init routine called from the PCI infrastructure, and
669 * when we reset the chip, or detect that it was reset internally,
670 * or it's administratively re-enabled.
672 * Memory allocation here and in called routines is only done in
673 * the first case (reinit == 0). We have to be careful, because even
674 * without memory allocation, we need to re-write all the chip registers
675 * TIDs, etc. after the reset or enable has completed.
677 int ipath_init_chip(struct ipath_devdata *dd, int reinit)
683 struct ipath_portdata *pd = NULL; /* keep gcc4 happy */
684 gfp_t gfp_flags = GFP_USER | __GFP_COMP;
687 ret = init_housekeeping(dd, &pd, reinit);
692 * we ignore most issues after reporting them, but have to specially
693 * handle hardware-disabled chips.
696 /* unique error, known to ipath_init_one */
702 * We could bump this to allow for full rcvegrcnt + rcvtidcnt,
703 * but then it no longer nicely fits power of two, and since
704 * we now use routines that backend onto __get_free_pages, the
705 * rest would be wasted.
707 dd->ipath_rcvhdrcnt = dd->ipath_rcvegrcnt;
708 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrcnt,
709 dd->ipath_rcvhdrcnt);
712 * Set up the shadow copies of the piobufavail registers,
713 * which we compare against the chip registers for now, and
714 * the in memory DMA'ed copies of the registers. This has to
715 * be done early, before we calculate lastport, etc.
717 piobufs = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k;
719 * calc number of pioavail registers, and save it; we have 2
722 dd->ipath_pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2)
723 / (sizeof(u64) * BITS_PER_BYTE / 2);
724 uports = dd->ipath_cfgports ? dd->ipath_cfgports - 1 : 0;
725 if (ipath_kpiobufs == 0) {
726 /* not set by user (this is default) */
733 kpiobufs = ipath_kpiobufs;
735 if (kpiobufs + (uports * IPATH_MIN_USER_PORT_BUFCNT) > piobufs) {
736 int i = (int) piobufs -
737 (int) (uports * IPATH_MIN_USER_PORT_BUFCNT);
740 dev_info(&dd->pcidev->dev, "Allocating %d PIO bufs of "
741 "%d for kernel leaves too few for %d user ports "
742 "(%d each); using %u\n", kpiobufs,
743 piobufs, uports, IPATH_MIN_USER_PORT_BUFCNT, i);
745 * shouldn't change ipath_kpiobufs, because could be
746 * different for different devices...
750 dd->ipath_lastport_piobuf = piobufs - kpiobufs;
751 dd->ipath_pbufsport =
752 uports ? dd->ipath_lastport_piobuf / uports : 0;
753 val32 = dd->ipath_lastport_piobuf - (dd->ipath_pbufsport * uports);
755 ipath_dbg("allocating %u pbufs/port leaves %u unused, "
756 "add to kernel\n", dd->ipath_pbufsport, val32);
757 dd->ipath_lastport_piobuf -= val32;
758 ipath_dbg("%u pbufs/port leaves %u unused, add to kernel\n",
759 dd->ipath_pbufsport, val32);
761 dd->ipath_lastpioindex = dd->ipath_lastport_piobuf;
762 ipath_cdbg(VERBOSE, "%d PIO bufs for kernel out of %d total %u "
763 "each for %u user ports\n", kpiobufs,
764 piobufs, dd->ipath_pbufsport, uports);
766 dd->ipath_f_early_init(dd);
768 * cancel any possible active sends from early driver load.
769 * Follows early_init because some chips have to initialize
770 * PIO buffers in early_init to avoid false parity errors.
772 ipath_cancel_sends(dd, 0);
774 /* early_init sets rcvhdrentsize and rcvhdrsize, so this must be
775 * done after early_init */
777 dd->ipath_rcvhdrentsize * (dd->ipath_rcvhdrcnt - 1);
778 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrentsize,
779 dd->ipath_rcvhdrentsize);
780 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrsize,
781 dd->ipath_rcvhdrsize);
784 ret = init_pioavailregs(dd);
785 init_shadow_tids(dd);
790 (void)ipath_write_kreg(dd, dd->ipath_kregs->kr_sendpioavailaddr,
791 dd->ipath_pioavailregs_phys);
793 * this is to detect s/w errors, which the h/w works around by
794 * ignoring the low 6 bits of address, if it wasn't aligned.
796 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpioavailaddr);
797 if (val != dd->ipath_pioavailregs_phys) {
798 ipath_dev_err(dd, "Catastrophic software error, "
799 "SendPIOAvailAddr written as %lx, "
800 "read back as %llx\n",
801 (unsigned long) dd->ipath_pioavailregs_phys,
802 (unsigned long long) val);
807 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvbthqp, IPATH_KD_QP);
810 * make sure we are not in freeze, and PIO send enabled, so
811 * writes to pbc happen
813 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask, 0ULL);
814 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
815 ~0ULL&~INFINIPATH_HWE_MEMBISTFAILED);
816 ipath_write_kreg(dd, dd->ipath_kregs->kr_control, 0ULL);
818 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
819 dd->ipath_sendctrl = INFINIPATH_S_PIOENABLE;
820 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
821 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
822 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
825 * before error clears, since we expect serdes pll errors during
826 * this, the first time after reset
828 if (bringup_link(dd)) {
829 dev_info(&dd->pcidev->dev, "Failed to bringup IB link\n");
835 * clear any "expected" hwerrs from reset and/or initialization
836 * clear any that aren't enabled (at least this once), and then
837 * set the enable mask
839 dd->ipath_f_init_hwerrors(dd);
840 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
841 ~0ULL&~INFINIPATH_HWE_MEMBISTFAILED);
842 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
843 dd->ipath_hwerrmask);
846 ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, -1LL);
847 /* enable errors that are masked, at least this first time. */
848 ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
849 ~dd->ipath_maskederrs);
850 dd->ipath_errormask = ipath_read_kreg64(dd,
851 dd->ipath_kregs->kr_errormask);
852 /* clear any interrupts up to this point (ints still not enabled) */
853 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, -1LL);
856 * Set up the port 0 (kernel) rcvhdr q and egr TIDs. If doing
857 * re-init, the simplest way to handle this is to free
858 * existing, and re-allocate.
859 * Need to re-create rest of port 0 portdata as well.
862 /* Alloc and init new ipath_portdata for port0,
863 * Then free old pd. Could lead to fragmentation, but also
864 * makes later support for hot-swap easier.
866 struct ipath_portdata *npd;
867 npd = create_portdata0(dd);
869 ipath_free_pddata(dd, pd);
870 dd->ipath_pd[0] = pd = npd;
872 ipath_dev_err(dd, "Unable to allocate portdata for"
873 " port 0, failing\n");
878 dd->ipath_f_tidtemplate(dd);
879 ret = ipath_create_rcvhdrq(dd, pd);
881 dd->ipath_hdrqtailptr =
882 (volatile __le64 *)pd->port_rcvhdrtail_kvaddr;
883 ret = create_port0_egr(dd);
886 ipath_dev_err(dd, "failed to allocate port 0 (kernel) "
887 "rcvhdrq and/or egr bufs\n");
889 enable_chip(dd, pd, reinit);
892 if (!ret && !reinit) {
893 /* used when we close a port, for DMA already in flight at close */
894 dd->ipath_dummy_hdrq = dma_alloc_coherent(
895 &dd->pcidev->dev, pd->port_rcvhdrq_size,
896 &dd->ipath_dummy_hdrq_phys,
898 if (!dd->ipath_dummy_hdrq ) {
899 dev_info(&dd->pcidev->dev,
900 "Couldn't allocate 0x%lx bytes for dummy hdrq\n",
901 pd->port_rcvhdrq_size);
902 /* fallback to just 0'ing */
903 dd->ipath_dummy_hdrq_phys = 0UL;
908 * cause retrigger of pending interrupts ignored during init,
909 * even if we had errors
911 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, 0ULL);
913 if(!dd->ipath_stats_timer_active) {
915 * first init, or after an admin disable/enable
916 * set up stats retrieval timer, even if we had errors
917 * in last portion of setup
919 init_timer(&dd->ipath_stats_timer);
920 dd->ipath_stats_timer.function = ipath_get_faststats;
921 dd->ipath_stats_timer.data = (unsigned long) dd;
922 /* every 5 seconds; */
923 dd->ipath_stats_timer.expires = jiffies + 5 * HZ;
924 /* takes ~16 seconds to overflow at full IB 4x bandwdith */
925 add_timer(&dd->ipath_stats_timer);
926 dd->ipath_stats_timer_active = 1;
931 *dd->ipath_statusp |= IPATH_STATUS_CHIP_PRESENT;
932 if (!dd->ipath_f_intrsetup(dd)) {
933 /* now we can enable all interrupts from the chip */
934 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask,
936 /* force re-interrupt of any pending interrupts. */
937 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear,
939 /* chip is usable; mark it as initialized */
940 *dd->ipath_statusp |= IPATH_STATUS_INITTED;
942 ipath_dev_err(dd, "No interrupts enabled, couldn't "
943 "setup interrupt address\n");
945 if (dd->ipath_cfgports > ipath_stats.sps_nports)
947 * sps_nports is a global, so, we set it to
948 * the highest number of ports of any of the
949 * chips we find; we never decrement it, at
950 * least for now. Since this might have changed
951 * over disable/enable or prior to reset, always
952 * do the check and potentially adjust.
954 ipath_stats.sps_nports = dd->ipath_cfgports;
956 ipath_dbg("Failed (%d) to initialize chip\n", ret);
958 /* if ret is non-zero, we probably should do some cleanup
963 static int ipath_set_kpiobufs(const char *str, struct kernel_param *kp)
965 struct ipath_devdata *dd;
970 ret = ipath_parse_ushort(str, &val);
972 spin_lock_irqsave(&ipath_devs_lock, flags);
982 list_for_each_entry(dd, &ipath_dev_list, ipath_list) {
983 if (dd->ipath_kregbase)
985 if (val > (dd->ipath_piobcnt2k + dd->ipath_piobcnt4k -
986 (dd->ipath_cfgports *
987 IPATH_MIN_USER_PORT_BUFCNT)))
991 "Allocating %d PIO bufs for kernel leaves "
992 "too few for %d user ports (%d each)\n",
993 val, dd->ipath_cfgports - 1,
994 IPATH_MIN_USER_PORT_BUFCNT);
998 dd->ipath_lastport_piobuf =
999 dd->ipath_piobcnt2k + dd->ipath_piobcnt4k - val;
1002 ipath_kpiobufs = val;
1005 spin_unlock_irqrestore(&ipath_devs_lock, flags);