drivers/infiniband/hw/ipath/ipath_init_chip.c

   1 /*
   2  * Copyright (c) 2006, 2007, 2008 QLogic Corporation. All rights reserved.
   3  * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 #include <linux/pci.h>
  35 #include <linux/netdevice.h>
  36 #include <linux/slab.h>
  37 #include <linux/stat.h>
  38 #include <linux/vmalloc.h>
  39
  40 #include "ipath_kernel.h"
  41 #include "ipath_common.h"
  42
  43 /*
  44  * min buffers we want to have per port, after driver
  45  */
  46 #define IPATH_MIN_USER_PORT_BUFCNT 7
  47
  48 /*
  49  * Number of ports we are configured to use (to allow for more pio
  50  * buffers per port, etc.)  Zero means use chip value.
  51  */
  52 static ushort ipath_cfgports;
  53
  54 module_param_named(cfgports, ipath_cfgports, ushort, S_IRUGO);
  55 MODULE_PARM_DESC(cfgports, "Set max number of ports to use");
  56
  57 /*
  58  * Number of buffers reserved for driver (verbs and layered drivers.)
  59  * Initialized based on number of PIO buffers if not set via module interface.
  60  * The problem with this is that it's global, but we'll use different
  61  * numbers for different chip types.
  62  */
  63 static ushort ipath_kpiobufs;
  64
  65 static int ipath_set_kpiobufs(const char *val, struct kernel_param *kp);
  66
  67 module_param_call(kpiobufs, ipath_set_kpiobufs, param_get_ushort,
  68                   &ipath_kpiobufs, S_IWUSR | S_IRUGO);
  69 MODULE_PARM_DESC(kpiobufs, "Set number of PIO buffers for driver");
  70
  71 /**
  72  * create_port0_egr - allocate the eager TID buffers
  73  * @dd: the infinipath device
  74  *
  75  * This code is now quite different for user and kernel, because
  76  * the kernel uses skb's, for the accelerated network performance.
  77  * This is the kernel (port0) version.
  78  *
  79  * Allocate the eager TID buffers and program them into infinipath.
  80  * We use the network layer alloc_skb() allocator to allocate the
  81  * memory, and either use the buffers as is for things like verbs
  82  * packets, or pass the buffers up to the ipath layered driver and
  83  * thence the network layer, replacing them as we do so (see
  84  * ipath_rcv_layer()).
  85  */
  86 static int create_port0_egr(struct ipath_devdata *dd)
  87 {
  88         unsigned e, egrcnt;
  89         struct ipath_skbinfo *skbinfo;
  90         int ret;
  91
  92         egrcnt = dd->ipath_p0_rcvegrcnt;
  93
  94         skbinfo = vmalloc(sizeof(*dd->ipath_port0_skbinfo) * egrcnt);
  95         if (skbinfo == NULL) {
  96                 ipath_dev_err(dd, "allocation error for eager TID "
  97                               "skb array\n");
  98                 ret = -ENOMEM;
  99                 goto bail;
 100         }
 101         for (e = 0; e < egrcnt; e++) {
 102                 /*
 103                  * This is a bit tricky in that we allocate extra
 104                  * space for 2 bytes of the 14 byte ethernet header.
 105                  * These two bytes are passed in the ipath header so
 106                  * the rest of the data is word aligned.  We allocate
 107                  * 4 bytes so that the data buffer stays word aligned.
 108                  * See ipath_kreceive() for more details.
 109                  */
 110                 skbinfo[e].skb = ipath_alloc_skb(dd, GFP_KERNEL);
 111                 if (!skbinfo[e].skb) {
 112                         ipath_dev_err(dd, "SKB allocation error for "
 113                                       "eager TID %u\n", e);
 114                         while (e != 0)
 115                                 dev_kfree_skb(skbinfo[--e].skb);
 116                         vfree(skbinfo);
 117                         ret = -ENOMEM;
 118                         goto bail;
 119                 }
 120         }
 121         /*
 122          * After loop above, so we can test non-NULL to see if ready
 123          * to use at receive, etc.
 124          */
 125         dd->ipath_port0_skbinfo = skbinfo;
 126
 127         for (e = 0; e < egrcnt; e++) {
 128                 dd->ipath_port0_skbinfo[e].phys =
 129                   ipath_map_single(dd->pcidev,
 130                                    dd->ipath_port0_skbinfo[e].skb->data,
 131                                    dd->ipath_ibmaxlen, PCI_DMA_FROMDEVICE);
 132                 dd->ipath_f_put_tid(dd, e + (u64 __iomem *)
 133                                     ((char __iomem *) dd->ipath_kregbase +
 134                                      dd->ipath_rcvegrbase),
 135                                     RCVHQ_RCV_TYPE_EAGER,
 136                                     dd->ipath_port0_skbinfo[e].phys);
 137         }
 138
 139         ret = 0;
 140
 141 bail:
 142         return ret;
 143 }
 144
 145 static int bringup_link(struct ipath_devdata *dd)
 146 {
 147         u64 val, ibc;
 148         int ret = 0;
 149
 150         /* hold IBC in reset */
 151         dd->ipath_control &= ~INFINIPATH_C_LINKENABLE;
 152         ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
 153                          dd->ipath_control);
 154
 155         /*
 156          * set initial max size pkt IBC will send, including ICRC; it's the
 157          * PIO buffer size in dwords, less 1; also see ipath_set_mtu()
 158          */
 159         val = (dd->ipath_ibmaxlen >> 2) + 1;
 160         ibc = val << dd->ibcc_mpl_shift;
 161
 162         /* flowcontrolwatermark is in units of KBytes */
 163         ibc |= 0x5ULL << INFINIPATH_IBCC_FLOWCTRLWATERMARK_SHIFT;
 164         /*
 165          * How often flowctrl sent.  More or less in usecs; balance against
 166          * watermark value, so that in theory senders always get a flow
 167          * control update in time to not let the IB link go idle.
 168          */
 169         ibc |= 0x3ULL << INFINIPATH_IBCC_FLOWCTRLPERIOD_SHIFT;
 170         /* max error tolerance */
 171         ibc |= 0xfULL << INFINIPATH_IBCC_PHYERRTHRESHOLD_SHIFT;
 172         /* use "real" buffer space for */
 173         ibc |= 4ULL << INFINIPATH_IBCC_CREDITSCALE_SHIFT;
 174         /* IB credit flow control. */
 175         ibc |= 0xfULL << INFINIPATH_IBCC_OVERRUNTHRESHOLD_SHIFT;
 176         /* initially come up waiting for TS1, without sending anything. */
 177         dd->ipath_ibcctrl = ibc;
 178         /*
 179          * Want to start out with both LINKCMD and LINKINITCMD in NOP
 180          * (0 and 0).  Don't put linkinitcmd in ipath_ibcctrl, want that
 181          * to stay a NOP. Flag that we are disabled, for the (unlikely)
 182          * case that some recovery path is trying to bring the link up
 183          * before we are ready.
 184          */
 185         ibc |= INFINIPATH_IBCC_LINKINITCMD_DISABLE <<
 186                 INFINIPATH_IBCC_LINKINITCMD_SHIFT;
 187         dd->ipath_flags |= IPATH_IB_LINK_DISABLED;
 188         ipath_cdbg(VERBOSE, "Writing 0x%llx to ibcctrl\n",
 189                    (unsigned long long) ibc);
 190         ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl, ibc);
 191
 192         // be sure chip saw it
 193         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 194
 195         ret = dd->ipath_f_bringup_serdes(dd);
 196
 197         if (ret)
 198                 dev_info(&dd->pcidev->dev, "Could not initialize SerDes, "
 199                          "not usable\n");
 200         else {
 201                 /* enable IBC */
 202                 dd->ipath_control |= INFINIPATH_C_LINKENABLE;
 203                 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
 204                                  dd->ipath_control);
 205         }
 206
 207         return ret;
 208 }
 209
 210 static struct ipath_portdata *create_portdata0(struct ipath_devdata *dd)
 211 {
 212         struct ipath_portdata *pd = NULL;
 213
 214         pd = kzalloc(sizeof(*pd), GFP_KERNEL);
 215         if (pd) {
 216                 pd->port_dd = dd;
 217                 pd->port_cnt = 1;
 218                 /* The port 0 pkey table is used by the layer interface. */
 219                 pd->port_pkeys[0] = IPATH_DEFAULT_P_KEY;
 220                 pd->port_seq_cnt = 1;
 221         }
 222         return pd;
 223 }
 224
 225 static int init_chip_first(struct ipath_devdata *dd)
 226 {
 227         struct ipath_portdata *pd;
 228         int ret = 0;
 229         u64 val;
 230
 231         spin_lock_init(&dd->ipath_kernel_tid_lock);
 232         spin_lock_init(&dd->ipath_user_tid_lock);
 233         spin_lock_init(&dd->ipath_sendctrl_lock);
 234         spin_lock_init(&dd->ipath_uctxt_lock);
 235         spin_lock_init(&dd->ipath_sdma_lock);
 236         spin_lock_init(&dd->ipath_gpio_lock);
 237         spin_lock_init(&dd->ipath_eep_st_lock);
 238         spin_lock_init(&dd->ipath_sdepb_lock);
 239         mutex_init(&dd->ipath_eep_lock);
 240
 241         /*
 242          * skip cfgports stuff because we are not allocating memory,
 243          * and we don't want problems if the portcnt changed due to
 244          * cfgports.  We do still check and report a difference, if
 245          * not same (should be impossible).
 246          */
 247         dd->ipath_f_config_ports(dd, ipath_cfgports);
 248         if (!ipath_cfgports)
 249                 dd->ipath_cfgports = dd->ipath_portcnt;
 250         else if (ipath_cfgports <= dd->ipath_portcnt) {
 251                 dd->ipath_cfgports = ipath_cfgports;
 252                 ipath_dbg("Configured to use %u ports out of %u in chip\n",
 253                           dd->ipath_cfgports, ipath_read_kreg32(dd,
 254                           dd->ipath_kregs->kr_portcnt));
 255         } else {
 256                 dd->ipath_cfgports = dd->ipath_portcnt;
 257                 ipath_dbg("Tried to configured to use %u ports; chip "
 258                           "only supports %u\n", ipath_cfgports,
 259                           ipath_read_kreg32(dd,
 260                                   dd->ipath_kregs->kr_portcnt));
 261         }
 262         /*
 263          * Allocate full portcnt array, rather than just cfgports, because
 264          * cleanup iterates across all possible ports.
 265          */
 266         dd->ipath_pd = kzalloc(sizeof(*dd->ipath_pd) * dd->ipath_portcnt,
 267                                GFP_KERNEL);
 268
 269         if (!dd->ipath_pd) {
 270                 ipath_dev_err(dd, "Unable to allocate portdata array, "
 271                               "failing\n");
 272                 ret = -ENOMEM;
 273                 goto done;
 274         }
 275
 276         pd = create_portdata0(dd);
 277         if (!pd) {
 278                 ipath_dev_err(dd, "Unable to allocate portdata for port "
 279                               "0, failing\n");
 280                 ret = -ENOMEM;
 281                 goto done;
 282         }
 283         dd->ipath_pd[0] = pd;
 284
 285         dd->ipath_rcvtidcnt =
 286                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidcnt);
 287         dd->ipath_rcvtidbase =
 288                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidbase);
 289         dd->ipath_rcvegrcnt =
 290                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt);
 291         dd->ipath_rcvegrbase =
 292                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrbase);
 293         dd->ipath_palign =
 294                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_pagealign);
 295         dd->ipath_piobufbase =
 296                 ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiobufbase);
 297         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiosize);
 298         dd->ipath_piosize2k = val & ~0U;
 299         dd->ipath_piosize4k = val >> 32;
 300         if (dd->ipath_piosize4k == 0 && ipath_mtu4096)
 301                 ipath_mtu4096 = 0; /* 4KB not supported by this chip */
 302         dd->ipath_ibmtu = ipath_mtu4096 ? 4096 : 2048;
 303         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiobufcnt);
 304         dd->ipath_piobcnt2k = val & ~0U;
 305         dd->ipath_piobcnt4k = val >> 32;
 306         dd->ipath_pio2kbase =
 307                 (u32 __iomem *) (((char __iomem *) dd->ipath_kregbase) +
 308                                  (dd->ipath_piobufbase & 0xffffffff));
 309         if (dd->ipath_piobcnt4k) {
 310                 dd->ipath_pio4kbase = (u32 __iomem *)
 311                         (((char __iomem *) dd->ipath_kregbase) +
 312                          (dd->ipath_piobufbase >> 32));
 313                 /*
 314                  * 4K buffers take 2 pages; we use roundup just to be
 315                  * paranoid; we calculate it once here, rather than on
 316                  * ever buf allocate
 317                  */
 318                 dd->ipath_4kalign = ALIGN(dd->ipath_piosize4k,
 319                                           dd->ipath_palign);
 320                 ipath_dbg("%u 2k(%x) piobufs @ %p, %u 4k(%x) @ %p "
 321                           "(%x aligned)\n",
 322                           dd->ipath_piobcnt2k, dd->ipath_piosize2k,
 323                           dd->ipath_pio2kbase, dd->ipath_piobcnt4k,
 324                           dd->ipath_piosize4k, dd->ipath_pio4kbase,
 325                           dd->ipath_4kalign);
 326         }
 327         else ipath_dbg("%u 2k piobufs @ %p\n",
 328                        dd->ipath_piobcnt2k, dd->ipath_pio2kbase);
 329
 330 done:
 331         return ret;
 332 }
 333
 334 /**
 335  * init_chip_reset - re-initialize after a reset, or enable
 336  * @dd: the infinipath device
 337  *
 338  * sanity check at least some of the values after reset, and
 339  * ensure no receive or transmit (explicitly, in case reset
 340  * failed
 341  */
 342 static int init_chip_reset(struct ipath_devdata *dd)
 343 {
 344         u32 rtmp;
 345         int i;
 346         unsigned long flags;
 347
 348         /*
 349          * ensure chip does no sends or receives, tail updates, or
 350          * pioavail updates while we re-initialize
 351          */
 352         dd->ipath_rcvctrl &= ~(1ULL << dd->ipath_r_tailupd_shift);
 353         for (i = 0; i < dd->ipath_portcnt; i++) {
 354                 clear_bit(dd->ipath_r_portenable_shift + i,
 355                           &dd->ipath_rcvctrl);
 356                 clear_bit(dd->ipath_r_intravail_shift + i,
 357                           &dd->ipath_rcvctrl);
 358         }
 359         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
 360                 dd->ipath_rcvctrl);
 361
 362         spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
 363         dd->ipath_sendctrl = 0U; /* no sdma, etc */
 364         ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
 365         ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 366         spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
 367
 368         ipath_write_kreg(dd, dd->ipath_kregs->kr_control, 0ULL);
 369
 370         rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidcnt);
 371         if (rtmp != dd->ipath_rcvtidcnt)
 372                 dev_info(&dd->pcidev->dev, "tidcnt was %u before "
 373                          "reset, now %u, using original\n",
 374                          dd->ipath_rcvtidcnt, rtmp);
 375         rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidbase);
 376         if (rtmp != dd->ipath_rcvtidbase)
 377                 dev_info(&dd->pcidev->dev, "tidbase was %u before "
 378                          "reset, now %u, using original\n",
 379                          dd->ipath_rcvtidbase, rtmp);
 380         rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt);
 381         if (rtmp != dd->ipath_rcvegrcnt)
 382                 dev_info(&dd->pcidev->dev, "egrcnt was %u before "
 383                          "reset, now %u, using original\n",
 384                          dd->ipath_rcvegrcnt, rtmp);
 385         rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrbase);
 386         if (rtmp != dd->ipath_rcvegrbase)
 387                 dev_info(&dd->pcidev->dev, "egrbase was %u before "
 388                          "reset, now %u, using original\n",
 389                          dd->ipath_rcvegrbase, rtmp);
 390
 391         return 0;
 392 }
 393
 394 static int init_pioavailregs(struct ipath_devdata *dd)
 395 {
 396         int ret;
 397
 398         dd->ipath_pioavailregs_dma = dma_alloc_coherent(
 399                 &dd->pcidev->dev, PAGE_SIZE, &dd->ipath_pioavailregs_phys,
 400                 GFP_KERNEL);
 401         if (!dd->ipath_pioavailregs_dma) {
 402                 ipath_dev_err(dd, "failed to allocate PIOavail reg area "
 403                               "in memory\n");
 404                 ret = -ENOMEM;
 405                 goto done;
 406         }
 407
 408         /*
 409          * we really want L2 cache aligned, but for current CPUs of
 410          * interest, they are the same.
 411          */
 412         dd->ipath_statusp = (u64 *)
 413                 ((char *)dd->ipath_pioavailregs_dma +
 414                  ((2 * L1_CACHE_BYTES +
 415                    dd->ipath_pioavregs * sizeof(u64)) & ~L1_CACHE_BYTES));
 416         /* copy the current value now that it's really allocated */
 417         *dd->ipath_statusp = dd->_ipath_status;
 418         /*
 419          * setup buffer to hold freeze msg, accessible to apps,
 420          * following statusp
 421          */
 422         dd->ipath_freezemsg = (char *)&dd->ipath_statusp[1];
 423         /* and its length */
 424         dd->ipath_freezelen = L1_CACHE_BYTES - sizeof(dd->ipath_statusp[0]);
 425
 426         ret = 0;
 427
 428 done:
 429         return ret;
 430 }
 431
 432 /**
 433  * init_shadow_tids - allocate the shadow TID array
 434  * @dd: the infinipath device
 435  *
 436  * allocate the shadow TID array, so we can ipath_munlock previous
 437  * entries.  It may make more sense to move the pageshadow to the
 438  * port data structure, so we only allocate memory for ports actually
 439  * in use, since we at 8k per port, now.
 440  */
 441 static void init_shadow_tids(struct ipath_devdata *dd)
 442 {
 443         struct page **pages;
 444         dma_addr_t *addrs;
 445
 446         pages = vzalloc(dd->ipath_cfgports * dd->ipath_rcvtidcnt *
 447                         sizeof(struct page *));
 448         if (!pages) {
 449                 ipath_dev_err(dd, "failed to allocate shadow page * "
 450                               "array, no expected sends!\n");
 451                 dd->ipath_pageshadow = NULL;
 452                 return;
 453         }
 454
 455         addrs = vmalloc(dd->ipath_cfgports * dd->ipath_rcvtidcnt *
 456                         sizeof(dma_addr_t));
 457         if (!addrs) {
 458                 ipath_dev_err(dd, "failed to allocate shadow dma handle "
 459                               "array, no expected sends!\n");
 460                 vfree(pages);
 461                 dd->ipath_pageshadow = NULL;
 462                 return;
 463         }
 464
 465         dd->ipath_pageshadow = pages;
 466         dd->ipath_physshadow = addrs;
 467 }
 468
 469 static void enable_chip(struct ipath_devdata *dd, int reinit)
 470 {
 471         u32 val;
 472         u64 rcvmask;
 473         unsigned long flags;
 474         int i;
 475
 476         if (!reinit)
 477                 init_waitqueue_head(&ipath_state_wait);
 478
 479         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
 480                          dd->ipath_rcvctrl);
 481
 482         spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
 483         /* Enable PIO send, and update of PIOavail regs to memory. */
 484         dd->ipath_sendctrl = INFINIPATH_S_PIOENABLE |
 485                 INFINIPATH_S_PIOBUFAVAILUPD;
 486
 487         /*
 488          * Set the PIO avail update threshold to host memory
 489          * on chips that support it.
 490          */
 491         if (dd->ipath_pioupd_thresh)
 492                 dd->ipath_sendctrl |= dd->ipath_pioupd_thresh
 493                         << INFINIPATH_S_UPDTHRESH_SHIFT;
 494         ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
 495         ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 496         spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
 497
 498         /*
 499          * Enable kernel ports' receive and receive interrupt.
 500          * Other ports done as user opens and inits them.
 501          */
 502         rcvmask = 1ULL;
 503         dd->ipath_rcvctrl |= (rcvmask << dd->ipath_r_portenable_shift) |
 504                 (rcvmask << dd->ipath_r_intravail_shift);
 505         if (!(dd->ipath_flags & IPATH_NODMA_RTAIL))
 506                 dd->ipath_rcvctrl |= (1ULL << dd->ipath_r_tailupd_shift);
 507
 508         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
 509                          dd->ipath_rcvctrl);
 510
 511         /*
 512          * now ready for use.  this should be cleared whenever we
 513          * detect a reset, or initiate one.
 514          */
 515         dd->ipath_flags |= IPATH_INITTED;
 516
 517         /*
 518          * Init our shadow copies of head from tail values,
 519          * and write head values to match.
 520          */
 521         val = ipath_read_ureg32(dd, ur_rcvegrindextail, 0);
 522         ipath_write_ureg(dd, ur_rcvegrindexhead, val, 0);
 523
 524         /* Initialize so we interrupt on next packet received */
 525         ipath_write_ureg(dd, ur_rcvhdrhead,
 526                          dd->ipath_rhdrhead_intr_off |
 527                          dd->ipath_pd[0]->port_head, 0);
 528
 529         /*
 530          * by now pioavail updates to memory should have occurred, so
 531          * copy them into our working/shadow registers; this is in
 532          * case something went wrong with abort, but mostly to get the
 533          * initial values of the generation bit correct.
 534          */
 535         for (i = 0; i < dd->ipath_pioavregs; i++) {
 536                 __le64 pioavail;
 537
 538                 /*
 539                  * Chip Errata bug 6641; even and odd qwords>3 are swapped.
 540                  */
 541                 if (i > 3 && (dd->ipath_flags & IPATH_SWAP_PIOBUFS))
 542                         pioavail = dd->ipath_pioavailregs_dma[i ^ 1];
 543                 else
 544                         pioavail = dd->ipath_pioavailregs_dma[i];
 545                 /*
 546                  * don't need to worry about ipath_pioavailkernel here
 547                  * because we will call ipath_chg_pioavailkernel() later
 548                  * in initialization, to busy out buffers as needed
 549                  */
 550                 dd->ipath_pioavailshadow[i] = le64_to_cpu(pioavail);
 551         }
 552         /* can get counters, stats, etc. */
 553         dd->ipath_flags |= IPATH_PRESENT;
 554 }
 555
 556 static int init_housekeeping(struct ipath_devdata *dd, int reinit)
 557 {
 558         char boardn[40];
 559         int ret = 0;
 560
 561         /*
 562          * have to clear shadow copies of registers at init that are
 563          * not otherwise set here, or all kinds of bizarre things
 564          * happen with driver on chip reset
 565          */
 566         dd->ipath_rcvhdrsize = 0;
 567
 568         /*
 569          * Don't clear ipath_flags as 8bit mode was set before
 570          * entering this func. However, we do set the linkstate to
 571          * unknown, so we can watch for a transition.
 572          * PRESENT is set because we want register reads to work,
 573          * and the kernel infrastructure saw it in config space;
 574          * We clear it if we have failures.
 575          */
 576         dd->ipath_flags |= IPATH_LINKUNK | IPATH_PRESENT;
 577         dd->ipath_flags &= ~(IPATH_LINKACTIVE | IPATH_LINKARMED |
 578                              IPATH_LINKDOWN | IPATH_LINKINIT);
 579
 580         ipath_cdbg(VERBOSE, "Try to read spc chip revision\n");
 581         dd->ipath_revision =
 582                 ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision);
 583
 584         /*
 585          * set up fundamental info we need to use the chip; we assume
 586          * if the revision reg and these regs are OK, we don't need to
 587          * special case the rest
 588          */
 589         dd->ipath_sregbase =
 590                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_sendregbase);
 591         dd->ipath_cregbase =
 592                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_counterregbase);
 593         dd->ipath_uregbase =
 594                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_userregbase);
 595         ipath_cdbg(VERBOSE, "ipath_kregbase %p, sendbase %x usrbase %x, "
 596                    "cntrbase %x\n", dd->ipath_kregbase, dd->ipath_sregbase,
 597                    dd->ipath_uregbase, dd->ipath_cregbase);
 598         if ((dd->ipath_revision & 0xffffffff) == 0xffffffff
 599             || (dd->ipath_sregbase & 0xffffffff) == 0xffffffff
 600             || (dd->ipath_cregbase & 0xffffffff) == 0xffffffff
 601             || (dd->ipath_uregbase & 0xffffffff) == 0xffffffff) {
 602                 ipath_dev_err(dd, "Register read failures from chip, "
 603                               "giving up initialization\n");
 604                 dd->ipath_flags &= ~IPATH_PRESENT;
 605                 ret = -ENODEV;
 606                 goto done;
 607         }
 608
 609
 610         /* clear diagctrl register, in case diags were running and crashed */
 611         ipath_write_kreg (dd, dd->ipath_kregs->kr_hwdiagctrl, 0);
 612
 613         /* clear the initial reset flag, in case first driver load */
 614         ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear,
 615                          INFINIPATH_E_RESET);
 616
 617         ipath_cdbg(VERBOSE, "Revision %llx (PCI %x)\n",
 618                    (unsigned long long) dd->ipath_revision,
 619                    dd->ipath_pcirev);
 620
 621         if (((dd->ipath_revision >> INFINIPATH_R_SOFTWARE_SHIFT) &
 622              INFINIPATH_R_SOFTWARE_MASK) != IPATH_CHIP_SWVERSION) {
 623                 ipath_dev_err(dd, "Driver only handles version %d, "
 624                               "chip swversion is %d (%llx), failng\n",
 625                               IPATH_CHIP_SWVERSION,
 626                               (int)(dd->ipath_revision >>
 627                                     INFINIPATH_R_SOFTWARE_SHIFT) &
 628                               INFINIPATH_R_SOFTWARE_MASK,
 629                               (unsigned long long) dd->ipath_revision);
 630                 ret = -ENOSYS;
 631                 goto done;
 632         }
 633         dd->ipath_majrev = (u8) ((dd->ipath_revision >>
 634                                   INFINIPATH_R_CHIPREVMAJOR_SHIFT) &
 635                                  INFINIPATH_R_CHIPREVMAJOR_MASK);
 636         dd->ipath_minrev = (u8) ((dd->ipath_revision >>
 637                                   INFINIPATH_R_CHIPREVMINOR_SHIFT) &
 638                                  INFINIPATH_R_CHIPREVMINOR_MASK);
 639         dd->ipath_boardrev = (u8) ((dd->ipath_revision >>
 640                                     INFINIPATH_R_BOARDID_SHIFT) &
 641                                    INFINIPATH_R_BOARDID_MASK);
 642
 643         ret = dd->ipath_f_get_boardname(dd, boardn, sizeof boardn);
 644
 645         snprintf(dd->ipath_boardversion, sizeof(dd->ipath_boardversion),
 646                  "ChipABI %u.%u, %s, InfiniPath%u %u.%u, PCI %u, "
 647                  "SW Compat %u\n",
 648                  IPATH_CHIP_VERS_MAJ, IPATH_CHIP_VERS_MIN, boardn,
 649                  (unsigned)(dd->ipath_revision >> INFINIPATH_R_ARCH_SHIFT) &
 650                  INFINIPATH_R_ARCH_MASK,
 651                  dd->ipath_majrev, dd->ipath_minrev, dd->ipath_pcirev,
 652                  (unsigned)(dd->ipath_revision >>
 653                             INFINIPATH_R_SOFTWARE_SHIFT) &
 654                  INFINIPATH_R_SOFTWARE_MASK);
 655
 656         ipath_dbg("%s", dd->ipath_boardversion);
 657
 658         if (ret)
 659                 goto done;
 660
 661         if (reinit)
 662                 ret = init_chip_reset(dd);
 663         else
 664                 ret = init_chip_first(dd);
 665
 666 done:
 667         return ret;
 668 }
 669
 670 static void verify_interrupt(unsigned long opaque)
 671 {
 672         struct ipath_devdata *dd = (struct ipath_devdata *) opaque;
 673
 674         if (!dd)
 675                 return; /* being torn down */
 676
 677         /*
 678          * If we don't have any interrupts, let the user know and
 679          * don't bother checking again.
 680          */
 681         if (dd->ipath_int_counter == 0) {
 682                 if (!dd->ipath_f_intr_fallback(dd))
 683                         dev_err(&dd->pcidev->dev, "No interrupts detected, "
 684                                 "not usable.\n");
 685                 else /* re-arm the timer to see if fallback works */
 686                         mod_timer(&dd->ipath_intrchk_timer, jiffies + HZ/2);
 687         } else
 688                 ipath_cdbg(VERBOSE, "%u interrupts at timer check\n",
 689                         dd->ipath_int_counter);
 690 }
 691
 692 /**
 693  * ipath_init_chip - do the actual initialization sequence on the chip
 694  * @dd: the infinipath device
 695  * @reinit: reinitializing, so don't allocate new memory
 696  *
 697  * Do the actual initialization sequence on the chip.  This is done
 698  * both from the init routine called from the PCI infrastructure, and
 699  * when we reset the chip, or detect that it was reset internally,
 700  * or it's administratively re-enabled.
 701  *
 702  * Memory allocation here and in called routines is only done in
 703  * the first case (reinit == 0).  We have to be careful, because even
 704  * without memory allocation, we need to re-write all the chip registers
 705  * TIDs, etc. after the reset or enable has completed.
 706  */
 707 int ipath_init_chip(struct ipath_devdata *dd, int reinit)
 708 {
 709         int ret = 0;
 710         u32 kpiobufs, defkbufs;
 711         u32 piobufs, uports;
 712         u64 val;
 713         struct ipath_portdata *pd;
 714         gfp_t gfp_flags = GFP_USER | __GFP_COMP;
 715
 716         ret = init_housekeeping(dd, reinit);
 717         if (ret)
 718                 goto done;
 719
 720         /*
 721          * we ignore most issues after reporting them, but have to specially
 722          * handle hardware-disabled chips.
 723          */
 724         if (ret == 2) {
 725                 /* unique error, known to ipath_init_one */
 726                 ret = -EPERM;
 727                 goto done;
 728         }
 729
 730         /*
 731          * We could bump this to allow for full rcvegrcnt + rcvtidcnt,
 732          * but then it no longer nicely fits power of two, and since
 733          * we now use routines that backend onto __get_free_pages, the
 734          * rest would be wasted.
 735          */
 736         dd->ipath_rcvhdrcnt = max(dd->ipath_p0_rcvegrcnt, dd->ipath_rcvegrcnt);
 737         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrcnt,
 738                          dd->ipath_rcvhdrcnt);
 739
 740         /*
 741          * Set up the shadow copies of the piobufavail registers,
 742          * which we compare against the chip registers for now, and
 743          * the in memory DMA'ed copies of the registers.  This has to
 744          * be done early, before we calculate lastport, etc.
 745          */
 746         piobufs = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k;
 747         /*
 748          * calc number of pioavail registers, and save it; we have 2
 749          * bits per buffer.
 750          */
 751         dd->ipath_pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2)
 752                 / (sizeof(u64) * BITS_PER_BYTE / 2);
 753         uports = dd->ipath_cfgports ? dd->ipath_cfgports - 1 : 0;
 754         if (piobufs > 144)
 755                 defkbufs = 32 + dd->ipath_pioreserved;
 756         else
 757                 defkbufs = 16 + dd->ipath_pioreserved;
 758
 759         if (ipath_kpiobufs && (ipath_kpiobufs +
 760                 (uports * IPATH_MIN_USER_PORT_BUFCNT)) > piobufs) {
 761                 int i = (int) piobufs -
 762                         (int) (uports * IPATH_MIN_USER_PORT_BUFCNT);
 763                 if (i < 1)
 764                         i = 1;
 765                 dev_info(&dd->pcidev->dev, "Allocating %d PIO bufs of "
 766                          "%d for kernel leaves too few for %d user ports "
 767                          "(%d each); using %u\n", ipath_kpiobufs,
 768                          piobufs, uports, IPATH_MIN_USER_PORT_BUFCNT, i);
 769                 /*
 770                  * shouldn't change ipath_kpiobufs, because could be
 771                  * different for different devices...
 772                  */
 773                 kpiobufs = i;
 774         } else if (ipath_kpiobufs)
 775                 kpiobufs = ipath_kpiobufs;
 776         else
 777                 kpiobufs = defkbufs;
 778         dd->ipath_lastport_piobuf = piobufs - kpiobufs;
 779         dd->ipath_pbufsport =
 780                 uports ? dd->ipath_lastport_piobuf / uports : 0;
 781         /* if not an even divisor, some user ports get extra buffers */
 782         dd->ipath_ports_extrabuf = dd->ipath_lastport_piobuf -
 783                 (dd->ipath_pbufsport * uports);
 784         if (dd->ipath_ports_extrabuf)
 785                 ipath_dbg("%u pbufs/port leaves some unused, add 1 buffer to "
 786                         "ports <= %u\n", dd->ipath_pbufsport,
 787                         dd->ipath_ports_extrabuf);
 788         dd->ipath_lastpioindex = 0;
 789         dd->ipath_lastpioindexl = dd->ipath_piobcnt2k;
 790         /* ipath_pioavailshadow initialized earlier */
 791         ipath_cdbg(VERBOSE, "%d PIO bufs for kernel out of %d total %u "
 792                    "each for %u user ports\n", kpiobufs,
 793                    piobufs, dd->ipath_pbufsport, uports);
 794         ret = dd->ipath_f_early_init(dd);
 795         if (ret) {
 796                 ipath_dev_err(dd, "Early initialization failure\n");
 797                 goto done;
 798         }
 799
 800         /*
 801          * Early_init sets rcvhdrentsize and rcvhdrsize, so this must be
 802          * done after early_init.
 803          */
 804         dd->ipath_hdrqlast =
 805                 dd->ipath_rcvhdrentsize * (dd->ipath_rcvhdrcnt - 1);
 806         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrentsize,
 807                          dd->ipath_rcvhdrentsize);
 808         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrsize,
 809                          dd->ipath_rcvhdrsize);
 810
 811         if (!reinit) {
 812                 ret = init_pioavailregs(dd);
 813                 init_shadow_tids(dd);
 814                 if (ret)
 815                         goto done;
 816         }
 817
 818         ipath_write_kreg(dd, dd->ipath_kregs->kr_sendpioavailaddr,
 819                          dd->ipath_pioavailregs_phys);
 820
 821         /*
 822          * this is to detect s/w errors, which the h/w works around by
 823          * ignoring the low 6 bits of address, if it wasn't aligned.
 824          */
 825         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpioavailaddr);
 826         if (val != dd->ipath_pioavailregs_phys) {
 827                 ipath_dev_err(dd, "Catastrophic software error, "
 828                               "SendPIOAvailAddr written as %lx, "
 829                               "read back as %llx\n",
 830                               (unsigned long) dd->ipath_pioavailregs_phys,
 831                               (unsigned long long) val);
 832                 ret = -EINVAL;
 833                 goto done;
 834         }
 835
 836         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvbthqp, IPATH_KD_QP);
 837
 838         /*
 839          * make sure we are not in freeze, and PIO send enabled, so
 840          * writes to pbc happen
 841          */
 842         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask, 0ULL);
 843         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
 844                          ~0ULL&~INFINIPATH_HWE_MEMBISTFAILED);
 845         ipath_write_kreg(dd, dd->ipath_kregs->kr_control, 0ULL);
 846
 847         /*
 848          * before error clears, since we expect serdes pll errors during
 849          * this, the first time after reset
 850          */
 851         if (bringup_link(dd)) {
 852                 dev_info(&dd->pcidev->dev, "Failed to bringup IB link\n");
 853                 ret = -ENETDOWN;
 854                 goto done;
 855         }
 856
 857         /*
 858          * clear any "expected" hwerrs from reset and/or initialization
 859          * clear any that aren't enabled (at least this once), and then
 860          * set the enable mask
 861          */
 862         dd->ipath_f_init_hwerrors(dd);
 863         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
 864                          ~0ULL&~INFINIPATH_HWE_MEMBISTFAILED);
 865         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 866                          dd->ipath_hwerrmask);
 867
 868         /* clear all */
 869         ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, -1LL);
 870         /* enable errors that are masked, at least this first time. */
 871         ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
 872                          ~dd->ipath_maskederrs);
 873         dd->ipath_maskederrs = 0; /* don't re-enable ignored in timer */
 874         dd->ipath_errormask =
 875                 ipath_read_kreg64(dd, dd->ipath_kregs->kr_errormask);
 876         /* clear any interrupts up to this point (ints still not enabled) */
 877         ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, -1LL);
 878
 879         dd->ipath_f_tidtemplate(dd);
 880
 881         /*
 882          * Set up the port 0 (kernel) rcvhdr q and egr TIDs.  If doing
 883          * re-init, the simplest way to handle this is to free
 884          * existing, and re-allocate.
 885          * Need to re-create rest of port 0 portdata as well.
 886          */
 887         pd = dd->ipath_pd[0];
 888         if (reinit) {
 889                 struct ipath_portdata *npd;
 890
 891                 /*
 892                  * Alloc and init new ipath_portdata for port0,
 893                  * Then free old pd. Could lead to fragmentation, but also
 894                  * makes later support for hot-swap easier.
 895                  */
 896                 npd = create_portdata0(dd);
 897                 if (npd) {
 898                         ipath_free_pddata(dd, pd);
 899                         dd->ipath_pd[0] = npd;
 900                         pd = npd;
 901                 } else {
 902                         ipath_dev_err(dd, "Unable to allocate portdata"
 903                                       " for port 0, failing\n");
 904                         ret = -ENOMEM;
 905                         goto done;
 906                 }
 907         }
 908         ret = ipath_create_rcvhdrq(dd, pd);
 909         if (!ret)
 910                 ret = create_port0_egr(dd);
 911         if (ret) {
 912                 ipath_dev_err(dd, "failed to allocate kernel port's "
 913                               "rcvhdrq and/or egr bufs\n");
 914                 goto done;
 915         }
 916         else
 917                 enable_chip(dd, reinit);
 918
 919         /* after enable_chip, so pioavailshadow setup */
 920         ipath_chg_pioavailkernel(dd, 0, piobufs, 1);
 921
 922         /*
 923          * Cancel any possible active sends from early driver load.
 924          * Follows early_init because some chips have to initialize
 925          * PIO buffers in early_init to avoid false parity errors.
 926          * After enable and ipath_chg_pioavailkernel so we can safely
 927          * enable pioavail updates and PIOENABLE; packets are now
 928          * ready to go out.
 929          */
 930         ipath_cancel_sends(dd, 1);
 931
 932         if (!reinit) {
 933                 /*
 934                  * Used when we close a port, for DMA already in flight
 935                  * at close.
 936                  */
 937                 dd->ipath_dummy_hdrq = dma_alloc_coherent(
 938                         &dd->pcidev->dev, dd->ipath_pd[0]->port_rcvhdrq_size,
 939                         &dd->ipath_dummy_hdrq_phys,
 940                         gfp_flags);
 941                 if (!dd->ipath_dummy_hdrq) {
 942                         dev_info(&dd->pcidev->dev,
 943                                 "Couldn't allocate 0x%lx bytes for dummy hdrq\n",
 944                                 dd->ipath_pd[0]->port_rcvhdrq_size);
 945                         /* fallback to just 0'ing */
 946                         dd->ipath_dummy_hdrq_phys = 0UL;
 947                 }
 948         }
 949
 950         /*
 951          * cause retrigger of pending interrupts ignored during init,
 952          * even if we had errors
 953          */
 954         ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, 0ULL);
 955
 956         if (!dd->ipath_stats_timer_active) {
 957                 /*
 958                  * first init, or after an admin disable/enable
 959                  * set up stats retrieval timer, even if we had errors
 960                  * in last portion of setup
 961                  */
 962                 init_timer(&dd->ipath_stats_timer);
 963                 dd->ipath_stats_timer.function = ipath_get_faststats;
 964                 dd->ipath_stats_timer.data = (unsigned long) dd;
 965                 /* every 5 seconds; */
 966                 dd->ipath_stats_timer.expires = jiffies + 5 * HZ;
 967                 /* takes ~16 seconds to overflow at full IB 4x bandwdith */
 968                 add_timer(&dd->ipath_stats_timer);
 969                 dd->ipath_stats_timer_active = 1;
 970         }
 971
 972         /* Set up SendDMA if chip supports it */
 973         if (dd->ipath_flags & IPATH_HAS_SEND_DMA)
 974                 ret = setup_sdma(dd);
 975
 976         /* Set up HoL state */
 977         init_timer(&dd->ipath_hol_timer);
 978         dd->ipath_hol_timer.function = ipath_hol_event;
 979         dd->ipath_hol_timer.data = (unsigned long)dd;
 980         dd->ipath_hol_state = IPATH_HOL_UP;
 981
 982 done:
 983         if (!ret) {
 984                 *dd->ipath_statusp |= IPATH_STATUS_CHIP_PRESENT;
 985                 if (!dd->ipath_f_intrsetup(dd)) {
 986                         /* now we can enable all interrupts from the chip */
 987                         ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask,
 988                                          -1LL);
 989                         /* force re-interrupt of any pending interrupts. */
 990                         ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear,
 991                                          0ULL);
 992                         /* chip is usable; mark it as initialized */
 993                         *dd->ipath_statusp |= IPATH_STATUS_INITTED;
 994
 995                         /*
 996                          * setup to verify we get an interrupt, and fallback
 997                          * to an alternate if necessary and possible
 998                          */
 999                         if (!reinit) {
1000                                 init_timer(&dd->ipath_intrchk_timer);
1001                                 dd->ipath_intrchk_timer.function =
1002                                         verify_interrupt;
1003                                 dd->ipath_intrchk_timer.data =
1004                                         (unsigned long) dd;
1005                         }
1006                         dd->ipath_intrchk_timer.expires = jiffies + HZ/2;
1007                         add_timer(&dd->ipath_intrchk_timer);
1008                 } else
1009                         ipath_dev_err(dd, "No interrupts enabled, couldn't "
1010                                       "setup interrupt address\n");
1011
1012                 if (dd->ipath_cfgports > ipath_stats.sps_nports)
1013                         /*
1014                          * sps_nports is a global, so, we set it to
1015                          * the highest number of ports of any of the
1016                          * chips we find; we never decrement it, at
1017                          * least for now.  Since this might have changed
1018                          * over disable/enable or prior to reset, always
1019                          * do the check and potentially adjust.
1020                          */
1021                         ipath_stats.sps_nports = dd->ipath_cfgports;
1022         } else
1023                 ipath_dbg("Failed (%d) to initialize chip\n", ret);
1024
1025         /* if ret is non-zero, we probably should do some cleanup
1026            here... */
1027         return ret;
1028 }
1029
1030 static int ipath_set_kpiobufs(const char *str, struct kernel_param *kp)
1031 {
1032         struct ipath_devdata *dd;
1033         unsigned long flags;
1034         unsigned short val;
1035         int ret;
1036
1037         ret = ipath_parse_ushort(str, &val);
1038
1039         spin_lock_irqsave(&ipath_devs_lock, flags);
1040
1041         if (ret < 0)
1042                 goto bail;
1043
1044         if (val == 0) {
1045                 ret = -EINVAL;
1046                 goto bail;
1047         }
1048
1049         list_for_each_entry(dd, &ipath_dev_list, ipath_list) {
1050                 if (dd->ipath_kregbase)
1051                         continue;
1052                 if (val > (dd->ipath_piobcnt2k + dd->ipath_piobcnt4k -
1053                            (dd->ipath_cfgports *
1054                             IPATH_MIN_USER_PORT_BUFCNT)))
1055                 {
1056                         ipath_dev_err(
1057                                 dd,
1058                                 "Allocating %d PIO bufs for kernel leaves "
1059                                 "too few for %d user ports (%d each)\n",
1060                                 val, dd->ipath_cfgports - 1,
1061                                 IPATH_MIN_USER_PORT_BUFCNT);
1062                         ret = -EINVAL;
1063                         goto bail;
1064                 }
1065                 dd->ipath_lastport_piobuf =
1066                         dd->ipath_piobcnt2k + dd->ipath_piobcnt4k - val;
1067         }
1068
1069         ipath_kpiobufs = val;
1070         ret = 0;
1071 bail:
1072         spin_unlock_irqrestore(&ipath_devs_lock, flags);
1073
1074         return ret;
1075 }