drivers/infiniband/hw/cxgb4/qp.c

   1 /*
   2  * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/module.h>
  34
  35 #include "iw_cxgb4.h"
  36
  37 static int db_delay_usecs = 1;
  38 module_param(db_delay_usecs, int, 0644);
  39 MODULE_PARM_DESC(db_delay_usecs, "Usecs to delay awaiting db fifo to drain");
  40
  41 static int ocqp_support = 1;
  42 module_param(ocqp_support, int, 0644);
  43 MODULE_PARM_DESC(ocqp_support, "Support on-chip SQs (default=1)");
  44
  45 int db_fc_threshold = 2000;
  46 module_param(db_fc_threshold, int, 0644);
  47 MODULE_PARM_DESC(db_fc_threshold, "QP count/threshold that triggers automatic "
  48                  "db flow control mode (default = 2000)");
  49
  50 static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state)
  51 {
  52         unsigned long flag;
  53         spin_lock_irqsave(&qhp->lock, flag);
  54         qhp->attr.state = state;
  55         spin_unlock_irqrestore(&qhp->lock, flag);
  56 }
  57
  58 static void dealloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
  59 {
  60         c4iw_ocqp_pool_free(rdev, sq->dma_addr, sq->memsize);
  61 }
  62
  63 static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
  64 {
  65         dma_free_coherent(&(rdev->lldi.pdev->dev), sq->memsize, sq->queue,
  66                           pci_unmap_addr(sq, mapping));
  67 }
  68
  69 static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
  70 {
  71         if (t4_sq_onchip(sq))
  72                 dealloc_oc_sq(rdev, sq);
  73         else
  74                 dealloc_host_sq(rdev, sq);
  75 }
  76
  77 static int alloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
  78 {
  79         if (!ocqp_support || !t4_ocqp_supported())
  80                 return -ENOSYS;
  81         sq->dma_addr = c4iw_ocqp_pool_alloc(rdev, sq->memsize);
  82         if (!sq->dma_addr)
  83                 return -ENOMEM;
  84         sq->phys_addr = rdev->oc_mw_pa + sq->dma_addr -
  85                         rdev->lldi.vr->ocq.start;
  86         sq->queue = (__force union t4_wr *)(rdev->oc_mw_kva + sq->dma_addr -
  87                                             rdev->lldi.vr->ocq.start);
  88         sq->flags |= T4_SQ_ONCHIP;
  89         return 0;
  90 }
  91
  92 static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
  93 {
  94         sq->queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), sq->memsize,
  95                                        &(sq->dma_addr), GFP_KERNEL);
  96         if (!sq->queue)
  97                 return -ENOMEM;
  98         sq->phys_addr = virt_to_phys(sq->queue);
  99         pci_unmap_addr_set(sq, mapping, sq->dma_addr);
 100         return 0;
 101 }
 102
 103 static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
 104                       struct c4iw_dev_ucontext *uctx)
 105 {
 106         /*
 107          * uP clears EQ contexts when the connection exits rdma mode,
 108          * so no need to post a RESET WR for these EQs.
 109          */
 110         dma_free_coherent(&(rdev->lldi.pdev->dev),
 111                           wq->rq.memsize, wq->rq.queue,
 112                           dma_unmap_addr(&wq->rq, mapping));
 113         dealloc_sq(rdev, &wq->sq);
 114         c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
 115         kfree(wq->rq.sw_rq);
 116         kfree(wq->sq.sw_sq);
 117         c4iw_put_qpid(rdev, wq->rq.qid, uctx);
 118         c4iw_put_qpid(rdev, wq->sq.qid, uctx);
 119         return 0;
 120 }
 121
 122 static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
 123                      struct t4_cq *rcq, struct t4_cq *scq,
 124                      struct c4iw_dev_ucontext *uctx)
 125 {
 126         int user = (uctx != &rdev->uctx);
 127         struct fw_ri_res_wr *res_wr;
 128         struct fw_ri_res *res;
 129         int wr_len;
 130         struct c4iw_wr_wait wr_wait;
 131         struct sk_buff *skb;
 132         int ret;
 133         int eqsize;
 134
 135         wq->sq.qid = c4iw_get_qpid(rdev, uctx);
 136         if (!wq->sq.qid)
 137                 return -ENOMEM;
 138
 139         wq->rq.qid = c4iw_get_qpid(rdev, uctx);
 140         if (!wq->rq.qid)
 141                 goto err1;
 142
 143         if (!user) {
 144                 wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq,
 145                                  GFP_KERNEL);
 146                 if (!wq->sq.sw_sq)
 147                         goto err2;
 148
 149                 wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq,
 150                                  GFP_KERNEL);
 151                 if (!wq->rq.sw_rq)
 152                         goto err3;
 153         }
 154
 155         /*
 156          * RQT must be a power of 2.
 157          */
 158         wq->rq.rqt_size = roundup_pow_of_two(wq->rq.size);
 159         wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size);
 160         if (!wq->rq.rqt_hwaddr)
 161                 goto err4;
 162
 163         if (user) {
 164                 if (alloc_oc_sq(rdev, &wq->sq) && alloc_host_sq(rdev, &wq->sq))
 165                         goto err5;
 166         } else
 167                 if (alloc_host_sq(rdev, &wq->sq))
 168                         goto err5;
 169         memset(wq->sq.queue, 0, wq->sq.memsize);
 170         dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr);
 171
 172         wq->rq.queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev),
 173                                           wq->rq.memsize, &(wq->rq.dma_addr),
 174                                           GFP_KERNEL);
 175         if (!wq->rq.queue)
 176                 goto err6;
 177         PDBG("%s sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx\n",
 178                 __func__, wq->sq.queue,
 179                 (unsigned long long)virt_to_phys(wq->sq.queue),
 180                 wq->rq.queue,
 181                 (unsigned long long)virt_to_phys(wq->rq.queue));
 182         memset(wq->rq.queue, 0, wq->rq.memsize);
 183         dma_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr);
 184
 185         wq->db = rdev->lldi.db_reg;
 186         wq->gts = rdev->lldi.gts_reg;
 187         if (user) {
 188                 wq->sq.udb = (u64)pci_resource_start(rdev->lldi.pdev, 2) +
 189                                         (wq->sq.qid << rdev->qpshift);
 190                 wq->sq.udb &= PAGE_MASK;
 191                 wq->rq.udb = (u64)pci_resource_start(rdev->lldi.pdev, 2) +
 192                                         (wq->rq.qid << rdev->qpshift);
 193                 wq->rq.udb &= PAGE_MASK;
 194         }
 195         wq->rdev = rdev;
 196         wq->rq.msn = 1;
 197
 198         /* build fw_ri_res_wr */
 199         wr_len = sizeof *res_wr + 2 * sizeof *res;
 200
 201         skb = alloc_skb(wr_len, GFP_KERNEL);
 202         if (!skb) {
 203                 ret = -ENOMEM;
 204                 goto err7;
 205         }
 206         set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
 207
 208         res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len);
 209         memset(res_wr, 0, wr_len);
 210         res_wr->op_nres = cpu_to_be32(
 211                         FW_WR_OP(FW_RI_RES_WR) |
 212                         V_FW_RI_RES_WR_NRES(2) |
 213                         FW_WR_COMPL(1));
 214         res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
 215         res_wr->cookie = (unsigned long) &wr_wait;
 216         res = res_wr->res;
 217         res->u.sqrq.restype = FW_RI_RES_TYPE_SQ;
 218         res->u.sqrq.op = FW_RI_RES_OP_WRITE;
 219
 220         /*
 221          * eqsize is the number of 64B entries plus the status page size.
 222          */
 223         eqsize = wq->sq.size * T4_SQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES;
 224
 225         res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
 226                 V_FW_RI_RES_WR_HOSTFCMODE(0) |  /* no host cidx updates */
 227                 V_FW_RI_RES_WR_CPRIO(0) |       /* don't keep in chip cache */
 228                 V_FW_RI_RES_WR_PCIECHN(0) |     /* set by uP at ri_init time */
 229                 (t4_sq_onchip(&wq->sq) ? F_FW_RI_RES_WR_ONCHIP : 0) |
 230                 V_FW_RI_RES_WR_IQID(scq->cqid));
 231         res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
 232                 V_FW_RI_RES_WR_DCAEN(0) |
 233                 V_FW_RI_RES_WR_DCACPU(0) |
 234                 V_FW_RI_RES_WR_FBMIN(2) |
 235                 V_FW_RI_RES_WR_FBMAX(2) |
 236                 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
 237                 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
 238                 V_FW_RI_RES_WR_EQSIZE(eqsize));
 239         res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid);
 240         res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr);
 241         res++;
 242         res->u.sqrq.restype = FW_RI_RES_TYPE_RQ;
 243         res->u.sqrq.op = FW_RI_RES_OP_WRITE;
 244
 245         /*
 246          * eqsize is the number of 64B entries plus the status page size.
 247          */
 248         eqsize = wq->rq.size * T4_RQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES;
 249         res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
 250                 V_FW_RI_RES_WR_HOSTFCMODE(0) |  /* no host cidx updates */
 251                 V_FW_RI_RES_WR_CPRIO(0) |       /* don't keep in chip cache */
 252                 V_FW_RI_RES_WR_PCIECHN(0) |     /* set by uP at ri_init time */
 253                 V_FW_RI_RES_WR_IQID(rcq->cqid));
 254         res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
 255                 V_FW_RI_RES_WR_DCAEN(0) |
 256                 V_FW_RI_RES_WR_DCACPU(0) |
 257                 V_FW_RI_RES_WR_FBMIN(2) |
 258                 V_FW_RI_RES_WR_FBMAX(2) |
 259                 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
 260                 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
 261                 V_FW_RI_RES_WR_EQSIZE(eqsize));
 262         res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid);
 263         res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr);
 264
 265         c4iw_init_wr_wait(&wr_wait);
 266
 267         ret = c4iw_ofld_send(rdev, skb);
 268         if (ret)
 269                 goto err7;
 270         ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, wq->sq.qid, __func__);
 271         if (ret)
 272                 goto err7;
 273
 274         PDBG("%s sqid 0x%x rqid 0x%x kdb 0x%p squdb 0x%llx rqudb 0x%llx\n",
 275              __func__, wq->sq.qid, wq->rq.qid, wq->db,
 276              (unsigned long long)wq->sq.udb, (unsigned long long)wq->rq.udb);
 277
 278         return 0;
 279 err7:
 280         dma_free_coherent(&(rdev->lldi.pdev->dev),
 281                           wq->rq.memsize, wq->rq.queue,
 282                           dma_unmap_addr(&wq->rq, mapping));
 283 err6:
 284         dealloc_sq(rdev, &wq->sq);
 285 err5:
 286         c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
 287 err4:
 288         kfree(wq->rq.sw_rq);
 289 err3:
 290         kfree(wq->sq.sw_sq);
 291 err2:
 292         c4iw_put_qpid(rdev, wq->rq.qid, uctx);
 293 err1:
 294         c4iw_put_qpid(rdev, wq->sq.qid, uctx);
 295         return -ENOMEM;
 296 }
 297
 298 static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp,
 299                       struct ib_send_wr *wr, int max, u32 *plenp)
 300 {
 301         u8 *dstp, *srcp;
 302         u32 plen = 0;
 303         int i;
 304         int rem, len;
 305
 306         dstp = (u8 *)immdp->data;
 307         for (i = 0; i < wr->num_sge; i++) {
 308                 if ((plen + wr->sg_list[i].length) > max)
 309                         return -EMSGSIZE;
 310                 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr;
 311                 plen += wr->sg_list[i].length;
 312                 rem = wr->sg_list[i].length;
 313                 while (rem) {
 314                         if (dstp == (u8 *)&sq->queue[sq->size])
 315                                 dstp = (u8 *)sq->queue;
 316                         if (rem <= (u8 *)&sq->queue[sq->size] - dstp)
 317                                 len = rem;
 318                         else
 319                                 len = (u8 *)&sq->queue[sq->size] - dstp;
 320                         memcpy(dstp, srcp, len);
 321                         dstp += len;
 322                         srcp += len;
 323                         rem -= len;
 324                 }
 325         }
 326         len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp);
 327         if (len)
 328                 memset(dstp, 0, len);
 329         immdp->op = FW_RI_DATA_IMMD;
 330         immdp->r1 = 0;
 331         immdp->r2 = 0;
 332         immdp->immdlen = cpu_to_be32(plen);
 333         *plenp = plen;
 334         return 0;
 335 }
 336
 337 static int build_isgl(__be64 *queue_start, __be64 *queue_end,
 338                       struct fw_ri_isgl *isglp, struct ib_sge *sg_list,
 339                       int num_sge, u32 *plenp)
 340
 341 {
 342         int i;
 343         u32 plen = 0;
 344         __be64 *flitp = (__be64 *)isglp->sge;
 345
 346         for (i = 0; i < num_sge; i++) {
 347                 if ((plen + sg_list[i].length) < plen)
 348                         return -EMSGSIZE;
 349                 plen += sg_list[i].length;
 350                 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) |
 351                                      sg_list[i].length);
 352                 if (++flitp == queue_end)
 353                         flitp = queue_start;
 354                 *flitp = cpu_to_be64(sg_list[i].addr);
 355                 if (++flitp == queue_end)
 356                         flitp = queue_start;
 357         }
 358         *flitp = (__force __be64)0;
 359         isglp->op = FW_RI_DATA_ISGL;
 360         isglp->r1 = 0;
 361         isglp->nsge = cpu_to_be16(num_sge);
 362         isglp->r2 = 0;
 363         if (plenp)
 364                 *plenp = plen;
 365         return 0;
 366 }
 367
 368 static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe,
 369                            struct ib_send_wr *wr, u8 *len16)
 370 {
 371         u32 plen;
 372         int size;
 373         int ret;
 374
 375         if (wr->num_sge > T4_MAX_SEND_SGE)
 376                 return -EINVAL;
 377         switch (wr->opcode) {
 378         case IB_WR_SEND:
 379                 if (wr->send_flags & IB_SEND_SOLICITED)
 380                         wqe->send.sendop_pkd = cpu_to_be32(
 381                                 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE));
 382                 else
 383                         wqe->send.sendop_pkd = cpu_to_be32(
 384                                 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND));
 385                 wqe->send.stag_inv = 0;
 386                 break;
 387         case IB_WR_SEND_WITH_INV:
 388                 if (wr->send_flags & IB_SEND_SOLICITED)
 389                         wqe->send.sendop_pkd = cpu_to_be32(
 390                                 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE_INV));
 391                 else
 392                         wqe->send.sendop_pkd = cpu_to_be32(
 393                                 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_INV));
 394                 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
 395                 break;
 396
 397         default:
 398                 return -EINVAL;
 399         }
 400
 401         plen = 0;
 402         if (wr->num_sge) {
 403                 if (wr->send_flags & IB_SEND_INLINE) {
 404                         ret = build_immd(sq, wqe->send.u.immd_src, wr,
 405                                          T4_MAX_SEND_INLINE, &plen);
 406                         if (ret)
 407                                 return ret;
 408                         size = sizeof wqe->send + sizeof(struct fw_ri_immd) +
 409                                plen;
 410                 } else {
 411                         ret = build_isgl((__be64 *)sq->queue,
 412                                          (__be64 *)&sq->queue[sq->size],
 413                                          wqe->send.u.isgl_src,
 414                                          wr->sg_list, wr->num_sge, &plen);
 415                         if (ret)
 416                                 return ret;
 417                         size = sizeof wqe->send + sizeof(struct fw_ri_isgl) +
 418                                wr->num_sge * sizeof(struct fw_ri_sge);
 419                 }
 420         } else {
 421                 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD;
 422                 wqe->send.u.immd_src[0].r1 = 0;
 423                 wqe->send.u.immd_src[0].r2 = 0;
 424                 wqe->send.u.immd_src[0].immdlen = 0;
 425                 size = sizeof wqe->send + sizeof(struct fw_ri_immd);
 426                 plen = 0;
 427         }
 428         *len16 = DIV_ROUND_UP(size, 16);
 429         wqe->send.plen = cpu_to_be32(plen);
 430         return 0;
 431 }
 432
 433 static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe,
 434                             struct ib_send_wr *wr, u8 *len16)
 435 {
 436         u32 plen;
 437         int size;
 438         int ret;
 439
 440         if (wr->num_sge > T4_MAX_SEND_SGE)
 441                 return -EINVAL;
 442         wqe->write.r2 = 0;
 443         wqe->write.stag_sink = cpu_to_be32(wr->wr.rdma.rkey);
 444         wqe->write.to_sink = cpu_to_be64(wr->wr.rdma.remote_addr);
 445         if (wr->num_sge) {
 446                 if (wr->send_flags & IB_SEND_INLINE) {
 447                         ret = build_immd(sq, wqe->write.u.immd_src, wr,
 448                                          T4_MAX_WRITE_INLINE, &plen);
 449                         if (ret)
 450                                 return ret;
 451                         size = sizeof wqe->write + sizeof(struct fw_ri_immd) +
 452                                plen;
 453                 } else {
 454                         ret = build_isgl((__be64 *)sq->queue,
 455                                          (__be64 *)&sq->queue[sq->size],
 456                                          wqe->write.u.isgl_src,
 457                                          wr->sg_list, wr->num_sge, &plen);
 458                         if (ret)
 459                                 return ret;
 460                         size = sizeof wqe->write + sizeof(struct fw_ri_isgl) +
 461                                wr->num_sge * sizeof(struct fw_ri_sge);
 462                 }
 463         } else {
 464                 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD;
 465                 wqe->write.u.immd_src[0].r1 = 0;
 466                 wqe->write.u.immd_src[0].r2 = 0;
 467                 wqe->write.u.immd_src[0].immdlen = 0;
 468                 size = sizeof wqe->write + sizeof(struct fw_ri_immd);
 469                 plen = 0;
 470         }
 471         *len16 = DIV_ROUND_UP(size, 16);
 472         wqe->write.plen = cpu_to_be32(plen);
 473         return 0;
 474 }
 475
 476 static int build_rdma_read(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16)
 477 {
 478         if (wr->num_sge > 1)
 479                 return -EINVAL;
 480         if (wr->num_sge) {
 481                 wqe->read.stag_src = cpu_to_be32(wr->wr.rdma.rkey);
 482                 wqe->read.to_src_hi = cpu_to_be32((u32)(wr->wr.rdma.remote_addr
 483                                                         >> 32));
 484                 wqe->read.to_src_lo = cpu_to_be32((u32)wr->wr.rdma.remote_addr);
 485                 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey);
 486                 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length);
 487                 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr
 488                                                          >> 32));
 489                 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr));
 490         } else {
 491                 wqe->read.stag_src = cpu_to_be32(2);
 492                 wqe->read.to_src_hi = 0;
 493                 wqe->read.to_src_lo = 0;
 494                 wqe->read.stag_sink = cpu_to_be32(2);
 495                 wqe->read.plen = 0;
 496                 wqe->read.to_sink_hi = 0;
 497                 wqe->read.to_sink_lo = 0;
 498         }
 499         wqe->read.r2 = 0;
 500         wqe->read.r5 = 0;
 501         *len16 = DIV_ROUND_UP(sizeof wqe->read, 16);
 502         return 0;
 503 }
 504
 505 static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe,
 506                            struct ib_recv_wr *wr, u8 *len16)
 507 {
 508         int ret;
 509
 510         ret = build_isgl((__be64 *)qhp->wq.rq.queue,
 511                          (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size],
 512                          &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL);
 513         if (ret)
 514                 return ret;
 515         *len16 = DIV_ROUND_UP(sizeof wqe->recv +
 516                               wr->num_sge * sizeof(struct fw_ri_sge), 16);
 517         return 0;
 518 }
 519
 520 static int build_fastreg(struct t4_sq *sq, union t4_wr *wqe,
 521                          struct ib_send_wr *wr, u8 *len16)
 522 {
 523
 524         struct fw_ri_immd *imdp;
 525         __be64 *p;
 526         int i;
 527         int pbllen = roundup(wr->wr.fast_reg.page_list_len * sizeof(u64), 32);
 528         int rem;
 529
 530         if (wr->wr.fast_reg.page_list_len > T4_MAX_FR_DEPTH)
 531                 return -EINVAL;
 532
 533         wqe->fr.qpbinde_to_dcacpu = 0;
 534         wqe->fr.pgsz_shift = wr->wr.fast_reg.page_shift - 12;
 535         wqe->fr.addr_type = FW_RI_VA_BASED_TO;
 536         wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->wr.fast_reg.access_flags);
 537         wqe->fr.len_hi = 0;
 538         wqe->fr.len_lo = cpu_to_be32(wr->wr.fast_reg.length);
 539         wqe->fr.stag = cpu_to_be32(wr->wr.fast_reg.rkey);
 540         wqe->fr.va_hi = cpu_to_be32(wr->wr.fast_reg.iova_start >> 32);
 541         wqe->fr.va_lo_fbo = cpu_to_be32(wr->wr.fast_reg.iova_start &
 542                                         0xffffffff);
 543         WARN_ON(pbllen > T4_MAX_FR_IMMD);
 544         imdp = (struct fw_ri_immd *)(&wqe->fr + 1);
 545         imdp->op = FW_RI_DATA_IMMD;
 546         imdp->r1 = 0;
 547         imdp->r2 = 0;
 548         imdp->immdlen = cpu_to_be32(pbllen);
 549         p = (__be64 *)(imdp + 1);
 550         rem = pbllen;
 551         for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) {
 552                 *p = cpu_to_be64((u64)wr->wr.fast_reg.page_list->page_list[i]);
 553                 rem -= sizeof *p;
 554                 if (++p == (__be64 *)&sq->queue[sq->size])
 555                         p = (__be64 *)sq->queue;
 556         }
 557         BUG_ON(rem < 0);
 558         while (rem) {
 559                 *p = 0;
 560                 rem -= sizeof *p;
 561                 if (++p == (__be64 *)&sq->queue[sq->size])
 562                         p = (__be64 *)sq->queue;
 563         }
 564         *len16 = DIV_ROUND_UP(sizeof wqe->fr + sizeof *imdp + pbllen, 16);
 565         return 0;
 566 }
 567
 568 static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr,
 569                           u8 *len16)
 570 {
 571         wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
 572         wqe->inv.r2 = 0;
 573         *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16);
 574         return 0;
 575 }
 576
 577 void c4iw_qp_add_ref(struct ib_qp *qp)
 578 {
 579         PDBG("%s ib_qp %p\n", __func__, qp);
 580         atomic_inc(&(to_c4iw_qp(qp)->refcnt));
 581 }
 582
 583 void c4iw_qp_rem_ref(struct ib_qp *qp)
 584 {
 585         PDBG("%s ib_qp %p\n", __func__, qp);
 586         if (atomic_dec_and_test(&(to_c4iw_qp(qp)->refcnt)))
 587                 wake_up(&(to_c4iw_qp(qp)->wait));
 588 }
 589
 590 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
 591                    struct ib_send_wr **bad_wr)
 592 {
 593         int err = 0;
 594         u8 len16 = 0;
 595         enum fw_wr_opcodes fw_opcode = 0;
 596         enum fw_ri_wr_flags fw_flags;
 597         struct c4iw_qp *qhp;
 598         union t4_wr *wqe;
 599         u32 num_wrs;
 600         struct t4_swsqe *swsqe;
 601         unsigned long flag;
 602         u16 idx = 0;
 603
 604         qhp = to_c4iw_qp(ibqp);
 605         spin_lock_irqsave(&qhp->lock, flag);
 606         if (t4_wq_in_error(&qhp->wq)) {
 607                 spin_unlock_irqrestore(&qhp->lock, flag);
 608                 return -EINVAL;
 609         }
 610         num_wrs = t4_sq_avail(&qhp->wq);
 611         if (num_wrs == 0) {
 612                 spin_unlock_irqrestore(&qhp->lock, flag);
 613                 return -ENOMEM;
 614         }
 615         while (wr) {
 616                 if (num_wrs == 0) {
 617                         err = -ENOMEM;
 618                         *bad_wr = wr;
 619                         break;
 620                 }
 621                 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue +
 622                       qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE);
 623
 624                 fw_flags = 0;
 625                 if (wr->send_flags & IB_SEND_SOLICITED)
 626                         fw_flags |= FW_RI_SOLICITED_EVENT_FLAG;
 627                 if (wr->send_flags & IB_SEND_SIGNALED)
 628                         fw_flags |= FW_RI_COMPLETION_FLAG;
 629                 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx];
 630                 switch (wr->opcode) {
 631                 case IB_WR_SEND_WITH_INV:
 632                 case IB_WR_SEND:
 633                         if (wr->send_flags & IB_SEND_FENCE)
 634                                 fw_flags |= FW_RI_READ_FENCE_FLAG;
 635                         fw_opcode = FW_RI_SEND_WR;
 636                         if (wr->opcode == IB_WR_SEND)
 637                                 swsqe->opcode = FW_RI_SEND;
 638                         else
 639                                 swsqe->opcode = FW_RI_SEND_WITH_INV;
 640                         err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16);
 641                         break;
 642                 case IB_WR_RDMA_WRITE:
 643                         fw_opcode = FW_RI_RDMA_WRITE_WR;
 644                         swsqe->opcode = FW_RI_RDMA_WRITE;
 645                         err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16);
 646                         break;
 647                 case IB_WR_RDMA_READ:
 648                 case IB_WR_RDMA_READ_WITH_INV:
 649                         fw_opcode = FW_RI_RDMA_READ_WR;
 650                         swsqe->opcode = FW_RI_READ_REQ;
 651                         if (wr->opcode == IB_WR_RDMA_READ_WITH_INV)
 652                                 fw_flags = FW_RI_RDMA_READ_INVALIDATE;
 653                         else
 654                                 fw_flags = 0;
 655                         err = build_rdma_read(wqe, wr, &len16);
 656                         if (err)
 657                                 break;
 658                         swsqe->read_len = wr->sg_list[0].length;
 659                         if (!qhp->wq.sq.oldest_read)
 660                                 qhp->wq.sq.oldest_read = swsqe;
 661                         break;
 662                 case IB_WR_FAST_REG_MR:
 663                         fw_opcode = FW_RI_FR_NSMR_WR;
 664                         swsqe->opcode = FW_RI_FAST_REGISTER;
 665                         err = build_fastreg(&qhp->wq.sq, wqe, wr, &len16);
 666                         break;
 667                 case IB_WR_LOCAL_INV:
 668                         if (wr->send_flags & IB_SEND_FENCE)
 669                                 fw_flags |= FW_RI_LOCAL_FENCE_FLAG;
 670                         fw_opcode = FW_RI_INV_LSTAG_WR;
 671                         swsqe->opcode = FW_RI_LOCAL_INV;
 672                         err = build_inv_stag(wqe, wr, &len16);
 673                         break;
 674                 default:
 675                         PDBG("%s post of type=%d TBD!\n", __func__,
 676                              wr->opcode);
 677                         err = -EINVAL;
 678                 }
 679                 if (err) {
 680                         *bad_wr = wr;
 681                         break;
 682                 }
 683                 swsqe->idx = qhp->wq.sq.pidx;
 684                 swsqe->complete = 0;
 685                 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED);
 686                 swsqe->wr_id = wr->wr_id;
 687
 688                 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16);
 689
 690                 PDBG("%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u\n",
 691                      __func__, (unsigned long long)wr->wr_id, qhp->wq.sq.pidx,
 692                      swsqe->opcode, swsqe->read_len);
 693                 wr = wr->next;
 694                 num_wrs--;
 695                 t4_sq_produce(&qhp->wq, len16);
 696                 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
 697         }
 698         if (t4_wq_db_enabled(&qhp->wq))
 699                 t4_ring_sq_db(&qhp->wq, idx);
 700         spin_unlock_irqrestore(&qhp->lock, flag);
 701         return err;
 702 }
 703
 704 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
 705                       struct ib_recv_wr **bad_wr)
 706 {
 707         int err = 0;
 708         struct c4iw_qp *qhp;
 709         union t4_recv_wr *wqe;
 710         u32 num_wrs;
 711         u8 len16 = 0;
 712         unsigned long flag;
 713         u16 idx = 0;
 714
 715         qhp = to_c4iw_qp(ibqp);
 716         spin_lock_irqsave(&qhp->lock, flag);
 717         if (t4_wq_in_error(&qhp->wq)) {
 718                 spin_unlock_irqrestore(&qhp->lock, flag);
 719                 return -EINVAL;
 720         }
 721         num_wrs = t4_rq_avail(&qhp->wq);
 722         if (num_wrs == 0) {
 723                 spin_unlock_irqrestore(&qhp->lock, flag);
 724                 return -ENOMEM;
 725         }
 726         while (wr) {
 727                 if (wr->num_sge > T4_MAX_RECV_SGE) {
 728                         err = -EINVAL;
 729                         *bad_wr = wr;
 730                         break;
 731                 }
 732                 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue +
 733                                            qhp->wq.rq.wq_pidx *
 734                                            T4_EQ_ENTRY_SIZE);
 735                 if (num_wrs)
 736                         err = build_rdma_recv(qhp, wqe, wr, &len16);
 737                 else
 738                         err = -ENOMEM;
 739                 if (err) {
 740                         *bad_wr = wr;
 741                         break;
 742                 }
 743
 744                 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id;
 745
 746                 wqe->recv.opcode = FW_RI_RECV_WR;
 747                 wqe->recv.r1 = 0;
 748                 wqe->recv.wrid = qhp->wq.rq.pidx;
 749                 wqe->recv.r2[0] = 0;
 750                 wqe->recv.r2[1] = 0;
 751                 wqe->recv.r2[2] = 0;
 752                 wqe->recv.len16 = len16;
 753                 PDBG("%s cookie 0x%llx pidx %u\n", __func__,
 754                      (unsigned long long) wr->wr_id, qhp->wq.rq.pidx);
 755                 t4_rq_produce(&qhp->wq, len16);
 756                 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
 757                 wr = wr->next;
 758                 num_wrs--;
 759         }
 760         if (t4_wq_db_enabled(&qhp->wq))
 761                 t4_ring_rq_db(&qhp->wq, idx);
 762         spin_unlock_irqrestore(&qhp->lock, flag);
 763         return err;
 764 }
 765
 766 int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw, struct ib_mw_bind *mw_bind)
 767 {
 768         return -ENOSYS;
 769 }
 770
 771 static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type,
 772                                     u8 *ecode)
 773 {
 774         int status;
 775         int tagged;
 776         int opcode;
 777         int rqtype;
 778         int send_inv;
 779
 780         if (!err_cqe) {
 781                 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
 782                 *ecode = 0;
 783                 return;
 784         }
 785
 786         status = CQE_STATUS(err_cqe);
 787         opcode = CQE_OPCODE(err_cqe);
 788         rqtype = RQ_TYPE(err_cqe);
 789         send_inv = (opcode == FW_RI_SEND_WITH_INV) ||
 790                    (opcode == FW_RI_SEND_WITH_SE_INV);
 791         tagged = (opcode == FW_RI_RDMA_WRITE) ||
 792                  (rqtype && (opcode == FW_RI_READ_RESP));
 793
 794         switch (status) {
 795         case T4_ERR_STAG:
 796                 if (send_inv) {
 797                         *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
 798                         *ecode = RDMAP_CANT_INV_STAG;
 799                 } else {
 800                         *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 801                         *ecode = RDMAP_INV_STAG;
 802                 }
 803                 break;
 804         case T4_ERR_PDID:
 805                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 806                 if ((opcode == FW_RI_SEND_WITH_INV) ||
 807                     (opcode == FW_RI_SEND_WITH_SE_INV))
 808                         *ecode = RDMAP_CANT_INV_STAG;
 809                 else
 810                         *ecode = RDMAP_STAG_NOT_ASSOC;
 811                 break;
 812         case T4_ERR_QPID:
 813                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 814                 *ecode = RDMAP_STAG_NOT_ASSOC;
 815                 break;
 816         case T4_ERR_ACCESS:
 817                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 818                 *ecode = RDMAP_ACC_VIOL;
 819                 break;
 820         case T4_ERR_WRAP:
 821                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 822                 *ecode = RDMAP_TO_WRAP;
 823                 break;
 824         case T4_ERR_BOUND:
 825                 if (tagged) {
 826                         *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
 827                         *ecode = DDPT_BASE_BOUNDS;
 828                 } else {
 829                         *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 830                         *ecode = RDMAP_BASE_BOUNDS;
 831                 }
 832                 break;
 833         case T4_ERR_INVALIDATE_SHARED_MR:
 834         case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
 835                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
 836                 *ecode = RDMAP_CANT_INV_STAG;
 837                 break;
 838         case T4_ERR_ECC:
 839         case T4_ERR_ECC_PSTAG:
 840         case T4_ERR_INTERNAL_ERR:
 841                 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA;
 842                 *ecode = 0;
 843                 break;
 844         case T4_ERR_OUT_OF_RQE:
 845                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 846                 *ecode = DDPU_INV_MSN_NOBUF;
 847                 break;
 848         case T4_ERR_PBL_ADDR_BOUND:
 849                 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
 850                 *ecode = DDPT_BASE_BOUNDS;
 851                 break;
 852         case T4_ERR_CRC:
 853                 *layer_type = LAYER_MPA|DDP_LLP;
 854                 *ecode = MPA_CRC_ERR;
 855                 break;
 856         case T4_ERR_MARKER:
 857                 *layer_type = LAYER_MPA|DDP_LLP;
 858                 *ecode = MPA_MARKER_ERR;
 859                 break;
 860         case T4_ERR_PDU_LEN_ERR:
 861                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 862                 *ecode = DDPU_MSG_TOOBIG;
 863                 break;
 864         case T4_ERR_DDP_VERSION:
 865                 if (tagged) {
 866                         *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
 867                         *ecode = DDPT_INV_VERS;
 868                 } else {
 869                         *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 870                         *ecode = DDPU_INV_VERS;
 871                 }
 872                 break;
 873         case T4_ERR_RDMA_VERSION:
 874                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
 875                 *ecode = RDMAP_INV_VERS;
 876                 break;
 877         case T4_ERR_OPCODE:
 878                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
 879                 *ecode = RDMAP_INV_OPCODE;
 880                 break;
 881         case T4_ERR_DDP_QUEUE_NUM:
 882                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 883                 *ecode = DDPU_INV_QN;
 884                 break;
 885         case T4_ERR_MSN:
 886         case T4_ERR_MSN_GAP:
 887         case T4_ERR_MSN_RANGE:
 888         case T4_ERR_IRD_OVERFLOW:
 889                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 890                 *ecode = DDPU_INV_MSN_RANGE;
 891                 break;
 892         case T4_ERR_TBIT:
 893                 *layer_type = LAYER_DDP|DDP_LOCAL_CATA;
 894                 *ecode = 0;
 895                 break;
 896         case T4_ERR_MO:
 897                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 898                 *ecode = DDPU_INV_MO;
 899                 break;
 900         default:
 901                 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
 902                 *ecode = 0;
 903                 break;
 904         }
 905 }
 906
 907 static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe,
 908                            gfp_t gfp)
 909 {
 910         struct fw_ri_wr *wqe;
 911         struct sk_buff *skb;
 912         struct terminate_message *term;
 913
 914         PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
 915              qhp->ep->hwtid);
 916
 917         skb = alloc_skb(sizeof *wqe, gfp);
 918         if (!skb)
 919                 return;
 920         set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
 921
 922         wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
 923         memset(wqe, 0, sizeof *wqe);
 924         wqe->op_compl = cpu_to_be32(FW_WR_OP(FW_RI_INIT_WR));
 925         wqe->flowid_len16 = cpu_to_be32(
 926                 FW_WR_FLOWID(qhp->ep->hwtid) |
 927                 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
 928
 929         wqe->u.terminate.type = FW_RI_TYPE_TERMINATE;
 930         wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term);
 931         term = (struct terminate_message *)wqe->u.terminate.termmsg;
 932         if (qhp->attr.layer_etype == (LAYER_MPA|DDP_LLP)) {
 933                 term->layer_etype = qhp->attr.layer_etype;
 934                 term->ecode = qhp->attr.ecode;
 935         } else
 936                 build_term_codes(err_cqe, &term->layer_etype, &term->ecode);
 937         c4iw_ofld_send(&qhp->rhp->rdev, skb);
 938 }
 939
 940 /*
 941  * Assumes qhp lock is held.
 942  */
 943 static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp,
 944                        struct c4iw_cq *schp)
 945 {
 946         int count;
 947         int flushed;
 948         unsigned long flag;
 949
 950         PDBG("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp);
 951
 952         /* locking hierarchy: cq lock first, then qp lock. */
 953         spin_lock_irqsave(&rchp->lock, flag);
 954         spin_lock(&qhp->lock);
 955         c4iw_flush_hw_cq(&rchp->cq);
 956         c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count);
 957         flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count);
 958         spin_unlock(&qhp->lock);
 959         spin_unlock_irqrestore(&rchp->lock, flag);
 960         if (flushed) {
 961                 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
 962                 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
 963                 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
 964         }
 965
 966         /* locking hierarchy: cq lock first, then qp lock. */
 967         spin_lock_irqsave(&schp->lock, flag);
 968         spin_lock(&qhp->lock);
 969         c4iw_flush_hw_cq(&schp->cq);
 970         c4iw_count_scqes(&schp->cq, &qhp->wq, &count);
 971         flushed = c4iw_flush_sq(&qhp->wq, &schp->cq, count);
 972         spin_unlock(&qhp->lock);
 973         spin_unlock_irqrestore(&schp->lock, flag);
 974         if (flushed) {
 975                 spin_lock_irqsave(&schp->comp_handler_lock, flag);
 976                 (*schp->ibcq.comp_handler)(&schp->ibcq, schp->ibcq.cq_context);
 977                 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
 978         }
 979 }
 980
 981 static void flush_qp(struct c4iw_qp *qhp)
 982 {
 983         struct c4iw_cq *rchp, *schp;
 984         unsigned long flag;
 985
 986         rchp = get_chp(qhp->rhp, qhp->attr.rcq);
 987         schp = get_chp(qhp->rhp, qhp->attr.scq);
 988
 989         if (qhp->ibqp.uobject) {
 990                 t4_set_wq_in_error(&qhp->wq);
 991                 t4_set_cq_in_error(&rchp->cq);
 992                 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
 993                 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
 994                 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
 995                 if (schp != rchp) {
 996                         t4_set_cq_in_error(&schp->cq);
 997                         spin_lock_irqsave(&schp->comp_handler_lock, flag);
 998                         (*schp->ibcq.comp_handler)(&schp->ibcq,
 999                                         schp->ibcq.cq_context);
1000                         spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1001                 }
1002                 return;
1003         }
1004         __flush_qp(qhp, rchp, schp);
1005 }
1006
1007 static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1008                      struct c4iw_ep *ep)
1009 {
1010         struct fw_ri_wr *wqe;
1011         int ret;
1012         struct sk_buff *skb;
1013
1014         PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1015              ep->hwtid);
1016
1017         skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
1018         if (!skb)
1019                 return -ENOMEM;
1020         set_wr_txq(skb, CPL_PRIORITY_DATA, ep->txq_idx);
1021
1022         wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1023         memset(wqe, 0, sizeof *wqe);
1024         wqe->op_compl = cpu_to_be32(
1025                 FW_WR_OP(FW_RI_INIT_WR) |
1026                 FW_WR_COMPL(1));
1027         wqe->flowid_len16 = cpu_to_be32(
1028                 FW_WR_FLOWID(ep->hwtid) |
1029                 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1030         wqe->cookie = (unsigned long) &ep->com.wr_wait;
1031
1032         wqe->u.fini.type = FW_RI_TYPE_FINI;
1033         ret = c4iw_ofld_send(&rhp->rdev, skb);
1034         if (ret)
1035                 goto out;
1036
1037         ret = c4iw_wait_for_reply(&rhp->rdev, &ep->com.wr_wait, qhp->ep->hwtid,
1038                              qhp->wq.sq.qid, __func__);
1039 out:
1040         PDBG("%s ret %d\n", __func__, ret);
1041         return ret;
1042 }
1043
1044 static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init)
1045 {
1046         PDBG("%s p2p_type = %d\n", __func__, p2p_type);
1047         memset(&init->u, 0, sizeof init->u);
1048         switch (p2p_type) {
1049         case FW_RI_INIT_P2PTYPE_RDMA_WRITE:
1050                 init->u.write.opcode = FW_RI_RDMA_WRITE_WR;
1051                 init->u.write.stag_sink = cpu_to_be32(1);
1052                 init->u.write.to_sink = cpu_to_be64(1);
1053                 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD;
1054                 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write +
1055                                                    sizeof(struct fw_ri_immd),
1056                                                    16);
1057                 break;
1058         case FW_RI_INIT_P2PTYPE_READ_REQ:
1059                 init->u.write.opcode = FW_RI_RDMA_READ_WR;
1060                 init->u.read.stag_src = cpu_to_be32(1);
1061                 init->u.read.to_src_lo = cpu_to_be32(1);
1062                 init->u.read.stag_sink = cpu_to_be32(1);
1063                 init->u.read.to_sink_lo = cpu_to_be32(1);
1064                 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16);
1065                 break;
1066         }
1067 }
1068
1069 static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
1070 {
1071         struct fw_ri_wr *wqe;
1072         int ret;
1073         struct sk_buff *skb;
1074
1075         PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1076              qhp->ep->hwtid);
1077
1078         skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
1079         if (!skb)
1080                 return -ENOMEM;
1081         set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1082
1083         wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1084         memset(wqe, 0, sizeof *wqe);
1085         wqe->op_compl = cpu_to_be32(
1086                 FW_WR_OP(FW_RI_INIT_WR) |
1087                 FW_WR_COMPL(1));
1088         wqe->flowid_len16 = cpu_to_be32(
1089                 FW_WR_FLOWID(qhp->ep->hwtid) |
1090                 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1091
1092         wqe->cookie = (unsigned long) &qhp->ep->com.wr_wait;
1093
1094         wqe->u.init.type = FW_RI_TYPE_INIT;
1095         wqe->u.init.mpareqbit_p2ptype =
1096                 V_FW_RI_WR_MPAREQBIT(qhp->attr.mpa_attr.initiator) |
1097                 V_FW_RI_WR_P2PTYPE(qhp->attr.mpa_attr.p2p_type);
1098         wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE;
1099         if (qhp->attr.mpa_attr.recv_marker_enabled)
1100                 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE;
1101         if (qhp->attr.mpa_attr.xmit_marker_enabled)
1102                 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE;
1103         if (qhp->attr.mpa_attr.crc_enabled)
1104                 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE;
1105
1106         wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE |
1107                             FW_RI_QP_RDMA_WRITE_ENABLE |
1108                             FW_RI_QP_BIND_ENABLE;
1109         if (!qhp->ibqp.uobject)
1110                 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE |
1111                                      FW_RI_QP_STAG0_ENABLE;
1112         wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq));
1113         wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd);
1114         wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid);
1115         wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid);
1116         wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid);
1117         wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq);
1118         wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq);
1119         wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord);
1120         wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird);
1121         wqe->u.init.iss = cpu_to_be32(qhp->ep->snd_seq);
1122         wqe->u.init.irs = cpu_to_be32(qhp->ep->rcv_seq);
1123         wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size);
1124         wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr -
1125                                          rhp->rdev.lldi.vr->rq.start);
1126         if (qhp->attr.mpa_attr.initiator)
1127                 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init);
1128
1129         ret = c4iw_ofld_send(&rhp->rdev, skb);
1130         if (ret)
1131                 goto out;
1132
1133         ret = c4iw_wait_for_reply(&rhp->rdev, &qhp->ep->com.wr_wait,
1134                                   qhp->ep->hwtid, qhp->wq.sq.qid, __func__);
1135 out:
1136         PDBG("%s ret %d\n", __func__, ret);
1137         return ret;
1138 }
1139
1140 /*
1141  * Called by the library when the qp has user dbs disabled due to
1142  * a DB_FULL condition.  This function will single-thread all user
1143  * DB rings to avoid overflowing the hw db-fifo.
1144  */
1145 static int ring_kernel_db(struct c4iw_qp *qhp, u32 qid, u16 inc)
1146 {
1147         int delay = db_delay_usecs;
1148
1149         mutex_lock(&qhp->rhp->db_mutex);
1150         do {
1151
1152                 /*
1153                  * The interrupt threshold is dbfifo_int_thresh << 6. So
1154                  * make sure we don't cross that and generate an interrupt.
1155                  */
1156                 if (cxgb4_dbfifo_count(qhp->rhp->rdev.lldi.ports[0], 1) <
1157                     (qhp->rhp->rdev.lldi.dbfifo_int_thresh << 5)) {
1158                         writel(V_QID(qid) | V_PIDX(inc), qhp->wq.db);
1159                         break;
1160                 }
1161                 set_current_state(TASK_UNINTERRUPTIBLE);
1162                 schedule_timeout(usecs_to_jiffies(delay));
1163                 delay = min(delay << 1, 2000);
1164         } while (1);
1165         mutex_unlock(&qhp->rhp->db_mutex);
1166         return 0;
1167 }
1168
1169 int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1170                    enum c4iw_qp_attr_mask mask,
1171                    struct c4iw_qp_attributes *attrs,
1172                    int internal)
1173 {
1174         int ret = 0;
1175         struct c4iw_qp_attributes newattr = qhp->attr;
1176         int disconnect = 0;
1177         int terminate = 0;
1178         int abort = 0;
1179         int free = 0;
1180         struct c4iw_ep *ep = NULL;
1181
1182         PDBG("%s qhp %p sqid 0x%x rqid 0x%x ep %p state %d -> %d\n", __func__,
1183              qhp, qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep, qhp->attr.state,
1184              (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1);
1185
1186         mutex_lock(&qhp->mutex);
1187
1188         /* Process attr changes if in IDLE */
1189         if (mask & C4IW_QP_ATTR_VALID_MODIFY) {
1190                 if (qhp->attr.state != C4IW_QP_STATE_IDLE) {
1191                         ret = -EIO;
1192                         goto out;
1193                 }
1194                 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ)
1195                         newattr.enable_rdma_read = attrs->enable_rdma_read;
1196                 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE)
1197                         newattr.enable_rdma_write = attrs->enable_rdma_write;
1198                 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND)
1199                         newattr.enable_bind = attrs->enable_bind;
1200                 if (mask & C4IW_QP_ATTR_MAX_ORD) {
1201                         if (attrs->max_ord > c4iw_max_read_depth) {
1202                                 ret = -EINVAL;
1203                                 goto out;
1204                         }
1205                         newattr.max_ord = attrs->max_ord;
1206                 }
1207                 if (mask & C4IW_QP_ATTR_MAX_IRD) {
1208                         if (attrs->max_ird > c4iw_max_read_depth) {
1209                                 ret = -EINVAL;
1210                                 goto out;
1211                         }
1212                         newattr.max_ird = attrs->max_ird;
1213                 }
1214                 qhp->attr = newattr;
1215         }
1216
1217         if (mask & C4IW_QP_ATTR_SQ_DB) {
1218                 ret = ring_kernel_db(qhp, qhp->wq.sq.qid, attrs->sq_db_inc);
1219                 goto out;
1220         }
1221         if (mask & C4IW_QP_ATTR_RQ_DB) {
1222                 ret = ring_kernel_db(qhp, qhp->wq.rq.qid, attrs->rq_db_inc);
1223                 goto out;
1224         }
1225
1226         if (!(mask & C4IW_QP_ATTR_NEXT_STATE))
1227                 goto out;
1228         if (qhp->attr.state == attrs->next_state)
1229                 goto out;
1230
1231         switch (qhp->attr.state) {
1232         case C4IW_QP_STATE_IDLE:
1233                 switch (attrs->next_state) {
1234                 case C4IW_QP_STATE_RTS:
1235                         if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) {
1236                                 ret = -EINVAL;
1237                                 goto out;
1238                         }
1239                         if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) {
1240                                 ret = -EINVAL;
1241                                 goto out;
1242                         }
1243                         qhp->attr.mpa_attr = attrs->mpa_attr;
1244                         qhp->attr.llp_stream_handle = attrs->llp_stream_handle;
1245                         qhp->ep = qhp->attr.llp_stream_handle;
1246                         set_state(qhp, C4IW_QP_STATE_RTS);
1247
1248                         /*
1249                          * Ref the endpoint here and deref when we
1250                          * disassociate the endpoint from the QP.  This
1251                          * happens in CLOSING->IDLE transition or *->ERROR
1252                          * transition.
1253                          */
1254                         c4iw_get_ep(&qhp->ep->com);
1255                         ret = rdma_init(rhp, qhp);
1256                         if (ret)
1257                                 goto err;
1258                         break;
1259                 case C4IW_QP_STATE_ERROR:
1260                         set_state(qhp, C4IW_QP_STATE_ERROR);
1261                         flush_qp(qhp);
1262                         break;
1263                 default:
1264                         ret = -EINVAL;
1265                         goto out;
1266                 }
1267                 break;
1268         case C4IW_QP_STATE_RTS:
1269                 switch (attrs->next_state) {
1270                 case C4IW_QP_STATE_CLOSING:
1271                         BUG_ON(atomic_read(&qhp->ep->com.kref.refcount) < 2);
1272                         set_state(qhp, C4IW_QP_STATE_CLOSING);
1273                         ep = qhp->ep;
1274                         if (!internal) {
1275                                 abort = 0;
1276                                 disconnect = 1;
1277                                 c4iw_get_ep(&qhp->ep->com);
1278                         }
1279                         if (qhp->ibqp.uobject)
1280                                 t4_set_wq_in_error(&qhp->wq);
1281                         ret = rdma_fini(rhp, qhp, ep);
1282                         if (ret)
1283                                 goto err;
1284                         break;
1285                 case C4IW_QP_STATE_TERMINATE:
1286                         set_state(qhp, C4IW_QP_STATE_TERMINATE);
1287                         qhp->attr.layer_etype = attrs->layer_etype;
1288                         qhp->attr.ecode = attrs->ecode;
1289                         if (qhp->ibqp.uobject)
1290                                 t4_set_wq_in_error(&qhp->wq);
1291                         ep = qhp->ep;
1292                         if (!internal)
1293                                 terminate = 1;
1294                         disconnect = 1;
1295                         c4iw_get_ep(&qhp->ep->com);
1296                         break;
1297                 case C4IW_QP_STATE_ERROR:
1298                         set_state(qhp, C4IW_QP_STATE_ERROR);
1299                         if (qhp->ibqp.uobject)
1300                                 t4_set_wq_in_error(&qhp->wq);
1301                         if (!internal) {
1302                                 abort = 1;
1303                                 disconnect = 1;
1304                                 ep = qhp->ep;
1305                                 c4iw_get_ep(&qhp->ep->com);
1306                         }
1307                         goto err;
1308                         break;
1309                 default:
1310                         ret = -EINVAL;
1311                         goto out;
1312                 }
1313                 break;
1314         case C4IW_QP_STATE_CLOSING:
1315                 if (!internal) {
1316                         ret = -EINVAL;
1317                         goto out;
1318                 }
1319                 switch (attrs->next_state) {
1320                 case C4IW_QP_STATE_IDLE:
1321                         flush_qp(qhp);
1322                         set_state(qhp, C4IW_QP_STATE_IDLE);
1323                         qhp->attr.llp_stream_handle = NULL;
1324                         c4iw_put_ep(&qhp->ep->com);
1325                         qhp->ep = NULL;
1326                         wake_up(&qhp->wait);
1327                         break;
1328                 case C4IW_QP_STATE_ERROR:
1329                         goto err;
1330                 default:
1331                         ret = -EINVAL;
1332                         goto err;
1333                 }
1334                 break;
1335         case C4IW_QP_STATE_ERROR:
1336                 if (attrs->next_state != C4IW_QP_STATE_IDLE) {
1337                         ret = -EINVAL;
1338                         goto out;
1339                 }
1340                 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) {
1341                         ret = -EINVAL;
1342                         goto out;
1343                 }
1344                 set_state(qhp, C4IW_QP_STATE_IDLE);
1345                 break;
1346         case C4IW_QP_STATE_TERMINATE:
1347                 if (!internal) {
1348                         ret = -EINVAL;
1349                         goto out;
1350                 }
1351                 goto err;
1352                 break;
1353         default:
1354                 printk(KERN_ERR "%s in a bad state %d\n",
1355                        __func__, qhp->attr.state);
1356                 ret = -EINVAL;
1357                 goto err;
1358                 break;
1359         }
1360         goto out;
1361 err:
1362         PDBG("%s disassociating ep %p qpid 0x%x\n", __func__, qhp->ep,
1363              qhp->wq.sq.qid);
1364
1365         /* disassociate the LLP connection */
1366         qhp->attr.llp_stream_handle = NULL;
1367         if (!ep)
1368                 ep = qhp->ep;
1369         qhp->ep = NULL;
1370         set_state(qhp, C4IW_QP_STATE_ERROR);
1371         free = 1;
1372         wake_up(&qhp->wait);
1373         BUG_ON(!ep);
1374         flush_qp(qhp);
1375 out:
1376         mutex_unlock(&qhp->mutex);
1377
1378         if (terminate)
1379                 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL);
1380
1381         /*
1382          * If disconnect is 1, then we need to initiate a disconnect
1383          * on the EP.  This can be a normal close (RTS->CLOSING) or
1384          * an abnormal close (RTS/CLOSING->ERROR).
1385          */
1386         if (disconnect) {
1387                 c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC :
1388                                                          GFP_KERNEL);
1389                 c4iw_put_ep(&ep->com);
1390         }
1391
1392         /*
1393          * If free is 1, then we've disassociated the EP from the QP
1394          * and we need to dereference the EP.
1395          */
1396         if (free)
1397                 c4iw_put_ep(&ep->com);
1398         PDBG("%s exit state %d\n", __func__, qhp->attr.state);
1399         return ret;
1400 }
1401
1402 static int enable_qp_db(int id, void *p, void *data)
1403 {
1404         struct c4iw_qp *qp = p;
1405
1406         t4_enable_wq_db(&qp->wq);
1407         return 0;
1408 }
1409
1410 int c4iw_destroy_qp(struct ib_qp *ib_qp)
1411 {
1412         struct c4iw_dev *rhp;
1413         struct c4iw_qp *qhp;
1414         struct c4iw_qp_attributes attrs;
1415         struct c4iw_ucontext *ucontext;
1416
1417         qhp = to_c4iw_qp(ib_qp);
1418         rhp = qhp->rhp;
1419
1420         attrs.next_state = C4IW_QP_STATE_ERROR;
1421         if (qhp->attr.state == C4IW_QP_STATE_TERMINATE)
1422                 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1);
1423         else
1424                 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0);
1425         wait_event(qhp->wait, !qhp->ep);
1426
1427         spin_lock_irq(&rhp->lock);
1428         remove_handle_nolock(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1429         rhp->qpcnt--;
1430         BUG_ON(rhp->qpcnt < 0);
1431         if (rhp->qpcnt <= db_fc_threshold && rhp->db_state == FLOW_CONTROL) {
1432                 rhp->rdev.stats.db_state_transitions++;
1433                 rhp->db_state = NORMAL;
1434                 idr_for_each(&rhp->qpidr, enable_qp_db, NULL);
1435         }
1436         spin_unlock_irq(&rhp->lock);
1437         atomic_dec(&qhp->refcnt);
1438         wait_event(qhp->wait, !atomic_read(&qhp->refcnt));
1439
1440         ucontext = ib_qp->uobject ?
1441                    to_c4iw_ucontext(ib_qp->uobject->context) : NULL;
1442         destroy_qp(&rhp->rdev, &qhp->wq,
1443                    ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1444
1445         PDBG("%s ib_qp %p qpid 0x%0x\n", __func__, ib_qp, qhp->wq.sq.qid);
1446         kfree(qhp);
1447         return 0;
1448 }
1449
1450 static int disable_qp_db(int id, void *p, void *data)
1451 {
1452         struct c4iw_qp *qp = p;
1453
1454         t4_disable_wq_db(&qp->wq);
1455         return 0;
1456 }
1457
1458 struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1459                              struct ib_udata *udata)
1460 {
1461         struct c4iw_dev *rhp;
1462         struct c4iw_qp *qhp;
1463         struct c4iw_pd *php;
1464         struct c4iw_cq *schp;
1465         struct c4iw_cq *rchp;
1466         struct c4iw_create_qp_resp uresp;
1467         int sqsize, rqsize;
1468         struct c4iw_ucontext *ucontext;
1469         int ret;
1470         struct c4iw_mm_entry *mm1, *mm2, *mm3, *mm4, *mm5 = NULL;
1471
1472         PDBG("%s ib_pd %p\n", __func__, pd);
1473
1474         if (attrs->qp_type != IB_QPT_RC)
1475                 return ERR_PTR(-EINVAL);
1476
1477         php = to_c4iw_pd(pd);
1478         rhp = php->rhp;
1479         schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid);
1480         rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid);
1481         if (!schp || !rchp)
1482                 return ERR_PTR(-EINVAL);
1483
1484         if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE)
1485                 return ERR_PTR(-EINVAL);
1486
1487         rqsize = roundup(attrs->cap.max_recv_wr + 1, 16);
1488         if (rqsize > T4_MAX_RQ_SIZE)
1489                 return ERR_PTR(-E2BIG);
1490
1491         sqsize = roundup(attrs->cap.max_send_wr + 1, 16);
1492         if (sqsize > T4_MAX_SQ_SIZE)
1493                 return ERR_PTR(-E2BIG);
1494
1495         ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL;
1496
1497
1498         qhp = kzalloc(sizeof(*qhp), GFP_KERNEL);
1499         if (!qhp)
1500                 return ERR_PTR(-ENOMEM);
1501         qhp->wq.sq.size = sqsize;
1502         qhp->wq.sq.memsize = (sqsize + 1) * sizeof *qhp->wq.sq.queue;
1503         qhp->wq.rq.size = rqsize;
1504         qhp->wq.rq.memsize = (rqsize + 1) * sizeof *qhp->wq.rq.queue;
1505
1506         if (ucontext) {
1507                 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE);
1508                 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE);
1509         }
1510
1511         PDBG("%s sqsize %u sqmemsize %zu rqsize %u rqmemsize %zu\n",
1512              __func__, sqsize, qhp->wq.sq.memsize, rqsize, qhp->wq.rq.memsize);
1513
1514         ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq,
1515                         ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1516         if (ret)
1517                 goto err1;
1518
1519         attrs->cap.max_recv_wr = rqsize - 1;
1520         attrs->cap.max_send_wr = sqsize - 1;
1521         attrs->cap.max_inline_data = T4_MAX_SEND_INLINE;
1522
1523         qhp->rhp = rhp;
1524         qhp->attr.pd = php->pdid;
1525         qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid;
1526         qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid;
1527         qhp->attr.sq_num_entries = attrs->cap.max_send_wr;
1528         qhp->attr.rq_num_entries = attrs->cap.max_recv_wr;
1529         qhp->attr.sq_max_sges = attrs->cap.max_send_sge;
1530         qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge;
1531         qhp->attr.rq_max_sges = attrs->cap.max_recv_sge;
1532         qhp->attr.state = C4IW_QP_STATE_IDLE;
1533         qhp->attr.next_state = C4IW_QP_STATE_IDLE;
1534         qhp->attr.enable_rdma_read = 1;
1535         qhp->attr.enable_rdma_write = 1;
1536         qhp->attr.enable_bind = 1;
1537         qhp->attr.max_ord = 1;
1538         qhp->attr.max_ird = 1;
1539         spin_lock_init(&qhp->lock);
1540         mutex_init(&qhp->mutex);
1541         init_waitqueue_head(&qhp->wait);
1542         atomic_set(&qhp->refcnt, 1);
1543
1544         spin_lock_irq(&rhp->lock);
1545         if (rhp->db_state != NORMAL)
1546                 t4_disable_wq_db(&qhp->wq);
1547         if (++rhp->qpcnt > db_fc_threshold && rhp->db_state == NORMAL) {
1548                 rhp->rdev.stats.db_state_transitions++;
1549                 rhp->db_state = FLOW_CONTROL;
1550                 idr_for_each(&rhp->qpidr, disable_qp_db, NULL);
1551         }
1552         ret = insert_handle_nolock(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid);
1553         spin_unlock_irq(&rhp->lock);
1554         if (ret)
1555                 goto err2;
1556
1557         if (udata) {
1558                 mm1 = kmalloc(sizeof *mm1, GFP_KERNEL);
1559                 if (!mm1) {
1560                         ret = -ENOMEM;
1561                         goto err3;
1562                 }
1563                 mm2 = kmalloc(sizeof *mm2, GFP_KERNEL);
1564                 if (!mm2) {
1565                         ret = -ENOMEM;
1566                         goto err4;
1567                 }
1568                 mm3 = kmalloc(sizeof *mm3, GFP_KERNEL);
1569                 if (!mm3) {
1570                         ret = -ENOMEM;
1571                         goto err5;
1572                 }
1573                 mm4 = kmalloc(sizeof *mm4, GFP_KERNEL);
1574                 if (!mm4) {
1575                         ret = -ENOMEM;
1576                         goto err6;
1577                 }
1578                 if (t4_sq_onchip(&qhp->wq.sq)) {
1579                         mm5 = kmalloc(sizeof *mm5, GFP_KERNEL);
1580                         if (!mm5) {
1581                                 ret = -ENOMEM;
1582                                 goto err7;
1583                         }
1584                         uresp.flags = C4IW_QPF_ONCHIP;
1585                 } else
1586                         uresp.flags = 0;
1587                 uresp.qid_mask = rhp->rdev.qpmask;
1588                 uresp.sqid = qhp->wq.sq.qid;
1589                 uresp.sq_size = qhp->wq.sq.size;
1590                 uresp.sq_memsize = qhp->wq.sq.memsize;
1591                 uresp.rqid = qhp->wq.rq.qid;
1592                 uresp.rq_size = qhp->wq.rq.size;
1593                 uresp.rq_memsize = qhp->wq.rq.memsize;
1594                 spin_lock(&ucontext->mmap_lock);
1595                 if (mm5) {
1596                         uresp.ma_sync_key = ucontext->key;
1597                         ucontext->key += PAGE_SIZE;
1598                 }
1599                 uresp.sq_key = ucontext->key;
1600                 ucontext->key += PAGE_SIZE;
1601                 uresp.rq_key = ucontext->key;
1602                 ucontext->key += PAGE_SIZE;
1603                 uresp.sq_db_gts_key = ucontext->key;
1604                 ucontext->key += PAGE_SIZE;
1605                 uresp.rq_db_gts_key = ucontext->key;
1606                 ucontext->key += PAGE_SIZE;
1607                 spin_unlock(&ucontext->mmap_lock);
1608                 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp);
1609                 if (ret)
1610                         goto err8;
1611                 mm1->key = uresp.sq_key;
1612                 mm1->addr = qhp->wq.sq.phys_addr;
1613                 mm1->len = PAGE_ALIGN(qhp->wq.sq.memsize);
1614                 insert_mmap(ucontext, mm1);
1615                 mm2->key = uresp.rq_key;
1616                 mm2->addr = virt_to_phys(qhp->wq.rq.queue);
1617                 mm2->len = PAGE_ALIGN(qhp->wq.rq.memsize);
1618                 insert_mmap(ucontext, mm2);
1619                 mm3->key = uresp.sq_db_gts_key;
1620                 mm3->addr = qhp->wq.sq.udb;
1621                 mm3->len = PAGE_SIZE;
1622                 insert_mmap(ucontext, mm3);
1623                 mm4->key = uresp.rq_db_gts_key;
1624                 mm4->addr = qhp->wq.rq.udb;
1625                 mm4->len = PAGE_SIZE;
1626                 insert_mmap(ucontext, mm4);
1627                 if (mm5) {
1628                         mm5->key = uresp.ma_sync_key;
1629                         mm5->addr = (pci_resource_start(rhp->rdev.lldi.pdev, 0)
1630                                     + A_PCIE_MA_SYNC) & PAGE_MASK;
1631                         mm5->len = PAGE_SIZE;
1632                         insert_mmap(ucontext, mm5);
1633                 }
1634         }
1635         qhp->ibqp.qp_num = qhp->wq.sq.qid;
1636         init_timer(&(qhp->timer));
1637         PDBG("%s qhp %p sq_num_entries %d, rq_num_entries %d qpid 0x%0x\n",
1638              __func__, qhp, qhp->attr.sq_num_entries, qhp->attr.rq_num_entries,
1639              qhp->wq.sq.qid);
1640         return &qhp->ibqp;
1641 err8:
1642         kfree(mm5);
1643 err7:
1644         kfree(mm4);
1645 err6:
1646         kfree(mm3);
1647 err5:
1648         kfree(mm2);
1649 err4:
1650         kfree(mm1);
1651 err3:
1652         remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1653 err2:
1654         destroy_qp(&rhp->rdev, &qhp->wq,
1655                    ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1656 err1:
1657         kfree(qhp);
1658         return ERR_PTR(ret);
1659 }
1660
1661 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1662                       int attr_mask, struct ib_udata *udata)
1663 {
1664         struct c4iw_dev *rhp;
1665         struct c4iw_qp *qhp;
1666         enum c4iw_qp_attr_mask mask = 0;
1667         struct c4iw_qp_attributes attrs;
1668
1669         PDBG("%s ib_qp %p\n", __func__, ibqp);
1670
1671         /* iwarp does not support the RTR state */
1672         if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR))
1673                 attr_mask &= ~IB_QP_STATE;
1674
1675         /* Make sure we still have something left to do */
1676         if (!attr_mask)
1677                 return 0;
1678
1679         memset(&attrs, 0, sizeof attrs);
1680         qhp = to_c4iw_qp(ibqp);
1681         rhp = qhp->rhp;
1682
1683         attrs.next_state = c4iw_convert_state(attr->qp_state);
1684         attrs.enable_rdma_read = (attr->qp_access_flags &
1685                                IB_ACCESS_REMOTE_READ) ?  1 : 0;
1686         attrs.enable_rdma_write = (attr->qp_access_flags &
1687                                 IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
1688         attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0;
1689
1690
1691         mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0;
1692         mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ?
1693                         (C4IW_QP_ATTR_ENABLE_RDMA_READ |
1694                          C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
1695                          C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0;
1696
1697         /*
1698          * Use SQ_PSN and RQ_PSN to pass in IDX_INC values for
1699          * ringing the queue db when we're in DB_FULL mode.
1700          */
1701         attrs.sq_db_inc = attr->sq_psn;
1702         attrs.rq_db_inc = attr->rq_psn;
1703         mask |= (attr_mask & IB_QP_SQ_PSN) ? C4IW_QP_ATTR_SQ_DB : 0;
1704         mask |= (attr_mask & IB_QP_RQ_PSN) ? C4IW_QP_ATTR_RQ_DB : 0;
1705
1706         return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0);
1707 }
1708
1709 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn)
1710 {
1711         PDBG("%s ib_dev %p qpn 0x%x\n", __func__, dev, qpn);
1712         return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn);
1713 }