2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
17 * - Redistributions in binary form must reproduce the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials
20 * provided with the distribution.
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
23 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
25 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
26 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
27 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
28 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 #ifndef __IW_CXGB4_H__
32 #define __IW_CXGB4_H__
34 #include <linux/mutex.h>
35 #include <linux/list.h>
36 #include <linux/spinlock.h>
37 #include <linux/idr.h>
38 #include <linux/completion.h>
39 #include <linux/netdevice.h>
40 #include <linux/sched.h>
41 #include <linux/pci.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/inet.h>
44 #include <linux/wait.h>
45 #include <linux/kref.h>
46 #include <linux/timer.h>
48 #include <linux/kfifo.h>
50 #include <asm/byteorder.h>
52 #include <net/net_namespace.h>
54 #include <rdma/ib_verbs.h>
55 #include <rdma/iw_cm.h>
58 #include "cxgb4_uld.h"
62 #define DRV_NAME "iw_cxgb4"
63 #define MOD DRV_NAME ":"
65 extern int c4iw_debug;
66 #define PDBG(fmt, args...) \
69 printk(MOD fmt, ## args); \
74 #define PBL_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->pbl.start)
75 #define RQT_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->rq.start)
77 static inline void *cplhdr(struct sk_buff *skb)
82 struct c4iw_resource {
83 struct kfifo tpt_fifo;
84 spinlock_t tpt_fifo_lock;
85 struct kfifo qid_fifo;
86 spinlock_t qid_fifo_lock;
87 struct kfifo pdid_fifo;
88 spinlock_t pdid_fifo_lock;
91 struct c4iw_qid_list {
92 struct list_head entry;
96 struct c4iw_dev_ucontext {
97 struct list_head qpids;
98 struct list_head cqids;
102 enum c4iw_rdev_flags {
103 T4_FATAL_ERROR = (1<<0),
114 struct c4iw_stat qid;
116 struct c4iw_stat stag;
117 struct c4iw_stat pbl;
118 struct c4iw_stat rqt;
119 struct c4iw_stat ocqp;
123 u64 db_state_transitions;
127 struct c4iw_resource resource;
128 unsigned long qpshift;
130 unsigned long cqshift;
132 struct c4iw_dev_ucontext uctx;
133 struct gen_pool *pbl_pool;
134 struct gen_pool *rqt_pool;
135 struct gen_pool *ocqp_pool;
137 struct cxgb4_lld_info lldi;
138 unsigned long oc_mw_pa;
139 void __iomem *oc_mw_kva;
140 struct c4iw_stats stats;
143 static inline int c4iw_fatal_error(struct c4iw_rdev *rdev)
145 return rdev->flags & T4_FATAL_ERROR;
148 static inline int c4iw_num_stags(struct c4iw_rdev *rdev)
150 return min((int)T4_MAX_NUM_STAG, (int)(rdev->lldi.vr->stag.size >> 5));
153 #define C4IW_WR_TO (10*HZ)
155 struct c4iw_wr_wait {
156 struct completion completion;
160 static inline void c4iw_init_wr_wait(struct c4iw_wr_wait *wr_waitp)
163 init_completion(&wr_waitp->completion);
166 static inline void c4iw_wake_up(struct c4iw_wr_wait *wr_waitp, int ret)
169 complete(&wr_waitp->completion);
172 static inline int c4iw_wait_for_reply(struct c4iw_rdev *rdev,
173 struct c4iw_wr_wait *wr_waitp,
177 unsigned to = C4IW_WR_TO;
181 ret = wait_for_completion_timeout(&wr_waitp->completion, to);
183 printk(KERN_ERR MOD "%s - Device %s not responding - "
184 "tid %u qpid %u\n", func,
185 pci_name(rdev->lldi.pdev), hwtid, qpid);
186 if (c4iw_fatal_error(rdev)) {
187 wr_waitp->ret = -EIO;
194 PDBG("%s: FW reply %d tid %u qpid %u\n",
195 pci_name(rdev->lldi.pdev), wr_waitp->ret, hwtid, qpid);
196 return wr_waitp->ret;
206 struct ib_device ibdev;
207 struct c4iw_rdev rdev;
208 u32 device_cap_flags;
213 struct mutex db_mutex;
214 struct dentry *debugfs_root;
215 enum db_state db_state;
219 static inline struct c4iw_dev *to_c4iw_dev(struct ib_device *ibdev)
221 return container_of(ibdev, struct c4iw_dev, ibdev);
224 static inline struct c4iw_dev *rdev_to_c4iw_dev(struct c4iw_rdev *rdev)
226 return container_of(rdev, struct c4iw_dev, rdev);
229 static inline struct c4iw_cq *get_chp(struct c4iw_dev *rhp, u32 cqid)
231 return idr_find(&rhp->cqidr, cqid);
234 static inline struct c4iw_qp *get_qhp(struct c4iw_dev *rhp, u32 qpid)
236 return idr_find(&rhp->qpidr, qpid);
239 static inline struct c4iw_mr *get_mhp(struct c4iw_dev *rhp, u32 mmid)
241 return idr_find(&rhp->mmidr, mmid);
244 static inline int _insert_handle(struct c4iw_dev *rhp, struct idr *idr,
245 void *handle, u32 id, int lock)
251 if (!idr_pre_get(idr, lock ? GFP_KERNEL : GFP_ATOMIC))
254 spin_lock_irq(&rhp->lock);
255 ret = idr_get_new_above(idr, handle, id, &newid);
258 spin_unlock_irq(&rhp->lock);
259 } while (ret == -EAGAIN);
264 static inline int insert_handle(struct c4iw_dev *rhp, struct idr *idr,
265 void *handle, u32 id)
267 return _insert_handle(rhp, idr, handle, id, 1);
270 static inline int insert_handle_nolock(struct c4iw_dev *rhp, struct idr *idr,
271 void *handle, u32 id)
273 return _insert_handle(rhp, idr, handle, id, 0);
276 static inline void _remove_handle(struct c4iw_dev *rhp, struct idr *idr,
280 spin_lock_irq(&rhp->lock);
283 spin_unlock_irq(&rhp->lock);
286 static inline void remove_handle(struct c4iw_dev *rhp, struct idr *idr, u32 id)
288 _remove_handle(rhp, idr, id, 1);
291 static inline void remove_handle_nolock(struct c4iw_dev *rhp,
292 struct idr *idr, u32 id)
294 _remove_handle(rhp, idr, id, 0);
300 struct c4iw_dev *rhp;
303 static inline struct c4iw_pd *to_c4iw_pd(struct ib_pd *ibpd)
305 return container_of(ibpd, struct c4iw_pd, ibpd);
308 struct tpt_attributes {
311 enum fw_ri_mem_perms perms;
320 u32 remote_invaliate_disable:1;
322 u32 mw_bind_enable:1;
328 struct ib_umem *umem;
329 struct c4iw_dev *rhp;
331 struct tpt_attributes attr;
334 static inline struct c4iw_mr *to_c4iw_mr(struct ib_mr *ibmr)
336 return container_of(ibmr, struct c4iw_mr, ibmr);
341 struct c4iw_dev *rhp;
343 struct tpt_attributes attr;
346 static inline struct c4iw_mw *to_c4iw_mw(struct ib_mw *ibmw)
348 return container_of(ibmw, struct c4iw_mw, ibmw);
351 struct c4iw_fr_page_list {
352 struct ib_fast_reg_page_list ibpl;
353 DEFINE_DMA_UNMAP_ADDR(mapping);
355 struct c4iw_dev *dev;
359 static inline struct c4iw_fr_page_list *to_c4iw_fr_page_list(
360 struct ib_fast_reg_page_list *ibpl)
362 return container_of(ibpl, struct c4iw_fr_page_list, ibpl);
367 struct c4iw_dev *rhp;
370 spinlock_t comp_handler_lock;
372 wait_queue_head_t wait;
375 static inline struct c4iw_cq *to_c4iw_cq(struct ib_cq *ibcq)
377 return container_of(ibcq, struct c4iw_cq, ibcq);
380 struct c4iw_mpa_attributes {
382 u8 recv_marker_enabled;
383 u8 xmit_marker_enabled;
385 u8 enhanced_rdma_conn;
390 struct c4iw_qp_attributes {
396 u32 sq_max_sges_rdma_write;
400 u8 enable_rdma_write;
402 u8 enable_mmid0_fastreg;
407 char terminate_buffer[52];
408 u32 terminate_msg_len;
409 u8 is_terminate_local;
410 struct c4iw_mpa_attributes mpa_attr;
411 struct c4iw_ep *llp_stream_handle;
420 struct c4iw_dev *rhp;
422 struct c4iw_qp_attributes attr;
427 wait_queue_head_t wait;
428 struct timer_list timer;
431 static inline struct c4iw_qp *to_c4iw_qp(struct ib_qp *ibqp)
433 return container_of(ibqp, struct c4iw_qp, ibqp);
436 struct c4iw_ucontext {
437 struct ib_ucontext ibucontext;
438 struct c4iw_dev_ucontext uctx;
440 spinlock_t mmap_lock;
441 struct list_head mmaps;
444 static inline struct c4iw_ucontext *to_c4iw_ucontext(struct ib_ucontext *c)
446 return container_of(c, struct c4iw_ucontext, ibucontext);
449 struct c4iw_mm_entry {
450 struct list_head entry;
456 static inline struct c4iw_mm_entry *remove_mmap(struct c4iw_ucontext *ucontext,
457 u32 key, unsigned len)
459 struct list_head *pos, *nxt;
460 struct c4iw_mm_entry *mm;
462 spin_lock(&ucontext->mmap_lock);
463 list_for_each_safe(pos, nxt, &ucontext->mmaps) {
465 mm = list_entry(pos, struct c4iw_mm_entry, entry);
466 if (mm->key == key && mm->len == len) {
467 list_del_init(&mm->entry);
468 spin_unlock(&ucontext->mmap_lock);
469 PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
470 key, (unsigned long long) mm->addr, mm->len);
474 spin_unlock(&ucontext->mmap_lock);
478 static inline void insert_mmap(struct c4iw_ucontext *ucontext,
479 struct c4iw_mm_entry *mm)
481 spin_lock(&ucontext->mmap_lock);
482 PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
483 mm->key, (unsigned long long) mm->addr, mm->len);
484 list_add_tail(&mm->entry, &ucontext->mmaps);
485 spin_unlock(&ucontext->mmap_lock);
488 enum c4iw_qp_attr_mask {
489 C4IW_QP_ATTR_NEXT_STATE = 1 << 0,
490 C4IW_QP_ATTR_SQ_DB = 1<<1,
491 C4IW_QP_ATTR_RQ_DB = 1<<2,
492 C4IW_QP_ATTR_ENABLE_RDMA_READ = 1 << 7,
493 C4IW_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8,
494 C4IW_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9,
495 C4IW_QP_ATTR_MAX_ORD = 1 << 11,
496 C4IW_QP_ATTR_MAX_IRD = 1 << 12,
497 C4IW_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22,
498 C4IW_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23,
499 C4IW_QP_ATTR_MPA_ATTR = 1 << 24,
500 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25,
501 C4IW_QP_ATTR_VALID_MODIFY = (C4IW_QP_ATTR_ENABLE_RDMA_READ |
502 C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
503 C4IW_QP_ATTR_MAX_ORD |
504 C4IW_QP_ATTR_MAX_IRD |
505 C4IW_QP_ATTR_LLP_STREAM_HANDLE |
506 C4IW_QP_ATTR_STREAM_MSG_BUFFER |
507 C4IW_QP_ATTR_MPA_ATTR |
508 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE)
511 int c4iw_modify_qp(struct c4iw_dev *rhp,
513 enum c4iw_qp_attr_mask mask,
514 struct c4iw_qp_attributes *attrs,
521 C4IW_QP_STATE_TERMINATE,
522 C4IW_QP_STATE_CLOSING,
526 static inline int c4iw_convert_state(enum ib_qp_state ib_state)
531 return C4IW_QP_STATE_IDLE;
533 return C4IW_QP_STATE_RTS;
535 return C4IW_QP_STATE_CLOSING;
537 return C4IW_QP_STATE_TERMINATE;
539 return C4IW_QP_STATE_ERROR;
545 static inline u32 c4iw_ib_to_tpt_access(int a)
547 return (a & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
548 (a & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0) |
549 (a & IB_ACCESS_LOCAL_WRITE ? FW_RI_MEM_ACCESS_LOCAL_WRITE : 0) |
550 FW_RI_MEM_ACCESS_LOCAL_READ;
553 static inline u32 c4iw_ib_to_tpt_bind_access(int acc)
555 return (acc & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
556 (acc & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0);
559 enum c4iw_mmid_state {
560 C4IW_STAG_STATE_VALID,
561 C4IW_STAG_STATE_INVALID
564 #define C4IW_NODE_DESC "cxgb4 Chelsio Communications"
566 #define MPA_KEY_REQ "MPA ID Req Frame"
567 #define MPA_KEY_REP "MPA ID Rep Frame"
569 #define MPA_MAX_PRIVATE_DATA 256
570 #define MPA_ENHANCED_RDMA_CONN 0x10
571 #define MPA_REJECT 0x20
573 #define MPA_MARKERS 0x80
574 #define MPA_FLAGS_MASK 0xE0
576 #define MPA_V2_PEER2PEER_MODEL 0x8000
577 #define MPA_V2_ZERO_LEN_FPDU_RTR 0x4000
578 #define MPA_V2_RDMA_WRITE_RTR 0x8000
579 #define MPA_V2_RDMA_READ_RTR 0x4000
580 #define MPA_V2_IRD_ORD_MASK 0x3FFF
582 #define c4iw_put_ep(ep) { \
583 PDBG("put_ep (via %s:%u) ep %p refcnt %d\n", __func__, __LINE__, \
584 ep, atomic_read(&((ep)->kref.refcount))); \
585 WARN_ON(atomic_read(&((ep)->kref.refcount)) < 1); \
586 kref_put(&((ep)->kref), _c4iw_free_ep); \
589 #define c4iw_get_ep(ep) { \
590 PDBG("get_ep (via %s:%u) ep %p, refcnt %d\n", __func__, __LINE__, \
591 ep, atomic_read(&((ep)->kref.refcount))); \
592 kref_get(&((ep)->kref)); \
594 void _c4iw_free_ep(struct kref *kref);
600 __be16 private_data_size;
604 struct mpa_v2_conn_params {
609 struct terminate_message {
616 #define TERM_MAX_LENGTH (sizeof(struct terminate_message) + 2 + 18 + 28)
618 enum c4iw_layers_types {
622 RDMAP_LOCAL_CATA = 0x00,
623 RDMAP_REMOTE_PROT = 0x01,
624 RDMAP_REMOTE_OP = 0x02,
625 DDP_LOCAL_CATA = 0x00,
626 DDP_TAGGED_ERR = 0x01,
627 DDP_UNTAGGED_ERR = 0x02,
631 enum c4iw_rdma_ecodes {
632 RDMAP_INV_STAG = 0x00,
633 RDMAP_BASE_BOUNDS = 0x01,
634 RDMAP_ACC_VIOL = 0x02,
635 RDMAP_STAG_NOT_ASSOC = 0x03,
636 RDMAP_TO_WRAP = 0x04,
637 RDMAP_INV_VERS = 0x05,
638 RDMAP_INV_OPCODE = 0x06,
639 RDMAP_STREAM_CATA = 0x07,
640 RDMAP_GLOBAL_CATA = 0x08,
641 RDMAP_CANT_INV_STAG = 0x09,
642 RDMAP_UNSPECIFIED = 0xff
645 enum c4iw_ddp_ecodes {
646 DDPT_INV_STAG = 0x00,
647 DDPT_BASE_BOUNDS = 0x01,
648 DDPT_STAG_NOT_ASSOC = 0x02,
650 DDPT_INV_VERS = 0x04,
652 DDPU_INV_MSN_NOBUF = 0x02,
653 DDPU_INV_MSN_RANGE = 0x03,
655 DDPU_MSG_TOOBIG = 0x05,
659 enum c4iw_mpa_ecodes {
661 MPA_MARKER_ERR = 0x03,
662 MPA_LOCAL_CATA = 0x05,
663 MPA_INSUFF_IRD = 0x06,
664 MPA_NOMATCH_RTR = 0x07,
683 PEER_ABORT_IN_PROGRESS = 0,
684 ABORT_REQ_IN_PROGRESS = 1,
685 RELEASE_RESOURCES = 2,
689 struct c4iw_ep_common {
690 struct iw_cm_id *cm_id;
692 struct c4iw_dev *dev;
693 enum c4iw_ep_state state;
696 struct sockaddr_in local_addr;
697 struct sockaddr_in remote_addr;
698 struct c4iw_wr_wait wr_wait;
702 struct c4iw_listen_ep {
703 struct c4iw_ep_common com;
709 struct c4iw_ep_common com;
710 struct c4iw_ep *parent_ep;
711 struct timer_list timer;
712 struct list_head entry;
717 struct l2t_entry *l2t;
718 struct dst_entry *dst;
719 struct sk_buff *mpa_skb;
720 struct c4iw_mpa_attributes mpa_attr;
721 u8 mpa_pkt[sizeof(struct mpa_message) + MPA_MAX_PRIVATE_DATA];
722 unsigned int mpa_pkt_len;
735 u8 retry_with_mpa_v1;
736 u8 tried_with_mpa_v1;
739 static inline struct c4iw_ep *to_ep(struct iw_cm_id *cm_id)
741 return cm_id->provider_data;
744 static inline struct c4iw_listen_ep *to_listen_ep(struct iw_cm_id *cm_id)
746 return cm_id->provider_data;
749 static inline int compute_wscale(int win)
753 while (wscale < 14 && (65535<<wscale) < win)
758 typedef int (*c4iw_handler_func)(struct c4iw_dev *dev, struct sk_buff *skb);
760 int c4iw_ep_redirect(void *ctx, struct dst_entry *old, struct dst_entry *new,
761 struct l2t_entry *l2t);
762 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qpid,
763 struct c4iw_dev_ucontext *uctx);
764 u32 c4iw_get_resource(struct kfifo *fifo, spinlock_t *lock);
765 void c4iw_put_resource(struct kfifo *fifo, u32 entry, spinlock_t *lock);
766 int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_tpt, u32 nr_pdid);
767 int c4iw_init_ctrl_qp(struct c4iw_rdev *rdev);
768 int c4iw_pblpool_create(struct c4iw_rdev *rdev);
769 int c4iw_rqtpool_create(struct c4iw_rdev *rdev);
770 int c4iw_ocqp_pool_create(struct c4iw_rdev *rdev);
771 void c4iw_pblpool_destroy(struct c4iw_rdev *rdev);
772 void c4iw_rqtpool_destroy(struct c4iw_rdev *rdev);
773 void c4iw_ocqp_pool_destroy(struct c4iw_rdev *rdev);
774 void c4iw_destroy_resource(struct c4iw_resource *rscp);
775 int c4iw_destroy_ctrl_qp(struct c4iw_rdev *rdev);
776 int c4iw_register_device(struct c4iw_dev *dev);
777 void c4iw_unregister_device(struct c4iw_dev *dev);
778 int __init c4iw_cm_init(void);
779 void __exit c4iw_cm_term(void);
780 void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
781 struct c4iw_dev_ucontext *uctx);
782 void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
783 struct c4iw_dev_ucontext *uctx);
784 int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
785 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
786 struct ib_send_wr **bad_wr);
787 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
788 struct ib_recv_wr **bad_wr);
789 int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw,
790 struct ib_mw_bind *mw_bind);
791 int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
792 int c4iw_create_listen(struct iw_cm_id *cm_id, int backlog);
793 int c4iw_destroy_listen(struct iw_cm_id *cm_id);
794 int c4iw_accept_cr(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
795 int c4iw_reject_cr(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len);
796 void c4iw_qp_add_ref(struct ib_qp *qp);
797 void c4iw_qp_rem_ref(struct ib_qp *qp);
798 void c4iw_free_fastreg_pbl(struct ib_fast_reg_page_list *page_list);
799 struct ib_fast_reg_page_list *c4iw_alloc_fastreg_pbl(
800 struct ib_device *device,
802 struct ib_mr *c4iw_alloc_fast_reg_mr(struct ib_pd *pd, int pbl_depth);
803 int c4iw_dealloc_mw(struct ib_mw *mw);
804 struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd);
805 struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start,
806 u64 length, u64 virt, int acc,
807 struct ib_udata *udata);
808 struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc);
809 struct ib_mr *c4iw_register_phys_mem(struct ib_pd *pd,
810 struct ib_phys_buf *buffer_list,
814 int c4iw_reregister_phys_mem(struct ib_mr *mr,
817 struct ib_phys_buf *buffer_list,
819 int acc, u64 *iova_start);
820 int c4iw_dereg_mr(struct ib_mr *ib_mr);
821 int c4iw_destroy_cq(struct ib_cq *ib_cq);
822 struct ib_cq *c4iw_create_cq(struct ib_device *ibdev, int entries,
824 struct ib_ucontext *ib_context,
825 struct ib_udata *udata);
826 int c4iw_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata);
827 int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
828 int c4iw_destroy_qp(struct ib_qp *ib_qp);
829 struct ib_qp *c4iw_create_qp(struct ib_pd *pd,
830 struct ib_qp_init_attr *attrs,
831 struct ib_udata *udata);
832 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
833 int attr_mask, struct ib_udata *udata);
834 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn);
835 u32 c4iw_rqtpool_alloc(struct c4iw_rdev *rdev, int size);
836 void c4iw_rqtpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
837 u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size);
838 void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
839 u32 c4iw_ocqp_pool_alloc(struct c4iw_rdev *rdev, int size);
840 void c4iw_ocqp_pool_free(struct c4iw_rdev *rdev, u32 addr, int size);
841 int c4iw_ofld_send(struct c4iw_rdev *rdev, struct sk_buff *skb);
842 void c4iw_flush_hw_cq(struct t4_cq *cq);
843 void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
844 void c4iw_count_scqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
845 int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp);
846 int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count);
847 int c4iw_flush_sq(struct t4_wq *wq, struct t4_cq *cq, int count);
848 int c4iw_ev_handler(struct c4iw_dev *rnicp, u32 qid);
849 u16 c4iw_rqes_posted(struct c4iw_qp *qhp);
850 int c4iw_post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe);
851 u32 c4iw_get_cqid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
852 void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid,
853 struct c4iw_dev_ucontext *uctx);
854 u32 c4iw_get_qpid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
855 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qid,
856 struct c4iw_dev_ucontext *uctx);
857 void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe);
859 extern struct cxgb4_client t4c_client;
860 extern c4iw_handler_func c4iw_handlers[NUM_CPL_CMDS];
861 extern int c4iw_max_read_depth;
862 extern int db_fc_threshold;