drivers/infiniband/hw/cxgb3/cxio_hal.c

   1 /*
   2  * Copyright (c) 2006 Chelsio, Inc. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32 #include <asm/delay.h>
  33
  34 #include <linux/mutex.h>
  35 #include <linux/netdevice.h>
  36 #include <linux/sched.h>
  37 #include <linux/spinlock.h>
  38 #include <linux/pci.h>
  39 #include <linux/dma-mapping.h>
  40 #include <net/net_namespace.h>
  41
  42 #include "cxio_resource.h"
  43 #include "cxio_hal.h"
  44 #include "cxgb3_offload.h"
  45 #include "sge_defs.h"
  46
  47 static LIST_HEAD(rdev_list);
  48 static cxio_hal_ev_callback_func_t cxio_ev_cb = NULL;
  49
  50 static struct cxio_rdev *cxio_hal_find_rdev_by_name(char *dev_name)
  51 {
  52         struct cxio_rdev *rdev;
  53
  54         list_for_each_entry(rdev, &rdev_list, entry)
  55                 if (!strcmp(rdev->dev_name, dev_name))
  56                         return rdev;
  57         return NULL;
  58 }
  59
  60 static struct cxio_rdev *cxio_hal_find_rdev_by_t3cdev(struct t3cdev *tdev)
  61 {
  62         struct cxio_rdev *rdev;
  63
  64         list_for_each_entry(rdev, &rdev_list, entry)
  65                 if (rdev->t3cdev_p == tdev)
  66                         return rdev;
  67         return NULL;
  68 }
  69
  70 int cxio_hal_cq_op(struct cxio_rdev *rdev_p, struct t3_cq *cq,
  71                    enum t3_cq_opcode op, u32 credit)
  72 {
  73         int ret;
  74         struct t3_cqe *cqe;
  75         u32 rptr;
  76
  77         struct rdma_cq_op setup;
  78         setup.id = cq->cqid;
  79         setup.credits = (op == CQ_CREDIT_UPDATE) ? credit : 0;
  80         setup.op = op;
  81         ret = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_OP, &setup);
  82
  83         if ((ret < 0) || (op == CQ_CREDIT_UPDATE))
  84                 return ret;
  85
  86         /*
  87          * If the rearm returned an index other than our current index,
  88          * then there might be CQE's in flight (being DMA'd).  We must wait
  89          * here for them to complete or the consumer can miss a notification.
  90          */
  91         if (Q_PTR2IDX((cq->rptr), cq->size_log2) != ret) {
  92                 int i=0;
  93
  94                 rptr = cq->rptr;
  95
  96                 /*
  97                  * Keep the generation correct by bumping rptr until it
  98                  * matches the index returned by the rearm - 1.
  99                  */
 100                 while (Q_PTR2IDX((rptr+1), cq->size_log2) != ret)
 101                         rptr++;
 102
 103                 /*
 104                  * Now rptr is the index for the (last) cqe that was
 105                  * in-flight at the time the HW rearmed the CQ.  We
 106                  * spin until that CQE is valid.
 107                  */
 108                 cqe = cq->queue + Q_PTR2IDX(rptr, cq->size_log2);
 109                 while (!CQ_VLD_ENTRY(rptr, cq->size_log2, cqe)) {
 110                         udelay(1);
 111                         if (i++ > 1000000) {
 112                                 BUG_ON(1);
 113                                 printk(KERN_ERR "%s: stalled rnic\n",
 114                                        rdev_p->dev_name);
 115                                 return -EIO;
 116                         }
 117                 }
 118
 119                 return 1;
 120         }
 121
 122         return 0;
 123 }
 124
 125 static int cxio_hal_clear_cq_ctx(struct cxio_rdev *rdev_p, u32 cqid)
 126 {
 127         struct rdma_cq_setup setup;
 128         setup.id = cqid;
 129         setup.base_addr = 0;    /* NULL address */
 130         setup.size = 0;         /* disaable the CQ */
 131         setup.credits = 0;
 132         setup.credit_thres = 0;
 133         setup.ovfl_mode = 0;
 134         return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
 135 }
 136
 137 static int cxio_hal_clear_qp_ctx(struct cxio_rdev *rdev_p, u32 qpid)
 138 {
 139         u64 sge_cmd;
 140         struct t3_modify_qp_wr *wqe;
 141         struct sk_buff *skb = alloc_skb(sizeof(*wqe), GFP_KERNEL);
 142         if (!skb) {
 143                 PDBG("%s alloc_skb failed\n", __func__);
 144                 return -ENOMEM;
 145         }
 146         wqe = (struct t3_modify_qp_wr *) skb_put(skb, sizeof(*wqe));
 147         memset(wqe, 0, sizeof(*wqe));
 148         build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_QP_MOD, 3, 0, qpid, 7);
 149         wqe->flags = cpu_to_be32(MODQP_WRITE_EC);
 150         sge_cmd = qpid << 8 | 3;
 151         wqe->sge_cmd = cpu_to_be64(sge_cmd);
 152         skb->priority = CPL_PRIORITY_CONTROL;
 153         return (cxgb3_ofld_send(rdev_p->t3cdev_p, skb));
 154 }
 155
 156 int cxio_create_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq)
 157 {
 158         struct rdma_cq_setup setup;
 159         int size = (1UL << (cq->size_log2)) * sizeof(struct t3_cqe);
 160
 161         cq->cqid = cxio_hal_get_cqid(rdev_p->rscp);
 162         if (!cq->cqid)
 163                 return -ENOMEM;
 164         cq->sw_queue = kzalloc(size, GFP_KERNEL);
 165         if (!cq->sw_queue)
 166                 return -ENOMEM;
 167         cq->queue = dma_alloc_coherent(&(rdev_p->rnic_info.pdev->dev),
 168                                              (1UL << (cq->size_log2)) *
 169                                              sizeof(struct t3_cqe),
 170                                              &(cq->dma_addr), GFP_KERNEL);
 171         if (!cq->queue) {
 172                 kfree(cq->sw_queue);
 173                 return -ENOMEM;
 174         }
 175         pci_unmap_addr_set(cq, mapping, cq->dma_addr);
 176         memset(cq->queue, 0, size);
 177         setup.id = cq->cqid;
 178         setup.base_addr = (u64) (cq->dma_addr);
 179         setup.size = 1UL << cq->size_log2;
 180         setup.credits = 65535;
 181         setup.credit_thres = 1;
 182         if (rdev_p->t3cdev_p->type != T3A)
 183                 setup.ovfl_mode = 0;
 184         else
 185                 setup.ovfl_mode = 1;
 186         return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
 187 }
 188
 189 int cxio_resize_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq)
 190 {
 191         struct rdma_cq_setup setup;
 192         setup.id = cq->cqid;
 193         setup.base_addr = (u64) (cq->dma_addr);
 194         setup.size = 1UL << cq->size_log2;
 195         setup.credits = setup.size;
 196         setup.credit_thres = setup.size;        /* TBD: overflow recovery */
 197         setup.ovfl_mode = 1;
 198         return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
 199 }
 200
 201 static u32 get_qpid(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
 202 {
 203         struct cxio_qpid_list *entry;
 204         u32 qpid;
 205         int i;
 206
 207         mutex_lock(&uctx->lock);
 208         if (!list_empty(&uctx->qpids)) {
 209                 entry = list_entry(uctx->qpids.next, struct cxio_qpid_list,
 210                                    entry);
 211                 list_del(&entry->entry);
 212                 qpid = entry->qpid;
 213                 kfree(entry);
 214         } else {
 215                 qpid = cxio_hal_get_qpid(rdev_p->rscp);
 216                 if (!qpid)
 217                         goto out;
 218                 for (i = qpid+1; i & rdev_p->qpmask; i++) {
 219                         entry = kmalloc(sizeof *entry, GFP_KERNEL);
 220                         if (!entry)
 221                                 break;
 222                         entry->qpid = i;
 223                         list_add_tail(&entry->entry, &uctx->qpids);
 224                 }
 225         }
 226 out:
 227         mutex_unlock(&uctx->lock);
 228         PDBG("%s qpid 0x%x\n", __func__, qpid);
 229         return qpid;
 230 }
 231
 232 static void put_qpid(struct cxio_rdev *rdev_p, u32 qpid,
 233                      struct cxio_ucontext *uctx)
 234 {
 235         struct cxio_qpid_list *entry;
 236
 237         entry = kmalloc(sizeof *entry, GFP_KERNEL);
 238         if (!entry)
 239                 return;
 240         PDBG("%s qpid 0x%x\n", __func__, qpid);
 241         entry->qpid = qpid;
 242         mutex_lock(&uctx->lock);
 243         list_add_tail(&entry->entry, &uctx->qpids);
 244         mutex_unlock(&uctx->lock);
 245 }
 246
 247 void cxio_release_ucontext(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
 248 {
 249         struct list_head *pos, *nxt;
 250         struct cxio_qpid_list *entry;
 251
 252         mutex_lock(&uctx->lock);
 253         list_for_each_safe(pos, nxt, &uctx->qpids) {
 254                 entry = list_entry(pos, struct cxio_qpid_list, entry);
 255                 list_del_init(&entry->entry);
 256                 if (!(entry->qpid & rdev_p->qpmask))
 257                         cxio_hal_put_qpid(rdev_p->rscp, entry->qpid);
 258                 kfree(entry);
 259         }
 260         mutex_unlock(&uctx->lock);
 261 }
 262
 263 void cxio_init_ucontext(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
 264 {
 265         INIT_LIST_HEAD(&uctx->qpids);
 266         mutex_init(&uctx->lock);
 267 }
 268
 269 int cxio_create_qp(struct cxio_rdev *rdev_p, u32 kernel_domain,
 270                    struct t3_wq *wq, struct cxio_ucontext *uctx)
 271 {
 272         int depth = 1UL << wq->size_log2;
 273         int rqsize = 1UL << wq->rq_size_log2;
 274
 275         wq->qpid = get_qpid(rdev_p, uctx);
 276         if (!wq->qpid)
 277                 return -ENOMEM;
 278
 279         wq->rq = kzalloc(depth * sizeof(u64), GFP_KERNEL);
 280         if (!wq->rq)
 281                 goto err1;
 282
 283         wq->rq_addr = cxio_hal_rqtpool_alloc(rdev_p, rqsize);
 284         if (!wq->rq_addr)
 285                 goto err2;
 286
 287         wq->sq = kzalloc(depth * sizeof(struct t3_swsq), GFP_KERNEL);
 288         if (!wq->sq)
 289                 goto err3;
 290
 291         wq->queue = dma_alloc_coherent(&(rdev_p->rnic_info.pdev->dev),
 292                                              depth * sizeof(union t3_wr),
 293                                              &(wq->dma_addr), GFP_KERNEL);
 294         if (!wq->queue)
 295                 goto err4;
 296
 297         memset(wq->queue, 0, depth * sizeof(union t3_wr));
 298         pci_unmap_addr_set(wq, mapping, wq->dma_addr);
 299         wq->doorbell = (void __iomem *)rdev_p->rnic_info.kdb_addr;
 300         if (!kernel_domain)
 301                 wq->udb = (u64)rdev_p->rnic_info.udbell_physbase +
 302                                         (wq->qpid << rdev_p->qpshift);
 303         PDBG("%s qpid 0x%x doorbell 0x%p udb 0x%llx\n", __func__,
 304              wq->qpid, wq->doorbell, (unsigned long long) wq->udb);
 305         return 0;
 306 err4:
 307         kfree(wq->sq);
 308 err3:
 309         cxio_hal_rqtpool_free(rdev_p, wq->rq_addr, rqsize);
 310 err2:
 311         kfree(wq->rq);
 312 err1:
 313         put_qpid(rdev_p, wq->qpid, uctx);
 314         return -ENOMEM;
 315 }
 316
 317 int cxio_destroy_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq)
 318 {
 319         int err;
 320         err = cxio_hal_clear_cq_ctx(rdev_p, cq->cqid);
 321         kfree(cq->sw_queue);
 322         dma_free_coherent(&(rdev_p->rnic_info.pdev->dev),
 323                           (1UL << (cq->size_log2))
 324                           * sizeof(struct t3_cqe), cq->queue,
 325                           pci_unmap_addr(cq, mapping));
 326         cxio_hal_put_cqid(rdev_p->rscp, cq->cqid);
 327         return err;
 328 }
 329
 330 int cxio_destroy_qp(struct cxio_rdev *rdev_p, struct t3_wq *wq,
 331                     struct cxio_ucontext *uctx)
 332 {
 333         dma_free_coherent(&(rdev_p->rnic_info.pdev->dev),
 334                           (1UL << (wq->size_log2))
 335                           * sizeof(union t3_wr), wq->queue,
 336                           pci_unmap_addr(wq, mapping));
 337         kfree(wq->sq);
 338         cxio_hal_rqtpool_free(rdev_p, wq->rq_addr, (1UL << wq->rq_size_log2));
 339         kfree(wq->rq);
 340         put_qpid(rdev_p, wq->qpid, uctx);
 341         return 0;
 342 }
 343
 344 static void insert_recv_cqe(struct t3_wq *wq, struct t3_cq *cq)
 345 {
 346         struct t3_cqe cqe;
 347
 348         PDBG("%s wq %p cq %p sw_rptr 0x%x sw_wptr 0x%x\n", __func__,
 349              wq, cq, cq->sw_rptr, cq->sw_wptr);
 350         memset(&cqe, 0, sizeof(cqe));
 351         cqe.header = cpu_to_be32(V_CQE_STATUS(TPT_ERR_SWFLUSH) |
 352                                  V_CQE_OPCODE(T3_SEND) |
 353                                  V_CQE_TYPE(0) |
 354                                  V_CQE_SWCQE(1) |
 355                                  V_CQE_QPID(wq->qpid) |
 356                                  V_CQE_GENBIT(Q_GENBIT(cq->sw_wptr,
 357                                                        cq->size_log2)));
 358         *(cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2)) = cqe;
 359         cq->sw_wptr++;
 360 }
 361
 362 int cxio_flush_rq(struct t3_wq *wq, struct t3_cq *cq, int count)
 363 {
 364         u32 ptr;
 365         int flushed = 0;
 366
 367         PDBG("%s wq %p cq %p\n", __func__, wq, cq);
 368
 369         /* flush RQ */
 370         PDBG("%s rq_rptr %u rq_wptr %u skip count %u\n", __func__,
 371             wq->rq_rptr, wq->rq_wptr, count);
 372         ptr = wq->rq_rptr + count;
 373         while (ptr++ != wq->rq_wptr) {
 374                 insert_recv_cqe(wq, cq);
 375                 flushed++;
 376         }
 377         return flushed;
 378 }
 379
 380 static void insert_sq_cqe(struct t3_wq *wq, struct t3_cq *cq,
 381                           struct t3_swsq *sqp)
 382 {
 383         struct t3_cqe cqe;
 384
 385         PDBG("%s wq %p cq %p sw_rptr 0x%x sw_wptr 0x%x\n", __func__,
 386              wq, cq, cq->sw_rptr, cq->sw_wptr);
 387         memset(&cqe, 0, sizeof(cqe));
 388         cqe.header = cpu_to_be32(V_CQE_STATUS(TPT_ERR_SWFLUSH) |
 389                                  V_CQE_OPCODE(sqp->opcode) |
 390                                  V_CQE_TYPE(1) |
 391                                  V_CQE_SWCQE(1) |
 392                                  V_CQE_QPID(wq->qpid) |
 393                                  V_CQE_GENBIT(Q_GENBIT(cq->sw_wptr,
 394                                                        cq->size_log2)));
 395         cqe.u.scqe.wrid_hi = sqp->sq_wptr;
 396
 397         *(cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2)) = cqe;
 398         cq->sw_wptr++;
 399 }
 400
 401 int cxio_flush_sq(struct t3_wq *wq, struct t3_cq *cq, int count)
 402 {
 403         __u32 ptr;
 404         int flushed = 0;
 405         struct t3_swsq *sqp = wq->sq + Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2);
 406
 407         ptr = wq->sq_rptr + count;
 408         sqp = wq->sq + Q_PTR2IDX(ptr, wq->sq_size_log2);
 409         while (ptr != wq->sq_wptr) {
 410                 insert_sq_cqe(wq, cq, sqp);
 411                 ptr++;
 412                 sqp = wq->sq + Q_PTR2IDX(ptr, wq->sq_size_log2);
 413                 flushed++;
 414         }
 415         return flushed;
 416 }
 417
 418 /*
 419  * Move all CQEs from the HWCQ into the SWCQ.
 420  */
 421 void cxio_flush_hw_cq(struct t3_cq *cq)
 422 {
 423         struct t3_cqe *cqe, *swcqe;
 424
 425         PDBG("%s cq %p cqid 0x%x\n", __func__, cq, cq->cqid);
 426         cqe = cxio_next_hw_cqe(cq);
 427         while (cqe) {
 428                 PDBG("%s flushing hwcq rptr 0x%x to swcq wptr 0x%x\n",
 429                      __func__, cq->rptr, cq->sw_wptr);
 430                 swcqe = cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2);
 431                 *swcqe = *cqe;
 432                 swcqe->header |= cpu_to_be32(V_CQE_SWCQE(1));
 433                 cq->sw_wptr++;
 434                 cq->rptr++;
 435                 cqe = cxio_next_hw_cqe(cq);
 436         }
 437 }
 438
 439 static int cqe_completes_wr(struct t3_cqe *cqe, struct t3_wq *wq)
 440 {
 441         if (CQE_OPCODE(*cqe) == T3_TERMINATE)
 442                 return 0;
 443
 444         if ((CQE_OPCODE(*cqe) == T3_RDMA_WRITE) && RQ_TYPE(*cqe))
 445                 return 0;
 446
 447         if ((CQE_OPCODE(*cqe) == T3_READ_RESP) && SQ_TYPE(*cqe))
 448                 return 0;
 449
 450         if ((CQE_OPCODE(*cqe) == T3_SEND) && RQ_TYPE(*cqe) &&
 451             Q_EMPTY(wq->rq_rptr, wq->rq_wptr))
 452                 return 0;
 453
 454         return 1;
 455 }
 456
 457 void cxio_count_scqes(struct t3_cq *cq, struct t3_wq *wq, int *count)
 458 {
 459         struct t3_cqe *cqe;
 460         u32 ptr;
 461
 462         *count = 0;
 463         ptr = cq->sw_rptr;
 464         while (!Q_EMPTY(ptr, cq->sw_wptr)) {
 465                 cqe = cq->sw_queue + (Q_PTR2IDX(ptr, cq->size_log2));
 466                 if ((SQ_TYPE(*cqe) ||
 467                      ((CQE_OPCODE(*cqe) == T3_READ_RESP) && wq->oldest_read)) &&
 468                     (CQE_QPID(*cqe) == wq->qpid))
 469                         (*count)++;
 470                 ptr++;
 471         }
 472         PDBG("%s cq %p count %d\n", __func__, cq, *count);
 473 }
 474
 475 void cxio_count_rcqes(struct t3_cq *cq, struct t3_wq *wq, int *count)
 476 {
 477         struct t3_cqe *cqe;
 478         u32 ptr;
 479
 480         *count = 0;
 481         PDBG("%s count zero %d\n", __func__, *count);
 482         ptr = cq->sw_rptr;
 483         while (!Q_EMPTY(ptr, cq->sw_wptr)) {
 484                 cqe = cq->sw_queue + (Q_PTR2IDX(ptr, cq->size_log2));
 485                 if (RQ_TYPE(*cqe) && (CQE_OPCODE(*cqe) != T3_READ_RESP) &&
 486                     (CQE_QPID(*cqe) == wq->qpid) && cqe_completes_wr(cqe, wq))
 487                         (*count)++;
 488                 ptr++;
 489         }
 490         PDBG("%s cq %p count %d\n", __func__, cq, *count);
 491 }
 492
 493 static int cxio_hal_init_ctrl_cq(struct cxio_rdev *rdev_p)
 494 {
 495         struct rdma_cq_setup setup;
 496         setup.id = 0;
 497         setup.base_addr = 0;    /* NULL address */
 498         setup.size = 1;         /* enable the CQ */
 499         setup.credits = 0;
 500
 501         /* force SGE to redirect to RspQ and interrupt */
 502         setup.credit_thres = 0;
 503         setup.ovfl_mode = 1;
 504         return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
 505 }
 506
 507 static int cxio_hal_init_ctrl_qp(struct cxio_rdev *rdev_p)
 508 {
 509         int err;
 510         u64 sge_cmd, ctx0, ctx1;
 511         u64 base_addr;
 512         struct t3_modify_qp_wr *wqe;
 513         struct sk_buff *skb;
 514
 515         skb = alloc_skb(sizeof(*wqe), GFP_KERNEL);
 516         if (!skb) {
 517                 PDBG("%s alloc_skb failed\n", __func__);
 518                 return -ENOMEM;
 519         }
 520         err = cxio_hal_init_ctrl_cq(rdev_p);
 521         if (err) {
 522                 PDBG("%s err %d initializing ctrl_cq\n", __func__, err);
 523                 goto err;
 524         }
 525         rdev_p->ctrl_qp.workq = dma_alloc_coherent(
 526                                         &(rdev_p->rnic_info.pdev->dev),
 527                                         (1 << T3_CTRL_QP_SIZE_LOG2) *
 528                                         sizeof(union t3_wr),
 529                                         &(rdev_p->ctrl_qp.dma_addr),
 530                                         GFP_KERNEL);
 531         if (!rdev_p->ctrl_qp.workq) {
 532                 PDBG("%s dma_alloc_coherent failed\n", __func__);
 533                 err = -ENOMEM;
 534                 goto err;
 535         }
 536         pci_unmap_addr_set(&rdev_p->ctrl_qp, mapping,
 537                            rdev_p->ctrl_qp.dma_addr);
 538         rdev_p->ctrl_qp.doorbell = (void __iomem *)rdev_p->rnic_info.kdb_addr;
 539         memset(rdev_p->ctrl_qp.workq, 0,
 540                (1 << T3_CTRL_QP_SIZE_LOG2) * sizeof(union t3_wr));
 541
 542         mutex_init(&rdev_p->ctrl_qp.lock);
 543         init_waitqueue_head(&rdev_p->ctrl_qp.waitq);
 544
 545         /* update HW Ctrl QP context */
 546         base_addr = rdev_p->ctrl_qp.dma_addr;
 547         base_addr >>= 12;
 548         ctx0 = (V_EC_SIZE((1 << T3_CTRL_QP_SIZE_LOG2)) |
 549                 V_EC_BASE_LO((u32) base_addr & 0xffff));
 550         ctx0 <<= 32;
 551         ctx0 |= V_EC_CREDITS(FW_WR_NUM);
 552         base_addr >>= 16;
 553         ctx1 = (u32) base_addr;
 554         base_addr >>= 32;
 555         ctx1 |= ((u64) (V_EC_BASE_HI((u32) base_addr & 0xf) | V_EC_RESPQ(0) |
 556                         V_EC_TYPE(0) | V_EC_GEN(1) |
 557                         V_EC_UP_TOKEN(T3_CTL_QP_TID) | F_EC_VALID)) << 32;
 558         wqe = (struct t3_modify_qp_wr *) skb_put(skb, sizeof(*wqe));
 559         memset(wqe, 0, sizeof(*wqe));
 560         build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_QP_MOD, 0, 0,
 561                        T3_CTL_QP_TID, 7);
 562         wqe->flags = cpu_to_be32(MODQP_WRITE_EC);
 563         sge_cmd = (3ULL << 56) | FW_RI_SGEEC_START << 8 | 3;
 564         wqe->sge_cmd = cpu_to_be64(sge_cmd);
 565         wqe->ctx1 = cpu_to_be64(ctx1);
 566         wqe->ctx0 = cpu_to_be64(ctx0);
 567         PDBG("CtrlQP dma_addr 0x%llx workq %p size %d\n",
 568              (unsigned long long) rdev_p->ctrl_qp.dma_addr,
 569              rdev_p->ctrl_qp.workq, 1 << T3_CTRL_QP_SIZE_LOG2);
 570         skb->priority = CPL_PRIORITY_CONTROL;
 571         return (cxgb3_ofld_send(rdev_p->t3cdev_p, skb));
 572 err:
 573         kfree_skb(skb);
 574         return err;
 575 }
 576
 577 static int cxio_hal_destroy_ctrl_qp(struct cxio_rdev *rdev_p)
 578 {
 579         dma_free_coherent(&(rdev_p->rnic_info.pdev->dev),
 580                           (1UL << T3_CTRL_QP_SIZE_LOG2)
 581                           * sizeof(union t3_wr), rdev_p->ctrl_qp.workq,
 582                           pci_unmap_addr(&rdev_p->ctrl_qp, mapping));
 583         return cxio_hal_clear_qp_ctx(rdev_p, T3_CTRL_QP_ID);
 584 }
 585
 586 /* write len bytes of data into addr (32B aligned address)
 587  * If data is NULL, clear len byte of memory to zero.
 588  * caller aquires the ctrl_qp lock before the call
 589  */
 590 static int cxio_hal_ctrl_qp_write_mem(struct cxio_rdev *rdev_p, u32 addr,
 591                                       u32 len, void *data)
 592 {
 593         u32 i, nr_wqe, copy_len;
 594         u8 *copy_data;
 595         u8 wr_len, utx_len;     /* length in 8 byte flit */
 596         enum t3_wr_flags flag;
 597         __be64 *wqe;
 598         u64 utx_cmd;
 599         addr &= 0x7FFFFFF;
 600         nr_wqe = len % 96 ? len / 96 + 1 : len / 96;    /* 96B max per WQE */
 601         PDBG("%s wptr 0x%x rptr 0x%x len %d, nr_wqe %d data %p addr 0x%0x\n",
 602              __func__, rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, len,
 603              nr_wqe, data, addr);
 604         utx_len = 3;            /* in 32B unit */
 605         for (i = 0; i < nr_wqe; i++) {
 606                 if (Q_FULL(rdev_p->ctrl_qp.rptr, rdev_p->ctrl_qp.wptr,
 607                            T3_CTRL_QP_SIZE_LOG2)) {
 608                         PDBG("%s ctrl_qp full wtpr 0x%0x rptr 0x%0x, "
 609                              "wait for more space i %d\n", __func__,
 610                              rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, i);
 611                         if (wait_event_interruptible(rdev_p->ctrl_qp.waitq,
 612                                              !Q_FULL(rdev_p->ctrl_qp.rptr,
 613                                                      rdev_p->ctrl_qp.wptr,
 614                                                      T3_CTRL_QP_SIZE_LOG2))) {
 615                                 PDBG("%s ctrl_qp workq interrupted\n",
 616                                      __func__);
 617                                 return -ERESTARTSYS;
 618                         }
 619                         PDBG("%s ctrl_qp wakeup, continue posting work request "
 620                              "i %d\n", __func__, i);
 621                 }
 622                 wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr %
 623                                                 (1 << T3_CTRL_QP_SIZE_LOG2)));
 624                 flag = 0;
 625                 if (i == (nr_wqe - 1)) {
 626                         /* last WQE */
 627                         flag = T3_COMPLETION_FLAG;
 628                         if (len % 32)
 629                                 utx_len = len / 32 + 1;
 630                         else
 631                                 utx_len = len / 32;
 632                 }
 633
 634                 /*
 635                  * Force a CQE to return the credit to the workq in case
 636                  * we posted more than half the max QP size of WRs
 637                  */
 638                 if ((i != 0) &&
 639                     (i % (((1 << T3_CTRL_QP_SIZE_LOG2)) >> 1) == 0)) {
 640                         flag = T3_COMPLETION_FLAG;
 641                         PDBG("%s force completion at i %d\n", __func__, i);
 642                 }
 643
 644                 /* build the utx mem command */
 645                 wqe += (sizeof(struct t3_bypass_wr) >> 3);
 646                 utx_cmd = (T3_UTX_MEM_WRITE << 28) | (addr + i * 3);
 647                 utx_cmd <<= 32;
 648                 utx_cmd |= (utx_len << 28) | ((utx_len << 2) + 1);
 649                 *wqe = cpu_to_be64(utx_cmd);
 650                 wqe++;
 651                 copy_data = (u8 *) data + i * 96;
 652                 copy_len = len > 96 ? 96 : len;
 653
 654                 /* clear memory content if data is NULL */
 655                 if (data)
 656                         memcpy(wqe, copy_data, copy_len);
 657                 else
 658                         memset(wqe, 0, copy_len);
 659                 if (copy_len % 32)
 660                         memset(((u8 *) wqe) + copy_len, 0,
 661                                32 - (copy_len % 32));
 662                 wr_len = ((sizeof(struct t3_bypass_wr)) >> 3) + 1 +
 663                          (utx_len << 2);
 664                 wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr %
 665                               (1 << T3_CTRL_QP_SIZE_LOG2)));
 666
 667                 /* wptr in the WRID[31:0] */
 668                 ((union t3_wrid *)(wqe+1))->id0.low = rdev_p->ctrl_qp.wptr;
 669
 670                 /*
 671                  * This must be the last write with a memory barrier
 672                  * for the genbit
 673                  */
 674                 build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_BP, flag,
 675                                Q_GENBIT(rdev_p->ctrl_qp.wptr,
 676                                         T3_CTRL_QP_SIZE_LOG2), T3_CTRL_QP_ID,
 677                                wr_len);
 678                 if (flag == T3_COMPLETION_FLAG)
 679                         ring_doorbell(rdev_p->ctrl_qp.doorbell, T3_CTRL_QP_ID);
 680                 len -= 96;
 681                 rdev_p->ctrl_qp.wptr++;
 682         }
 683         return 0;
 684 }
 685
 686 /* IN: stag key, pdid, perm, zbva, to, len, page_size, pbl_size and pbl_addr
 687  * OUT: stag index
 688  * TBD: shared memory region support
 689  */
 690 static int __cxio_tpt_op(struct cxio_rdev *rdev_p, u32 reset_tpt_entry,
 691                          u32 *stag, u8 stag_state, u32 pdid,
 692                          enum tpt_mem_type type, enum tpt_mem_perm perm,
 693                          u32 zbva, u64 to, u32 len, u8 page_size,
 694                          u32 pbl_size, u32 pbl_addr)
 695 {
 696         int err;
 697         struct tpt_entry tpt;
 698         u32 stag_idx;
 699         u32 wptr;
 700
 701         stag_state = stag_state > 0;
 702         stag_idx = (*stag) >> 8;
 703
 704         if ((!reset_tpt_entry) && !(*stag != T3_STAG_UNSET)) {
 705                 stag_idx = cxio_hal_get_stag(rdev_p->rscp);
 706                 if (!stag_idx)
 707                         return -ENOMEM;
 708                 *stag = (stag_idx << 8) | ((*stag) & 0xFF);
 709         }
 710         PDBG("%s stag_state 0x%0x type 0x%0x pdid 0x%0x, stag_idx 0x%x\n",
 711              __func__, stag_state, type, pdid, stag_idx);
 712
 713         mutex_lock(&rdev_p->ctrl_qp.lock);
 714
 715         /* write TPT entry */
 716         if (reset_tpt_entry)
 717                 memset(&tpt, 0, sizeof(tpt));
 718         else {
 719                 tpt.valid_stag_pdid = cpu_to_be32(F_TPT_VALID |
 720                                 V_TPT_STAG_KEY((*stag) & M_TPT_STAG_KEY) |
 721                                 V_TPT_STAG_STATE(stag_state) |
 722                                 V_TPT_STAG_TYPE(type) | V_TPT_PDID(pdid));
 723                 BUG_ON(page_size >= 28);
 724                 tpt.flags_pagesize_qpid = cpu_to_be32(V_TPT_PERM(perm) |
 725                                 F_TPT_MW_BIND_ENABLE |
 726                                 V_TPT_ADDR_TYPE((zbva ? TPT_ZBTO : TPT_VATO)) |
 727                                 V_TPT_PAGE_SIZE(page_size));
 728                 tpt.rsvd_pbl_addr = reset_tpt_entry ? 0 :
 729                                     cpu_to_be32(V_TPT_PBL_ADDR(PBL_OFF(rdev_p, pbl_addr)>>3));
 730                 tpt.len = cpu_to_be32(len);
 731                 tpt.va_hi = cpu_to_be32((u32) (to >> 32));
 732                 tpt.va_low_or_fbo = cpu_to_be32((u32) (to & 0xFFFFFFFFULL));
 733                 tpt.rsvd_bind_cnt_or_pstag = 0;
 734                 tpt.rsvd_pbl_size = reset_tpt_entry ? 0 :
 735                                   cpu_to_be32(V_TPT_PBL_SIZE(pbl_size >> 2));
 736         }
 737         err = cxio_hal_ctrl_qp_write_mem(rdev_p,
 738                                        stag_idx +
 739                                        (rdev_p->rnic_info.tpt_base >> 5),
 740                                        sizeof(tpt), &tpt);
 741
 742         /* release the stag index to free pool */
 743         if (reset_tpt_entry)
 744                 cxio_hal_put_stag(rdev_p->rscp, stag_idx);
 745
 746         wptr = rdev_p->ctrl_qp.wptr;
 747         mutex_unlock(&rdev_p->ctrl_qp.lock);
 748         if (!err)
 749                 if (wait_event_interruptible(rdev_p->ctrl_qp.waitq,
 750                                              SEQ32_GE(rdev_p->ctrl_qp.rptr,
 751                                                       wptr)))
 752                         return -ERESTARTSYS;
 753         return err;
 754 }
 755
 756 int cxio_write_pbl(struct cxio_rdev *rdev_p, __be64 *pbl,
 757                    u32 pbl_addr, u32 pbl_size)
 758 {
 759         u32 wptr;
 760         int err;
 761
 762         PDBG("%s *pdb_addr 0x%x, pbl_base 0x%x, pbl_size %d\n",
 763              __func__, pbl_addr, rdev_p->rnic_info.pbl_base,
 764              pbl_size);
 765
 766         mutex_lock(&rdev_p->ctrl_qp.lock);
 767         err = cxio_hal_ctrl_qp_write_mem(rdev_p, pbl_addr >> 5, pbl_size << 3,
 768                                          pbl);
 769         wptr = rdev_p->ctrl_qp.wptr;
 770         mutex_unlock(&rdev_p->ctrl_qp.lock);
 771         if (err)
 772                 return err;
 773
 774         if (wait_event_interruptible(rdev_p->ctrl_qp.waitq,
 775                                      SEQ32_GE(rdev_p->ctrl_qp.rptr,
 776                                               wptr)))
 777                 return -ERESTARTSYS;
 778
 779         return 0;
 780 }
 781
 782 int cxio_register_phys_mem(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid,
 783                            enum tpt_mem_perm perm, u32 zbva, u64 to, u32 len,
 784                            u8 page_size, u32 pbl_size, u32 pbl_addr)
 785 {
 786         *stag = T3_STAG_UNSET;
 787         return __cxio_tpt_op(rdev_p, 0, stag, 1, pdid, TPT_NON_SHARED_MR, perm,
 788                              zbva, to, len, page_size, pbl_size, pbl_addr);
 789 }
 790
 791 int cxio_reregister_phys_mem(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid,
 792                            enum tpt_mem_perm perm, u32 zbva, u64 to, u32 len,
 793                            u8 page_size, u32 pbl_size, u32 pbl_addr)
 794 {
 795         return __cxio_tpt_op(rdev_p, 0, stag, 1, pdid, TPT_NON_SHARED_MR, perm,
 796                              zbva, to, len, page_size, pbl_size, pbl_addr);
 797 }
 798
 799 int cxio_dereg_mem(struct cxio_rdev *rdev_p, u32 stag, u32 pbl_size,
 800                    u32 pbl_addr)
 801 {
 802         return __cxio_tpt_op(rdev_p, 1, &stag, 0, 0, 0, 0, 0, 0ULL, 0, 0,
 803                              pbl_size, pbl_addr);
 804 }
 805
 806 int cxio_allocate_window(struct cxio_rdev *rdev_p, u32 * stag, u32 pdid)
 807 {
 808         *stag = T3_STAG_UNSET;
 809         return __cxio_tpt_op(rdev_p, 0, stag, 0, pdid, TPT_MW, 0, 0, 0ULL, 0, 0,
 810                              0, 0);
 811 }
 812
 813 int cxio_deallocate_window(struct cxio_rdev *rdev_p, u32 stag)
 814 {
 815         return __cxio_tpt_op(rdev_p, 1, &stag, 0, 0, 0, 0, 0, 0ULL, 0, 0,
 816                              0, 0);
 817 }
 818
 819 int cxio_rdma_init(struct cxio_rdev *rdev_p, struct t3_rdma_init_attr *attr)
 820 {
 821         struct t3_rdma_init_wr *wqe;
 822         struct sk_buff *skb = alloc_skb(sizeof(*wqe), GFP_ATOMIC);
 823         if (!skb)
 824                 return -ENOMEM;
 825         PDBG("%s rdev_p %p\n", __func__, rdev_p);
 826         wqe = (struct t3_rdma_init_wr *) __skb_put(skb, sizeof(*wqe));
 827         wqe->wrh.op_seop_flags = cpu_to_be32(V_FW_RIWR_OP(T3_WR_INIT));
 828         wqe->wrh.gen_tid_len = cpu_to_be32(V_FW_RIWR_TID(attr->tid) |
 829                                            V_FW_RIWR_LEN(sizeof(*wqe) >> 3));
 830         wqe->wrid.id1 = 0;
 831         wqe->qpid = cpu_to_be32(attr->qpid);
 832         wqe->pdid = cpu_to_be32(attr->pdid);
 833         wqe->scqid = cpu_to_be32(attr->scqid);
 834         wqe->rcqid = cpu_to_be32(attr->rcqid);
 835         wqe->rq_addr = cpu_to_be32(attr->rq_addr - rdev_p->rnic_info.rqt_base);
 836         wqe->rq_size = cpu_to_be32(attr->rq_size);
 837         wqe->mpaattrs = attr->mpaattrs;
 838         wqe->qpcaps = attr->qpcaps;
 839         wqe->ulpdu_size = cpu_to_be16(attr->tcp_emss);
 840         wqe->rqe_count = cpu_to_be16(attr->rqe_count);
 841         wqe->flags_rtr_type = cpu_to_be16(attr->flags|V_RTR_TYPE(attr->rtr_type));
 842         wqe->ord = cpu_to_be32(attr->ord);
 843         wqe->ird = cpu_to_be32(attr->ird);
 844         wqe->qp_dma_addr = cpu_to_be64(attr->qp_dma_addr);
 845         wqe->qp_dma_size = cpu_to_be32(attr->qp_dma_size);
 846         wqe->irs = cpu_to_be32(attr->irs);
 847         skb->priority = 0;      /* 0=>ToeQ; 1=>CtrlQ */
 848         return (cxgb3_ofld_send(rdev_p->t3cdev_p, skb));
 849 }
 850
 851 void cxio_register_ev_cb(cxio_hal_ev_callback_func_t ev_cb)
 852 {
 853         cxio_ev_cb = ev_cb;
 854 }
 855
 856 void cxio_unregister_ev_cb(cxio_hal_ev_callback_func_t ev_cb)
 857 {
 858         cxio_ev_cb = NULL;
 859 }
 860
 861 static int cxio_hal_ev_handler(struct t3cdev *t3cdev_p, struct sk_buff *skb)
 862 {
 863         static int cnt;
 864         struct cxio_rdev *rdev_p = NULL;
 865         struct respQ_msg_t *rsp_msg = (struct respQ_msg_t *) skb->data;
 866         PDBG("%d: %s cq_id 0x%x cq_ptr 0x%x genbit %0x overflow %0x an %0x"
 867              " se %0x notify %0x cqbranch %0x creditth %0x\n",
 868              cnt, __func__, RSPQ_CQID(rsp_msg), RSPQ_CQPTR(rsp_msg),
 869              RSPQ_GENBIT(rsp_msg), RSPQ_OVERFLOW(rsp_msg), RSPQ_AN(rsp_msg),
 870              RSPQ_SE(rsp_msg), RSPQ_NOTIFY(rsp_msg), RSPQ_CQBRANCH(rsp_msg),
 871              RSPQ_CREDIT_THRESH(rsp_msg));
 872         PDBG("CQE: QPID 0x%0x genbit %0x type 0x%0x status 0x%0x opcode %d "
 873              "len 0x%0x wrid_hi_stag 0x%x wrid_low_msn 0x%x\n",
 874              CQE_QPID(rsp_msg->cqe), CQE_GENBIT(rsp_msg->cqe),
 875              CQE_TYPE(rsp_msg->cqe), CQE_STATUS(rsp_msg->cqe),
 876              CQE_OPCODE(rsp_msg->cqe), CQE_LEN(rsp_msg->cqe),
 877              CQE_WRID_HI(rsp_msg->cqe), CQE_WRID_LOW(rsp_msg->cqe));
 878         rdev_p = (struct cxio_rdev *)t3cdev_p->ulp;
 879         if (!rdev_p) {
 880                 PDBG("%s called by t3cdev %p with null ulp\n", __func__,
 881                      t3cdev_p);
 882                 return 0;
 883         }
 884         if (CQE_QPID(rsp_msg->cqe) == T3_CTRL_QP_ID) {
 885                 rdev_p->ctrl_qp.rptr = CQE_WRID_LOW(rsp_msg->cqe) + 1;
 886                 wake_up_interruptible(&rdev_p->ctrl_qp.waitq);
 887                 dev_kfree_skb_irq(skb);
 888         } else if (CQE_QPID(rsp_msg->cqe) == 0xfff8)
 889                 dev_kfree_skb_irq(skb);
 890         else if (cxio_ev_cb)
 891                 (*cxio_ev_cb) (rdev_p, skb);
 892         else
 893                 dev_kfree_skb_irq(skb);
 894         cnt++;
 895         return 0;
 896 }
 897
 898 /* Caller takes care of locking if needed */
 899 int cxio_rdev_open(struct cxio_rdev *rdev_p)
 900 {
 901         struct net_device *netdev_p = NULL;
 902         int err = 0;
 903         if (strlen(rdev_p->dev_name)) {
 904                 if (cxio_hal_find_rdev_by_name(rdev_p->dev_name)) {
 905                         return -EBUSY;
 906                 }
 907                 netdev_p = dev_get_by_name(&init_net, rdev_p->dev_name);
 908                 if (!netdev_p) {
 909                         return -EINVAL;
 910                 }
 911                 dev_put(netdev_p);
 912         } else if (rdev_p->t3cdev_p) {
 913                 if (cxio_hal_find_rdev_by_t3cdev(rdev_p->t3cdev_p)) {
 914                         return -EBUSY;
 915                 }
 916                 netdev_p = rdev_p->t3cdev_p->lldev;
 917                 strncpy(rdev_p->dev_name, rdev_p->t3cdev_p->name,
 918                         T3_MAX_DEV_NAME_LEN);
 919         } else {
 920                 PDBG("%s t3cdev_p or dev_name must be set\n", __func__);
 921                 return -EINVAL;
 922         }
 923
 924         list_add_tail(&rdev_p->entry, &rdev_list);
 925
 926         PDBG("%s opening rnic dev %s\n", __func__, rdev_p->dev_name);
 927         memset(&rdev_p->ctrl_qp, 0, sizeof(rdev_p->ctrl_qp));
 928         if (!rdev_p->t3cdev_p)
 929                 rdev_p->t3cdev_p = dev2t3cdev(netdev_p);
 930         rdev_p->t3cdev_p->ulp = (void *) rdev_p;
 931         err = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_GET_PARAMS,
 932                                          &(rdev_p->rnic_info));
 933         if (err) {
 934                 printk(KERN_ERR "%s t3cdev_p(%p)->ctl returned error %d.\n",
 935                      __func__, rdev_p->t3cdev_p, err);
 936                 goto err1;
 937         }
 938         err = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, GET_PORTS,
 939                                     &(rdev_p->port_info));
 940         if (err) {
 941                 printk(KERN_ERR "%s t3cdev_p(%p)->ctl returned error %d.\n",
 942                      __func__, rdev_p->t3cdev_p, err);
 943                 goto err1;
 944         }
 945
 946         /*
 947          * qpshift is the number of bits to shift the qpid left in order
 948          * to get the correct address of the doorbell for that qp.
 949          */
 950         cxio_init_ucontext(rdev_p, &rdev_p->uctx);
 951         rdev_p->qpshift = PAGE_SHIFT -
 952                           ilog2(65536 >>
 953                                     ilog2(rdev_p->rnic_info.udbell_len >>
 954                                               PAGE_SHIFT));
 955         rdev_p->qpnr = rdev_p->rnic_info.udbell_len >> PAGE_SHIFT;
 956         rdev_p->qpmask = (65536 >> ilog2(rdev_p->qpnr)) - 1;
 957         PDBG("%s rnic %s info: tpt_base 0x%0x tpt_top 0x%0x num stags %d "
 958              "pbl_base 0x%0x pbl_top 0x%0x rqt_base 0x%0x, rqt_top 0x%0x\n",
 959              __func__, rdev_p->dev_name, rdev_p->rnic_info.tpt_base,
 960              rdev_p->rnic_info.tpt_top, cxio_num_stags(rdev_p),
 961              rdev_p->rnic_info.pbl_base,
 962              rdev_p->rnic_info.pbl_top, rdev_p->rnic_info.rqt_base,
 963              rdev_p->rnic_info.rqt_top);
 964         PDBG("udbell_len 0x%0x udbell_physbase 0x%lx kdb_addr %p qpshift %lu "
 965              "qpnr %d qpmask 0x%x\n",
 966              rdev_p->rnic_info.udbell_len,
 967              rdev_p->rnic_info.udbell_physbase, rdev_p->rnic_info.kdb_addr,
 968              rdev_p->qpshift, rdev_p->qpnr, rdev_p->qpmask);
 969
 970         err = cxio_hal_init_ctrl_qp(rdev_p);
 971         if (err) {
 972                 printk(KERN_ERR "%s error %d initializing ctrl_qp.\n",
 973                        __func__, err);
 974                 goto err1;
 975         }
 976         err = cxio_hal_init_resource(rdev_p, cxio_num_stags(rdev_p), 0,
 977                                      0, T3_MAX_NUM_QP, T3_MAX_NUM_CQ,
 978                                      T3_MAX_NUM_PD);
 979         if (err) {
 980                 printk(KERN_ERR "%s error %d initializing hal resources.\n",
 981                        __func__, err);
 982                 goto err2;
 983         }
 984         err = cxio_hal_pblpool_create(rdev_p);
 985         if (err) {
 986                 printk(KERN_ERR "%s error %d initializing pbl mem pool.\n",
 987                        __func__, err);
 988                 goto err3;
 989         }
 990         err = cxio_hal_rqtpool_create(rdev_p);
 991         if (err) {
 992                 printk(KERN_ERR "%s error %d initializing rqt mem pool.\n",
 993                        __func__, err);
 994                 goto err4;
 995         }
 996         return 0;
 997 err4:
 998         cxio_hal_pblpool_destroy(rdev_p);
 999 err3:
1000         cxio_hal_destroy_resource(rdev_p->rscp);
1001 err2:
1002         cxio_hal_destroy_ctrl_qp(rdev_p);
1003 err1:
1004         list_del(&rdev_p->entry);
1005         return err;
1006 }
1007
1008 void cxio_rdev_close(struct cxio_rdev *rdev_p)
1009 {
1010         if (rdev_p) {
1011                 cxio_hal_pblpool_destroy(rdev_p);
1012                 cxio_hal_rqtpool_destroy(rdev_p);
1013                 list_del(&rdev_p->entry);
1014                 rdev_p->t3cdev_p->ulp = NULL;
1015                 cxio_hal_destroy_ctrl_qp(rdev_p);
1016                 cxio_hal_destroy_resource(rdev_p->rscp);
1017         }
1018 }
1019
1020 int __init cxio_hal_init(void)
1021 {
1022         if (cxio_hal_init_rhdl_resource(T3_MAX_NUM_RI))
1023                 return -ENOMEM;
1024         t3_register_cpl_handler(CPL_ASYNC_NOTIF, cxio_hal_ev_handler);
1025         return 0;
1026 }
1027
1028 void __exit cxio_hal_exit(void)
1029 {
1030         struct cxio_rdev *rdev, *tmp;
1031
1032         t3_register_cpl_handler(CPL_ASYNC_NOTIF, NULL);
1033         list_for_each_entry_safe(rdev, tmp, &rdev_list, entry)
1034                 cxio_rdev_close(rdev);
1035         cxio_hal_destroy_rhdl_resource();
1036 }
1037
1038 static void flush_completed_wrs(struct t3_wq *wq, struct t3_cq *cq)
1039 {
1040         struct t3_swsq *sqp;
1041         __u32 ptr = wq->sq_rptr;
1042         int count = Q_COUNT(wq->sq_rptr, wq->sq_wptr);
1043
1044         sqp = wq->sq + Q_PTR2IDX(ptr, wq->sq_size_log2);
1045         while (count--)
1046                 if (!sqp->signaled) {
1047                         ptr++;
1048                         sqp = wq->sq + Q_PTR2IDX(ptr,  wq->sq_size_log2);
1049                 } else if (sqp->complete) {
1050
1051                         /*
1052                          * Insert this completed cqe into the swcq.
1053                          */
1054                         PDBG("%s moving cqe into swcq sq idx %ld cq idx %ld\n",
1055                              __func__, Q_PTR2IDX(ptr,  wq->sq_size_log2),
1056                              Q_PTR2IDX(cq->sw_wptr, cq->size_log2));
1057                         sqp->cqe.header |= htonl(V_CQE_SWCQE(1));
1058                         *(cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2))
1059                                 = sqp->cqe;
1060                         cq->sw_wptr++;
1061                         sqp->signaled = 0;
1062                         break;
1063                 } else
1064                         break;
1065 }
1066
1067 static void create_read_req_cqe(struct t3_wq *wq, struct t3_cqe *hw_cqe,
1068                                 struct t3_cqe *read_cqe)
1069 {
1070         read_cqe->u.scqe.wrid_hi = wq->oldest_read->sq_wptr;
1071         read_cqe->len = wq->oldest_read->read_len;
1072         read_cqe->header = htonl(V_CQE_QPID(CQE_QPID(*hw_cqe)) |
1073                                  V_CQE_SWCQE(SW_CQE(*hw_cqe)) |
1074                                  V_CQE_OPCODE(T3_READ_REQ) |
1075                                  V_CQE_TYPE(1));
1076 }
1077
1078 /*
1079  * Return a ptr to the next read wr in the SWSQ or NULL.
1080  */
1081 static void advance_oldest_read(struct t3_wq *wq)
1082 {
1083
1084         u32 rptr = wq->oldest_read - wq->sq + 1;
1085         u32 wptr = Q_PTR2IDX(wq->sq_wptr, wq->sq_size_log2);
1086
1087         while (Q_PTR2IDX(rptr, wq->sq_size_log2) != wptr) {
1088                 wq->oldest_read = wq->sq + Q_PTR2IDX(rptr, wq->sq_size_log2);
1089
1090                 if (wq->oldest_read->opcode == T3_READ_REQ)
1091                         return;
1092                 rptr++;
1093         }
1094         wq->oldest_read = NULL;
1095 }
1096
1097 /*
1098  * cxio_poll_cq
1099  *
1100  * Caller must:
1101  *     check the validity of the first CQE,
1102  *     supply the wq assicated with the qpid.
1103  *
1104  * credit: cq credit to return to sge.
1105  * cqe_flushed: 1 iff the CQE is flushed.
1106  * cqe: copy of the polled CQE.
1107  *
1108  * return value:
1109  *     0       CQE returned,
1110  *    -1       CQE skipped, try again.
1111  */
1112 int cxio_poll_cq(struct t3_wq *wq, struct t3_cq *cq, struct t3_cqe *cqe,
1113                      u8 *cqe_flushed, u64 *cookie, u32 *credit)
1114 {
1115         int ret = 0;
1116         struct t3_cqe *hw_cqe, read_cqe;
1117
1118         *cqe_flushed = 0;
1119         *credit = 0;
1120         hw_cqe = cxio_next_cqe(cq);
1121
1122         PDBG("%s CQE OOO %d qpid 0x%0x genbit %d type %d status 0x%0x"
1123              " opcode 0x%0x len 0x%0x wrid_hi_stag 0x%x wrid_low_msn 0x%x\n",
1124              __func__, CQE_OOO(*hw_cqe), CQE_QPID(*hw_cqe),
1125              CQE_GENBIT(*hw_cqe), CQE_TYPE(*hw_cqe), CQE_STATUS(*hw_cqe),
1126              CQE_OPCODE(*hw_cqe), CQE_LEN(*hw_cqe), CQE_WRID_HI(*hw_cqe),
1127              CQE_WRID_LOW(*hw_cqe));
1128
1129         /*
1130          * skip cqe's not affiliated with a QP.
1131          */
1132         if (wq == NULL) {
1133                 ret = -1;
1134                 goto skip_cqe;
1135         }
1136
1137         /*
1138          * Gotta tweak READ completions:
1139          *      1) the cqe doesn't contain the sq_wptr from the wr.
1140          *      2) opcode not reflected from the wr.
1141          *      3) read_len not reflected from the wr.
1142          *      4) cq_type is RQ_TYPE not SQ_TYPE.
1143          */
1144         if (RQ_TYPE(*hw_cqe) && (CQE_OPCODE(*hw_cqe) == T3_READ_RESP)) {
1145
1146                 /*
1147                  * If this is an unsolicited read response, then the read
1148                  * was generated by the kernel driver as part of peer-2-peer
1149                  * connection setup.  So ignore the completion.
1150                  */
1151                 if (!wq->oldest_read) {
1152                         if (CQE_STATUS(*hw_cqe))
1153                                 wq->error = 1;
1154                         ret = -1;
1155                         goto skip_cqe;
1156                 }
1157
1158                 /*
1159                  * Don't write to the HWCQ, so create a new read req CQE
1160                  * in local memory.
1161                  */
1162                 create_read_req_cqe(wq, hw_cqe, &read_cqe);
1163                 hw_cqe = &read_cqe;
1164                 advance_oldest_read(wq);
1165         }
1166
1167         /*
1168          * T3A: Discard TERMINATE CQEs.
1169          */
1170         if (CQE_OPCODE(*hw_cqe) == T3_TERMINATE) {
1171                 ret = -1;
1172                 wq->error = 1;
1173                 goto skip_cqe;
1174         }
1175
1176         if (CQE_STATUS(*hw_cqe) || wq->error) {
1177                 *cqe_flushed = wq->error;
1178                 wq->error = 1;
1179
1180                 /*
1181                  * T3A inserts errors into the CQE.  We cannot return
1182                  * these as work completions.
1183                  */
1184                 /* incoming write failures */
1185                 if ((CQE_OPCODE(*hw_cqe) == T3_RDMA_WRITE)
1186                      && RQ_TYPE(*hw_cqe)) {
1187                         ret = -1;
1188                         goto skip_cqe;
1189                 }
1190                 /* incoming read request failures */
1191                 if ((CQE_OPCODE(*hw_cqe) == T3_READ_RESP) && SQ_TYPE(*hw_cqe)) {
1192                         ret = -1;
1193                         goto skip_cqe;
1194                 }
1195
1196                 /* incoming SEND with no receive posted failures */
1197                 if ((CQE_OPCODE(*hw_cqe) == T3_SEND) && RQ_TYPE(*hw_cqe) &&
1198                     Q_EMPTY(wq->rq_rptr, wq->rq_wptr)) {
1199                         ret = -1;
1200                         goto skip_cqe;
1201                 }
1202                 goto proc_cqe;
1203         }
1204
1205         /*
1206          * RECV completion.
1207          */
1208         if (RQ_TYPE(*hw_cqe)) {
1209
1210                 /*
1211                  * HW only validates 4 bits of MSN.  So we must validate that
1212                  * the MSN in the SEND is the next expected MSN.  If its not,
1213                  * then we complete this with TPT_ERR_MSN and mark the wq in
1214                  * error.
1215                  */
1216                 if (unlikely((CQE_WRID_MSN(*hw_cqe) != (wq->rq_rptr + 1)))) {
1217                         wq->error = 1;
1218                         hw_cqe->header |= htonl(V_CQE_STATUS(TPT_ERR_MSN));
1219                         goto proc_cqe;
1220                 }
1221                 goto proc_cqe;
1222         }
1223
1224         /*
1225          * If we get here its a send completion.
1226          *
1227          * Handle out of order completion. These get stuffed
1228          * in the SW SQ. Then the SW SQ is walked to move any
1229          * now in-order completions into the SW CQ.  This handles
1230          * 2 cases:
1231          *      1) reaping unsignaled WRs when the first subsequent
1232          *         signaled WR is completed.
1233          *      2) out of order read completions.
1234          */
1235         if (!SW_CQE(*hw_cqe) && (CQE_WRID_SQ_WPTR(*hw_cqe) != wq->sq_rptr)) {
1236                 struct t3_swsq *sqp;
1237
1238                 PDBG("%s out of order completion going in swsq at idx %ld\n",
1239                      __func__,
1240                      Q_PTR2IDX(CQE_WRID_SQ_WPTR(*hw_cqe), wq->sq_size_log2));
1241                 sqp = wq->sq +
1242                       Q_PTR2IDX(CQE_WRID_SQ_WPTR(*hw_cqe), wq->sq_size_log2);
1243                 sqp->cqe = *hw_cqe;
1244                 sqp->complete = 1;
1245                 ret = -1;
1246                 goto flush_wq;
1247         }
1248
1249 proc_cqe:
1250         *cqe = *hw_cqe;
1251
1252         /*
1253          * Reap the associated WR(s) that are freed up with this
1254          * completion.
1255          */
1256         if (SQ_TYPE(*hw_cqe)) {
1257                 wq->sq_rptr = CQE_WRID_SQ_WPTR(*hw_cqe);
1258                 PDBG("%s completing sq idx %ld\n", __func__,
1259                      Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2));
1260                 *cookie = (wq->sq +
1261                            Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2))->wr_id;
1262                 wq->sq_rptr++;
1263         } else {
1264                 PDBG("%s completing rq idx %ld\n", __func__,
1265                      Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2));
1266                 *cookie = *(wq->rq + Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2));
1267                 wq->rq_rptr++;
1268         }
1269
1270 flush_wq:
1271         /*
1272          * Flush any completed cqes that are now in-order.
1273          */
1274         flush_completed_wrs(wq, cq);
1275
1276 skip_cqe:
1277         if (SW_CQE(*hw_cqe)) {
1278                 PDBG("%s cq %p cqid 0x%x skip sw cqe sw_rptr 0x%x\n",
1279                      __func__, cq, cq->cqid, cq->sw_rptr);
1280                 ++cq->sw_rptr;
1281         } else {
1282                 PDBG("%s cq %p cqid 0x%x skip hw cqe rptr 0x%x\n",
1283                      __func__, cq, cq->cqid, cq->rptr);
1284                 ++cq->rptr;
1285
1286                 /*
1287                  * T3A: compute credits.
1288                  */
1289                 if (((cq->rptr - cq->wptr) > (1 << (cq->size_log2 - 1)))
1290                     || ((cq->rptr - cq->wptr) >= 128)) {
1291                         *credit = cq->rptr - cq->wptr;
1292                         cq->wptr = cq->rptr;
1293                 }
1294         }
1295         return ret;
1296 }