2 * (C) Copyright 2008 Intel Corporation
4 * Andy Henroid <andrew.d.henroid@intel.com>
5 * Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
9 * Save DIMM power on Intel 7300-based platforms when all CPUs/cores
10 * are idle, using the DIMM thermal throttling capability.
12 * This driver depends on the Intel integrated DMA controller (I/O AT).
13 * If the driver for I/O AT (drivers/dma/ioatdma*) is also enabled,
14 * this driver should work cooperatively.
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/sched.h>
23 #include <linux/notifier.h>
24 #include <linux/cpumask.h>
25 #include <linux/ktime.h>
26 #include <linux/delay.h>
27 #include <linux/debugfs.h>
28 #include <linux/stop_machine.h>
29 #include <linux/i7300_idle.h>
33 #include "../dma/ioat/hw.h"
34 #include "../dma/ioat/registers.h"
36 #define I7300_IDLE_DRIVER_VERSION "1.55"
37 #define I7300_PRINT "i7300_idle:"
39 #define MAX_STOP_RETRIES 10
42 module_param_named(debug, debug, uint, 0644);
43 MODULE_PARM_DESC(debug, "Enable debug printks in this driver");
46 module_param_named(forceload, forceload, uint, 0644);
47 MODULE_PARM_DESC(debug, "Enable driver testing on unvalidated i5000");
49 #define dprintk(fmt, arg...) \
50 do { if (debug) printk(KERN_INFO I7300_PRINT fmt, ##arg); } while (0)
53 * Value to set THRTLOW to when initiating throttling
55 * 1 = Throttle when > 4 activations per eval window (Maximum throttling)
56 * 2 = Throttle when > 8 activations
57 * 168 = Throttle when > 672 activations (Minimum throttling)
59 #define MAX_THROTTLE_LOW_LIMIT 168
60 static uint throttle_low_limit = 1;
61 module_param_named(throttle_low_limit, throttle_low_limit, uint, 0644);
62 MODULE_PARM_DESC(throttle_low_limit,
63 "Value for THRTLOWLM activation field "
64 "(0 = disable throttle, 1 = Max throttle, 168 = Min throttle)");
67 * simple invocation and duration statistics
69 static unsigned long total_starts;
70 static unsigned long total_us;
73 static unsigned long past_skip;
76 static struct pci_dev *fbd_dev;
78 static spinlock_t i7300_idle_lock;
79 static int i7300_idle_active;
81 static u8 i7300_idle_thrtctl_saved;
82 static u8 i7300_idle_thrtlow_saved;
83 static u32 i7300_idle_mc_saved;
85 static cpumask_var_t idle_cpumask;
86 static ktime_t start_ktime;
87 static unsigned long avg_idle_us;
89 static struct dentry *debugfs_dir;
91 /* Begin: I/O AT Helper routines */
93 #define IOAT_CHANBASE(ioat_ctl, chan) (ioat_ctl + 0x80 + 0x80 * chan)
94 /* Snoop control (disable snoops when coherency is not important) */
95 #define IOAT_DESC_SADDR_SNP_CTL (1UL << 1)
96 #define IOAT_DESC_DADDR_SNP_CTL (1UL << 2)
98 static struct pci_dev *ioat_dev;
99 static struct ioat_dma_descriptor *ioat_desc; /* I/O AT desc & data (1 page) */
100 static unsigned long ioat_desc_phys;
101 static u8 *ioat_iomap; /* I/O AT memory-mapped control regs (aka CB_BAR) */
102 static u8 *ioat_chanbase;
104 /* Start I/O AT memory copy */
105 static int i7300_idle_ioat_start(void)
108 /* Clear error (due to circular descriptor pointer) */
109 err = readl(ioat_chanbase + IOAT_CHANERR_OFFSET);
111 writel(err, ioat_chanbase + IOAT_CHANERR_OFFSET);
113 writeb(IOAT_CHANCMD_START, ioat_chanbase + IOAT1_CHANCMD_OFFSET);
117 /* Stop I/O AT memory copy */
118 static void i7300_idle_ioat_stop(void)
123 for (i = 0; i < MAX_STOP_RETRIES; i++) {
124 writeb(IOAT_CHANCMD_RESET,
125 ioat_chanbase + IOAT1_CHANCMD_OFFSET);
129 sts = readq(ioat_chanbase + IOAT1_CHANSTS_OFFSET) &
132 if (sts != IOAT_CHANSTS_ACTIVE)
137 if (i == MAX_STOP_RETRIES) {
138 dprintk("failed to stop I/O AT after %d retries\n",
143 /* Test I/O AT by copying 1024 byte from 2k to 1k */
144 static int __init i7300_idle_ioat_selftest(u8 *ctl,
145 struct ioat_dma_descriptor *desc, unsigned long desc_phys)
149 memset(desc, 0, 2048);
150 memset((u8 *) desc + 2048, 0xab, 1024);
154 desc[0].src_addr = desc_phys + 2048;
155 desc[0].dst_addr = desc_phys + 1024;
158 writeb(IOAT_CHANCMD_RESET, ioat_chanbase + IOAT1_CHANCMD_OFFSET);
159 writeb(IOAT_CHANCMD_START, ioat_chanbase + IOAT1_CHANCMD_OFFSET);
163 chan_sts = readq(ioat_chanbase + IOAT1_CHANSTS_OFFSET) &
166 if (chan_sts != IOAT_CHANSTS_DONE) {
167 /* Not complete, reset the channel */
168 writeb(IOAT_CHANCMD_RESET,
169 ioat_chanbase + IOAT1_CHANCMD_OFFSET);
173 if (*(u32 *) ((u8 *) desc + 3068) != 0xabababab ||
174 *(u32 *) ((u8 *) desc + 2044) != 0xabababab) {
175 dprintk("Data values src 0x%x, dest 0x%x, memset 0x%x\n",
176 *(u32 *) ((u8 *) desc + 2048),
177 *(u32 *) ((u8 *) desc + 1024),
178 *(u32 *) ((u8 *) desc + 3072));
184 static struct device dummy_dma_dev = {
185 .init_name = "fallback device",
186 .coherent_dma_mask = DMA_BIT_MASK(64),
187 .dma_mask = &dummy_dma_dev.coherent_dma_mask,
190 /* Setup and initialize I/O AT */
191 /* This driver needs I/O AT as the throttling takes effect only when there is
192 * some memory activity. We use I/O AT to set up a dummy copy, while all CPUs
193 * go idle and memory is throttled.
195 static int __init i7300_idle_ioat_init(void)
197 u8 ver, chan_count, ioat_chan;
200 ioat_iomap = (u8 *) ioremap_nocache(pci_resource_start(ioat_dev, 0),
201 pci_resource_len(ioat_dev, 0));
204 printk(KERN_ERR I7300_PRINT "failed to map I/O AT registers\n");
208 ver = readb(ioat_iomap + IOAT_VER_OFFSET);
209 if (ver != IOAT_VER_1_2) {
210 printk(KERN_ERR I7300_PRINT "unknown I/O AT version (%u.%u)\n",
211 ver >> 4, ver & 0xf);
215 chan_count = readb(ioat_iomap + IOAT_CHANCNT_OFFSET);
217 printk(KERN_ERR I7300_PRINT "unexpected # of I/O AT channels "
223 ioat_chan = chan_count - 1;
224 ioat_chanbase = IOAT_CHANBASE(ioat_iomap, ioat_chan);
226 chan_ctl = readw(ioat_chanbase + IOAT_CHANCTRL_OFFSET);
227 if (chan_ctl & IOAT_CHANCTRL_CHANNEL_IN_USE) {
228 printk(KERN_ERR I7300_PRINT "channel %d in use\n", ioat_chan);
232 writew(IOAT_CHANCTRL_CHANNEL_IN_USE,
233 ioat_chanbase + IOAT_CHANCTRL_OFFSET);
235 ioat_desc = (struct ioat_dma_descriptor *)dma_alloc_coherent(
236 &dummy_dma_dev, 4096,
237 (dma_addr_t *)&ioat_desc_phys, GFP_KERNEL);
239 printk(KERN_ERR I7300_PRINT "failed to allocate I/O AT desc\n");
240 goto err_mark_unused;
243 writel(ioat_desc_phys & 0xffffffffUL,
244 ioat_chanbase + IOAT1_CHAINADDR_OFFSET_LOW);
245 writel(ioat_desc_phys >> 32,
246 ioat_chanbase + IOAT1_CHAINADDR_OFFSET_HIGH);
248 if (i7300_idle_ioat_selftest(ioat_iomap, ioat_desc, ioat_desc_phys)) {
249 printk(KERN_ERR I7300_PRINT "I/O AT self-test failed\n");
253 /* Setup circular I/O AT descriptor chain */
254 ioat_desc[0].ctl = IOAT_DESC_SADDR_SNP_CTL | IOAT_DESC_DADDR_SNP_CTL;
255 ioat_desc[0].src_addr = ioat_desc_phys + 2048;
256 ioat_desc[0].dst_addr = ioat_desc_phys + 3072;
257 ioat_desc[0].size = 128;
258 ioat_desc[0].next = ioat_desc_phys + sizeof(struct ioat_dma_descriptor);
260 ioat_desc[1].ctl = ioat_desc[0].ctl;
261 ioat_desc[1].src_addr = ioat_desc[0].src_addr;
262 ioat_desc[1].dst_addr = ioat_desc[0].dst_addr;
263 ioat_desc[1].size = ioat_desc[0].size;
264 ioat_desc[1].next = ioat_desc_phys;
269 dma_free_coherent(&dummy_dma_dev, 4096, (void *)ioat_desc, 0);
271 writew(0, ioat_chanbase + IOAT_CHANCTRL_OFFSET);
279 static void __exit i7300_idle_ioat_exit(void)
284 i7300_idle_ioat_stop();
286 /* Wait for a while for the channel to halt before releasing */
287 for (i = 0; i < MAX_STOP_RETRIES; i++) {
288 writeb(IOAT_CHANCMD_RESET,
289 ioat_chanbase + IOAT1_CHANCMD_OFFSET);
291 chan_sts = readq(ioat_chanbase + IOAT1_CHANSTS_OFFSET) &
294 if (chan_sts != IOAT_CHANSTS_ACTIVE) {
295 writew(0, ioat_chanbase + IOAT_CHANCTRL_OFFSET);
301 chan_sts = readq(ioat_chanbase + IOAT1_CHANSTS_OFFSET) &
305 * We tried to reset multiple times. If IO A/T channel is still active
306 * flag an error and return without cleanup. Memory leak is better
307 * than random corruption in that extreme error situation.
309 if (chan_sts == IOAT_CHANSTS_ACTIVE) {
310 printk(KERN_ERR I7300_PRINT "Unable to stop IO A/T channels."
311 " Not freeing resources\n");
315 dma_free_coherent(&dummy_dma_dev, 4096, (void *)ioat_desc, 0);
319 /* End: I/O AT Helper routines */
321 #define DIMM_THRTLOW 0x64
322 #define DIMM_THRTCTL 0x67
323 #define DIMM_THRTCTL_THRMHUNT (1UL << 0)
325 #define DIMM_GTW_MODE (1UL << 17)
326 #define DIMM_GBLACT 0x60
329 * Keep track of an exponential-decaying average of recent idle durations.
330 * The latest duration gets DURATION_WEIGHT_PCT percentage weight
331 * in this average, with the old average getting the remaining weight.
333 * High weights emphasize recent history, low weights include long history.
335 #define DURATION_WEIGHT_PCT 55
338 * When the decaying average of recent durations or the predicted duration
339 * of the next timer interrupt is shorter than duration_threshold, the
340 * driver will decline to throttle.
342 #define DURATION_THRESHOLD_US 100
345 /* Store DIMM thermal throttle configuration */
346 static int i7300_idle_thrt_save(void)
351 pci_read_config_byte(fbd_dev, DIMM_THRTCTL, &i7300_idle_thrtctl_saved);
352 pci_read_config_byte(fbd_dev, DIMM_THRTLOW, &i7300_idle_thrtlow_saved);
353 pci_read_config_dword(fbd_dev, DIMM_MC, &i7300_idle_mc_saved);
355 * Make sure we have Global Throttling Window Mode set to have a
356 * "short" window. This (mostly) works around an issue where
357 * throttling persists until the end of the global throttling window
358 * size. On the tested system, this was resulting in a maximum of
359 * 64 ms to exit throttling (average 32 ms). The actual numbers
360 * depends on system frequencies. Setting the short window reduces
361 * this by a factor of 4096.
363 * We will only do this only if the system is set for
364 * unlimited-activations while in open-loop throttling (i.e., when
365 * Global Activation Throttle Limit is zero).
367 pci_read_config_byte(fbd_dev, DIMM_GBLACT, &gblactlm);
368 dprintk("thrtctl_saved = 0x%02x, thrtlow_saved = 0x%02x\n",
369 i7300_idle_thrtctl_saved,
370 i7300_idle_thrtlow_saved);
371 dprintk("mc_saved = 0x%08x, gblactlm = 0x%02x\n",
375 new_mc_val = i7300_idle_mc_saved | DIMM_GTW_MODE;
376 pci_write_config_dword(fbd_dev, DIMM_MC, new_mc_val);
379 dprintk("could not set GTW_MODE = 1 (OLTT enabled)\n");
384 /* Restore DIMM thermal throttle configuration */
385 static void i7300_idle_thrt_restore(void)
387 pci_write_config_dword(fbd_dev, DIMM_MC, i7300_idle_mc_saved);
388 pci_write_config_byte(fbd_dev, DIMM_THRTLOW, i7300_idle_thrtlow_saved);
389 pci_write_config_byte(fbd_dev, DIMM_THRTCTL, i7300_idle_thrtctl_saved);
392 /* Enable DIMM thermal throttling */
393 static void i7300_idle_start(void)
398 new_ctl = i7300_idle_thrtctl_saved & ~DIMM_THRTCTL_THRMHUNT;
399 pci_write_config_byte(fbd_dev, DIMM_THRTCTL, new_ctl);
401 limit = throttle_low_limit;
402 if (unlikely(limit > MAX_THROTTLE_LOW_LIMIT))
403 limit = MAX_THROTTLE_LOW_LIMIT;
405 pci_write_config_byte(fbd_dev, DIMM_THRTLOW, limit);
407 new_ctl = i7300_idle_thrtctl_saved | DIMM_THRTCTL_THRMHUNT;
408 pci_write_config_byte(fbd_dev, DIMM_THRTCTL, new_ctl);
411 /* Disable DIMM thermal throttling */
412 static void i7300_idle_stop(void)
417 new_ctl = i7300_idle_thrtctl_saved & ~DIMM_THRTCTL_THRMHUNT;
418 pci_write_config_byte(fbd_dev, DIMM_THRTCTL, new_ctl);
420 pci_write_config_byte(fbd_dev, DIMM_THRTLOW, i7300_idle_thrtlow_saved);
421 pci_write_config_byte(fbd_dev, DIMM_THRTCTL, i7300_idle_thrtctl_saved);
422 pci_read_config_byte(fbd_dev, DIMM_THRTCTL, &got_ctl);
423 WARN_ON_ONCE(got_ctl != i7300_idle_thrtctl_saved);
428 * i7300_avg_duration_check()
429 * return 0 if the decaying average of recent idle durations is
430 * more than DURATION_THRESHOLD_US
432 static int i7300_avg_duration_check(void)
434 if (avg_idle_us >= DURATION_THRESHOLD_US)
443 /* Idle notifier to look at idle CPUs */
444 static int i7300_idle_notifier(struct notifier_block *nb, unsigned long val,
449 static ktime_t idle_begin_time;
450 static int time_init = 1;
452 if (!throttle_low_limit)
455 if (unlikely(time_init)) {
457 idle_begin_time = ktime_get();
460 spin_lock_irqsave(&i7300_idle_lock, flags);
461 if (val == IDLE_START) {
463 cpumask_set_cpu(smp_processor_id(), idle_cpumask);
465 if (cpumask_weight(idle_cpumask) != num_online_cpus())
468 now_ktime = ktime_get();
469 idle_begin_time = now_ktime;
471 if (i7300_avg_duration_check())
474 i7300_idle_active = 1;
476 start_ktime = now_ktime;
479 i7300_idle_ioat_start();
481 } else if (val == IDLE_END) {
482 cpumask_clear_cpu(smp_processor_id(), idle_cpumask);
483 if (cpumask_weight(idle_cpumask) == (num_online_cpus() - 1)) {
484 /* First CPU coming out of idle */
485 u64 idle_duration_us;
487 now_ktime = ktime_get();
489 idle_duration_us = ktime_to_us(ktime_sub
490 (now_ktime, idle_begin_time));
493 ((100 - DURATION_WEIGHT_PCT) * avg_idle_us +
494 DURATION_WEIGHT_PCT * idle_duration_us) / 100;
496 if (i7300_idle_active) {
499 idle_ktime = ktime_sub(now_ktime, start_ktime);
500 total_us += ktime_to_us(idle_ktime);
502 i7300_idle_ioat_stop();
504 i7300_idle_active = 0;
509 spin_unlock_irqrestore(&i7300_idle_lock, flags);
513 static struct notifier_block i7300_idle_nb = {
514 .notifier_call = i7300_idle_notifier,
517 MODULE_DEVICE_TABLE(pci, pci_tbl);
519 int stats_open_generic(struct inode *inode, struct file *fp)
521 fp->private_data = inode->i_private;
525 static ssize_t stats_read_ul(struct file *fp, char __user *ubuf, size_t count,
528 unsigned long *p = fp->private_data;
532 len = snprintf(buf, 32, "%lu\n", *p);
533 return simple_read_from_buffer(ubuf, count, off, buf, len);
536 static const struct file_operations idle_fops = {
537 .open = stats_open_generic,
538 .read = stats_read_ul,
539 .llseek = default_llseek,
542 struct debugfs_file_info {
546 } debugfs_file_list[] = {
547 {&total_starts, "total_starts", NULL},
548 {&total_us, "total_us", NULL},
550 {&past_skip, "past_skip", NULL},
555 static int __init i7300_idle_init(void)
557 spin_lock_init(&i7300_idle_lock);
560 if (i7300_idle_platform_probe(&fbd_dev, &ioat_dev, forceload))
563 if (i7300_idle_thrt_save())
566 if (i7300_idle_ioat_init())
569 if (!zalloc_cpumask_var(&idle_cpumask, GFP_KERNEL))
572 debugfs_dir = debugfs_create_dir("i7300_idle", NULL);
576 while (debugfs_file_list[i].ptr != NULL) {
577 debugfs_file_list[i].file = debugfs_create_file(
578 debugfs_file_list[i].name,
581 debugfs_file_list[i].ptr,
587 idle_notifier_register(&i7300_idle_nb);
589 printk(KERN_INFO "i7300_idle: loaded v%s\n", I7300_IDLE_DRIVER_VERSION);
593 static void __exit i7300_idle_exit(void)
595 idle_notifier_unregister(&i7300_idle_nb);
596 free_cpumask_var(idle_cpumask);
601 while (debugfs_file_list[i].file != NULL) {
602 debugfs_remove(debugfs_file_list[i].file);
606 debugfs_remove(debugfs_dir);
608 i7300_idle_thrt_restore();
609 i7300_idle_ioat_exit();
612 module_init(i7300_idle_init);
613 module_exit(i7300_idle_exit);
615 MODULE_AUTHOR("Andy Henroid <andrew.d.henroid@intel.com>");
616 MODULE_DESCRIPTION("Intel Chipset DIMM Idle Power Saving Driver v"
617 I7300_IDLE_DRIVER_VERSION);
618 MODULE_LICENSE("GPL");