2 * linux/drivers/ide/pci/sl82c105.c
4 * SL82C105/Winbond 553 IDE driver
8 * Drive tuning added from Rebel.com's kernel sources
9 * -- Russell King (15/11/98) linux@arm.linux.org.uk
11 * Merge in Russell's HW workarounds, fix various problems
12 * with the timing registers setup.
13 * -- Benjamin Herrenschmidt (01/11/03) benh@kernel.crashing.org
15 * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
18 #include <linux/types.h>
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/timer.h>
23 #include <linux/ioport.h>
24 #include <linux/interrupt.h>
25 #include <linux/blkdev.h>
26 #include <linux/hdreg.h>
27 #include <linux/pci.h>
28 #include <linux/ide.h>
36 #define DBG(arg) printk arg
41 * SL82C105 PCI config register 0x40 bits.
43 #define CTRL_IDE_IRQB (1 << 30)
44 #define CTRL_IDE_IRQA (1 << 28)
45 #define CTRL_LEGIRQ (1 << 11)
46 #define CTRL_P1F16 (1 << 5)
47 #define CTRL_P1EN (1 << 4)
48 #define CTRL_P0F16 (1 << 1)
49 #define CTRL_P0EN (1 << 0)
52 * Convert a PIO mode and cycle time to the required on/off times
53 * for the interface. This has protection against runaway timings.
55 static unsigned int get_pio_timings(ide_drive_t *drive, u8 pio)
57 unsigned int cmd_on, cmd_off;
60 cmd_on = (ide_pio_timings[pio].active_time + 29) / 30;
61 cmd_off = (ide_pio_cycle_time(drive, pio) - 30 * cmd_on + 29) / 30;
69 if (pio > 2 || ide_dev_has_iordy(drive->id))
72 return (cmd_on - 1) << 8 | (cmd_off - 1) | iordy;
76 * Configure the chipset for PIO mode.
78 static u8 sl82c105_tune_pio(ide_drive_t *drive, u8 pio)
80 struct pci_dev *dev = HWIF(drive)->pci_dev;
81 int reg = 0x44 + drive->dn * 4;
84 DBG(("sl82c105_tune_pio(drive:%s, pio:%u)\n", drive->name, pio));
86 pio = ide_get_best_pio_mode(drive, pio, 5);
88 drv_ctrl = get_pio_timings(drive, pio);
91 * Store the PIO timings so that we can restore them
92 * in case DMA will be turned off...
94 drive->drive_data &= 0xffff0000;
95 drive->drive_data |= drv_ctrl;
97 if (!drive->using_dma) {
99 * If we are actually using MW DMA, then we can not
100 * reprogram the interface drive control register.
102 pci_write_config_word(dev, reg, drv_ctrl);
103 pci_read_config_word (dev, reg, &drv_ctrl);
106 printk(KERN_DEBUG "%s: selected %s (%dns) (%04X)\n", drive->name,
107 ide_xfer_verbose(pio + XFER_PIO_0),
108 ide_pio_cycle_time(drive, pio), drv_ctrl);
114 * Configure the drive and chipset for a new transfer speed.
116 static int sl82c105_tune_chipset(ide_drive_t *drive, const u8 speed)
118 static u16 mwdma_timings[] = {0x0707, 0x0201, 0x0200};
121 DBG(("sl82c105_tune_chipset(drive:%s, speed:%s)\n",
122 drive->name, ide_xfer_verbose(speed)));
128 drv_ctrl = mwdma_timings[speed - XFER_MW_DMA_0];
131 * Store the DMA timings so that we can actually program
132 * them when DMA will be turned on...
134 drive->drive_data &= 0x0000ffff;
135 drive->drive_data |= (unsigned long)drv_ctrl << 16;
138 * If we are already using DMA, we just reprogram
139 * the drive control register.
141 if (drive->using_dma) {
142 struct pci_dev *dev = HWIF(drive)->pci_dev;
143 int reg = 0x44 + drive->dn * 4;
145 pci_write_config_word(dev, reg, drv_ctrl);
154 (void) sl82c105_tune_pio(drive, speed - XFER_PIO_0);
160 return ide_config_drive_speed(drive, speed);
164 * Check to see if the drive and chipset are capable of DMA mode.
166 static int sl82c105_ide_dma_check(ide_drive_t *drive)
168 DBG(("sl82c105_ide_dma_check(drive:%s)\n", drive->name));
170 if (ide_tune_dma(drive))
177 * The SL82C105 holds off all IDE interrupts while in DMA mode until
178 * all DMA activity is completed. Sometimes this causes problems (eg,
179 * when the drive wants to report an error condition).
181 * 0x7e is a "chip testing" register. Bit 2 resets the DMA controller
182 * state machine. We need to kick this to work around various bugs.
184 static inline void sl82c105_reset_host(struct pci_dev *dev)
188 pci_read_config_word(dev, 0x7e, &val);
189 pci_write_config_word(dev, 0x7e, val | (1 << 2));
190 pci_write_config_word(dev, 0x7e, val & ~(1 << 2));
194 * If we get an IRQ timeout, it might be that the DMA state machine
195 * got confused. Fix from Todd Inglett. Details from Winbond.
197 * This function is called when the IDE timer expires, the drive
198 * indicates that it is READY, and we were waiting for DMA to complete.
200 static void sl82c105_dma_lost_irq(ide_drive_t *drive)
202 ide_hwif_t *hwif = HWIF(drive);
203 struct pci_dev *dev = hwif->pci_dev;
204 u32 val, mask = hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA;
207 printk("sl82c105: lost IRQ, resetting host\n");
210 * Check the raw interrupt from the drive.
212 pci_read_config_dword(dev, 0x40, &val);
214 printk("sl82c105: drive was requesting IRQ, but host lost it\n");
217 * Was DMA enabled? If so, disable it - we're resetting the
218 * host. The IDE layer will be handling the drive for us.
220 dma_cmd = inb(hwif->dma_command);
222 outb(dma_cmd & ~1, hwif->dma_command);
223 printk("sl82c105: DMA was enabled\n");
226 sl82c105_reset_host(dev);
230 * ATAPI devices can cause the SL82C105 DMA state machine to go gaga.
231 * Winbond recommend that the DMA state machine is reset prior to
232 * setting the bus master DMA enable bit.
234 * The generic IDE core will have disabled the BMEN bit before this
235 * function is called.
237 static void sl82c105_dma_start(ide_drive_t *drive)
239 ide_hwif_t *hwif = HWIF(drive);
240 struct pci_dev *dev = hwif->pci_dev;
242 sl82c105_reset_host(dev);
243 ide_dma_start(drive);
246 static void sl82c105_dma_timeout(ide_drive_t *drive)
248 DBG(("sl82c105_dma_timeout(drive:%s)\n", drive->name));
250 sl82c105_reset_host(HWIF(drive)->pci_dev);
251 ide_dma_timeout(drive);
254 static int sl82c105_ide_dma_on(ide_drive_t *drive)
256 struct pci_dev *dev = HWIF(drive)->pci_dev;
257 int rc, reg = 0x44 + drive->dn * 4;
259 DBG(("sl82c105_ide_dma_on(drive:%s)\n", drive->name));
261 rc = __ide_dma_on(drive);
263 pci_write_config_word(dev, reg, drive->drive_data >> 16);
265 printk(KERN_INFO "%s: DMA enabled\n", drive->name);
270 static void sl82c105_dma_off_quietly(ide_drive_t *drive)
272 struct pci_dev *dev = HWIF(drive)->pci_dev;
273 int reg = 0x44 + drive->dn * 4;
275 DBG(("sl82c105_dma_off_quietly(drive:%s)\n", drive->name));
277 pci_write_config_word(dev, reg, drive->drive_data);
279 ide_dma_off_quietly(drive);
283 * Ok, that is nasty, but we must make sure the DMA timings
284 * won't be used for a PIO access. The solution here is
285 * to make sure the 16 bits mode is diabled on the channel
286 * when DMA is enabled, thus causing the chip to use PIO0
287 * timings for those operations.
289 static void sl82c105_selectproc(ide_drive_t *drive)
291 ide_hwif_t *hwif = HWIF(drive);
292 struct pci_dev *dev = hwif->pci_dev;
295 //DBG(("sl82c105_selectproc(drive:%s)\n", drive->name));
297 mask = hwif->channel ? CTRL_P1F16 : CTRL_P0F16;
298 old = val = (u32)pci_get_drvdata(dev);
299 if (drive->using_dma)
304 pci_write_config_dword(dev, 0x40, val);
305 pci_set_drvdata(dev, (void *)val);
310 * ATA reset will clear the 16 bits mode in the control
311 * register, we need to update our cache
313 static void sl82c105_resetproc(ide_drive_t *drive)
315 struct pci_dev *dev = HWIF(drive)->pci_dev;
318 DBG(("sl82c105_resetproc(drive:%s)\n", drive->name));
320 pci_read_config_dword(dev, 0x40, &val);
321 pci_set_drvdata(dev, (void *)val);
325 * We only deal with PIO mode here - DMA mode 'using_dma' is not
326 * initialised at the point that this function is called.
328 static void sl82c105_tune_drive(ide_drive_t *drive, u8 pio)
330 DBG(("sl82c105_tune_drive(drive:%s, pio:%u)\n", drive->name, pio));
332 pio = sl82c105_tune_pio(drive, pio);
333 (void) ide_config_drive_speed(drive, XFER_PIO_0 + pio);
337 * Return the revision of the Winbond bridge
338 * which this function is part of.
340 static unsigned int sl82c105_bridge_revision(struct pci_dev *dev)
342 struct pci_dev *bridge;
345 * The bridge should be part of the same device, but function 0.
347 bridge = pci_get_bus_and_slot(dev->bus->number,
348 PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
353 * Make sure it is a Winbond 553 and is an ISA bridge.
355 if (bridge->vendor != PCI_VENDOR_ID_WINBOND ||
356 bridge->device != PCI_DEVICE_ID_WINBOND_83C553 ||
357 bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) {
362 * We need to find function 0's revision, not function 1
366 return bridge->revision;
370 * Enable the PCI device
372 * --BenH: It's arch fixup code that should enable channels that
373 * have not been enabled by firmware. I decided we can still enable
374 * channel 0 here at least, but channel 1 has to be enabled by
375 * firmware or arch code. We still set both to 16 bits mode.
377 static unsigned int __devinit init_chipset_sl82c105(struct pci_dev *dev, const char *msg)
381 DBG(("init_chipset_sl82c105()\n"));
383 pci_read_config_dword(dev, 0x40, &val);
384 val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16;
385 pci_write_config_dword(dev, 0x40, val);
386 pci_set_drvdata(dev, (void *)val);
392 * Initialise IDE channel
394 static void __devinit init_hwif_sl82c105(ide_hwif_t *hwif)
398 DBG(("init_hwif_sl82c105(hwif: ide%d)\n", hwif->index));
400 hwif->tuneproc = &sl82c105_tune_drive;
401 hwif->speedproc = &sl82c105_tune_chipset;
402 hwif->selectproc = &sl82c105_selectproc;
403 hwif->resetproc = &sl82c105_resetproc;
406 * We support 32-bit I/O on this interface, and
407 * it doesn't have problems with interrupts.
409 hwif->drives[0].io_32bit = hwif->drives[1].io_32bit = 1;
410 hwif->drives[0].unmask = hwif->drives[1].unmask = 1;
413 * We always autotune PIO, this is done before DMA is checked,
414 * so there's no risk of accidentally disabling DMA
416 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
421 rev = sl82c105_bridge_revision(hwif->pci_dev);
424 * Never ever EVER under any circumstances enable
425 * DMA when the bridge is this old.
427 printk(" %s: Winbond W83C553 bridge revision %d, "
428 "BM-DMA disabled\n", hwif->name, rev);
433 hwif->mwdma_mask = 0x07;
435 hwif->ide_dma_check = &sl82c105_ide_dma_check;
436 hwif->ide_dma_on = &sl82c105_ide_dma_on;
437 hwif->dma_off_quietly = &sl82c105_dma_off_quietly;
438 hwif->dma_lost_irq = &sl82c105_dma_lost_irq;
439 hwif->dma_start = &sl82c105_dma_start;
440 hwif->dma_timeout = &sl82c105_dma_timeout;
444 hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
447 hwif->serialized = hwif->mate->serialized = 1;
450 static ide_pci_device_t sl82c105_chipset __devinitdata = {
452 .init_chipset = init_chipset_sl82c105,
453 .init_hwif = init_hwif_sl82c105,
454 .autodma = NOAUTODMA,
455 .enablebits = {{0x40,0x01,0x01}, {0x40,0x10,0x10}},
456 .bootable = ON_BOARD,
457 .pio_mask = ATA_PIO5,
460 static int __devinit sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id)
462 return ide_setup_pci_device(dev, &sl82c105_chipset);
465 static struct pci_device_id sl82c105_pci_tbl[] = {
466 { PCI_DEVICE(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105), 0},
469 MODULE_DEVICE_TABLE(pci, sl82c105_pci_tbl);
471 static struct pci_driver driver = {
472 .name = "W82C105_IDE",
473 .id_table = sl82c105_pci_tbl,
474 .probe = sl82c105_init_one,
477 static int __init sl82c105_ide_init(void)
479 return ide_pci_register_driver(&driver);
482 module_init(sl82c105_ide_init);
484 MODULE_DESCRIPTION("PCI driver module for W82C105 IDE");
485 MODULE_LICENSE("GPL");