2 * linux/drivers/ide/pci/sc1200.c Version 0.92 Mar 10 2007
4 * Copyright (C) 2000-2002 Mark Lord <mlord@pobox.com>
5 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
7 * May be copied or modified under the terms of the GNU General Public License
9 * Development of this chipset driver was funded
10 * by the nice folks at National Semiconductor.
13 * Available from National Semiconductor
16 #include <linux/module.h>
17 #include <linux/types.h>
18 #include <linux/kernel.h>
19 #include <linux/delay.h>
20 #include <linux/timer.h>
22 #include <linux/ioport.h>
23 #include <linux/blkdev.h>
24 #include <linux/hdreg.h>
25 #include <linux/interrupt.h>
26 #include <linux/pci.h>
27 #include <linux/init.h>
28 #include <linux/ide.h>
33 #define SC1200_REV_A 0x00
34 #define SC1200_REV_B1 0x01
35 #define SC1200_REV_B3 0x02
36 #define SC1200_REV_C1 0x03
37 #define SC1200_REV_D1 0x04
39 #define PCI_CLK_33 0x00
40 #define PCI_CLK_48 0x01
41 #define PCI_CLK_66 0x02
42 #define PCI_CLK_33A 0x03
44 static unsigned short sc1200_get_pci_clock (void)
46 unsigned char chip_id, silicon_revision;
47 unsigned int pci_clock;
49 * Check the silicon revision, as not all versions of the chip
50 * have the register with the fast PCI bus timings.
52 chip_id = inb (0x903c);
53 silicon_revision = inb (0x903d);
55 // Read the fast pci clock frequency
56 if (chip_id == 0x04 && silicon_revision < SC1200_REV_B1) {
57 pci_clock = PCI_CLK_33;
59 // check clock generator configuration (cfcc)
60 // the clock is in bits 8 and 9 of this word
62 pci_clock = inw (0x901e);
65 if (pci_clock == PCI_CLK_33A)
66 pci_clock = PCI_CLK_33;
71 extern char *ide_xfer_verbose (byte xfer_rate);
74 * Set a new transfer mode at the drive
76 static int sc1200_set_xfer_mode (ide_drive_t *drive, byte mode)
78 printk("%s: sc1200_set_xfer_mode(%s)\n", drive->name, ide_xfer_verbose(mode));
79 return ide_config_drive_speed(drive, mode);
83 * Here are the standard PIO mode 0-4 timings for each "format".
84 * Format-0 uses fast data reg timings, with slower command reg timings.
85 * Format-1 uses fast timings for all registers, but won't work with all drives.
87 static const unsigned int sc1200_pio_timings[4][5] =
88 {{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010}, // format0 33Mhz
89 {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}, // format1, 33Mhz
90 {0xfaa3f4f3, 0xc23232b2, 0x513101c1, 0x31213121, 0x10211021}, // format1, 48Mhz
91 {0xfff4fff4, 0xf35353d3, 0x814102f1, 0x42314231, 0x11311131}}; // format1, 66Mhz
94 * After chip reset, the PIO timings are set to 0x00009172, which is not valid.
96 //#define SC1200_BAD_PIO(timings) (((timings)&~0x80000000)==0x00009172)
99 * The SC1200 specifies that two drives sharing a cable cannot mix
100 * UDMA/MDMA. It has to be one or the other, for the pair, though
101 * different timings can still be chosen for each drive. We could
102 * set the appropriate timing bits on the fly, but that might be
103 * a bit confusing. So, for now we statically handle this requirement
104 * by looking at our mate drive to see what it is capable of, before
105 * choosing a mode for our own drive.
107 static u8 sc1200_udma_filter(ide_drive_t *drive)
109 ide_hwif_t *hwif = drive->hwif;
110 ide_drive_t *mate = &hwif->drives[(drive->dn & 1) ^ 1];
111 struct hd_driveid *mateid = mate->id;
112 u8 mask = hwif->ultra_mask;
114 if (mate->present == 0)
117 if ((mateid->capability & 1) && __ide_dma_bad_drive(mate) == 0) {
118 if ((mateid->field_valid & 4) && (mateid->dma_ultra & 7))
120 if ((mateid->field_valid & 2) && (mateid->dma_mword & 7))
128 * sc1200_config_dma2() handles selection/setting of DMA/UDMA modes
129 * for both the chipset and drive.
131 static int sc1200_config_dma2 (ide_drive_t *drive, int mode)
133 ide_hwif_t *hwif = HWIF(drive);
134 int unit = drive->select.b.unit;
135 unsigned int reg, timings;
136 unsigned short pci_clock;
137 unsigned int basereg = hwif->channel ? 0x50 : 0x40;
140 * Default to DMA-off in case we run into trouble here.
142 hwif->dma_off_quietly(drive); /* turn off DMA while we fiddle */
143 outb(inb(hwif->dma_base+2)&~(unit?0x40:0x20), hwif->dma_base+2); /* clear DMA_capable bit */
146 * Tell the drive to switch to the new mode; abort on failure.
148 if (!mode || sc1200_set_xfer_mode(drive, mode)) {
149 printk("SC1200: set xfer mode failure\n");
150 return 1; /* failure */
153 pci_clock = sc1200_get_pci_clock();
156 * Now tune the chipset to match the drive:
158 * Note that each DMA mode has several timings associated with it.
159 * The correct timing depends on the fast PCI clock freq.
165 case PCI_CLK_33: timings = 0x00921250; break;
166 case PCI_CLK_48: timings = 0x00932470; break;
167 case PCI_CLK_66: timings = 0x009436a1; break;
172 case PCI_CLK_33: timings = 0x00911140; break;
173 case PCI_CLK_48: timings = 0x00922260; break;
174 case PCI_CLK_66: timings = 0x00933481; break;
179 case PCI_CLK_33: timings = 0x00911030; break;
180 case PCI_CLK_48: timings = 0x00922140; break;
181 case PCI_CLK_66: timings = 0x00923261; break;
186 case PCI_CLK_33: timings = 0x00077771; break;
187 case PCI_CLK_48: timings = 0x000bbbb2; break;
188 case PCI_CLK_66: timings = 0x000ffff3; break;
193 case PCI_CLK_33: timings = 0x00012121; break;
194 case PCI_CLK_48: timings = 0x00024241; break;
195 case PCI_CLK_66: timings = 0x00035352; break;
200 case PCI_CLK_33: timings = 0x00002020; break;
201 case PCI_CLK_48: timings = 0x00013131; break;
202 case PCI_CLK_66: timings = 0x00015151; break;
208 printk("%s: sc1200_config_dma: huh? mode=%02x clk=%x \n", drive->name, mode, pci_clock);
209 return 1; /* failure */
212 if (unit == 0) { /* are we configuring drive0? */
213 pci_read_config_dword(hwif->pci_dev, basereg+4, ®);
214 timings |= reg & 0x80000000; /* preserve PIO format bit */
215 pci_write_config_dword(hwif->pci_dev, basereg+4, timings);
217 pci_write_config_dword(hwif->pci_dev, basereg+12, timings);
220 outb(inb(hwif->dma_base+2)|(unit?0x40:0x20), hwif->dma_base+2); /* set DMA_capable bit */
222 return 0; /* success */
226 * sc1200_config_dma() handles selection/setting of DMA/UDMA modes
227 * for both the chipset and drive.
229 static int sc1200_config_dma (ide_drive_t *drive)
233 if (ide_use_dma(drive))
234 mode = ide_max_dma_mode(drive);
236 return sc1200_config_dma2(drive, mode);
240 /* Replacement for the standard ide_dma_end action in
243 * returns 1 on error, 0 otherwise
245 static int sc1200_ide_dma_end (ide_drive_t *drive)
247 ide_hwif_t *hwif = HWIF(drive);
248 unsigned long dma_base = hwif->dma_base;
251 dma_stat = inb(dma_base+2); /* get DMA status */
254 printk(" ide_dma_end dma_stat=%0x err=%x newerr=%x\n",
255 dma_stat, ((dma_stat&7)!=4), ((dma_stat&2)==2));
257 outb(dma_stat|0x1b, dma_base+2); /* clear the INTR & ERROR bits */
258 outb(inb(dma_base)&~1, dma_base); /* !! DO THIS HERE !! stop DMA */
260 drive->waiting_for_dma = 0;
261 ide_destroy_dmatable(drive); /* purge DMA mappings */
263 return (dma_stat & 7) != 4; /* verify good DMA status */
267 * sc1200_tuneproc() handles selection/setting of PIO modes
268 * for both the chipset and drive.
270 * All existing BIOSs for this chipset guarantee that all drives
271 * will have valid default PIO timings set up before we get here.
273 static void sc1200_tuneproc (ide_drive_t *drive, byte pio) /* mode=255 means "autotune" */
275 ide_hwif_t *hwif = HWIF(drive);
277 static byte modes[5] = {XFER_PIO_0, XFER_PIO_1, XFER_PIO_2, XFER_PIO_3, XFER_PIO_4};
281 case 200: mode = XFER_UDMA_0; break;
282 case 201: mode = XFER_UDMA_1; break;
283 case 202: mode = XFER_UDMA_2; break;
284 case 100: mode = XFER_MW_DMA_0; break;
285 case 101: mode = XFER_MW_DMA_1; break;
286 case 102: mode = XFER_MW_DMA_2; break;
289 printk("SC1200: %s: changing (U)DMA mode\n", drive->name);
290 (void)sc1200_config_dma2(drive, mode);
294 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
295 printk("SC1200: %s: setting PIO mode%d\n", drive->name, pio);
296 if (!sc1200_set_xfer_mode(drive, modes[pio])) {
297 unsigned int basereg = hwif->channel ? 0x50 : 0x40;
298 pci_read_config_dword (hwif->pci_dev, basereg+4, &format);
299 format = (format >> 31) & 1;
301 format += sc1200_get_pci_clock();
302 pci_write_config_dword(hwif->pci_dev, basereg + (drive->select.b.unit << 3), sc1200_pio_timings[format][pio]);
307 static ide_hwif_t *lookup_pci_dev (ide_hwif_t *prev, struct pci_dev *dev)
311 for (h = 0; h < MAX_HWIFS; h++) {
312 ide_hwif_t *hwif = &ide_hwifs[h];
315 prev = NULL; // found previous, now look for next match
317 if (hwif && hwif->pci_dev == dev)
318 return hwif; // found next match
321 return NULL; // not found
324 typedef struct sc1200_saved_state_s {
326 } sc1200_saved_state_t;
329 static int sc1200_suspend (struct pci_dev *dev, pm_message_t state)
331 ide_hwif_t *hwif = NULL;
333 printk("SC1200: suspend(%u)\n", state.event);
335 if (state.event == PM_EVENT_ON) {
336 // we only save state when going from full power to less
339 // Loop over all interfaces that are part of this PCI device:
341 while ((hwif = lookup_pci_dev(hwif, dev)) != NULL) {
342 sc1200_saved_state_t *ss;
343 unsigned int basereg, r;
345 // allocate a permanent save area, if not already allocated
347 ss = (sc1200_saved_state_t *)hwif->config_data;
349 ss = kmalloc(sizeof(sc1200_saved_state_t), GFP_KERNEL);
352 hwif->config_data = (unsigned long)ss;
354 ss = (sc1200_saved_state_t *)hwif->config_data;
356 // Save timing registers: this may be unnecessary if
359 basereg = hwif->channel ? 0x50 : 0x40;
360 for (r = 0; r < 4; ++r) {
361 pci_read_config_dword (hwif->pci_dev, basereg + (r<<2), &ss->regs[r]);
366 /* You don't need to iterate over disks -- sysfs should have done that for you already */
368 pci_disable_device(dev);
369 pci_set_power_state(dev, pci_choose_state(dev, state));
370 dev->current_state = state.event;
374 static int sc1200_resume (struct pci_dev *dev)
376 ide_hwif_t *hwif = NULL;
378 pci_set_power_state(dev, PCI_D0); // bring chip back from sleep state
379 dev->current_state = PM_EVENT_ON;
380 pci_enable_device(dev);
382 // loop over all interfaces that are part of this pci device:
384 while ((hwif = lookup_pci_dev(hwif, dev)) != NULL) {
385 unsigned int basereg, r, d, format;
386 sc1200_saved_state_t *ss = (sc1200_saved_state_t *)hwif->config_data;
389 // Restore timing registers: this may be unnecessary if BIOS also does it
391 basereg = hwif->channel ? 0x50 : 0x40;
393 for (r = 0; r < 4; ++r) {
394 pci_write_config_dword(hwif->pci_dev, basereg + (r<<2), ss->regs[r]);
398 // Re-program drive PIO modes
400 pci_read_config_dword(hwif->pci_dev, basereg+4, &format);
401 format = (format >> 31) & 1;
403 format += sc1200_get_pci_clock();
404 for (d = 0; d < 2; ++d) {
405 ide_drive_t *drive = &(hwif->drives[d]);
406 if (drive->present) {
407 unsigned int pio, timings;
408 pci_read_config_dword(hwif->pci_dev, basereg+(drive->select.b.unit << 3), &timings);
409 for (pio = 0; pio <= 4; ++pio) {
410 if (sc1200_pio_timings[format][pio] == timings)
414 pio = 255; /* autotune */
415 (void)sc1200_tuneproc(drive, pio);
419 // Re-program drive DMA modes
421 for (d = 0; d < MAX_DRIVES; ++d) {
422 ide_drive_t *drive = &(hwif->drives[d]);
423 if (drive->present && !__ide_dma_bad_drive(drive)) {
424 int was_using_dma = drive->using_dma;
425 hwif->dma_off_quietly(drive);
426 sc1200_config_dma(drive);
427 if (!was_using_dma && drive->using_dma) {
428 hwif->dma_off_quietly(drive);
438 * This gets invoked by the IDE driver once for each channel,
439 * and performs channel-specific pre-initialization before drive probing.
441 static void __devinit init_hwif_sc1200 (ide_hwif_t *hwif)
444 hwif->serialized = hwif->mate->serialized = 1;
446 if (hwif->dma_base) {
447 hwif->udma_filter = sc1200_udma_filter;
448 hwif->ide_dma_check = &sc1200_config_dma;
449 hwif->ide_dma_end = &sc1200_ide_dma_end;
452 hwif->tuneproc = &sc1200_tuneproc;
455 hwif->ultra_mask = 0x07;
456 hwif->mwdma_mask = 0x07;
458 hwif->drives[0].autodma = hwif->autodma;
459 hwif->drives[1].autodma = hwif->autodma;
462 static ide_pci_device_t sc1200_chipset __devinitdata = {
464 .init_hwif = init_hwif_sc1200,
467 .bootable = ON_BOARD,
470 static int __devinit sc1200_init_one(struct pci_dev *dev, const struct pci_device_id *id)
472 return ide_setup_pci_device(dev, &sc1200_chipset);
475 static struct pci_device_id sc1200_pci_tbl[] = {
476 { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SCx200_IDE), 0},
479 MODULE_DEVICE_TABLE(pci, sc1200_pci_tbl);
481 static struct pci_driver driver = {
482 .name = "SC1200_IDE",
483 .id_table = sc1200_pci_tbl,
484 .probe = sc1200_init_one,
486 .suspend = sc1200_suspend,
487 .resume = sc1200_resume,
491 static int __init sc1200_ide_init(void)
493 return ide_pci_register_driver(&driver);
496 module_init(sc1200_ide_init);
498 MODULE_AUTHOR("Mark Lord");
499 MODULE_DESCRIPTION("PCI driver module for NS SC1200 IDE");
500 MODULE_LICENSE("GPL");