drivers/ide/pci/pdc202xx_old.c

   1 /*
   2  *  linux/drivers/ide/pci/pdc202xx_old.c        Version 0.51    Jul 27, 2007
   3  *
   4  *  Copyright (C) 1998-2002             Andre Hedrick <andre@linux-ide.org>
   5  *  Copyright (C) 2006-2007             MontaVista Software, Inc.
   6  *  Copyright (C) 2007                  Bartlomiej Zolnierkiewicz
   7  *
   8  *  Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this
   9  *  compiled into the kernel if you have more than one card installed.
  10  *  Note that BIOS v1.29 is reported to fix the problem.  Since this is
  11  *  safe chipset tuning, including this support is harmless
  12  *
  13  *  Promise Ultra66 cards with BIOS v1.11 this
  14  *  compiled into the kernel if you have more than one card installed.
  15  *
  16  *  Promise Ultra100 cards.
  17  *
  18  *  The latest chipset code will support the following ::
  19  *  Three Ultra33 controllers and 12 drives.
  20  *  8 are UDMA supported and 4 are limited to DMA mode 2 multi-word.
  21  *  The 8/4 ratio is a BIOS code limit by promise.
  22  *
  23  *  UNLESS you enable "CONFIG_PDC202XX_BURST"
  24  *
  25  */
  26
  27 /*
  28  *  Portions Copyright (C) 1999 Promise Technology, Inc.
  29  *  Author: Frank Tiernan (frankt@promise.com)
  30  *  Released under terms of General Public License
  31  */
  32
  33 #include <linux/types.h>
  34 #include <linux/module.h>
  35 #include <linux/kernel.h>
  36 #include <linux/delay.h>
  37 #include <linux/timer.h>
  38 #include <linux/mm.h>
  39 #include <linux/ioport.h>
  40 #include <linux/blkdev.h>
  41 #include <linux/hdreg.h>
  42 #include <linux/interrupt.h>
  43 #include <linux/pci.h>
  44 #include <linux/init.h>
  45 #include <linux/ide.h>
  46
  47 #include <asm/io.h>
  48 #include <asm/irq.h>
  49
  50 #define PDC202XX_DEBUG_DRIVE_INFO       0
  51
  52 static const char *pdc_quirk_drives[] = {
  53         "QUANTUM FIREBALLlct08 08",
  54         "QUANTUM FIREBALLP KA6.4",
  55         "QUANTUM FIREBALLP KA9.1",
  56         "QUANTUM FIREBALLP LM20.4",
  57         "QUANTUM FIREBALLP KX13.6",
  58         "QUANTUM FIREBALLP KX20.5",
  59         "QUANTUM FIREBALLP KX27.3",
  60         "QUANTUM FIREBALLP LM20.5",
  61         NULL
  62 };
  63
  64 static void pdc_old_disable_66MHz_clock(ide_hwif_t *);
  65
  66 static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed)
  67 {
  68         ide_hwif_t *hwif        = HWIF(drive);
  69         struct pci_dev *dev     = hwif->pci_dev;
  70         u8 drive_pci            = 0x60 + (drive->dn << 2);
  71
  72         u8                      AP = 0, BP = 0, CP = 0;
  73         u8                      TA = 0, TB = 0, TC = 0;
  74
  75 #if PDC202XX_DEBUG_DRIVE_INFO
  76         u32                     drive_conf = 0;
  77         pci_read_config_dword(dev, drive_pci, &drive_conf);
  78 #endif
  79
  80         /*
  81          * TODO: do this once per channel
  82          */
  83         if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
  84                 pdc_old_disable_66MHz_clock(hwif);
  85
  86         pci_read_config_byte(dev, drive_pci,     &AP);
  87         pci_read_config_byte(dev, drive_pci + 1, &BP);
  88         pci_read_config_byte(dev, drive_pci + 2, &CP);
  89
  90         switch(speed) {
  91                 case XFER_UDMA_5:
  92                 case XFER_UDMA_4:       TB = 0x20; TC = 0x01; break;
  93                 case XFER_UDMA_2:       TB = 0x20; TC = 0x01; break;
  94                 case XFER_UDMA_3:
  95                 case XFER_UDMA_1:       TB = 0x40; TC = 0x02; break;
  96                 case XFER_UDMA_0:
  97                 case XFER_MW_DMA_2:     TB = 0x60; TC = 0x03; break;
  98                 case XFER_MW_DMA_1:     TB = 0x60; TC = 0x04; break;
  99                 case XFER_MW_DMA_0:     TB = 0xE0; TC = 0x0F; break;
 100                 case XFER_SW_DMA_2:     TB = 0x60; TC = 0x05; break;
 101                 case XFER_SW_DMA_1:     TB = 0x80; TC = 0x06; break;
 102                 case XFER_SW_DMA_0:     TB = 0xC0; TC = 0x0B; break;
 103                 case XFER_PIO_4:        TA = 0x01; TB = 0x04; break;
 104                 case XFER_PIO_3:        TA = 0x02; TB = 0x06; break;
 105                 case XFER_PIO_2:        TA = 0x03; TB = 0x08; break;
 106                 case XFER_PIO_1:        TA = 0x05; TB = 0x0C; break;
 107                 case XFER_PIO_0:
 108                 default:                TA = 0x09; TB = 0x13; break;
 109         }
 110
 111         if (speed < XFER_SW_DMA_0) {
 112                 /*
 113                  * preserve SYNC_INT / ERDDY_EN bits while clearing
 114                  * Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
 115                  */
 116                 AP &= ~0x3f;
 117                 if (drive->id->capability & 4)
 118                         AP |= 0x20;     /* set IORDY_EN bit */
 119                 if (drive->media == ide_disk)
 120                         AP |= 0x10;     /* set Prefetch_EN bit */
 121                 /* clear PB[4:0] bits of register B */
 122                 BP &= ~0x1f;
 123                 pci_write_config_byte(dev, drive_pci,     AP | TA);
 124                 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
 125         } else {
 126                 /* clear MB[2:0] bits of register B */
 127                 BP &= ~0xe0;
 128                 /* clear MC[3:0] bits of register C */
 129                 CP &= ~0x0f;
 130                 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
 131                 pci_write_config_byte(dev, drive_pci + 2, CP | TC);
 132         }
 133
 134 #if PDC202XX_DEBUG_DRIVE_INFO
 135         printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
 136                 drive->name, ide_xfer_verbose(speed),
 137                 drive->dn, drive_conf);
 138         pci_read_config_dword(dev, drive_pci, &drive_conf);
 139         printk("0x%08x\n", drive_conf);
 140 #endif
 141 }
 142
 143 static void pdc202xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
 144 {
 145         pdc202xx_set_mode(drive, XFER_PIO_0 + pio);
 146 }
 147
 148 static u8 pdc202xx_old_cable_detect (ide_hwif_t *hwif)
 149 {
 150         u16 CIS = 0, mask = (hwif->channel) ? (1<<11) : (1<<10);
 151
 152         pci_read_config_word(hwif->pci_dev, 0x50, &CIS);
 153
 154         return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
 155 }
 156
 157 /*
 158  * Set the control register to use the 66MHz system
 159  * clock for UDMA 3/4/5 mode operation when necessary.
 160  *
 161  * FIXME: this register is shared by both channels, some locking is needed
 162  *
 163  * It may also be possible to leave the 66MHz clock on
 164  * and readjust the timing parameters.
 165  */
 166 static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
 167 {
 168         unsigned long clock_reg = hwif->dma_master + 0x11;
 169         u8 clock = inb(clock_reg);
 170
 171         outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
 172 }
 173
 174 static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
 175 {
 176         unsigned long clock_reg = hwif->dma_master + 0x11;
 177         u8 clock = inb(clock_reg);
 178
 179         outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
 180 }
 181
 182 static int pdc202xx_config_drive_xfer_rate (ide_drive_t *drive)
 183 {
 184         drive->init_speed = 0;
 185
 186         if (ide_tune_dma(drive))
 187                 return 0;
 188
 189         if (ide_use_fast_pio(drive))
 190                 ide_set_max_pio(drive);
 191
 192         return -1;
 193 }
 194
 195 static int pdc202xx_quirkproc (ide_drive_t *drive)
 196 {
 197         const char **list, *model = drive->id->model;
 198
 199         for (list = pdc_quirk_drives; *list != NULL; list++)
 200                 if (strstr(model, *list) != NULL)
 201                         return 2;
 202         return 0;
 203 }
 204
 205 static void pdc202xx_old_ide_dma_start(ide_drive_t *drive)
 206 {
 207         if (drive->current_speed > XFER_UDMA_2)
 208                 pdc_old_enable_66MHz_clock(drive->hwif);
 209         if (drive->media != ide_disk || drive->addressing == 1) {
 210                 struct request *rq      = HWGROUP(drive)->rq;
 211                 ide_hwif_t *hwif        = HWIF(drive);
 212                 unsigned long high_16   = hwif->dma_master;
 213                 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
 214                 u32 word_count  = 0;
 215                 u8 clock = inb(high_16 + 0x11);
 216
 217                 outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
 218                 word_count = (rq->nr_sectors << 8);
 219                 word_count = (rq_data_dir(rq) == READ) ?
 220                                         word_count | 0x05000000 :
 221                                         word_count | 0x06000000;
 222                 outl(word_count, atapi_reg);
 223         }
 224         ide_dma_start(drive);
 225 }
 226
 227 static int pdc202xx_old_ide_dma_end(ide_drive_t *drive)
 228 {
 229         if (drive->media != ide_disk || drive->addressing == 1) {
 230                 ide_hwif_t *hwif        = HWIF(drive);
 231                 unsigned long high_16   = hwif->dma_master;
 232                 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
 233                 u8 clock                = 0;
 234
 235                 outl(0, atapi_reg); /* zero out extra */
 236                 clock = inb(high_16 + 0x11);
 237                 outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
 238         }
 239         if (drive->current_speed > XFER_UDMA_2)
 240                 pdc_old_disable_66MHz_clock(drive->hwif);
 241         return __ide_dma_end(drive);
 242 }
 243
 244 static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive)
 245 {
 246         ide_hwif_t *hwif        = HWIF(drive);
 247         unsigned long high_16   = hwif->dma_master;
 248         u8 dma_stat             = inb(hwif->dma_status);
 249         u8 sc1d                 = inb(high_16 + 0x001d);
 250
 251         if (hwif->channel) {
 252                 /* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
 253                 if ((sc1d & 0x50) == 0x50)
 254                         goto somebody_else;
 255                 else if ((sc1d & 0x40) == 0x40)
 256                         return (dma_stat & 4) == 4;
 257         } else {
 258                 /* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
 259                 if ((sc1d & 0x05) == 0x05)
 260                         goto somebody_else;
 261                 else if ((sc1d & 0x04) == 0x04)
 262                         return (dma_stat & 4) == 4;
 263         }
 264 somebody_else:
 265         return (dma_stat & 4) == 4;     /* return 1 if INTR asserted */
 266 }
 267
 268 static void pdc202xx_dma_lost_irq(ide_drive_t *drive)
 269 {
 270         ide_hwif_t *hwif = HWIF(drive);
 271
 272         if (hwif->resetproc != NULL)
 273                 hwif->resetproc(drive);
 274
 275         ide_dma_lost_irq(drive);
 276 }
 277
 278 static void pdc202xx_dma_timeout(ide_drive_t *drive)
 279 {
 280         ide_hwif_t *hwif = HWIF(drive);
 281
 282         if (hwif->resetproc != NULL)
 283                 hwif->resetproc(drive);
 284
 285         ide_dma_timeout(drive);
 286 }
 287
 288 static void pdc202xx_reset_host (ide_hwif_t *hwif)
 289 {
 290         unsigned long high_16   = hwif->dma_master;
 291         u8 udma_speed_flag      = inb(high_16 | 0x001f);
 292
 293         outb(udma_speed_flag | 0x10, high_16 | 0x001f);
 294         mdelay(100);
 295         outb(udma_speed_flag & ~0x10, high_16 | 0x001f);
 296         mdelay(2000);   /* 2 seconds ?! */
 297
 298         printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
 299                 hwif->channel ? "Secondary" : "Primary");
 300 }
 301
 302 static void pdc202xx_reset (ide_drive_t *drive)
 303 {
 304         ide_hwif_t *hwif        = HWIF(drive);
 305         ide_hwif_t *mate        = hwif->mate;
 306
 307         pdc202xx_reset_host(hwif);
 308         pdc202xx_reset_host(mate);
 309
 310         ide_set_max_pio(drive);
 311 }
 312
 313 static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev,
 314                                                         const char *name)
 315 {
 316         return dev->irq;
 317 }
 318
 319 static void __devinit init_hwif_pdc202xx(ide_hwif_t *hwif)
 320 {
 321         struct pci_dev *dev = hwif->pci_dev;
 322
 323         /* PDC20265 has problems with large LBA48 requests */
 324         if ((dev->device == PCI_DEVICE_ID_PROMISE_20267) ||
 325             (dev->device == PCI_DEVICE_ID_PROMISE_20265))
 326                 hwif->rqsize = 256;
 327
 328         hwif->autodma = 0;
 329
 330         hwif->set_pio_mode = &pdc202xx_set_pio_mode;
 331         hwif->set_dma_mode = &pdc202xx_set_mode;
 332
 333         hwif->quirkproc = &pdc202xx_quirkproc;
 334
 335         if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246)
 336                 hwif->resetproc = &pdc202xx_reset;
 337
 338         hwif->err_stops_fifo = 1;
 339
 340         hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
 341
 342         if (hwif->dma_base == 0)
 343                 return;
 344
 345         hwif->ultra_mask = hwif->cds->udma_mask;
 346         hwif->mwdma_mask = 0x07;
 347         hwif->swdma_mask = 0x07;
 348         hwif->atapi_dma = 1;
 349
 350         hwif->ide_dma_check = &pdc202xx_config_drive_xfer_rate;
 351         hwif->dma_lost_irq = &pdc202xx_dma_lost_irq;
 352         hwif->dma_timeout = &pdc202xx_dma_timeout;
 353
 354         if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246) {
 355                 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
 356                         hwif->cbl = pdc202xx_old_cable_detect(hwif);
 357
 358                 hwif->dma_start = &pdc202xx_old_ide_dma_start;
 359                 hwif->ide_dma_end = &pdc202xx_old_ide_dma_end;
 360         }
 361         hwif->ide_dma_test_irq = &pdc202xx_old_ide_dma_test_irq;
 362
 363         if (!noautodma)
 364                 hwif->autodma = 1;
 365         hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
 366 }
 367
 368 static void __devinit init_dma_pdc202xx(ide_hwif_t *hwif, unsigned long dmabase)
 369 {
 370         u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
 371
 372         if (hwif->channel) {
 373                 ide_setup_dma(hwif, dmabase, 8);
 374                 return;
 375         }
 376
 377         udma_speed_flag = inb(dmabase | 0x1f);
 378         primary_mode    = inb(dmabase | 0x1a);
 379         secondary_mode  = inb(dmabase | 0x1b);
 380         printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
 381                 "Primary %s Mode " \
 382                 "Secondary %s Mode.\n", hwif->cds->name,
 383                 (udma_speed_flag & 1) ? "EN" : "DIS",
 384                 (primary_mode & 1) ? "MASTER" : "PCI",
 385                 (secondary_mode & 1) ? "MASTER" : "PCI" );
 386
 387 #ifdef CONFIG_PDC202XX_BURST
 388         if (!(udma_speed_flag & 1)) {
 389                 printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
 390                         hwif->cds->name, udma_speed_flag,
 391                         (udma_speed_flag|1));
 392                 outb(udma_speed_flag | 1, dmabase | 0x1f);
 393                 printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN");
 394         }
 395 #endif /* CONFIG_PDC202XX_BURST */
 396
 397         ide_setup_dma(hwif, dmabase, 8);
 398 }
 399
 400 static int __devinit init_setup_pdc202ata4(struct pci_dev *dev,
 401                                            ide_pci_device_t *d)
 402 {
 403         if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
 404                 u8 irq = 0, irq2 = 0;
 405                 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
 406                 /* 0xbc */
 407                 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
 408                 if (irq != irq2) {
 409                         pci_write_config_byte(dev,
 410                                 (PCI_INTERRUPT_LINE)|0x80, irq);     /* 0xbc */
 411                         printk(KERN_INFO "%s: pci-config space interrupt "
 412                                 "mirror fixed.\n", d->name);
 413                 }
 414         }
 415         return ide_setup_pci_device(dev, d);
 416 }
 417
 418 static int __devinit init_setup_pdc20265(struct pci_dev *dev,
 419                                          ide_pci_device_t *d)
 420 {
 421         if ((dev->bus->self) &&
 422             (dev->bus->self->vendor == PCI_VENDOR_ID_INTEL) &&
 423             ((dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) ||
 424              (dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960RM))) {
 425                 printk(KERN_INFO "ide: Skipping Promise PDC20265 "
 426                         "attached to I2O RAID controller.\n");
 427                 return -ENODEV;
 428         }
 429         return ide_setup_pci_device(dev, d);
 430 }
 431
 432 static int __devinit init_setup_pdc202xx(struct pci_dev *dev,
 433                                          ide_pci_device_t *d)
 434 {
 435         return ide_setup_pci_device(dev, d);
 436 }
 437
 438 static ide_pci_device_t pdc202xx_chipsets[] __devinitdata = {
 439         {       /* 0 */
 440                 .name           = "PDC20246",
 441                 .init_setup     = init_setup_pdc202ata4,
 442                 .init_chipset   = init_chipset_pdc202xx,
 443                 .init_hwif      = init_hwif_pdc202xx,
 444                 .init_dma       = init_dma_pdc202xx,
 445                 .autodma        = AUTODMA,
 446                 .bootable       = OFF_BOARD,
 447                 .extra          = 16,
 448                 .pio_mask       = ATA_PIO4,
 449                 .udma_mask      = 0x07, /* udma0-2 */
 450         },{     /* 1 */
 451                 .name           = "PDC20262",
 452                 .init_setup     = init_setup_pdc202ata4,
 453                 .init_chipset   = init_chipset_pdc202xx,
 454                 .init_hwif      = init_hwif_pdc202xx,
 455                 .init_dma       = init_dma_pdc202xx,
 456                 .autodma        = AUTODMA,
 457                 .bootable       = OFF_BOARD,
 458                 .extra          = 48,
 459                 .pio_mask       = ATA_PIO4,
 460                 .udma_mask      = 0x1f, /* udma0-4 */
 461         },{     /* 2 */
 462                 .name           = "PDC20263",
 463                 .init_setup     = init_setup_pdc202ata4,
 464                 .init_chipset   = init_chipset_pdc202xx,
 465                 .init_hwif      = init_hwif_pdc202xx,
 466                 .init_dma       = init_dma_pdc202xx,
 467                 .autodma        = AUTODMA,
 468                 .bootable       = OFF_BOARD,
 469                 .extra          = 48,
 470                 .pio_mask       = ATA_PIO4,
 471                 .udma_mask      = 0x1f, /* udma0-4 */
 472         },{     /* 3 */
 473                 .name           = "PDC20265",
 474                 .init_setup     = init_setup_pdc20265,
 475                 .init_chipset   = init_chipset_pdc202xx,
 476                 .init_hwif      = init_hwif_pdc202xx,
 477                 .init_dma       = init_dma_pdc202xx,
 478                 .autodma        = AUTODMA,
 479                 .bootable       = OFF_BOARD,
 480                 .extra          = 48,
 481                 .pio_mask       = ATA_PIO4,
 482                 .udma_mask      = 0x3f, /* udma0-5 */
 483         },{     /* 4 */
 484                 .name           = "PDC20267",
 485                 .init_setup     = init_setup_pdc202xx,
 486                 .init_chipset   = init_chipset_pdc202xx,
 487                 .init_hwif      = init_hwif_pdc202xx,
 488                 .init_dma       = init_dma_pdc202xx,
 489                 .autodma        = AUTODMA,
 490                 .bootable       = OFF_BOARD,
 491                 .extra          = 48,
 492                 .pio_mask       = ATA_PIO4,
 493                 .udma_mask      = 0x3f, /* udma0-5 */
 494         }
 495 };
 496
 497 /**
 498  *      pdc202xx_init_one       -       called when a PDC202xx is found
 499  *      @dev: the pdc202xx device
 500  *      @id: the matching pci id
 501  *
 502  *      Called when the PCI registration layer (or the IDE initialization)
 503  *      finds a device matching our IDE device tables.
 504  */
 505
 506 static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 507 {
 508         ide_pci_device_t *d = &pdc202xx_chipsets[id->driver_data];
 509
 510         return d->init_setup(dev, d);
 511 }
 512
 513 static struct pci_device_id pdc202xx_pci_tbl[] = {
 514         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20246, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 515         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20262, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
 516         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
 517         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20265, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
 518         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20267, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
 519         { 0, },
 520 };
 521 MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
 522
 523 static struct pci_driver driver = {
 524         .name           = "Promise_Old_IDE",
 525         .id_table       = pdc202xx_pci_tbl,
 526         .probe          = pdc202xx_init_one,
 527 };
 528
 529 static int __init pdc202xx_ide_init(void)
 530 {
 531         return ide_pci_register_driver(&driver);
 532 }
 533
 534 module_init(pdc202xx_ide_init);
 535
 536 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
 537 MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
 538 MODULE_LICENSE("GPL");