2 * linux/drivers/ide/pci/aec62xx.c Version 0.11 March 27, 2002
4 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
8 #include <linux/module.h>
9 #include <linux/types.h>
10 #include <linux/pci.h>
11 #include <linux/delay.h>
12 #include <linux/hdreg.h>
13 #include <linux/ide.h>
14 #include <linux/init.h>
18 struct chipset_bus_clock_list_entry {
24 static const struct chipset_bus_clock_list_entry aec6xxx_33_base [] = {
25 { XFER_UDMA_6, 0x31, 0x07 },
26 { XFER_UDMA_5, 0x31, 0x06 },
27 { XFER_UDMA_4, 0x31, 0x05 },
28 { XFER_UDMA_3, 0x31, 0x04 },
29 { XFER_UDMA_2, 0x31, 0x03 },
30 { XFER_UDMA_1, 0x31, 0x02 },
31 { XFER_UDMA_0, 0x31, 0x01 },
33 { XFER_MW_DMA_2, 0x31, 0x00 },
34 { XFER_MW_DMA_1, 0x31, 0x00 },
35 { XFER_MW_DMA_0, 0x0a, 0x00 },
36 { XFER_PIO_4, 0x31, 0x00 },
37 { XFER_PIO_3, 0x33, 0x00 },
38 { XFER_PIO_2, 0x08, 0x00 },
39 { XFER_PIO_1, 0x0a, 0x00 },
40 { XFER_PIO_0, 0x00, 0x00 },
44 static const struct chipset_bus_clock_list_entry aec6xxx_34_base [] = {
45 { XFER_UDMA_6, 0x41, 0x06 },
46 { XFER_UDMA_5, 0x41, 0x05 },
47 { XFER_UDMA_4, 0x41, 0x04 },
48 { XFER_UDMA_3, 0x41, 0x03 },
49 { XFER_UDMA_2, 0x41, 0x02 },
50 { XFER_UDMA_1, 0x41, 0x01 },
51 { XFER_UDMA_0, 0x41, 0x01 },
53 { XFER_MW_DMA_2, 0x41, 0x00 },
54 { XFER_MW_DMA_1, 0x42, 0x00 },
55 { XFER_MW_DMA_0, 0x7a, 0x00 },
56 { XFER_PIO_4, 0x41, 0x00 },
57 { XFER_PIO_3, 0x43, 0x00 },
58 { XFER_PIO_2, 0x78, 0x00 },
59 { XFER_PIO_1, 0x7a, 0x00 },
60 { XFER_PIO_0, 0x70, 0x00 },
65 ((struct chipset_bus_clock_list_entry *) pci_get_drvdata((D)))
69 * TO DO: active tuning and correction of cards without a bios.
71 static u8 pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
73 for ( ; chipset_table->xfer_speed ; chipset_table++)
74 if (chipset_table->xfer_speed == speed) {
75 return chipset_table->chipset_settings;
77 return chipset_table->chipset_settings;
80 static u8 pci_bus_clock_list_ultra (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
82 for ( ; chipset_table->xfer_speed ; chipset_table++)
83 if (chipset_table->xfer_speed == speed) {
84 return chipset_table->ultra_settings;
86 return chipset_table->ultra_settings;
89 static u8 aec62xx_ratemask (ide_drive_t *drive)
91 ide_hwif_t *hwif = HWIF(drive);
94 switch(hwif->pci_dev->device) {
95 case PCI_DEVICE_ID_ARTOP_ATP865:
96 case PCI_DEVICE_ID_ARTOP_ATP865R:
97 mode = (inb(hwif->channel ?
98 hwif->mate->dma_status :
99 hwif->dma_status) & 0x10) ? 4 : 3;
101 case PCI_DEVICE_ID_ARTOP_ATP860:
102 case PCI_DEVICE_ID_ARTOP_ATP860R:
105 case PCI_DEVICE_ID_ARTOP_ATP850UF:
110 if (!eighty_ninty_three(drive))
111 mode = min(mode, (u8)1);
115 static int aec6210_tune_chipset (ide_drive_t *drive, u8 xferspeed)
117 ide_hwif_t *hwif = HWIF(drive);
118 struct pci_dev *dev = hwif->pci_dev;
120 u8 speed = ide_rate_filter(aec62xx_ratemask(drive), xferspeed);
121 u8 ultra = 0, ultra_conf = 0;
122 u8 tmp0 = 0, tmp1 = 0, tmp2 = 0;
125 local_irq_save(flags);
126 /* 0x40|(2*drive->dn): Active, 0x41|(2*drive->dn): Recovery */
127 pci_read_config_word(dev, 0x40|(2*drive->dn), &d_conf);
128 tmp0 = pci_bus_clock_list(speed, BUSCLOCK(dev));
129 d_conf = ((tmp0 & 0xf0) << 4) | (tmp0 & 0xf);
130 pci_write_config_word(dev, 0x40|(2*drive->dn), d_conf);
134 pci_read_config_byte(dev, 0x54, &ultra);
135 tmp1 = ((0x00 << (2*drive->dn)) | (ultra & ~(3 << (2*drive->dn))));
136 ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev));
137 tmp2 = ((ultra_conf << (2*drive->dn)) | (tmp1 & ~(3 << (2*drive->dn))));
138 pci_write_config_byte(dev, 0x54, tmp2);
139 local_irq_restore(flags);
140 return(ide_config_drive_speed(drive, speed));
143 static int aec6260_tune_chipset (ide_drive_t *drive, u8 xferspeed)
145 ide_hwif_t *hwif = HWIF(drive);
146 struct pci_dev *dev = hwif->pci_dev;
147 u8 speed = ide_rate_filter(aec62xx_ratemask(drive), xferspeed);
148 u8 unit = (drive->select.b.unit & 0x01);
149 u8 tmp1 = 0, tmp2 = 0;
150 u8 ultra = 0, drive_conf = 0, ultra_conf = 0;
153 local_irq_save(flags);
154 /* high 4-bits: Active, low 4-bits: Recovery */
155 pci_read_config_byte(dev, 0x40|drive->dn, &drive_conf);
156 drive_conf = pci_bus_clock_list(speed, BUSCLOCK(dev));
157 pci_write_config_byte(dev, 0x40|drive->dn, drive_conf);
159 pci_read_config_byte(dev, (0x44|hwif->channel), &ultra);
160 tmp1 = ((0x00 << (4*unit)) | (ultra & ~(7 << (4*unit))));
161 ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev));
162 tmp2 = ((ultra_conf << (4*unit)) | (tmp1 & ~(7 << (4*unit))));
163 pci_write_config_byte(dev, (0x44|hwif->channel), tmp2);
164 local_irq_restore(flags);
165 return(ide_config_drive_speed(drive, speed));
168 static int aec62xx_tune_chipset (ide_drive_t *drive, u8 speed)
170 switch (HWIF(drive)->pci_dev->device) {
171 case PCI_DEVICE_ID_ARTOP_ATP865:
172 case PCI_DEVICE_ID_ARTOP_ATP865R:
173 case PCI_DEVICE_ID_ARTOP_ATP860:
174 case PCI_DEVICE_ID_ARTOP_ATP860R:
175 return ((int) aec6260_tune_chipset(drive, speed));
176 case PCI_DEVICE_ID_ARTOP_ATP850UF:
177 return ((int) aec6210_tune_chipset(drive, speed));
183 static int config_chipset_for_dma (ide_drive_t *drive)
185 u8 speed = ide_dma_speed(drive, aec62xx_ratemask(drive));
190 (void) aec62xx_tune_chipset(drive, speed);
191 return ide_dma_enable(drive);
194 static void aec62xx_tune_drive (ide_drive_t *drive, u8 pio)
197 u8 new_pio = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, 5, NULL);
200 case 5: speed = new_pio; break;
201 case 4: speed = XFER_PIO_4; break;
202 case 3: speed = XFER_PIO_3; break;
203 case 2: speed = XFER_PIO_2; break;
204 case 1: speed = XFER_PIO_1; break;
205 default: speed = XFER_PIO_0; break;
207 (void) aec62xx_tune_chipset(drive, speed);
210 static int aec62xx_config_drive_xfer_rate (ide_drive_t *drive)
212 ide_hwif_t *hwif = HWIF(drive);
214 if (ide_use_dma(drive) && config_chipset_for_dma(drive))
215 return hwif->ide_dma_on(drive);
217 if (ide_use_fast_pio(drive))
218 aec62xx_tune_drive(drive, 5);
220 return hwif->ide_dma_off_quietly(drive);
223 static int aec62xx_irq_timeout (ide_drive_t *drive)
225 ide_hwif_t *hwif = HWIF(drive);
226 struct pci_dev *dev = hwif->pci_dev;
228 switch(dev->device) {
229 case PCI_DEVICE_ID_ARTOP_ATP860:
230 case PCI_DEVICE_ID_ARTOP_ATP860R:
231 case PCI_DEVICE_ID_ARTOP_ATP865:
232 case PCI_DEVICE_ID_ARTOP_ATP865R:
233 printk(" AEC62XX time out ");
240 static unsigned int __devinit init_chipset_aec62xx(struct pci_dev *dev, const char *name)
242 int bus_speed = system_bus_clock();
244 if (dev->resource[PCI_ROM_RESOURCE].start) {
245 pci_write_config_dword(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
246 printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name,
247 (unsigned long)dev->resource[PCI_ROM_RESOURCE].start);
251 pci_set_drvdata(dev, (void *) aec6xxx_33_base);
253 pci_set_drvdata(dev, (void *) aec6xxx_34_base);
255 /* These are necessary to get AEC6280 Macintosh cards to work */
256 if ((dev->device == PCI_DEVICE_ID_ARTOP_ATP865) ||
257 (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)) {
258 u8 reg49h = 0, reg4ah = 0;
259 /* Clear reset and test bits. */
260 pci_read_config_byte(dev, 0x49, ®49h);
261 pci_write_config_byte(dev, 0x49, reg49h & ~0x30);
262 /* Enable chip interrupt output. */
263 pci_read_config_byte(dev, 0x4a, ®4ah);
264 pci_write_config_byte(dev, 0x4a, reg4ah & ~0x01);
265 /* Enable burst mode. */
266 pci_read_config_byte(dev, 0x4a, ®4ah);
267 pci_write_config_byte(dev, 0x4a, reg4ah | 0x80);
273 static void __devinit init_hwif_aec62xx(ide_hwif_t *hwif)
276 hwif->tuneproc = &aec62xx_tune_drive;
277 hwif->speedproc = &aec62xx_tune_chipset;
279 if (hwif->pci_dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF)
280 hwif->serialized = hwif->channel;
283 hwif->mate->serialized = hwif->serialized;
285 if (!hwif->dma_base) {
286 hwif->drives[0].autotune = 1;
287 hwif->drives[1].autotune = 1;
291 hwif->ultra_mask = 0x7f;
292 hwif->mwdma_mask = 0x07;
293 hwif->swdma_mask = 0x07;
295 hwif->ide_dma_check = &aec62xx_config_drive_xfer_rate;
296 hwif->ide_dma_lostirq = &aec62xx_irq_timeout;
297 hwif->ide_dma_timeout = &aec62xx_irq_timeout;
300 hwif->drives[0].autodma = hwif->autodma;
301 hwif->drives[1].autodma = hwif->autodma;
304 static void __devinit init_dma_aec62xx(ide_hwif_t *hwif, unsigned long dmabase)
306 struct pci_dev *dev = hwif->pci_dev;
308 if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) {
312 spin_lock_irqsave(&ide_lock, flags);
313 pci_read_config_byte(dev, 0x54, ®54h);
314 pci_write_config_byte(dev, 0x54, reg54h & ~(hwif->channel ? 0xF0 : 0x0F));
315 spin_unlock_irqrestore(&ide_lock, flags);
318 pci_read_config_byte(hwif->pci_dev, 0x49, &ata66);
319 if (!(hwif->udma_four))
320 hwif->udma_four = (ata66&(hwif->channel?0x02:0x01))?0:1;
323 ide_setup_dma(hwif, dmabase, 8);
326 static int __devinit init_setup_aec62xx(struct pci_dev *dev, ide_pci_device_t *d)
328 return ide_setup_pci_device(dev, d);
331 static int __devinit init_setup_aec6x80(struct pci_dev *dev, ide_pci_device_t *d)
333 unsigned long bar4reg = pci_resource_start(dev, 4);
335 if (inb(bar4reg+2) & 0x10) {
336 strcpy(d->name, "AEC6880");
337 if (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)
338 strcpy(d->name, "AEC6880R");
340 strcpy(d->name, "AEC6280");
341 if (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)
342 strcpy(d->name, "AEC6280R");
345 return ide_setup_pci_device(dev, d);
348 static ide_pci_device_t aec62xx_chipsets[] __devinitdata = {
351 .init_setup = init_setup_aec62xx,
352 .init_chipset = init_chipset_aec62xx,
353 .init_hwif = init_hwif_aec62xx,
354 .init_dma = init_dma_aec62xx,
357 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
358 .bootable = OFF_BOARD,
361 .init_setup = init_setup_aec62xx,
362 .init_chipset = init_chipset_aec62xx,
363 .init_hwif = init_hwif_aec62xx,
364 .init_dma = init_dma_aec62xx,
366 .autodma = NOAUTODMA,
367 .bootable = OFF_BOARD,
370 .init_setup = init_setup_aec62xx,
371 .init_chipset = init_chipset_aec62xx,
372 .init_hwif = init_hwif_aec62xx,
373 .init_dma = init_dma_aec62xx,
376 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
377 .bootable = NEVER_BOARD,
380 .init_setup = init_setup_aec6x80,
381 .init_chipset = init_chipset_aec62xx,
382 .init_hwif = init_hwif_aec62xx,
383 .init_dma = init_dma_aec62xx,
386 .bootable = OFF_BOARD,
389 .init_setup = init_setup_aec6x80,
390 .init_chipset = init_chipset_aec62xx,
391 .init_hwif = init_hwif_aec62xx,
392 .init_dma = init_dma_aec62xx,
395 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
396 .bootable = OFF_BOARD,
401 * aec62xx_init_one - called when a AEC is found
402 * @dev: the aec62xx device
403 * @id: the matching pci id
405 * Called when the PCI registration layer (or the IDE initialization)
406 * finds a device matching our IDE device tables.
409 static int __devinit aec62xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
411 ide_pci_device_t *d = &aec62xx_chipsets[id->driver_data];
413 return d->init_setup(dev, d);
416 static struct pci_device_id aec62xx_pci_tbl[] = {
417 { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
418 { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
419 { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860R, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
420 { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP865, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
421 { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP865R, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
424 MODULE_DEVICE_TABLE(pci, aec62xx_pci_tbl);
426 static struct pci_driver driver = {
427 .name = "AEC62xx_IDE",
428 .id_table = aec62xx_pci_tbl,
429 .probe = aec62xx_init_one,
432 static int __init aec62xx_ide_init(void)
434 return ide_pci_register_driver(&driver);
437 module_init(aec62xx_ide_init);
439 MODULE_AUTHOR("Andre Hedrick");
440 MODULE_DESCRIPTION("PCI driver module for ARTOP AEC62xx IDE");
441 MODULE_LICENSE("GPL");