drivers/ide/arm/icside.c

   1 /*
   2  * Copyright (c) 1996-2004 Russell King.
   3  *
   4  * Please note that this platform does not support 32-bit IDE IO.
   5  */
   6
   7 #include <linux/string.h>
   8 #include <linux/module.h>
   9 #include <linux/ioport.h>
  10 #include <linux/slab.h>
  11 #include <linux/blkdev.h>
  12 #include <linux/errno.h>
  13 #include <linux/hdreg.h>
  14 #include <linux/ide.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/device.h>
  17 #include <linux/init.h>
  18 #include <linux/scatterlist.h>
  19 #include <linux/io.h>
  20
  21 #include <asm/dma.h>
  22 #include <asm/ecard.h>
  23
  24 #define ICS_IDENT_OFFSET                0x2280
  25
  26 #define ICS_ARCIN_V5_INTRSTAT           0x0000
  27 #define ICS_ARCIN_V5_INTROFFSET         0x0004
  28 #define ICS_ARCIN_V5_IDEOFFSET          0x2800
  29 #define ICS_ARCIN_V5_IDEALTOFFSET       0x2b80
  30 #define ICS_ARCIN_V5_IDESTEPPING        6
  31
  32 #define ICS_ARCIN_V6_IDEOFFSET_1        0x2000
  33 #define ICS_ARCIN_V6_INTROFFSET_1       0x2200
  34 #define ICS_ARCIN_V6_INTRSTAT_1         0x2290
  35 #define ICS_ARCIN_V6_IDEALTOFFSET_1     0x2380
  36 #define ICS_ARCIN_V6_IDEOFFSET_2        0x3000
  37 #define ICS_ARCIN_V6_INTROFFSET_2       0x3200
  38 #define ICS_ARCIN_V6_INTRSTAT_2         0x3290
  39 #define ICS_ARCIN_V6_IDEALTOFFSET_2     0x3380
  40 #define ICS_ARCIN_V6_IDESTEPPING        6
  41
  42 struct cardinfo {
  43         unsigned int dataoffset;
  44         unsigned int ctrloffset;
  45         unsigned int stepping;
  46 };
  47
  48 static struct cardinfo icside_cardinfo_v5 = {
  49         .dataoffset     = ICS_ARCIN_V5_IDEOFFSET,
  50         .ctrloffset     = ICS_ARCIN_V5_IDEALTOFFSET,
  51         .stepping       = ICS_ARCIN_V5_IDESTEPPING,
  52 };
  53
  54 static struct cardinfo icside_cardinfo_v6_1 = {
  55         .dataoffset     = ICS_ARCIN_V6_IDEOFFSET_1,
  56         .ctrloffset     = ICS_ARCIN_V6_IDEALTOFFSET_1,
  57         .stepping       = ICS_ARCIN_V6_IDESTEPPING,
  58 };
  59
  60 static struct cardinfo icside_cardinfo_v6_2 = {
  61         .dataoffset     = ICS_ARCIN_V6_IDEOFFSET_2,
  62         .ctrloffset     = ICS_ARCIN_V6_IDEALTOFFSET_2,
  63         .stepping       = ICS_ARCIN_V6_IDESTEPPING,
  64 };
  65
  66 struct icside_state {
  67         unsigned int channel;
  68         unsigned int enabled;
  69         void __iomem *irq_port;
  70         void __iomem *ioc_base;
  71         unsigned int type;
  72         ide_hwif_t *hwif[2];
  73 };
  74
  75 #define ICS_TYPE_A3IN   0
  76 #define ICS_TYPE_A3USER 1
  77 #define ICS_TYPE_V6     3
  78 #define ICS_TYPE_V5     15
  79 #define ICS_TYPE_NOTYPE ((unsigned int)-1)
  80
  81 /* ---------------- Version 5 PCB Support Functions --------------------- */
  82 /* Prototype: icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
  83  * Purpose  : enable interrupts from card
  84  */
  85 static void icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
  86 {
  87         struct icside_state *state = ec->irq_data;
  88
  89         writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET);
  90 }
  91
  92 /* Prototype: icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
  93  * Purpose  : disable interrupts from card
  94  */
  95 static void icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
  96 {
  97         struct icside_state *state = ec->irq_data;
  98
  99         readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET);
 100 }
 101
 102 static const expansioncard_ops_t icside_ops_arcin_v5 = {
 103         .irqenable      = icside_irqenable_arcin_v5,
 104         .irqdisable     = icside_irqdisable_arcin_v5,
 105 };
 106
 107
 108 /* ---------------- Version 6 PCB Support Functions --------------------- */
 109 /* Prototype: icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
 110  * Purpose  : enable interrupts from card
 111  */
 112 static void icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
 113 {
 114         struct icside_state *state = ec->irq_data;
 115         void __iomem *base = state->irq_port;
 116
 117         state->enabled = 1;
 118
 119         switch (state->channel) {
 120         case 0:
 121                 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
 122                 readb(base + ICS_ARCIN_V6_INTROFFSET_2);
 123                 break;
 124         case 1:
 125                 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
 126                 readb(base + ICS_ARCIN_V6_INTROFFSET_1);
 127                 break;
 128         }
 129 }
 130
 131 /* Prototype: icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
 132  * Purpose  : disable interrupts from card
 133  */
 134 static void icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
 135 {
 136         struct icside_state *state = ec->irq_data;
 137
 138         state->enabled = 0;
 139
 140         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 141         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 142 }
 143
 144 /* Prototype: icside_irqprobe(struct expansion_card *ec)
 145  * Purpose  : detect an active interrupt from card
 146  */
 147 static int icside_irqpending_arcin_v6(struct expansion_card *ec)
 148 {
 149         struct icside_state *state = ec->irq_data;
 150
 151         return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 ||
 152                readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1;
 153 }
 154
 155 static const expansioncard_ops_t icside_ops_arcin_v6 = {
 156         .irqenable      = icside_irqenable_arcin_v6,
 157         .irqdisable     = icside_irqdisable_arcin_v6,
 158         .irqpending     = icside_irqpending_arcin_v6,
 159 };
 160
 161 /*
 162  * Handle routing of interrupts.  This is called before
 163  * we write the command to the drive.
 164  */
 165 static void icside_maskproc(ide_drive_t *drive, int mask)
 166 {
 167         ide_hwif_t *hwif = HWIF(drive);
 168         struct icside_state *state = hwif->hwif_data;
 169         unsigned long flags;
 170
 171         local_irq_save(flags);
 172
 173         state->channel = hwif->channel;
 174
 175         if (state->enabled && !mask) {
 176                 switch (hwif->channel) {
 177                 case 0:
 178                         writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 179                         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 180                         break;
 181                 case 1:
 182                         writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 183                         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 184                         break;
 185                 }
 186         } else {
 187                 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 188                 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 189         }
 190
 191         local_irq_restore(flags);
 192 }
 193
 194 #ifdef CONFIG_BLK_DEV_IDEDMA_ICS
 195 /*
 196  * SG-DMA support.
 197  *
 198  * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
 199  * There is only one DMA controller per card, which means that only
 200  * one drive can be accessed at one time.  NOTE! We do not enforce that
 201  * here, but we rely on the main IDE driver spotting that both
 202  * interfaces use the same IRQ, which should guarantee this.
 203  */
 204
 205 /*
 206  * Configure the IOMD to give the appropriate timings for the transfer
 207  * mode being requested.  We take the advice of the ATA standards, and
 208  * calculate the cycle time based on the transfer mode, and the EIDE
 209  * MW DMA specs that the drive provides in the IDENTIFY command.
 210  *
 211  * We have the following IOMD DMA modes to choose from:
 212  *
 213  *      Type    Active          Recovery        Cycle
 214  *      A       250 (250)       312 (550)       562 (800)
 215  *      B       187             250             437
 216  *      C       125 (125)       125 (375)       250 (500)
 217  *      D       62              125             187
 218  *
 219  * (figures in brackets are actual measured timings)
 220  *
 221  * However, we also need to take care of the read/write active and
 222  * recovery timings:
 223  *
 224  *                      Read    Write
 225  *      Mode    Active  -- Recovery --  Cycle   IOMD type
 226  *      MW0     215     50      215     480     A
 227  *      MW1     80      50      50      150     C
 228  *      MW2     70      25      25      120     C
 229  */
 230 static void icside_set_dma_mode(ide_drive_t *drive, const u8 xfer_mode)
 231 {
 232         int cycle_time, use_dma_info = 0;
 233
 234         switch (xfer_mode) {
 235         case XFER_MW_DMA_2:
 236                 cycle_time = 250;
 237                 use_dma_info = 1;
 238                 break;
 239
 240         case XFER_MW_DMA_1:
 241                 cycle_time = 250;
 242                 use_dma_info = 1;
 243                 break;
 244
 245         case XFER_MW_DMA_0:
 246                 cycle_time = 480;
 247                 break;
 248
 249         case XFER_SW_DMA_2:
 250         case XFER_SW_DMA_1:
 251         case XFER_SW_DMA_0:
 252                 cycle_time = 480;
 253                 break;
 254         }
 255
 256         /*
 257          * If we're going to be doing MW_DMA_1 or MW_DMA_2, we should
 258          * take care to note the values in the ID...
 259          */
 260         if (use_dma_info && drive->id->eide_dma_time > cycle_time)
 261                 cycle_time = drive->id->eide_dma_time;
 262
 263         drive->drive_data = cycle_time;
 264
 265         printk("%s: %s selected (peak %dMB/s)\n", drive->name,
 266                 ide_xfer_verbose(xfer_mode), 2000 / drive->drive_data);
 267 }
 268
 269 static void icside_dma_host_set(ide_drive_t *drive, int on)
 270 {
 271 }
 272
 273 static int icside_dma_end(ide_drive_t *drive)
 274 {
 275         ide_hwif_t *hwif = HWIF(drive);
 276         struct expansion_card *ec = ECARD_DEV(hwif->dev);
 277
 278         drive->waiting_for_dma = 0;
 279
 280         disable_dma(ec->dma);
 281
 282         /* Teardown mappings after DMA has completed. */
 283         ide_destroy_dmatable(drive);
 284
 285         return get_dma_residue(ec->dma) != 0;
 286 }
 287
 288 static void icside_dma_start(ide_drive_t *drive)
 289 {
 290         ide_hwif_t *hwif = HWIF(drive);
 291         struct expansion_card *ec = ECARD_DEV(hwif->dev);
 292
 293         /* We can not enable DMA on both channels simultaneously. */
 294         BUG_ON(dma_channel_active(ec->dma));
 295         enable_dma(ec->dma);
 296 }
 297
 298 static int icside_dma_setup(ide_drive_t *drive)
 299 {
 300         ide_hwif_t *hwif = HWIF(drive);
 301         struct expansion_card *ec = ECARD_DEV(hwif->dev);
 302         struct request *rq = hwif->hwgroup->rq;
 303         unsigned int dma_mode;
 304
 305         if (rq_data_dir(rq))
 306                 dma_mode = DMA_MODE_WRITE;
 307         else
 308                 dma_mode = DMA_MODE_READ;
 309
 310         /*
 311          * We can not enable DMA on both channels.
 312          */
 313         BUG_ON(dma_channel_active(ec->dma));
 314
 315         hwif->sg_nents = ide_build_sglist(drive, rq);
 316
 317         /*
 318          * Ensure that we have the right interrupt routed.
 319          */
 320         icside_maskproc(drive, 0);
 321
 322         /*
 323          * Route the DMA signals to the correct interface.
 324          */
 325         writeb(hwif->select_data, hwif->config_data);
 326
 327         /*
 328          * Select the correct timing for this drive.
 329          */
 330         set_dma_speed(ec->dma, drive->drive_data);
 331
 332         /*
 333          * Tell the DMA engine about the SG table and
 334          * data direction.
 335          */
 336         set_dma_sg(ec->dma, hwif->sg_table, hwif->sg_nents);
 337         set_dma_mode(ec->dma, dma_mode);
 338
 339         drive->waiting_for_dma = 1;
 340
 341         return 0;
 342 }
 343
 344 static void icside_dma_exec_cmd(ide_drive_t *drive, u8 cmd)
 345 {
 346         /* issue cmd to drive */
 347         ide_execute_command(drive, cmd, ide_dma_intr, 2 * WAIT_CMD, NULL);
 348 }
 349
 350 static int icside_dma_test_irq(ide_drive_t *drive)
 351 {
 352         ide_hwif_t *hwif = HWIF(drive);
 353         struct icside_state *state = hwif->hwif_data;
 354
 355         return readb(state->irq_port +
 356                      (hwif->channel ?
 357                         ICS_ARCIN_V6_INTRSTAT_2 :
 358                         ICS_ARCIN_V6_INTRSTAT_1)) & 1;
 359 }
 360
 361 static void icside_dma_timeout(ide_drive_t *drive)
 362 {
 363         printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name);
 364
 365         if (icside_dma_test_irq(drive))
 366                 return;
 367
 368         ide_dump_status(drive, "DMA timeout", HWIF(drive)->INB(IDE_STATUS_REG));
 369
 370         icside_dma_end(drive);
 371 }
 372
 373 static void icside_dma_lost_irq(ide_drive_t *drive)
 374 {
 375         printk(KERN_ERR "%s: IRQ lost\n", drive->name);
 376 }
 377
 378 static void icside_dma_init(ide_hwif_t *hwif)
 379 {
 380         hwif->mwdma_mask        = 7; /* MW0..2 */
 381         hwif->swdma_mask        = 7; /* SW0..2 */
 382
 383         hwif->dmatable_cpu      = NULL;
 384         hwif->dmatable_dma      = 0;
 385         hwif->set_dma_mode      = icside_set_dma_mode;
 386
 387         hwif->dma_host_set      = icside_dma_host_set;
 388         hwif->dma_setup         = icside_dma_setup;
 389         hwif->dma_exec_cmd      = icside_dma_exec_cmd;
 390         hwif->dma_start         = icside_dma_start;
 391         hwif->ide_dma_end       = icside_dma_end;
 392         hwif->ide_dma_test_irq  = icside_dma_test_irq;
 393         hwif->dma_timeout       = icside_dma_timeout;
 394         hwif->dma_lost_irq      = icside_dma_lost_irq;
 395 }
 396 #else
 397 #define icside_dma_init(hwif)   (0)
 398 #endif
 399
 400 static ide_hwif_t *
 401 icside_setup(void __iomem *base, struct cardinfo *info, struct expansion_card *ec)
 402 {
 403         unsigned long port = (unsigned long)base + info->dataoffset;
 404         ide_hwif_t *hwif;
 405
 406         hwif = ide_find_port(port);
 407         if (hwif) {
 408                 int i;
 409
 410                 /*
 411                  * Ensure we're using MMIO
 412                  */
 413                 default_hwif_mmiops(hwif);
 414                 hwif->mmio = 1;
 415
 416                 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
 417                         hwif->io_ports[i] = port;
 418                         port += 1 << info->stepping;
 419                 }
 420                 hwif->io_ports[IDE_CONTROL_OFFSET] = (unsigned long)base + info->ctrloffset;
 421                 hwif->irq     = ec->irq;
 422                 hwif->noprobe = 0;
 423                 hwif->chipset = ide_acorn;
 424                 hwif->gendev.parent = &ec->dev;
 425                 hwif->dev = &ec->dev;
 426         }
 427
 428         return hwif;
 429 }
 430
 431 static int __init
 432 icside_register_v5(struct icside_state *state, struct expansion_card *ec)
 433 {
 434         ide_hwif_t *hwif;
 435         void __iomem *base;
 436         u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
 437
 438         base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0);
 439         if (!base)
 440                 return -ENOMEM;
 441
 442         state->irq_port = base;
 443
 444         ec->irqaddr  = base + ICS_ARCIN_V5_INTRSTAT;
 445         ec->irqmask  = 1;
 446
 447         ecard_setirq(ec, &icside_ops_arcin_v5, state);
 448
 449         /*
 450          * Be on the safe side - disable interrupts
 451          */
 452         icside_irqdisable_arcin_v5(ec, 0);
 453
 454         hwif = icside_setup(base, &icside_cardinfo_v5, ec);
 455         if (!hwif)
 456                 return -ENODEV;
 457
 458         state->hwif[0] = hwif;
 459
 460         idx[0] = hwif->index;
 461
 462         ide_device_add(idx);
 463
 464         return 0;
 465 }
 466
 467 static int __init
 468 icside_register_v6(struct icside_state *state, struct expansion_card *ec)
 469 {
 470         ide_hwif_t *hwif, *mate;
 471         void __iomem *ioc_base, *easi_base;
 472         unsigned int sel = 0;
 473         int ret;
 474         u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
 475
 476         ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
 477         if (!ioc_base) {
 478                 ret = -ENOMEM;
 479                 goto out;
 480         }
 481
 482         easi_base = ioc_base;
 483
 484         if (ecard_resource_flags(ec, ECARD_RES_EASI)) {
 485                 easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0);
 486                 if (!easi_base) {
 487                         ret = -ENOMEM;
 488                         goto out;
 489                 }
 490
 491                 /*
 492                  * Enable access to the EASI region.
 493                  */
 494                 sel = 1 << 5;
 495         }
 496
 497         writeb(sel, ioc_base);
 498
 499         ecard_setirq(ec, &icside_ops_arcin_v6, state);
 500
 501         state->irq_port   = easi_base;
 502         state->ioc_base   = ioc_base;
 503
 504         /*
 505          * Be on the safe side - disable interrupts
 506          */
 507         icside_irqdisable_arcin_v6(ec, 0);
 508
 509         /*
 510          * Find and register the interfaces.
 511          */
 512         hwif = icside_setup(easi_base, &icside_cardinfo_v6_1, ec);
 513         mate = icside_setup(easi_base, &icside_cardinfo_v6_2, ec);
 514
 515         if (!hwif || !mate) {
 516                 ret = -ENODEV;
 517                 goto out;
 518         }
 519
 520         state->hwif[0]    = hwif;
 521         state->hwif[1]    = mate;
 522
 523         hwif->maskproc    = icside_maskproc;
 524         hwif->channel     = 0;
 525         hwif->hwif_data   = state;
 526         hwif->mate        = mate;
 527         hwif->serialized  = 1;
 528         hwif->config_data = (unsigned long)ioc_base;
 529         hwif->select_data = sel;
 530
 531         mate->maskproc    = icside_maskproc;
 532         mate->channel     = 1;
 533         mate->hwif_data   = state;
 534         mate->mate        = hwif;
 535         mate->serialized  = 1;
 536         mate->config_data = (unsigned long)ioc_base;
 537         mate->select_data = sel | 1;
 538
 539         if (ec->dma != NO_DMA && !request_dma(ec->dma, hwif->name)) {
 540                 icside_dma_init(hwif);
 541                 icside_dma_init(mate);
 542         }
 543
 544         idx[0] = hwif->index;
 545         idx[1] = mate->index;
 546
 547         ide_device_add(idx);
 548
 549         return 0;
 550
 551  out:
 552         return ret;
 553 }
 554
 555 static int __devinit
 556 icside_probe(struct expansion_card *ec, const struct ecard_id *id)
 557 {
 558         struct icside_state *state;
 559         void __iomem *idmem;
 560         int ret;
 561
 562         ret = ecard_request_resources(ec);
 563         if (ret)
 564                 goto out;
 565
 566         state = kzalloc(sizeof(struct icside_state), GFP_KERNEL);
 567         if (!state) {
 568                 ret = -ENOMEM;
 569                 goto release;
 570         }
 571
 572         state->type     = ICS_TYPE_NOTYPE;
 573
 574         idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
 575         if (idmem) {
 576                 unsigned int type;
 577
 578                 type = readb(idmem + ICS_IDENT_OFFSET) & 1;
 579                 type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1;
 580                 type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2;
 581                 type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3;
 582                 ecardm_iounmap(ec, idmem);
 583
 584                 state->type = type;
 585         }
 586
 587         switch (state->type) {
 588         case ICS_TYPE_A3IN:
 589                 dev_warn(&ec->dev, "A3IN unsupported\n");
 590                 ret = -ENODEV;
 591                 break;
 592
 593         case ICS_TYPE_A3USER:
 594                 dev_warn(&ec->dev, "A3USER unsupported\n");
 595                 ret = -ENODEV;
 596                 break;
 597
 598         case ICS_TYPE_V5:
 599                 ret = icside_register_v5(state, ec);
 600                 break;
 601
 602         case ICS_TYPE_V6:
 603                 ret = icside_register_v6(state, ec);
 604                 break;
 605
 606         default:
 607                 dev_warn(&ec->dev, "unknown interface type\n");
 608                 ret = -ENODEV;
 609                 break;
 610         }
 611
 612         if (ret == 0) {
 613                 ecard_set_drvdata(ec, state);
 614                 goto out;
 615         }
 616
 617         kfree(state);
 618  release:
 619         ecard_release_resources(ec);
 620  out:
 621         return ret;
 622 }
 623
 624 static void __devexit icside_remove(struct expansion_card *ec)
 625 {
 626         struct icside_state *state = ecard_get_drvdata(ec);
 627
 628         switch (state->type) {
 629         case ICS_TYPE_V5:
 630                 /* FIXME: tell IDE to stop using the interface */
 631
 632                 /* Disable interrupts */
 633                 icside_irqdisable_arcin_v5(ec, 0);
 634                 break;
 635
 636         case ICS_TYPE_V6:
 637                 /* FIXME: tell IDE to stop using the interface */
 638                 if (ec->dma != NO_DMA)
 639                         free_dma(ec->dma);
 640
 641                 /* Disable interrupts */
 642                 icside_irqdisable_arcin_v6(ec, 0);
 643
 644                 /* Reset the ROM pointer/EASI selection */
 645                 writeb(0, state->ioc_base);
 646                 break;
 647         }
 648
 649         ecard_set_drvdata(ec, NULL);
 650
 651         kfree(state);
 652         ecard_release_resources(ec);
 653 }
 654
 655 static void icside_shutdown(struct expansion_card *ec)
 656 {
 657         struct icside_state *state = ecard_get_drvdata(ec);
 658         unsigned long flags;
 659
 660         /*
 661          * Disable interrupts from this card.  We need to do
 662          * this before disabling EASI since we may be accessing
 663          * this register via that region.
 664          */
 665         local_irq_save(flags);
 666         ec->ops->irqdisable(ec, 0);
 667         local_irq_restore(flags);
 668
 669         /*
 670          * Reset the ROM pointer so that we can read the ROM
 671          * after a soft reboot.  This also disables access to
 672          * the IDE taskfile via the EASI region.
 673          */
 674         if (state->ioc_base)
 675                 writeb(0, state->ioc_base);
 676 }
 677
 678 static const struct ecard_id icside_ids[] = {
 679         { MANU_ICS,  PROD_ICS_IDE  },
 680         { MANU_ICS2, PROD_ICS2_IDE },
 681         { 0xffff, 0xffff }
 682 };
 683
 684 static struct ecard_driver icside_driver = {
 685         .probe          = icside_probe,
 686         .remove         = __devexit_p(icside_remove),
 687         .shutdown       = icside_shutdown,
 688         .id_table       = icside_ids,
 689         .drv = {
 690                 .name   = "icside",
 691         },
 692 };
 693
 694 static int __init icside_init(void)
 695 {
 696         return ecard_register_driver(&icside_driver);
 697 }
 698
 699 MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
 700 MODULE_LICENSE("GPL");
 701 MODULE_DESCRIPTION("ICS IDE driver");
 702
 703 module_init(icside_init);