drivers/ide/arm/icside.c

   1 /*
   2  * linux/drivers/ide/arm/icside.c
   3  *
   4  * Copyright (c) 1996-2004 Russell King.
   5  *
   6  * Please note that this platform does not support 32-bit IDE IO.
   7  */
   8
   9 #include <linux/string.h>
  10 #include <linux/module.h>
  11 #include <linux/ioport.h>
  12 #include <linux/slab.h>
  13 #include <linux/blkdev.h>
  14 #include <linux/errno.h>
  15 #include <linux/hdreg.h>
  16 #include <linux/ide.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/device.h>
  19 #include <linux/init.h>
  20 #include <linux/scatterlist.h>
  21 #include <linux/io.h>
  22
  23 #include <asm/dma.h>
  24 #include <asm/ecard.h>
  25
  26 #define ICS_IDENT_OFFSET                0x2280
  27
  28 #define ICS_ARCIN_V5_INTRSTAT           0x0000
  29 #define ICS_ARCIN_V5_INTROFFSET         0x0004
  30 #define ICS_ARCIN_V5_IDEOFFSET          0x2800
  31 #define ICS_ARCIN_V5_IDEALTOFFSET       0x2b80
  32 #define ICS_ARCIN_V5_IDESTEPPING        6
  33
  34 #define ICS_ARCIN_V6_IDEOFFSET_1        0x2000
  35 #define ICS_ARCIN_V6_INTROFFSET_1       0x2200
  36 #define ICS_ARCIN_V6_INTRSTAT_1         0x2290
  37 #define ICS_ARCIN_V6_IDEALTOFFSET_1     0x2380
  38 #define ICS_ARCIN_V6_IDEOFFSET_2        0x3000
  39 #define ICS_ARCIN_V6_INTROFFSET_2       0x3200
  40 #define ICS_ARCIN_V6_INTRSTAT_2         0x3290
  41 #define ICS_ARCIN_V6_IDEALTOFFSET_2     0x3380
  42 #define ICS_ARCIN_V6_IDESTEPPING        6
  43
  44 struct cardinfo {
  45         unsigned int dataoffset;
  46         unsigned int ctrloffset;
  47         unsigned int stepping;
  48 };
  49
  50 static struct cardinfo icside_cardinfo_v5 = {
  51         .dataoffset     = ICS_ARCIN_V5_IDEOFFSET,
  52         .ctrloffset     = ICS_ARCIN_V5_IDEALTOFFSET,
  53         .stepping       = ICS_ARCIN_V5_IDESTEPPING,
  54 };
  55
  56 static struct cardinfo icside_cardinfo_v6_1 = {
  57         .dataoffset     = ICS_ARCIN_V6_IDEOFFSET_1,
  58         .ctrloffset     = ICS_ARCIN_V6_IDEALTOFFSET_1,
  59         .stepping       = ICS_ARCIN_V6_IDESTEPPING,
  60 };
  61
  62 static struct cardinfo icside_cardinfo_v6_2 = {
  63         .dataoffset     = ICS_ARCIN_V6_IDEOFFSET_2,
  64         .ctrloffset     = ICS_ARCIN_V6_IDEALTOFFSET_2,
  65         .stepping       = ICS_ARCIN_V6_IDESTEPPING,
  66 };
  67
  68 struct icside_state {
  69         unsigned int channel;
  70         unsigned int enabled;
  71         void __iomem *irq_port;
  72         void __iomem *ioc_base;
  73         unsigned int type;
  74         /* parent device... until the IDE core gets one of its own */
  75         struct device *dev;
  76         ide_hwif_t *hwif[2];
  77 };
  78
  79 #define ICS_TYPE_A3IN   0
  80 #define ICS_TYPE_A3USER 1
  81 #define ICS_TYPE_V6     3
  82 #define ICS_TYPE_V5     15
  83 #define ICS_TYPE_NOTYPE ((unsigned int)-1)
  84
  85 /* ---------------- Version 5 PCB Support Functions --------------------- */
  86 /* Prototype: icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
  87  * Purpose  : enable interrupts from card
  88  */
  89 static void icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
  90 {
  91         struct icside_state *state = ec->irq_data;
  92
  93         writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET);
  94 }
  95
  96 /* Prototype: icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
  97  * Purpose  : disable interrupts from card
  98  */
  99 static void icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
 100 {
 101         struct icside_state *state = ec->irq_data;
 102
 103         readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET);
 104 }
 105
 106 static const expansioncard_ops_t icside_ops_arcin_v5 = {
 107         .irqenable      = icside_irqenable_arcin_v5,
 108         .irqdisable     = icside_irqdisable_arcin_v5,
 109 };
 110
 111
 112 /* ---------------- Version 6 PCB Support Functions --------------------- */
 113 /* Prototype: icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
 114  * Purpose  : enable interrupts from card
 115  */
 116 static void icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
 117 {
 118         struct icside_state *state = ec->irq_data;
 119         void __iomem *base = state->irq_port;
 120
 121         state->enabled = 1;
 122
 123         switch (state->channel) {
 124         case 0:
 125                 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
 126                 readb(base + ICS_ARCIN_V6_INTROFFSET_2);
 127                 break;
 128         case 1:
 129                 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
 130                 readb(base + ICS_ARCIN_V6_INTROFFSET_1);
 131                 break;
 132         }
 133 }
 134
 135 /* Prototype: icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
 136  * Purpose  : disable interrupts from card
 137  */
 138 static void icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
 139 {
 140         struct icside_state *state = ec->irq_data;
 141
 142         state->enabled = 0;
 143
 144         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 145         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 146 }
 147
 148 /* Prototype: icside_irqprobe(struct expansion_card *ec)
 149  * Purpose  : detect an active interrupt from card
 150  */
 151 static int icside_irqpending_arcin_v6(struct expansion_card *ec)
 152 {
 153         struct icside_state *state = ec->irq_data;
 154
 155         return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 ||
 156                readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1;
 157 }
 158
 159 static const expansioncard_ops_t icside_ops_arcin_v6 = {
 160         .irqenable      = icside_irqenable_arcin_v6,
 161         .irqdisable     = icside_irqdisable_arcin_v6,
 162         .irqpending     = icside_irqpending_arcin_v6,
 163 };
 164
 165 /*
 166  * Handle routing of interrupts.  This is called before
 167  * we write the command to the drive.
 168  */
 169 static void icside_maskproc(ide_drive_t *drive, int mask)
 170 {
 171         ide_hwif_t *hwif = HWIF(drive);
 172         struct icside_state *state = hwif->hwif_data;
 173         unsigned long flags;
 174
 175         local_irq_save(flags);
 176
 177         state->channel = hwif->channel;
 178
 179         if (state->enabled && !mask) {
 180                 switch (hwif->channel) {
 181                 case 0:
 182                         writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 183                         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 184                         break;
 185                 case 1:
 186                         writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 187                         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 188                         break;
 189                 }
 190         } else {
 191                 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 192                 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 193         }
 194
 195         local_irq_restore(flags);
 196 }
 197
 198 #ifdef CONFIG_BLK_DEV_IDEDMA_ICS
 199 /*
 200  * SG-DMA support.
 201  *
 202  * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
 203  * There is only one DMA controller per card, which means that only
 204  * one drive can be accessed at one time.  NOTE! We do not enforce that
 205  * here, but we rely on the main IDE driver spotting that both
 206  * interfaces use the same IRQ, which should guarantee this.
 207  */
 208
 209 static void icside_build_sglist(ide_drive_t *drive, struct request *rq)
 210 {
 211         ide_hwif_t *hwif = drive->hwif;
 212         struct icside_state *state = hwif->hwif_data;
 213         struct scatterlist *sg = hwif->sg_table;
 214
 215         ide_map_sg(drive, rq);
 216
 217         if (rq_data_dir(rq) == READ)
 218                 hwif->sg_dma_direction = DMA_FROM_DEVICE;
 219         else
 220                 hwif->sg_dma_direction = DMA_TO_DEVICE;
 221
 222         hwif->sg_nents = dma_map_sg(state->dev, sg, hwif->sg_nents,
 223                                     hwif->sg_dma_direction);
 224 }
 225
 226 /*
 227  * Configure the IOMD to give the appropriate timings for the transfer
 228  * mode being requested.  We take the advice of the ATA standards, and
 229  * calculate the cycle time based on the transfer mode, and the EIDE
 230  * MW DMA specs that the drive provides in the IDENTIFY command.
 231  *
 232  * We have the following IOMD DMA modes to choose from:
 233  *
 234  *      Type    Active          Recovery        Cycle
 235  *      A       250 (250)       312 (550)       562 (800)
 236  *      B       187             250             437
 237  *      C       125 (125)       125 (375)       250 (500)
 238  *      D       62              125             187
 239  *
 240  * (figures in brackets are actual measured timings)
 241  *
 242  * However, we also need to take care of the read/write active and
 243  * recovery timings:
 244  *
 245  *                      Read    Write
 246  *      Mode    Active  -- Recovery --  Cycle   IOMD type
 247  *      MW0     215     50      215     480     A
 248  *      MW1     80      50      50      150     C
 249  *      MW2     70      25      25      120     C
 250  */
 251 static void icside_set_dma_mode(ide_drive_t *drive, const u8 xfer_mode)
 252 {
 253         int cycle_time, use_dma_info = 0;
 254
 255         switch (xfer_mode) {
 256         case XFER_MW_DMA_2:
 257                 cycle_time = 250;
 258                 use_dma_info = 1;
 259                 break;
 260
 261         case XFER_MW_DMA_1:
 262                 cycle_time = 250;
 263                 use_dma_info = 1;
 264                 break;
 265
 266         case XFER_MW_DMA_0:
 267                 cycle_time = 480;
 268                 break;
 269
 270         case XFER_SW_DMA_2:
 271         case XFER_SW_DMA_1:
 272         case XFER_SW_DMA_0:
 273                 cycle_time = 480;
 274                 break;
 275         default:
 276                 return;
 277         }
 278
 279         /*
 280          * If we're going to be doing MW_DMA_1 or MW_DMA_2, we should
 281          * take care to note the values in the ID...
 282          */
 283         if (use_dma_info && drive->id->eide_dma_time > cycle_time)
 284                 cycle_time = drive->id->eide_dma_time;
 285
 286         drive->drive_data = cycle_time;
 287
 288         printk("%s: %s selected (peak %dMB/s)\n", drive->name,
 289                 ide_xfer_verbose(xfer_mode), 2000 / drive->drive_data);
 290 }
 291
 292 static void icside_dma_host_off(ide_drive_t *drive)
 293 {
 294 }
 295
 296 static void icside_dma_off_quietly(ide_drive_t *drive)
 297 {
 298         drive->using_dma = 0;
 299 }
 300
 301 static void icside_dma_host_on(ide_drive_t *drive)
 302 {
 303 }
 304
 305 static int icside_dma_on(ide_drive_t *drive)
 306 {
 307         drive->using_dma = 1;
 308
 309         return 0;
 310 }
 311
 312 static int icside_dma_end(ide_drive_t *drive)
 313 {
 314         ide_hwif_t *hwif = HWIF(drive);
 315         struct icside_state *state = hwif->hwif_data;
 316
 317         drive->waiting_for_dma = 0;
 318
 319         disable_dma(hwif->hw.dma);
 320
 321         /* Teardown mappings after DMA has completed. */
 322         dma_unmap_sg(state->dev, hwif->sg_table, hwif->sg_nents,
 323                      hwif->sg_dma_direction);
 324
 325         return get_dma_residue(hwif->hw.dma) != 0;
 326 }
 327
 328 static void icside_dma_start(ide_drive_t *drive)
 329 {
 330         ide_hwif_t *hwif = HWIF(drive);
 331
 332         /* We can not enable DMA on both channels simultaneously. */
 333         BUG_ON(dma_channel_active(hwif->hw.dma));
 334         enable_dma(hwif->hw.dma);
 335 }
 336
 337 static int icside_dma_setup(ide_drive_t *drive)
 338 {
 339         ide_hwif_t *hwif = HWIF(drive);
 340         struct request *rq = hwif->hwgroup->rq;
 341         unsigned int dma_mode;
 342
 343         if (rq_data_dir(rq))
 344                 dma_mode = DMA_MODE_WRITE;
 345         else
 346                 dma_mode = DMA_MODE_READ;
 347
 348         /*
 349          * We can not enable DMA on both channels.
 350          */
 351         BUG_ON(dma_channel_active(hwif->hw.dma));
 352
 353         icside_build_sglist(drive, rq);
 354
 355         /*
 356          * Ensure that we have the right interrupt routed.
 357          */
 358         icside_maskproc(drive, 0);
 359
 360         /*
 361          * Route the DMA signals to the correct interface.
 362          */
 363         writeb(hwif->select_data, hwif->config_data);
 364
 365         /*
 366          * Select the correct timing for this drive.
 367          */
 368         set_dma_speed(hwif->hw.dma, drive->drive_data);
 369
 370         /*
 371          * Tell the DMA engine about the SG table and
 372          * data direction.
 373          */
 374         set_dma_sg(hwif->hw.dma, hwif->sg_table, hwif->sg_nents);
 375         set_dma_mode(hwif->hw.dma, dma_mode);
 376
 377         drive->waiting_for_dma = 1;
 378
 379         return 0;
 380 }
 381
 382 static void icside_dma_exec_cmd(ide_drive_t *drive, u8 cmd)
 383 {
 384         /* issue cmd to drive */
 385         ide_execute_command(drive, cmd, ide_dma_intr, 2 * WAIT_CMD, NULL);
 386 }
 387
 388 static int icside_dma_test_irq(ide_drive_t *drive)
 389 {
 390         ide_hwif_t *hwif = HWIF(drive);
 391         struct icside_state *state = hwif->hwif_data;
 392
 393         return readb(state->irq_port +
 394                      (hwif->channel ?
 395                         ICS_ARCIN_V6_INTRSTAT_2 :
 396                         ICS_ARCIN_V6_INTRSTAT_1)) & 1;
 397 }
 398
 399 static void icside_dma_timeout(ide_drive_t *drive)
 400 {
 401         printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name);
 402
 403         if (icside_dma_test_irq(drive))
 404                 return;
 405
 406         ide_dump_status(drive, "DMA timeout", HWIF(drive)->INB(IDE_STATUS_REG));
 407
 408         icside_dma_end(drive);
 409 }
 410
 411 static void icside_dma_lost_irq(ide_drive_t *drive)
 412 {
 413         printk(KERN_ERR "%s: IRQ lost\n", drive->name);
 414 }
 415
 416 static void icside_dma_init(ide_hwif_t *hwif)
 417 {
 418         hwif->mwdma_mask        = 7; /* MW0..2 */
 419         hwif->swdma_mask        = 7; /* SW0..2 */
 420
 421         hwif->dmatable_cpu      = NULL;
 422         hwif->dmatable_dma      = 0;
 423         hwif->set_dma_mode      = icside_set_dma_mode;
 424
 425         hwif->dma_host_off      = icside_dma_host_off;
 426         hwif->dma_off_quietly   = icside_dma_off_quietly;
 427         hwif->dma_host_on       = icside_dma_host_on;
 428         hwif->ide_dma_on        = icside_dma_on;
 429         hwif->dma_setup         = icside_dma_setup;
 430         hwif->dma_exec_cmd      = icside_dma_exec_cmd;
 431         hwif->dma_start         = icside_dma_start;
 432         hwif->ide_dma_end       = icside_dma_end;
 433         hwif->ide_dma_test_irq  = icside_dma_test_irq;
 434         hwif->dma_timeout       = icside_dma_timeout;
 435         hwif->dma_lost_irq      = icside_dma_lost_irq;
 436 }
 437 #else
 438 #define icside_dma_init(hwif)   (0)
 439 #endif
 440
 441 static ide_hwif_t *icside_find_hwif(unsigned long dataport)
 442 {
 443         ide_hwif_t *hwif;
 444         int index;
 445
 446         for (index = 0; index < MAX_HWIFS; ++index) {
 447                 hwif = &ide_hwifs[index];
 448                 if (hwif->io_ports[IDE_DATA_OFFSET] == dataport)
 449                         goto found;
 450         }
 451
 452         for (index = 0; index < MAX_HWIFS; ++index) {
 453                 hwif = &ide_hwifs[index];
 454                 if (!hwif->io_ports[IDE_DATA_OFFSET])
 455                         goto found;
 456         }
 457
 458         hwif = NULL;
 459 found:
 460         return hwif;
 461 }
 462
 463 static ide_hwif_t *
 464 icside_setup(void __iomem *base, struct cardinfo *info, struct expansion_card *ec)
 465 {
 466         unsigned long port = (unsigned long)base + info->dataoffset;
 467         ide_hwif_t *hwif;
 468
 469         hwif = icside_find_hwif(port);
 470         if (hwif) {
 471                 int i;
 472
 473                 memset(&hwif->hw, 0, sizeof(hw_regs_t));
 474
 475                 /*
 476                  * Ensure we're using MMIO
 477                  */
 478                 default_hwif_mmiops(hwif);
 479                 hwif->mmio = 1;
 480
 481                 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
 482                         hwif->hw.io_ports[i] = port;
 483                         hwif->io_ports[i] = port;
 484                         port += 1 << info->stepping;
 485                 }
 486                 hwif->hw.io_ports[IDE_CONTROL_OFFSET] = (unsigned long)base + info->ctrloffset;
 487                 hwif->io_ports[IDE_CONTROL_OFFSET] = (unsigned long)base + info->ctrloffset;
 488                 hwif->hw.irq  = ec->irq;
 489                 hwif->irq     = ec->irq;
 490                 hwif->noprobe = 0;
 491                 hwif->chipset = ide_acorn;
 492                 hwif->gendev.parent = &ec->dev;
 493         }
 494
 495         return hwif;
 496 }
 497
 498 static int __init
 499 icside_register_v5(struct icside_state *state, struct expansion_card *ec)
 500 {
 501         ide_hwif_t *hwif;
 502         void __iomem *base;
 503         u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
 504
 505         base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0);
 506         if (!base)
 507                 return -ENOMEM;
 508
 509         state->irq_port = base;
 510
 511         ec->irqaddr  = base + ICS_ARCIN_V5_INTRSTAT;
 512         ec->irqmask  = 1;
 513
 514         ecard_setirq(ec, &icside_ops_arcin_v5, state);
 515
 516         /*
 517          * Be on the safe side - disable interrupts
 518          */
 519         icside_irqdisable_arcin_v5(ec, 0);
 520
 521         hwif = icside_setup(base, &icside_cardinfo_v5, ec);
 522         if (!hwif)
 523                 return -ENODEV;
 524
 525         state->hwif[0] = hwif;
 526
 527         idx[0] = hwif->index;
 528
 529         ide_device_add(idx);
 530
 531         return 0;
 532 }
 533
 534 static int __init
 535 icside_register_v6(struct icside_state *state, struct expansion_card *ec)
 536 {
 537         ide_hwif_t *hwif, *mate;
 538         void __iomem *ioc_base, *easi_base;
 539         unsigned int sel = 0;
 540         int ret;
 541         u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
 542
 543         ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
 544         if (!ioc_base) {
 545                 ret = -ENOMEM;
 546                 goto out;
 547         }
 548
 549         easi_base = ioc_base;
 550
 551         if (ecard_resource_flags(ec, ECARD_RES_EASI)) {
 552                 easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0);
 553                 if (!easi_base) {
 554                         ret = -ENOMEM;
 555                         goto out;
 556                 }
 557
 558                 /*
 559                  * Enable access to the EASI region.
 560                  */
 561                 sel = 1 << 5;
 562         }
 563
 564         writeb(sel, ioc_base);
 565
 566         ecard_setirq(ec, &icside_ops_arcin_v6, state);
 567
 568         state->irq_port   = easi_base;
 569         state->ioc_base   = ioc_base;
 570
 571         /*
 572          * Be on the safe side - disable interrupts
 573          */
 574         icside_irqdisable_arcin_v6(ec, 0);
 575
 576         /*
 577          * Find and register the interfaces.
 578          */
 579         hwif = icside_setup(easi_base, &icside_cardinfo_v6_1, ec);
 580         mate = icside_setup(easi_base, &icside_cardinfo_v6_2, ec);
 581
 582         if (!hwif || !mate) {
 583                 ret = -ENODEV;
 584                 goto out;
 585         }
 586
 587         state->hwif[0]    = hwif;
 588         state->hwif[1]    = mate;
 589
 590         hwif->maskproc    = icside_maskproc;
 591         hwif->channel     = 0;
 592         hwif->hwif_data   = state;
 593         hwif->mate        = mate;
 594         hwif->serialized  = 1;
 595         hwif->config_data = (unsigned long)ioc_base;
 596         hwif->select_data = sel;
 597         hwif->hw.dma      = ec->dma;
 598
 599         mate->maskproc    = icside_maskproc;
 600         mate->channel     = 1;
 601         mate->hwif_data   = state;
 602         mate->mate        = hwif;
 603         mate->serialized  = 1;
 604         mate->config_data = (unsigned long)ioc_base;
 605         mate->select_data = sel | 1;
 606         mate->hw.dma      = ec->dma;
 607
 608         if (ec->dma != NO_DMA && !request_dma(ec->dma, hwif->name)) {
 609                 icside_dma_init(hwif);
 610                 icside_dma_init(mate);
 611         }
 612
 613         idx[0] = hwif->index;
 614         idx[1] = mate->index;
 615
 616         ide_device_add(idx);
 617
 618         return 0;
 619
 620  out:
 621         return ret;
 622 }
 623
 624 static int __devinit
 625 icside_probe(struct expansion_card *ec, const struct ecard_id *id)
 626 {
 627         struct icside_state *state;
 628         void __iomem *idmem;
 629         int ret;
 630
 631         ret = ecard_request_resources(ec);
 632         if (ret)
 633                 goto out;
 634
 635         state = kzalloc(sizeof(struct icside_state), GFP_KERNEL);
 636         if (!state) {
 637                 ret = -ENOMEM;
 638                 goto release;
 639         }
 640
 641         state->type     = ICS_TYPE_NOTYPE;
 642         state->dev      = &ec->dev;
 643
 644         idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
 645         if (idmem) {
 646                 unsigned int type;
 647
 648                 type = readb(idmem + ICS_IDENT_OFFSET) & 1;
 649                 type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1;
 650                 type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2;
 651                 type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3;
 652                 ecardm_iounmap(ec, idmem);
 653
 654                 state->type = type;
 655         }
 656
 657         switch (state->type) {
 658         case ICS_TYPE_A3IN:
 659                 dev_warn(&ec->dev, "A3IN unsupported\n");
 660                 ret = -ENODEV;
 661                 break;
 662
 663         case ICS_TYPE_A3USER:
 664                 dev_warn(&ec->dev, "A3USER unsupported\n");
 665                 ret = -ENODEV;
 666                 break;
 667
 668         case ICS_TYPE_V5:
 669                 ret = icside_register_v5(state, ec);
 670                 break;
 671
 672         case ICS_TYPE_V6:
 673                 ret = icside_register_v6(state, ec);
 674                 break;
 675
 676         default:
 677                 dev_warn(&ec->dev, "unknown interface type\n");
 678                 ret = -ENODEV;
 679                 break;
 680         }
 681
 682         if (ret == 0) {
 683                 ecard_set_drvdata(ec, state);
 684                 goto out;
 685         }
 686
 687         kfree(state);
 688  release:
 689         ecard_release_resources(ec);
 690  out:
 691         return ret;
 692 }
 693
 694 static void __devexit icside_remove(struct expansion_card *ec)
 695 {
 696         struct icside_state *state = ecard_get_drvdata(ec);
 697
 698         switch (state->type) {
 699         case ICS_TYPE_V5:
 700                 /* FIXME: tell IDE to stop using the interface */
 701
 702                 /* Disable interrupts */
 703                 icside_irqdisable_arcin_v5(ec, 0);
 704                 break;
 705
 706         case ICS_TYPE_V6:
 707                 /* FIXME: tell IDE to stop using the interface */
 708                 if (ec->dma != NO_DMA)
 709                         free_dma(ec->dma);
 710
 711                 /* Disable interrupts */
 712                 icside_irqdisable_arcin_v6(ec, 0);
 713
 714                 /* Reset the ROM pointer/EASI selection */
 715                 writeb(0, state->ioc_base);
 716                 break;
 717         }
 718
 719         ecard_set_drvdata(ec, NULL);
 720
 721         kfree(state);
 722         ecard_release_resources(ec);
 723 }
 724
 725 static void icside_shutdown(struct expansion_card *ec)
 726 {
 727         struct icside_state *state = ecard_get_drvdata(ec);
 728         unsigned long flags;
 729
 730         /*
 731          * Disable interrupts from this card.  We need to do
 732          * this before disabling EASI since we may be accessing
 733          * this register via that region.
 734          */
 735         local_irq_save(flags);
 736         ec->ops->irqdisable(ec, 0);
 737         local_irq_restore(flags);
 738
 739         /*
 740          * Reset the ROM pointer so that we can read the ROM
 741          * after a soft reboot.  This also disables access to
 742          * the IDE taskfile via the EASI region.
 743          */
 744         if (state->ioc_base)
 745                 writeb(0, state->ioc_base);
 746 }
 747
 748 static const struct ecard_id icside_ids[] = {
 749         { MANU_ICS,  PROD_ICS_IDE  },
 750         { MANU_ICS2, PROD_ICS2_IDE },
 751         { 0xffff, 0xffff }
 752 };
 753
 754 static struct ecard_driver icside_driver = {
 755         .probe          = icside_probe,
 756         .remove         = __devexit_p(icside_remove),
 757         .shutdown       = icside_shutdown,
 758         .id_table       = icside_ids,
 759         .drv = {
 760                 .name   = "icside",
 761         },
 762 };
 763
 764 static int __init icside_init(void)
 765 {
 766         return ecard_register_driver(&icside_driver);
 767 }
 768
 769 MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
 770 MODULE_LICENSE("GPL");
 771 MODULE_DESCRIPTION("ICS IDE driver");
 772
 773 module_init(icside_init);