drivers/ide/arm/icside.c

   1 /*
   2  * Copyright (c) 1996-2004 Russell King.
   3  *
   4  * Please note that this platform does not support 32-bit IDE IO.
   5  */
   6
   7 #include <linux/string.h>
   8 #include <linux/module.h>
   9 #include <linux/ioport.h>
  10 #include <linux/slab.h>
  11 #include <linux/blkdev.h>
  12 #include <linux/errno.h>
  13 #include <linux/hdreg.h>
  14 #include <linux/ide.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/device.h>
  17 #include <linux/init.h>
  18 #include <linux/scatterlist.h>
  19 #include <linux/io.h>
  20
  21 #include <asm/dma.h>
  22 #include <asm/ecard.h>
  23
  24 #define ICS_IDENT_OFFSET                0x2280
  25
  26 #define ICS_ARCIN_V5_INTRSTAT           0x0000
  27 #define ICS_ARCIN_V5_INTROFFSET         0x0004
  28 #define ICS_ARCIN_V5_IDEOFFSET          0x2800
  29 #define ICS_ARCIN_V5_IDEALTOFFSET       0x2b80
  30 #define ICS_ARCIN_V5_IDESTEPPING        6
  31
  32 #define ICS_ARCIN_V6_IDEOFFSET_1        0x2000
  33 #define ICS_ARCIN_V6_INTROFFSET_1       0x2200
  34 #define ICS_ARCIN_V6_INTRSTAT_1         0x2290
  35 #define ICS_ARCIN_V6_IDEALTOFFSET_1     0x2380
  36 #define ICS_ARCIN_V6_IDEOFFSET_2        0x3000
  37 #define ICS_ARCIN_V6_INTROFFSET_2       0x3200
  38 #define ICS_ARCIN_V6_INTRSTAT_2         0x3290
  39 #define ICS_ARCIN_V6_IDEALTOFFSET_2     0x3380
  40 #define ICS_ARCIN_V6_IDESTEPPING        6
  41
  42 struct cardinfo {
  43         unsigned int dataoffset;
  44         unsigned int ctrloffset;
  45         unsigned int stepping;
  46 };
  47
  48 static struct cardinfo icside_cardinfo_v5 = {
  49         .dataoffset     = ICS_ARCIN_V5_IDEOFFSET,
  50         .ctrloffset     = ICS_ARCIN_V5_IDEALTOFFSET,
  51         .stepping       = ICS_ARCIN_V5_IDESTEPPING,
  52 };
  53
  54 static struct cardinfo icside_cardinfo_v6_1 = {
  55         .dataoffset     = ICS_ARCIN_V6_IDEOFFSET_1,
  56         .ctrloffset     = ICS_ARCIN_V6_IDEALTOFFSET_1,
  57         .stepping       = ICS_ARCIN_V6_IDESTEPPING,
  58 };
  59
  60 static struct cardinfo icside_cardinfo_v6_2 = {
  61         .dataoffset     = ICS_ARCIN_V6_IDEOFFSET_2,
  62         .ctrloffset     = ICS_ARCIN_V6_IDEALTOFFSET_2,
  63         .stepping       = ICS_ARCIN_V6_IDESTEPPING,
  64 };
  65
  66 struct icside_state {
  67         unsigned int channel;
  68         unsigned int enabled;
  69         void __iomem *irq_port;
  70         void __iomem *ioc_base;
  71         unsigned int type;
  72         ide_hwif_t *hwif[2];
  73 };
  74
  75 #define ICS_TYPE_A3IN   0
  76 #define ICS_TYPE_A3USER 1
  77 #define ICS_TYPE_V6     3
  78 #define ICS_TYPE_V5     15
  79 #define ICS_TYPE_NOTYPE ((unsigned int)-1)
  80
  81 /* ---------------- Version 5 PCB Support Functions --------------------- */
  82 /* Prototype: icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
  83  * Purpose  : enable interrupts from card
  84  */
  85 static void icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
  86 {
  87         struct icside_state *state = ec->irq_data;
  88
  89         writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET);
  90 }
  91
  92 /* Prototype: icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
  93  * Purpose  : disable interrupts from card
  94  */
  95 static void icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
  96 {
  97         struct icside_state *state = ec->irq_data;
  98
  99         readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET);
 100 }
 101
 102 static const expansioncard_ops_t icside_ops_arcin_v5 = {
 103         .irqenable      = icside_irqenable_arcin_v5,
 104         .irqdisable     = icside_irqdisable_arcin_v5,
 105 };
 106
 107
 108 /* ---------------- Version 6 PCB Support Functions --------------------- */
 109 /* Prototype: icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
 110  * Purpose  : enable interrupts from card
 111  */
 112 static void icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
 113 {
 114         struct icside_state *state = ec->irq_data;
 115         void __iomem *base = state->irq_port;
 116
 117         state->enabled = 1;
 118
 119         switch (state->channel) {
 120         case 0:
 121                 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
 122                 readb(base + ICS_ARCIN_V6_INTROFFSET_2);
 123                 break;
 124         case 1:
 125                 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
 126                 readb(base + ICS_ARCIN_V6_INTROFFSET_1);
 127                 break;
 128         }
 129 }
 130
 131 /* Prototype: icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
 132  * Purpose  : disable interrupts from card
 133  */
 134 static void icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
 135 {
 136         struct icside_state *state = ec->irq_data;
 137
 138         state->enabled = 0;
 139
 140         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 141         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 142 }
 143
 144 /* Prototype: icside_irqprobe(struct expansion_card *ec)
 145  * Purpose  : detect an active interrupt from card
 146  */
 147 static int icside_irqpending_arcin_v6(struct expansion_card *ec)
 148 {
 149         struct icside_state *state = ec->irq_data;
 150
 151         return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 ||
 152                readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1;
 153 }
 154
 155 static const expansioncard_ops_t icside_ops_arcin_v6 = {
 156         .irqenable      = icside_irqenable_arcin_v6,
 157         .irqdisable     = icside_irqdisable_arcin_v6,
 158         .irqpending     = icside_irqpending_arcin_v6,
 159 };
 160
 161 /*
 162  * Handle routing of interrupts.  This is called before
 163  * we write the command to the drive.
 164  */
 165 static void icside_maskproc(ide_drive_t *drive, int mask)
 166 {
 167         ide_hwif_t *hwif = HWIF(drive);
 168         struct icside_state *state = hwif->hwif_data;
 169         unsigned long flags;
 170
 171         local_irq_save(flags);
 172
 173         state->channel = hwif->channel;
 174
 175         if (state->enabled && !mask) {
 176                 switch (hwif->channel) {
 177                 case 0:
 178                         writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 179                         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 180                         break;
 181                 case 1:
 182                         writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 183                         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 184                         break;
 185                 }
 186         } else {
 187                 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 188                 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 189         }
 190
 191         local_irq_restore(flags);
 192 }
 193
 194 static const struct ide_port_ops icside_v6_no_dma_port_ops = {
 195         .maskproc               = icside_maskproc,
 196 };
 197
 198 #ifdef CONFIG_BLK_DEV_IDEDMA_ICS
 199 /*
 200  * SG-DMA support.
 201  *
 202  * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
 203  * There is only one DMA controller per card, which means that only
 204  * one drive can be accessed at one time.  NOTE! We do not enforce that
 205  * here, but we rely on the main IDE driver spotting that both
 206  * interfaces use the same IRQ, which should guarantee this.
 207  */
 208
 209 /*
 210  * Configure the IOMD to give the appropriate timings for the transfer
 211  * mode being requested.  We take the advice of the ATA standards, and
 212  * calculate the cycle time based on the transfer mode, and the EIDE
 213  * MW DMA specs that the drive provides in the IDENTIFY command.
 214  *
 215  * We have the following IOMD DMA modes to choose from:
 216  *
 217  *      Type    Active          Recovery        Cycle
 218  *      A       250 (250)       312 (550)       562 (800)
 219  *      B       187             250             437
 220  *      C       125 (125)       125 (375)       250 (500)
 221  *      D       62              125             187
 222  *
 223  * (figures in brackets are actual measured timings)
 224  *
 225  * However, we also need to take care of the read/write active and
 226  * recovery timings:
 227  *
 228  *                      Read    Write
 229  *      Mode    Active  -- Recovery --  Cycle   IOMD type
 230  *      MW0     215     50      215     480     A
 231  *      MW1     80      50      50      150     C
 232  *      MW2     70      25      25      120     C
 233  */
 234 static void icside_set_dma_mode(ide_drive_t *drive, const u8 xfer_mode)
 235 {
 236         int cycle_time, use_dma_info = 0;
 237
 238         switch (xfer_mode) {
 239         case XFER_MW_DMA_2:
 240                 cycle_time = 250;
 241                 use_dma_info = 1;
 242                 break;
 243
 244         case XFER_MW_DMA_1:
 245                 cycle_time = 250;
 246                 use_dma_info = 1;
 247                 break;
 248
 249         case XFER_MW_DMA_0:
 250                 cycle_time = 480;
 251                 break;
 252
 253         case XFER_SW_DMA_2:
 254         case XFER_SW_DMA_1:
 255         case XFER_SW_DMA_0:
 256                 cycle_time = 480;
 257                 break;
 258         }
 259
 260         /*
 261          * If we're going to be doing MW_DMA_1 or MW_DMA_2, we should
 262          * take care to note the values in the ID...
 263          */
 264         if (use_dma_info && drive->id->eide_dma_time > cycle_time)
 265                 cycle_time = drive->id->eide_dma_time;
 266
 267         drive->drive_data = cycle_time;
 268
 269         printk("%s: %s selected (peak %dMB/s)\n", drive->name,
 270                 ide_xfer_verbose(xfer_mode), 2000 / drive->drive_data);
 271 }
 272
 273 static const struct ide_port_ops icside_v6_port_ops = {
 274         .set_dma_mode           = icside_set_dma_mode,
 275         .maskproc               = icside_maskproc,
 276 };
 277
 278 static void icside_dma_host_set(ide_drive_t *drive, int on)
 279 {
 280 }
 281
 282 static int icside_dma_end(ide_drive_t *drive)
 283 {
 284         ide_hwif_t *hwif = HWIF(drive);
 285         struct expansion_card *ec = ECARD_DEV(hwif->dev);
 286
 287         drive->waiting_for_dma = 0;
 288
 289         disable_dma(ec->dma);
 290
 291         /* Teardown mappings after DMA has completed. */
 292         ide_destroy_dmatable(drive);
 293
 294         return get_dma_residue(ec->dma) != 0;
 295 }
 296
 297 static void icside_dma_start(ide_drive_t *drive)
 298 {
 299         ide_hwif_t *hwif = HWIF(drive);
 300         struct expansion_card *ec = ECARD_DEV(hwif->dev);
 301
 302         /* We can not enable DMA on both channels simultaneously. */
 303         BUG_ON(dma_channel_active(ec->dma));
 304         enable_dma(ec->dma);
 305 }
 306
 307 static int icside_dma_setup(ide_drive_t *drive)
 308 {
 309         ide_hwif_t *hwif = HWIF(drive);
 310         struct expansion_card *ec = ECARD_DEV(hwif->dev);
 311         struct request *rq = hwif->hwgroup->rq;
 312         unsigned int dma_mode;
 313
 314         if (rq_data_dir(rq))
 315                 dma_mode = DMA_MODE_WRITE;
 316         else
 317                 dma_mode = DMA_MODE_READ;
 318
 319         /*
 320          * We can not enable DMA on both channels.
 321          */
 322         BUG_ON(dma_channel_active(ec->dma));
 323
 324         hwif->sg_nents = ide_build_sglist(drive, rq);
 325
 326         /*
 327          * Ensure that we have the right interrupt routed.
 328          */
 329         icside_maskproc(drive, 0);
 330
 331         /*
 332          * Route the DMA signals to the correct interface.
 333          */
 334         writeb(hwif->select_data, hwif->config_data);
 335
 336         /*
 337          * Select the correct timing for this drive.
 338          */
 339         set_dma_speed(ec->dma, drive->drive_data);
 340
 341         /*
 342          * Tell the DMA engine about the SG table and
 343          * data direction.
 344          */
 345         set_dma_sg(ec->dma, hwif->sg_table, hwif->sg_nents);
 346         set_dma_mode(ec->dma, dma_mode);
 347
 348         drive->waiting_for_dma = 1;
 349
 350         return 0;
 351 }
 352
 353 static void icside_dma_exec_cmd(ide_drive_t *drive, u8 cmd)
 354 {
 355         /* issue cmd to drive */
 356         ide_execute_command(drive, cmd, ide_dma_intr, 2 * WAIT_CMD, NULL);
 357 }
 358
 359 static int icside_dma_test_irq(ide_drive_t *drive)
 360 {
 361         ide_hwif_t *hwif = HWIF(drive);
 362         struct icside_state *state = hwif->hwif_data;
 363
 364         return readb(state->irq_port +
 365                      (hwif->channel ?
 366                         ICS_ARCIN_V6_INTRSTAT_2 :
 367                         ICS_ARCIN_V6_INTRSTAT_1)) & 1;
 368 }
 369
 370 static void icside_dma_timeout(ide_drive_t *drive)
 371 {
 372         printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name);
 373
 374         if (icside_dma_test_irq(drive))
 375                 return;
 376
 377         ide_dump_status(drive, "DMA timeout", ide_read_status(drive));
 378
 379         icside_dma_end(drive);
 380 }
 381
 382 static void icside_dma_lost_irq(ide_drive_t *drive)
 383 {
 384         printk(KERN_ERR "%s: IRQ lost\n", drive->name);
 385 }
 386
 387 static int icside_dma_init(ide_hwif_t *hwif, const struct ide_port_info *d)
 388 {
 389         hwif->dmatable_cpu      = NULL;
 390         hwif->dmatable_dma      = 0;
 391
 392         return 0;
 393 }
 394
 395 static const struct ide_dma_ops icside_v6_dma_ops = {
 396         .dma_host_set           = icside_dma_host_set,
 397         .dma_setup              = icside_dma_setup,
 398         .dma_exec_cmd           = icside_dma_exec_cmd,
 399         .dma_start              = icside_dma_start,
 400         .dma_end                = icside_dma_end,
 401         .dma_test_irq           = icside_dma_test_irq,
 402         .dma_timeout            = icside_dma_timeout,
 403         .dma_lost_irq           = icside_dma_lost_irq,
 404 };
 405 #else
 406 #define icside_v6_dma_ops NULL
 407 #endif
 408
 409 static int icside_dma_off_init(ide_hwif_t *hwif, const struct ide_port_info *d)
 410 {
 411         return -EOPNOTSUPP;
 412 }
 413
 414 static ide_hwif_t *
 415 icside_setup(void __iomem *base, struct cardinfo *info, struct expansion_card *ec)
 416 {
 417         unsigned long port = (unsigned long)base + info->dataoffset;
 418         ide_hwif_t *hwif;
 419
 420         hwif = ide_find_port();
 421         if (hwif) {
 422                 /*
 423                  * Ensure we're using MMIO
 424                  */
 425                 default_hwif_mmiops(hwif);
 426
 427                 hwif->io_ports.data_addr = port;
 428                 hwif->io_ports.error_addr = port + (1 << info->stepping);
 429                 hwif->io_ports.nsect_addr = port + (2 << info->stepping);
 430                 hwif->io_ports.lbal_addr = port + (3 << info->stepping);
 431                 hwif->io_ports.lbam_addr = port + (4 << info->stepping);
 432                 hwif->io_ports.lbah_addr = port + (5 << info->stepping);
 433                 hwif->io_ports.device_addr = port + (6 << info->stepping);
 434                 hwif->io_ports.status_addr = port + (7 << info->stepping);
 435                 hwif->io_ports.ctl_addr =
 436                         (unsigned long)base + info->ctrloffset;
 437                 hwif->irq     = ec->irq;
 438                 hwif->chipset = ide_acorn;
 439                 hwif->gendev.parent = &ec->dev;
 440                 hwif->dev = &ec->dev;
 441         }
 442
 443         return hwif;
 444 }
 445
 446 static int __init
 447 icside_register_v5(struct icside_state *state, struct expansion_card *ec)
 448 {
 449         ide_hwif_t *hwif;
 450         void __iomem *base;
 451         u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
 452
 453         base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0);
 454         if (!base)
 455                 return -ENOMEM;
 456
 457         state->irq_port = base;
 458
 459         ec->irqaddr  = base + ICS_ARCIN_V5_INTRSTAT;
 460         ec->irqmask  = 1;
 461
 462         ecard_setirq(ec, &icside_ops_arcin_v5, state);
 463
 464         /*
 465          * Be on the safe side - disable interrupts
 466          */
 467         icside_irqdisable_arcin_v5(ec, 0);
 468
 469         hwif = icside_setup(base, &icside_cardinfo_v5, ec);
 470         if (!hwif)
 471                 return -ENODEV;
 472
 473         state->hwif[0] = hwif;
 474
 475         idx[0] = hwif->index;
 476
 477         ide_device_add(idx, NULL);
 478
 479         return 0;
 480 }
 481
 482 static const struct ide_port_info icside_v6_port_info __initdata = {
 483         .init_dma               = icside_dma_off_init,
 484         .port_ops               = &icside_v6_no_dma_port_ops,
 485         .dma_ops                = &icside_v6_dma_ops,
 486         .host_flags             = IDE_HFLAG_SERIALIZE | IDE_HFLAG_MMIO,
 487         .mwdma_mask             = ATA_MWDMA2,
 488         .swdma_mask             = ATA_SWDMA2,
 489 };
 490
 491 static int __init
 492 icside_register_v6(struct icside_state *state, struct expansion_card *ec)
 493 {
 494         ide_hwif_t *hwif, *mate;
 495         void __iomem *ioc_base, *easi_base;
 496         unsigned int sel = 0;
 497         int ret;
 498         u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
 499         struct ide_port_info d = icside_v6_port_info;
 500
 501         ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
 502         if (!ioc_base) {
 503                 ret = -ENOMEM;
 504                 goto out;
 505         }
 506
 507         easi_base = ioc_base;
 508
 509         if (ecard_resource_flags(ec, ECARD_RES_EASI)) {
 510                 easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0);
 511                 if (!easi_base) {
 512                         ret = -ENOMEM;
 513                         goto out;
 514                 }
 515
 516                 /*
 517                  * Enable access to the EASI region.
 518                  */
 519                 sel = 1 << 5;
 520         }
 521
 522         writeb(sel, ioc_base);
 523
 524         ecard_setirq(ec, &icside_ops_arcin_v6, state);
 525
 526         state->irq_port   = easi_base;
 527         state->ioc_base   = ioc_base;
 528
 529         /*
 530          * Be on the safe side - disable interrupts
 531          */
 532         icside_irqdisable_arcin_v6(ec, 0);
 533
 534         /*
 535          * Find and register the interfaces.
 536          */
 537         hwif = icside_setup(easi_base, &icside_cardinfo_v6_1, ec);
 538         mate = icside_setup(easi_base, &icside_cardinfo_v6_2, ec);
 539
 540         if (!hwif || !mate) {
 541                 ret = -ENODEV;
 542                 goto out;
 543         }
 544
 545         state->hwif[0]    = hwif;
 546         state->hwif[1]    = mate;
 547
 548         hwif->hwif_data   = state;
 549         hwif->config_data = (unsigned long)ioc_base;
 550         hwif->select_data = sel;
 551
 552         mate->hwif_data   = state;
 553         mate->config_data = (unsigned long)ioc_base;
 554         mate->select_data = sel | 1;
 555
 556         if (ec->dma != NO_DMA && !request_dma(ec->dma, hwif->name)) {
 557                 d.init_dma = icside_dma_init;
 558                 d.port_ops = &icside_v6_port_ops;
 559                 d.dma_ops = NULL;
 560         }
 561
 562         idx[0] = hwif->index;
 563         idx[1] = mate->index;
 564
 565         ide_device_add(idx, &d);
 566
 567         return 0;
 568
 569  out:
 570         return ret;
 571 }
 572
 573 static int __devinit
 574 icside_probe(struct expansion_card *ec, const struct ecard_id *id)
 575 {
 576         struct icside_state *state;
 577         void __iomem *idmem;
 578         int ret;
 579
 580         ret = ecard_request_resources(ec);
 581         if (ret)
 582                 goto out;
 583
 584         state = kzalloc(sizeof(struct icside_state), GFP_KERNEL);
 585         if (!state) {
 586                 ret = -ENOMEM;
 587                 goto release;
 588         }
 589
 590         state->type     = ICS_TYPE_NOTYPE;
 591
 592         idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
 593         if (idmem) {
 594                 unsigned int type;
 595
 596                 type = readb(idmem + ICS_IDENT_OFFSET) & 1;
 597                 type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1;
 598                 type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2;
 599                 type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3;
 600                 ecardm_iounmap(ec, idmem);
 601
 602                 state->type = type;
 603         }
 604
 605         switch (state->type) {
 606         case ICS_TYPE_A3IN:
 607                 dev_warn(&ec->dev, "A3IN unsupported\n");
 608                 ret = -ENODEV;
 609                 break;
 610
 611         case ICS_TYPE_A3USER:
 612                 dev_warn(&ec->dev, "A3USER unsupported\n");
 613                 ret = -ENODEV;
 614                 break;
 615
 616         case ICS_TYPE_V5:
 617                 ret = icside_register_v5(state, ec);
 618                 break;
 619
 620         case ICS_TYPE_V6:
 621                 ret = icside_register_v6(state, ec);
 622                 break;
 623
 624         default:
 625                 dev_warn(&ec->dev, "unknown interface type\n");
 626                 ret = -ENODEV;
 627                 break;
 628         }
 629
 630         if (ret == 0) {
 631                 ecard_set_drvdata(ec, state);
 632                 goto out;
 633         }
 634
 635         kfree(state);
 636  release:
 637         ecard_release_resources(ec);
 638  out:
 639         return ret;
 640 }
 641
 642 static void __devexit icside_remove(struct expansion_card *ec)
 643 {
 644         struct icside_state *state = ecard_get_drvdata(ec);
 645
 646         switch (state->type) {
 647         case ICS_TYPE_V5:
 648                 /* FIXME: tell IDE to stop using the interface */
 649
 650                 /* Disable interrupts */
 651                 icside_irqdisable_arcin_v5(ec, 0);
 652                 break;
 653
 654         case ICS_TYPE_V6:
 655                 /* FIXME: tell IDE to stop using the interface */
 656                 if (ec->dma != NO_DMA)
 657                         free_dma(ec->dma);
 658
 659                 /* Disable interrupts */
 660                 icside_irqdisable_arcin_v6(ec, 0);
 661
 662                 /* Reset the ROM pointer/EASI selection */
 663                 writeb(0, state->ioc_base);
 664                 break;
 665         }
 666
 667         ecard_set_drvdata(ec, NULL);
 668
 669         kfree(state);
 670         ecard_release_resources(ec);
 671 }
 672
 673 static void icside_shutdown(struct expansion_card *ec)
 674 {
 675         struct icside_state *state = ecard_get_drvdata(ec);
 676         unsigned long flags;
 677
 678         /*
 679          * Disable interrupts from this card.  We need to do
 680          * this before disabling EASI since we may be accessing
 681          * this register via that region.
 682          */
 683         local_irq_save(flags);
 684         ec->ops->irqdisable(ec, 0);
 685         local_irq_restore(flags);
 686
 687         /*
 688          * Reset the ROM pointer so that we can read the ROM
 689          * after a soft reboot.  This also disables access to
 690          * the IDE taskfile via the EASI region.
 691          */
 692         if (state->ioc_base)
 693                 writeb(0, state->ioc_base);
 694 }
 695
 696 static const struct ecard_id icside_ids[] = {
 697         { MANU_ICS,  PROD_ICS_IDE  },
 698         { MANU_ICS2, PROD_ICS2_IDE },
 699         { 0xffff, 0xffff }
 700 };
 701
 702 static struct ecard_driver icside_driver = {
 703         .probe          = icside_probe,
 704         .remove         = __devexit_p(icside_remove),
 705         .shutdown       = icside_shutdown,
 706         .id_table       = icside_ids,
 707         .drv = {
 708                 .name   = "icside",
 709         },
 710 };
 711
 712 static int __init icside_init(void)
 713 {
 714         return ecard_register_driver(&icside_driver);
 715 }
 716
 717 MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
 718 MODULE_LICENSE("GPL");
 719 MODULE_DESCRIPTION("ICS IDE driver");
 720
 721 module_init(icside_init);