1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2017 STMicroelectronics
13 #include <dm/device.h>
14 #include <linux/err.h>
17 /* STM32 I2C registers */
18 struct stm32_i2c_regs {
19 u32 cr1; /* I2C control register 1 */
20 u32 cr2; /* I2C control register 2 */
21 u32 oar1; /* I2C own address 1 register */
22 u32 oar2; /* I2C own address 2 register */
23 u32 timingr; /* I2C timing register */
24 u32 timeoutr; /* I2C timeout register */
25 u32 isr; /* I2C interrupt and status register */
26 u32 icr; /* I2C interrupt clear register */
27 u32 pecr; /* I2C packet error checking register */
28 u32 rxdr; /* I2C receive data register */
29 u32 txdr; /* I2C transmit data register */
32 #define STM32_I2C_CR1 0x00
33 #define STM32_I2C_CR2 0x04
34 #define STM32_I2C_TIMINGR 0x10
35 #define STM32_I2C_ISR 0x18
36 #define STM32_I2C_ICR 0x1C
37 #define STM32_I2C_RXDR 0x24
38 #define STM32_I2C_TXDR 0x28
40 /* STM32 I2C control 1 */
41 #define STM32_I2C_CR1_ANFOFF BIT(12)
42 #define STM32_I2C_CR1_ERRIE BIT(7)
43 #define STM32_I2C_CR1_TCIE BIT(6)
44 #define STM32_I2C_CR1_STOPIE BIT(5)
45 #define STM32_I2C_CR1_NACKIE BIT(4)
46 #define STM32_I2C_CR1_ADDRIE BIT(3)
47 #define STM32_I2C_CR1_RXIE BIT(2)
48 #define STM32_I2C_CR1_TXIE BIT(1)
49 #define STM32_I2C_CR1_PE BIT(0)
51 /* STM32 I2C control 2 */
52 #define STM32_I2C_CR2_AUTOEND BIT(25)
53 #define STM32_I2C_CR2_RELOAD BIT(24)
54 #define STM32_I2C_CR2_NBYTES_MASK GENMASK(23, 16)
55 #define STM32_I2C_CR2_NBYTES(n) ((n & 0xff) << 16)
56 #define STM32_I2C_CR2_NACK BIT(15)
57 #define STM32_I2C_CR2_STOP BIT(14)
58 #define STM32_I2C_CR2_START BIT(13)
59 #define STM32_I2C_CR2_HEAD10R BIT(12)
60 #define STM32_I2C_CR2_ADD10 BIT(11)
61 #define STM32_I2C_CR2_RD_WRN BIT(10)
62 #define STM32_I2C_CR2_SADD10_MASK GENMASK(9, 0)
63 #define STM32_I2C_CR2_SADD10(n) (n & STM32_I2C_CR2_SADD10_MASK)
64 #define STM32_I2C_CR2_SADD7_MASK GENMASK(7, 1)
65 #define STM32_I2C_CR2_SADD7(n) ((n & 0x7f) << 1)
66 #define STM32_I2C_CR2_RESET_MASK (STM32_I2C_CR2_HEAD10R \
67 | STM32_I2C_CR2_NBYTES_MASK \
68 | STM32_I2C_CR2_SADD7_MASK \
69 | STM32_I2C_CR2_RELOAD \
70 | STM32_I2C_CR2_RD_WRN)
72 /* STM32 I2C Interrupt Status */
73 #define STM32_I2C_ISR_BUSY BIT(15)
74 #define STM32_I2C_ISR_ARLO BIT(9)
75 #define STM32_I2C_ISR_BERR BIT(8)
76 #define STM32_I2C_ISR_TCR BIT(7)
77 #define STM32_I2C_ISR_TC BIT(6)
78 #define STM32_I2C_ISR_STOPF BIT(5)
79 #define STM32_I2C_ISR_NACKF BIT(4)
80 #define STM32_I2C_ISR_ADDR BIT(3)
81 #define STM32_I2C_ISR_RXNE BIT(2)
82 #define STM32_I2C_ISR_TXIS BIT(1)
83 #define STM32_I2C_ISR_TXE BIT(0)
84 #define STM32_I2C_ISR_ERRORS (STM32_I2C_ISR_BERR \
87 /* STM32 I2C Interrupt Clear */
88 #define STM32_I2C_ICR_ARLOCF BIT(9)
89 #define STM32_I2C_ICR_BERRCF BIT(8)
90 #define STM32_I2C_ICR_STOPCF BIT(5)
91 #define STM32_I2C_ICR_NACKCF BIT(4)
93 /* STM32 I2C Timing */
94 #define STM32_I2C_TIMINGR_PRESC(n) ((n & 0xf) << 28)
95 #define STM32_I2C_TIMINGR_SCLDEL(n) ((n & 0xf) << 20)
96 #define STM32_I2C_TIMINGR_SDADEL(n) ((n & 0xf) << 16)
97 #define STM32_I2C_TIMINGR_SCLH(n) ((n & 0xff) << 8)
98 #define STM32_I2C_TIMINGR_SCLL(n) (n & 0xff)
100 #define STM32_I2C_MAX_LEN 0xff
102 #define STM32_I2C_DNF_DEFAULT 0
103 #define STM32_I2C_DNF_MAX 16
105 #define STM32_I2C_ANALOG_FILTER_ENABLE 1
106 #define STM32_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */
107 #define STM32_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */
109 #define STM32_I2C_RISE_TIME_DEFAULT 25 /* ns */
110 #define STM32_I2C_FALL_TIME_DEFAULT 10 /* ns */
112 #define STM32_PRESC_MAX BIT(4)
113 #define STM32_SCLDEL_MAX BIT(4)
114 #define STM32_SDADEL_MAX BIT(4)
115 #define STM32_SCLH_MAX BIT(8)
116 #define STM32_SCLL_MAX BIT(8)
118 #define STM32_NSEC_PER_SEC 1000000000L
121 * struct stm32_i2c_spec - private i2c specification timing
122 * @rate: I2C bus speed (Hz)
123 * @rate_min: 80% of I2C bus speed (Hz)
124 * @rate_max: 120% of I2C bus speed (Hz)
125 * @fall_max: Max fall time of both SDA and SCL signals (ns)
126 * @rise_max: Max rise time of both SDA and SCL signals (ns)
127 * @hddat_min: Min data hold time (ns)
128 * @vddat_max: Max data valid time (ns)
129 * @sudat_min: Min data setup time (ns)
130 * @l_min: Min low period of the SCL clock (ns)
131 * @h_min: Min high period of the SCL clock (ns)
134 struct stm32_i2c_spec {
148 * struct stm32_i2c_setup - private I2C timing setup parameters
149 * @speed_freq: I2C speed frequency (Hz)
150 * @clock_src: I2C clock source frequency (Hz)
151 * @rise_time: Rise time (ns)
152 * @fall_time: Fall time (ns)
153 * @dnf: Digital filter coefficient (0-16)
154 * @analog_filter: Analog filter delay (On/Off)
156 struct stm32_i2c_setup {
166 * struct stm32_i2c_timings - private I2C output parameters
167 * @prec: Prescaler value
168 * @scldel: Data setup time
169 * @sdadel: Data hold time
170 * @sclh: SCL high period (master mode)
171 * @sclh: SCL low period (master mode)
173 struct stm32_i2c_timings {
174 struct list_head node;
182 struct stm32_i2c_priv {
183 struct stm32_i2c_regs *regs;
185 struct stm32_i2c_setup *setup;
189 static const struct stm32_i2c_spec i2c_specs[] = {
190 /* Standard speed - 100 KHz */
191 [IC_SPEED_MODE_STANDARD] = {
192 .rate = I2C_SPEED_STANDARD_RATE,
203 /* Fast speed - 400 KHz */
204 [IC_SPEED_MODE_FAST] = {
205 .rate = I2C_SPEED_FAST_RATE,
216 /* Fast Plus Speed - 1 MHz */
217 [IC_SPEED_MODE_FAST_PLUS] = {
218 .rate = I2C_SPEED_FAST_PLUS_RATE,
231 static const struct stm32_i2c_setup stm32f7_setup = {
232 .rise_time = STM32_I2C_RISE_TIME_DEFAULT,
233 .fall_time = STM32_I2C_FALL_TIME_DEFAULT,
234 .dnf = STM32_I2C_DNF_DEFAULT,
235 .analog_filter = STM32_I2C_ANALOG_FILTER_ENABLE,
238 static int stm32_i2c_check_device_busy(struct stm32_i2c_priv *i2c_priv)
240 struct stm32_i2c_regs *regs = i2c_priv->regs;
241 u32 status = readl(®s->isr);
243 if (status & STM32_I2C_ISR_BUSY)
249 static void stm32_i2c_message_start(struct stm32_i2c_priv *i2c_priv,
250 struct i2c_msg *msg, bool stop)
252 struct stm32_i2c_regs *regs = i2c_priv->regs;
253 u32 cr2 = readl(®s->cr2);
255 /* Set transfer direction */
256 cr2 &= ~STM32_I2C_CR2_RD_WRN;
257 if (msg->flags & I2C_M_RD)
258 cr2 |= STM32_I2C_CR2_RD_WRN;
260 /* Set slave address */
261 cr2 &= ~(STM32_I2C_CR2_HEAD10R | STM32_I2C_CR2_ADD10);
262 if (msg->flags & I2C_M_TEN) {
263 cr2 &= ~STM32_I2C_CR2_SADD10_MASK;
264 cr2 |= STM32_I2C_CR2_SADD10(msg->addr);
265 cr2 |= STM32_I2C_CR2_ADD10;
267 cr2 &= ~STM32_I2C_CR2_SADD7_MASK;
268 cr2 |= STM32_I2C_CR2_SADD7(msg->addr);
271 /* Set nb bytes to transfer and reload or autoend bits */
272 cr2 &= ~(STM32_I2C_CR2_NBYTES_MASK | STM32_I2C_CR2_RELOAD |
273 STM32_I2C_CR2_AUTOEND);
274 if (msg->len > STM32_I2C_MAX_LEN) {
275 cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN);
276 cr2 |= STM32_I2C_CR2_RELOAD;
278 cr2 |= STM32_I2C_CR2_NBYTES(msg->len);
281 /* Write configurations register */
282 writel(cr2, ®s->cr2);
284 /* START/ReSTART generation */
285 setbits_le32(®s->cr2, STM32_I2C_CR2_START);
289 * RELOAD mode must be selected if total number of data bytes to be
290 * sent is greater than MAX_LEN
293 static void stm32_i2c_handle_reload(struct stm32_i2c_priv *i2c_priv,
294 struct i2c_msg *msg, bool stop)
296 struct stm32_i2c_regs *regs = i2c_priv->regs;
297 u32 cr2 = readl(®s->cr2);
299 cr2 &= ~STM32_I2C_CR2_NBYTES_MASK;
301 if (msg->len > STM32_I2C_MAX_LEN) {
302 cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN);
304 cr2 &= ~STM32_I2C_CR2_RELOAD;
305 cr2 |= STM32_I2C_CR2_NBYTES(msg->len);
308 writel(cr2, ®s->cr2);
311 static int stm32_i2c_wait_flags(struct stm32_i2c_priv *i2c_priv,
312 u32 flags, u32 *status)
314 struct stm32_i2c_regs *regs = i2c_priv->regs;
315 u32 time_start = get_timer(0);
317 *status = readl(®s->isr);
318 while (!(*status & flags)) {
319 if (get_timer(time_start) > CONFIG_SYS_HZ) {
320 debug("%s: i2c timeout\n", __func__);
324 *status = readl(®s->isr);
330 static int stm32_i2c_check_end_of_message(struct stm32_i2c_priv *i2c_priv)
332 struct stm32_i2c_regs *regs = i2c_priv->regs;
333 u32 mask = STM32_I2C_ISR_ERRORS | STM32_I2C_ISR_NACKF |
338 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
342 if (status & STM32_I2C_ISR_BERR) {
343 debug("%s: Bus error\n", __func__);
345 /* Clear BERR flag */
346 setbits_le32(®s->icr, STM32_I2C_ICR_BERRCF);
351 if (status & STM32_I2C_ISR_ARLO) {
352 debug("%s: Arbitration lost\n", __func__);
354 /* Clear ARLO flag */
355 setbits_le32(®s->icr, STM32_I2C_ICR_ARLOCF);
360 if (status & STM32_I2C_ISR_NACKF) {
361 debug("%s: Receive NACK\n", __func__);
363 /* Clear NACK flag */
364 setbits_le32(®s->icr, STM32_I2C_ICR_NACKCF);
366 /* Wait until STOPF flag is set */
367 mask = STM32_I2C_ISR_STOPF;
368 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
375 if (status & STM32_I2C_ISR_STOPF) {
376 /* Clear STOP flag */
377 setbits_le32(®s->icr, STM32_I2C_ICR_STOPCF);
379 /* Clear control register 2 */
380 setbits_le32(®s->cr2, STM32_I2C_CR2_RESET_MASK);
386 static int stm32_i2c_message_xfer(struct stm32_i2c_priv *i2c_priv,
387 struct i2c_msg *msg, bool stop)
389 struct stm32_i2c_regs *regs = i2c_priv->regs;
391 u32 mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE :
392 STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF;
393 int bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ?
394 STM32_I2C_MAX_LEN : msg->len;
398 mask |= STM32_I2C_ISR_ERRORS;
400 stm32_i2c_message_start(i2c_priv, msg, stop);
404 * Wait until TXIS/NACKF/BERR/ARLO flags or
405 * RXNE/BERR/ARLO flags are set
407 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
411 if (status & (STM32_I2C_ISR_NACKF | STM32_I2C_ISR_ERRORS))
414 if (status & STM32_I2C_ISR_RXNE) {
415 *msg->buf++ = readb(®s->rxdr);
420 if (status & STM32_I2C_ISR_TXIS) {
421 writeb(*msg->buf++, ®s->txdr);
426 if (!bytes_to_rw && msg->len) {
427 /* Wait until TCR flag is set */
428 mask = STM32_I2C_ISR_TCR;
429 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
433 bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ?
434 STM32_I2C_MAX_LEN : msg->len;
435 mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE :
436 STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF;
438 stm32_i2c_handle_reload(i2c_priv, msg, stop);
439 } else if (!bytes_to_rw) {
440 /* Wait until TC flag is set */
441 mask = STM32_I2C_ISR_TC;
442 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
447 /* Message sent, new message has to be sent */
452 /* End of transfer, send stop condition */
453 mask = STM32_I2C_CR2_STOP;
454 setbits_le32(®s->cr2, mask);
456 return stm32_i2c_check_end_of_message(i2c_priv);
459 static int stm32_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
462 struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus);
465 ret = stm32_i2c_check_device_busy(i2c_priv);
469 for (; nmsgs > 0; nmsgs--, msg++) {
470 ret = stm32_i2c_message_xfer(i2c_priv, msg, nmsgs == 1);
478 static int stm32_i2c_compute_solutions(struct stm32_i2c_setup *setup,
479 const struct stm32_i2c_spec *specs,
480 struct list_head *solutions)
482 struct stm32_i2c_timings *v;
483 u32 p_prev = STM32_PRESC_MAX;
484 u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
486 u32 af_delay_min, af_delay_max;
488 int sdadel_min, sdadel_max, scldel_min;
491 af_delay_min = setup->analog_filter ?
492 STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0;
493 af_delay_max = setup->analog_filter ?
494 STM32_I2C_ANALOG_FILTER_DELAY_MAX : 0;
496 sdadel_min = specs->hddat_min + setup->fall_time -
497 af_delay_min - (setup->dnf + 3) * i2cclk;
499 sdadel_max = specs->vddat_max - setup->rise_time -
500 af_delay_max - (setup->dnf + 4) * i2cclk;
502 scldel_min = setup->rise_time + specs->sudat_min;
509 debug("%s: SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n", __func__,
510 sdadel_min, sdadel_max, scldel_min);
512 /* Compute possible values for PRESC, SCLDEL and SDADEL */
513 for (p = 0; p < STM32_PRESC_MAX; p++) {
514 for (l = 0; l < STM32_SCLDEL_MAX; l++) {
515 int scldel = (l + 1) * (p + 1) * i2cclk;
517 if (scldel < scldel_min)
520 for (a = 0; a < STM32_SDADEL_MAX; a++) {
521 int sdadel = (a * (p + 1) + 1) * i2cclk;
523 if (((sdadel >= sdadel_min) &&
524 (sdadel <= sdadel_max)) &&
526 v = calloc(1, sizeof(*v));
535 list_add_tail(&v->node, solutions);
545 if (list_empty(solutions)) {
546 pr_err("%s: no Prescaler solution\n", __func__);
553 static int stm32_i2c_choose_solution(struct stm32_i2c_setup *setup,
554 const struct stm32_i2c_spec *specs,
555 struct list_head *solutions,
556 struct stm32_i2c_timings *s)
558 struct stm32_i2c_timings *v;
559 u32 i2cbus = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
561 u32 clk_error_prev = i2cbus;
562 u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
564 u32 clk_min, clk_max;
569 bool sol_found = false;
572 af_delay_min = setup->analog_filter ?
573 STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0;
574 dnf_delay = setup->dnf * i2cclk;
576 tsync = af_delay_min + dnf_delay + (2 * i2cclk);
577 clk_max = STM32_NSEC_PER_SEC / specs->rate_min;
578 clk_min = STM32_NSEC_PER_SEC / specs->rate_max;
581 * Among Prescaler possibilities discovered above figures out SCL Low
582 * and High Period. Provided:
583 * - SCL Low Period has to be higher than Low Period of the SCL Clock
584 * defined by I2C Specification. I2C Clock has to be lower than
585 * (SCL Low Period - Analog/Digital filters) / 4.
586 * - SCL High Period has to be lower than High Period of the SCL Clock
587 * defined by I2C Specification
588 * - I2C Clock has to be lower than SCL High Period
590 list_for_each_entry(v, solutions, node) {
591 u32 prescaler = (v->presc + 1) * i2cclk;
593 for (l = 0; l < STM32_SCLL_MAX; l++) {
594 u32 tscl_l = (l + 1) * prescaler + tsync;
596 if (tscl_l < specs->l_min ||
598 ((tscl_l - af_delay_min - dnf_delay) / 4))) {
602 for (h = 0; h < STM32_SCLH_MAX; h++) {
603 u32 tscl_h = (h + 1) * prescaler + tsync;
604 u32 tscl = tscl_l + tscl_h +
605 setup->rise_time + setup->fall_time;
607 if ((tscl >= clk_min) && (tscl <= clk_max) &&
608 (tscl_h >= specs->h_min) &&
613 clk_error = tscl - i2cbus;
615 clk_error = i2cbus - tscl;
617 if (clk_error < clk_error_prev) {
618 clk_error_prev = clk_error;
622 memcpy(s, v, sizeof(*s));
630 pr_err("%s: no solution at all\n", __func__);
637 static const struct stm32_i2c_spec *get_specs(u32 rate)
641 for (i = 0; i < ARRAY_SIZE(i2c_specs); i++)
642 if (rate <= i2c_specs[i].rate)
643 return &i2c_specs[i];
646 return ERR_PTR(-EINVAL);
649 static int stm32_i2c_compute_timing(struct stm32_i2c_priv *i2c_priv,
650 struct stm32_i2c_setup *setup,
651 struct stm32_i2c_timings *output)
653 const struct stm32_i2c_spec *specs;
654 struct stm32_i2c_timings *v, *_v;
655 struct list_head solutions;
658 specs = get_specs(setup->speed_freq);
659 if (specs == ERR_PTR(-EINVAL)) {
660 pr_err("%s: speed out of bound {%d}\n", __func__,
665 if (setup->rise_time > specs->rise_max ||
666 setup->fall_time > specs->fall_max) {
667 pr_err("%s :timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
669 setup->rise_time, specs->rise_max,
670 setup->fall_time, specs->fall_max);
674 if (setup->dnf > STM32_I2C_DNF_MAX) {
675 pr_err("%s: DNF out of bound %d/%d\n", __func__,
676 setup->dnf, STM32_I2C_DNF_MAX);
680 INIT_LIST_HEAD(&solutions);
681 ret = stm32_i2c_compute_solutions(setup, specs, &solutions);
685 ret = stm32_i2c_choose_solution(setup, specs, &solutions, output);
689 debug("%s: Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
690 __func__, output->presc,
691 output->scldel, output->sdadel,
692 output->scll, output->sclh);
695 /* Release list and memory */
696 list_for_each_entry_safe(v, _v, &solutions, node) {
704 static u32 get_lower_rate(u32 rate)
708 for (i = ARRAY_SIZE(i2c_specs) - 1; i >= 0; i--)
709 if (rate > i2c_specs[i].rate)
710 return i2c_specs[i].rate;
712 return i2c_specs[0].rate;
715 static int stm32_i2c_setup_timing(struct stm32_i2c_priv *i2c_priv,
716 struct stm32_i2c_timings *timing)
718 struct stm32_i2c_setup *setup = i2c_priv->setup;
721 setup->speed_freq = i2c_priv->speed;
722 setup->clock_src = clk_get_rate(&i2c_priv->clk);
724 if (!setup->clock_src) {
725 pr_err("%s: clock rate is 0\n", __func__);
730 ret = stm32_i2c_compute_timing(i2c_priv, setup, timing);
732 debug("%s: failed to compute I2C timings.\n",
734 if (setup->speed_freq > I2C_SPEED_STANDARD_RATE) {
736 get_lower_rate(setup->speed_freq);
737 debug("%s: downgrade I2C Speed Freq to (%i)\n",
738 __func__, setup->speed_freq);
746 pr_err("%s: impossible to compute I2C timings.\n", __func__);
750 debug("%s: I2C Freq(%i), Clk Source(%i)\n", __func__,
751 setup->speed_freq, setup->clock_src);
752 debug("%s: I2C Rise(%i) and Fall(%i) Time\n", __func__,
753 setup->rise_time, setup->fall_time);
754 debug("%s: I2C Analog Filter(%s), DNF(%i)\n", __func__,
755 setup->analog_filter ? "On" : "Off", setup->dnf);
757 i2c_priv->speed = setup->speed_freq;
762 static int stm32_i2c_hw_config(struct stm32_i2c_priv *i2c_priv)
764 struct stm32_i2c_regs *regs = i2c_priv->regs;
765 struct stm32_i2c_timings t;
769 ret = stm32_i2c_setup_timing(i2c_priv, &t);
774 clrbits_le32(®s->cr1, STM32_I2C_CR1_PE);
776 /* Timing settings */
777 timing |= STM32_I2C_TIMINGR_PRESC(t.presc);
778 timing |= STM32_I2C_TIMINGR_SCLDEL(t.scldel);
779 timing |= STM32_I2C_TIMINGR_SDADEL(t.sdadel);
780 timing |= STM32_I2C_TIMINGR_SCLH(t.sclh);
781 timing |= STM32_I2C_TIMINGR_SCLL(t.scll);
782 writel(timing, ®s->timingr);
785 if (i2c_priv->setup->analog_filter)
786 clrbits_le32(®s->cr1, STM32_I2C_CR1_ANFOFF);
788 setbits_le32(®s->cr1, STM32_I2C_CR1_ANFOFF);
789 setbits_le32(®s->cr1, STM32_I2C_CR1_PE);
794 static int stm32_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
796 struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus);
798 if (speed > I2C_SPEED_FAST_PLUS_RATE) {
799 debug("%s: Speed %d not supported\n", __func__, speed);
803 i2c_priv->speed = speed;
805 return stm32_i2c_hw_config(i2c_priv);
808 static int stm32_i2c_probe(struct udevice *dev)
810 struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
811 struct reset_ctl reset_ctl;
815 addr = dev_read_addr(dev);
816 if (addr == FDT_ADDR_T_NONE)
819 i2c_priv->regs = (struct stm32_i2c_regs *)addr;
821 ret = clk_get_by_index(dev, 0, &i2c_priv->clk);
825 ret = clk_enable(&i2c_priv->clk);
829 ret = reset_get_by_index(dev, 0, &reset_ctl);
833 reset_assert(&reset_ctl);
835 reset_deassert(&reset_ctl);
840 clk_disable(&i2c_priv->clk);
842 clk_free(&i2c_priv->clk);
847 static int stm32_ofdata_to_platdata(struct udevice *dev)
849 struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
850 u32 rise_time, fall_time;
852 i2c_priv->setup = (struct stm32_i2c_setup *)dev_get_driver_data(dev);
853 if (!i2c_priv->setup)
856 rise_time = dev_read_u32_default(dev, "i2c-scl-rising-time-ns", 0);
858 i2c_priv->setup->rise_time = rise_time;
860 fall_time = dev_read_u32_default(dev, "i2c-scl-falling-time-ns", 0);
862 i2c_priv->setup->fall_time = fall_time;
867 static const struct dm_i2c_ops stm32_i2c_ops = {
868 .xfer = stm32_i2c_xfer,
869 .set_bus_speed = stm32_i2c_set_bus_speed,
872 static const struct udevice_id stm32_i2c_of_match[] = {
873 { .compatible = "st,stm32f7-i2c", .data = (ulong)&stm32f7_setup },
877 U_BOOT_DRIVER(stm32f7_i2c) = {
878 .name = "stm32f7-i2c",
880 .of_match = stm32_i2c_of_match,
881 .ofdata_to_platdata = stm32_ofdata_to_platdata,
882 .probe = stm32_i2c_probe,
883 .priv_auto_alloc_size = sizeof(struct stm32_i2c_priv),
884 .ops = &stm32_i2c_ops,