2 Copyright (c) 2001,2002 Christer Weinigel <wingel@nano-system.com>
4 National Semiconductor SCx200 ACCESS.bus support
6 Based on i2c-keywest.c which is:
7 Copyright (c) 2001 Benjamin Herrenschmidt <benh@kernel.crashing.org>
8 Copyright (c) 2000 Philip Edelbrock <phil@stimpy.netroedge.com>
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2 of the
13 License, or (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/module.h>
26 #include <linux/errno.h>
27 #include <linux/kernel.h>
28 #include <linux/init.h>
29 #include <linux/i2c.h>
30 #include <linux/smp_lock.h>
31 #include <linux/pci.h>
32 #include <linux/delay.h>
35 #include <linux/scx200.h>
37 #define NAME "scx200_acb"
39 MODULE_AUTHOR("Christer Weinigel <wingel@nano-system.com>");
40 MODULE_DESCRIPTION("NatSemi SCx200 ACCESS.bus Driver");
41 MODULE_LICENSE("GPL");
44 static int base[MAX_DEVICES] = { 0x820, 0x840 };
45 module_param_array(base, int, NULL, 0);
46 MODULE_PARM_DESC(base, "Base addresses for the ACCESS.bus controllers");
48 /* The hardware supports interrupt driven mode too, but I haven't
51 #define POLL_TIMEOUT (HZ)
53 enum scx200_acb_state {
63 static const char *scx200_acb_state_name[] = {
73 /* Physical interface */
74 struct scx200_acb_iface {
75 struct scx200_acb_iface *next;
76 struct i2c_adapter adapter;
80 /* State machine data */
81 enum scx200_acb_state state;
90 /* Register Definitions */
91 #define ACBSDA (iface->base + 0)
92 #define ACBST (iface->base + 1)
93 #define ACBST_SDAST 0x40 /* SDA Status */
94 #define ACBST_BER 0x20
95 #define ACBST_NEGACK 0x10 /* Negative Acknowledge */
96 #define ACBST_STASTR 0x08 /* Stall After Start */
97 #define ACBST_MASTER 0x02
98 #define ACBCST (iface->base + 2)
99 #define ACBCST_BB 0x02
100 #define ACBCTL1 (iface->base + 3)
101 #define ACBCTL1_STASTRE 0x80
102 #define ACBCTL1_NMINTE 0x40
103 #define ACBCTL1_ACK 0x10
104 #define ACBCTL1_STOP 0x02
105 #define ACBCTL1_START 0x01
106 #define ACBADDR (iface->base + 4)
107 #define ACBCTL2 (iface->base + 5)
108 #define ACBCTL2_ENABLE 0x01
110 /************************************************************************/
112 static void scx200_acb_machine(struct scx200_acb_iface *iface, u8 status)
116 dev_dbg(&iface->adapter.dev, "state %s, status = 0x%02x\n",
117 scx200_acb_state_name[iface->state], status);
119 if (status & ACBST_BER) {
120 errmsg = "bus error";
123 if (!(status & ACBST_MASTER)) {
124 errmsg = "not master";
127 if (status & ACBST_NEGACK) {
128 dev_dbg(&iface->adapter.dev, "negative ack in state %s\n",
129 scx200_acb_state_name[iface->state]);
131 iface->state = state_idle;
132 iface->result = -ENXIO;
134 outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1);
135 outb(ACBST_STASTR | ACBST_NEGACK, ACBST);
139 switch (iface->state) {
141 dev_warn(&iface->adapter.dev, "interrupt in idle state\n");
145 /* Do a pointer write first */
146 outb(iface->address_byte & ~1, ACBSDA);
148 iface->state = state_command;
152 outb(iface->command, ACBSDA);
154 if (iface->address_byte & 1)
155 iface->state = state_repeat_start;
157 iface->state = state_write;
160 case state_repeat_start:
161 outb(inb(ACBCTL1) | ACBCTL1_START, ACBCTL1);
165 if (iface->address_byte & 1) {
167 outb(inb(ACBCTL1) | ACBCTL1_ACK, ACBCTL1);
169 outb(inb(ACBCTL1) & ~ACBCTL1_ACK, ACBCTL1);
170 outb(iface->address_byte, ACBSDA);
172 iface->state = state_read;
174 outb(iface->address_byte, ACBSDA);
176 iface->state = state_write;
181 /* Set ACK if receiving the last byte */
183 outb(inb(ACBCTL1) | ACBCTL1_ACK, ACBCTL1);
185 outb(inb(ACBCTL1) & ~ACBCTL1_ACK, ACBCTL1);
187 *iface->ptr++ = inb(ACBSDA);
190 if (iface->len == 0) {
192 iface->state = state_idle;
193 outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1);
199 if (iface->len == 0) {
201 iface->state = state_idle;
202 outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1);
206 outb(*iface->ptr++, ACBSDA);
215 dev_err(&iface->adapter.dev, "%s in state %s\n", errmsg,
216 scx200_acb_state_name[iface->state]);
218 iface->state = state_idle;
219 iface->result = -EIO;
220 iface->needs_reset = 1;
224 static void scx200_acb_poll(struct scx200_acb_iface *iface)
227 unsigned long timeout;
229 timeout = jiffies + POLL_TIMEOUT;
230 while (time_before(jiffies, timeout)) {
232 if ((status & (ACBST_SDAST|ACBST_BER|ACBST_NEGACK)) != 0) {
233 scx200_acb_machine(iface, status);
239 dev_err(&iface->adapter.dev, "timeout in state %s\n",
240 scx200_acb_state_name[iface->state]);
242 iface->state = state_idle;
243 iface->result = -EIO;
244 iface->needs_reset = 1;
246 #endif /* POLLED_MODE */
248 static void scx200_acb_reset(struct scx200_acb_iface *iface)
250 /* Disable the ACCESS.bus device and Configure the SCL
251 frequency: 16 clock cycles */
255 /* Disable slave address */
257 /* Enable the ACCESS.bus device */
258 outb(inb(ACBCTL2) | ACBCTL2_ENABLE, ACBCTL2);
259 /* Free STALL after START */
260 outb(inb(ACBCTL1) & ~(ACBCTL1_STASTRE | ACBCTL1_NMINTE), ACBCTL1);
262 outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1);
263 /* Clear BER, NEGACK and STASTR bits */
264 outb(ACBST_BER | ACBST_NEGACK | ACBST_STASTR, ACBST);
266 outb(inb(ACBCST) | ACBCST_BB, ACBCST);
269 static s32 scx200_acb_smbus_xfer(struct i2c_adapter *adapter,
270 u16 address, unsigned short flags,
271 char rw, u8 command, int size,
272 union i2c_smbus_data *data)
274 struct scx200_acb_iface *iface = i2c_get_adapdata(adapter);
281 case I2C_SMBUS_QUICK:
288 buffer = rw ? &data->byte : &command;
291 case I2C_SMBUS_BYTE_DATA:
293 buffer = &data->byte;
296 case I2C_SMBUS_WORD_DATA:
298 cur_word = cpu_to_le16(data->word);
299 buffer = (u8 *)&cur_word;
302 case I2C_SMBUS_BLOCK_DATA:
303 len = data->block[0];
304 buffer = &data->block[1];
311 dev_dbg(&adapter->dev,
312 "size=%d, address=0x%x, command=0x%x, len=%d, read=%d\n",
313 size, address, command, len, rw);
315 if (!len && rw == I2C_SMBUS_READ) {
316 dev_dbg(&adapter->dev, "zero length read\n");
322 iface->address_byte = (address << 1) | rw;
323 iface->command = command;
326 iface->result = -EINVAL;
327 iface->needs_reset = 0;
329 outb(inb(ACBCTL1) | ACBCTL1_START, ACBCTL1);
331 if (size == I2C_SMBUS_QUICK || size == I2C_SMBUS_BYTE)
332 iface->state = state_quick;
334 iface->state = state_address;
337 while (iface->state != state_idle)
338 scx200_acb_poll(iface);
339 #else /* POLLED_MODE */
340 #error Interrupt driven mode not implemented
341 #endif /* POLLED_MODE */
343 if (iface->needs_reset)
344 scx200_acb_reset(iface);
350 if (rc == 0 && size == I2C_SMBUS_WORD_DATA && rw == I2C_SMBUS_READ)
351 data->word = le16_to_cpu(cur_word);
354 dev_dbg(&adapter->dev, "transfer done, result: %d", rc);
358 for (i = 0; i < len; ++i)
359 printk(" %02x", buffer[i]);
367 static u32 scx200_acb_func(struct i2c_adapter *adapter)
369 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
370 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
371 I2C_FUNC_SMBUS_BLOCK_DATA;
374 /* For now, we only handle combined mode (smbus) */
375 static struct i2c_algorithm scx200_acb_algorithm = {
376 .smbus_xfer = scx200_acb_smbus_xfer,
377 .functionality = scx200_acb_func,
380 static struct scx200_acb_iface *scx200_acb_list;
382 static int scx200_acb_probe(struct scx200_acb_iface *iface)
386 /* Disable the ACCESS.bus device and Configure the SCL
387 frequency: 16 clock cycles */
390 if (inb(ACBCTL2) != 0x70) {
391 pr_debug(NAME ": ACBCTL2 readback failed\n");
395 outb(inb(ACBCTL1) | ACBCTL1_NMINTE, ACBCTL1);
399 pr_debug(NAME ": disabled, but ACBCTL1=0x%02x\n",
404 outb(inb(ACBCTL2) | ACBCTL2_ENABLE, ACBCTL2);
406 outb(inb(ACBCTL1) | ACBCTL1_NMINTE, ACBCTL1);
409 if ((val & ACBCTL1_NMINTE) != ACBCTL1_NMINTE) {
410 pr_debug(NAME ": enabled, but NMINTE won't be set, "
411 "ACBCTL1=0x%02x\n", val);
418 static int __init scx200_acb_create(int base, int index)
420 struct scx200_acb_iface *iface;
421 struct i2c_adapter *adapter;
423 char description[64];
425 iface = kzalloc(sizeof(*iface), GFP_KERNEL);
427 printk(KERN_ERR NAME ": can't allocate memory\n");
432 adapter = &iface->adapter;
433 i2c_set_adapdata(adapter, iface);
434 snprintf(adapter->name, I2C_NAME_SIZE, "SCx200 ACB%d", index);
435 adapter->owner = THIS_MODULE;
436 adapter->id = I2C_HW_SMBUS_SCX200;
437 adapter->algo = &scx200_acb_algorithm;
438 adapter->class = I2C_CLASS_HWMON;
440 init_MUTEX(&iface->sem);
442 snprintf(description, sizeof(description),
443 "NatSemi SCx200 ACCESS.bus [%s]", adapter->name);
444 if (request_region(base, 8, description) == 0) {
445 printk(KERN_ERR NAME ": can't allocate io 0x%x-0x%x\n",
452 rc = scx200_acb_probe(iface);
454 printk(KERN_WARNING NAME ": probe failed\n");
458 scx200_acb_reset(iface);
460 if (i2c_add_adapter(adapter) < 0) {
461 printk(KERN_ERR NAME ": failed to register\n");
467 iface->next = scx200_acb_list;
468 scx200_acb_list = iface;
474 release_region(iface->base, 8);
481 static struct pci_device_id scx200[] = {
482 { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SCx200_BRIDGE) },
483 { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SC1100_BRIDGE) },
487 static int __init scx200_acb_init(void)
492 pr_debug(NAME ": NatSemi SCx200 ACCESS.bus Driver\n");
494 /* Verify that this really is a SCx200 processor */
495 if (pci_dev_present(scx200) == 0)
499 for (i = 0; i < MAX_DEVICES; ++i) {
501 rc = scx200_acb_create(base[i], i);
508 static void __exit scx200_acb_cleanup(void)
510 struct scx200_acb_iface *iface;
513 while ((iface = scx200_acb_list) != NULL) {
514 scx200_acb_list = iface->next;
517 i2c_del_adapter(&iface->adapter);
518 release_region(iface->base, 8);
525 module_init(scx200_acb_init);
526 module_exit(scx200_acb_cleanup);