2 * drivers/i2c/busses/i2c-tegra.c
4 * Copyright (C) 2010 Google, Inc.
5 * Author: Colin Cross <ccross@android.com>
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/platform_device.h>
21 #include <linux/clk.h>
22 #include <linux/err.h>
23 #include <linux/i2c.h>
25 #include <linux/interrupt.h>
26 #include <linux/delay.h>
27 #include <linux/slab.h>
28 #include <linux/i2c-tegra.h>
29 #include <linux/of_i2c.h>
30 #include <linux/module.h>
32 #include <asm/unaligned.h>
36 #define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
37 #define BYTES_PER_FIFO_WORD 4
39 #define I2C_CNFG 0x000
40 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT 12
41 #define I2C_CNFG_PACKET_MODE_EN (1<<10)
42 #define I2C_CNFG_NEW_MASTER_FSM (1<<11)
43 #define I2C_STATUS 0x01C
44 #define I2C_SL_CNFG 0x020
45 #define I2C_SL_CNFG_NACK (1<<1)
46 #define I2C_SL_CNFG_NEWSL (1<<2)
47 #define I2C_SL_ADDR1 0x02c
48 #define I2C_SL_ADDR2 0x030
49 #define I2C_TX_FIFO 0x050
50 #define I2C_RX_FIFO 0x054
51 #define I2C_PACKET_TRANSFER_STATUS 0x058
52 #define I2C_FIFO_CONTROL 0x05c
53 #define I2C_FIFO_CONTROL_TX_FLUSH (1<<1)
54 #define I2C_FIFO_CONTROL_RX_FLUSH (1<<0)
55 #define I2C_FIFO_CONTROL_TX_TRIG_SHIFT 5
56 #define I2C_FIFO_CONTROL_RX_TRIG_SHIFT 2
57 #define I2C_FIFO_STATUS 0x060
58 #define I2C_FIFO_STATUS_TX_MASK 0xF0
59 #define I2C_FIFO_STATUS_TX_SHIFT 4
60 #define I2C_FIFO_STATUS_RX_MASK 0x0F
61 #define I2C_FIFO_STATUS_RX_SHIFT 0
62 #define I2C_INT_MASK 0x064
63 #define I2C_INT_STATUS 0x068
64 #define I2C_INT_PACKET_XFER_COMPLETE (1<<7)
65 #define I2C_INT_ALL_PACKETS_XFER_COMPLETE (1<<6)
66 #define I2C_INT_TX_FIFO_OVERFLOW (1<<5)
67 #define I2C_INT_RX_FIFO_UNDERFLOW (1<<4)
68 #define I2C_INT_NO_ACK (1<<3)
69 #define I2C_INT_ARBITRATION_LOST (1<<2)
70 #define I2C_INT_TX_FIFO_DATA_REQ (1<<1)
71 #define I2C_INT_RX_FIFO_DATA_REQ (1<<0)
72 #define I2C_CLK_DIVISOR 0x06c
74 #define DVC_CTRL_REG1 0x000
75 #define DVC_CTRL_REG1_INTR_EN (1<<10)
76 #define DVC_CTRL_REG2 0x004
77 #define DVC_CTRL_REG3 0x008
78 #define DVC_CTRL_REG3_SW_PROG (1<<26)
79 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN (1<<30)
80 #define DVC_STATUS 0x00c
81 #define DVC_STATUS_I2C_DONE_INTR (1<<30)
83 #define I2C_ERR_NONE 0x00
84 #define I2C_ERR_NO_ACK 0x01
85 #define I2C_ERR_ARBITRATION_LOST 0x02
86 #define I2C_ERR_UNKNOWN_INTERRUPT 0x04
88 #define PACKET_HEADER0_HEADER_SIZE_SHIFT 28
89 #define PACKET_HEADER0_PACKET_ID_SHIFT 16
90 #define PACKET_HEADER0_CONT_ID_SHIFT 12
91 #define PACKET_HEADER0_PROTOCOL_I2C (1<<4)
93 #define I2C_HEADER_HIGHSPEED_MODE (1<<22)
94 #define I2C_HEADER_CONT_ON_NAK (1<<21)
95 #define I2C_HEADER_SEND_START_BYTE (1<<20)
96 #define I2C_HEADER_READ (1<<19)
97 #define I2C_HEADER_10BIT_ADDR (1<<18)
98 #define I2C_HEADER_IE_ENABLE (1<<17)
99 #define I2C_HEADER_REPEAT_START (1<<16)
100 #define I2C_HEADER_MASTER_ADDR_SHIFT 12
101 #define I2C_HEADER_SLAVE_ADDR_SHIFT 1
104 * struct tegra_i2c_dev - per device i2c context
105 * @dev: device reference for power management
106 * @adapter: core i2c layer adapter information
107 * @clk: clock reference for i2c controller
108 * @i2c_clk: clock reference for i2c bus
109 * @iomem: memory resource for registers
110 * @base: ioremapped registers cookie
111 * @cont_id: i2c controller id, used for for packet header
112 * @irq: irq number of transfer complete interrupt
113 * @is_dvc: identifies the DVC i2c controller, has a different register layout
114 * @msg_complete: transfer completion notifier
115 * @msg_err: error code for completed message
116 * @msg_buf: pointer to current message data
117 * @msg_buf_remaining: size of unsent data in the message buffer
118 * @msg_read: identifies read transfers
119 * @bus_clk_rate: current i2c bus clock rate
120 * @is_suspended: prevents i2c controller accesses after suspend is called
122 struct tegra_i2c_dev {
124 struct i2c_adapter adapter;
127 struct resource *iomem;
133 struct completion msg_complete;
136 size_t msg_buf_remaining;
138 unsigned long bus_clk_rate;
142 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg)
144 writel(val, i2c_dev->base + reg);
147 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
149 return readl(i2c_dev->base + reg);
153 * i2c_writel and i2c_readl will offset the register if necessary to talk
154 * to the I2C block inside the DVC block
156 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
160 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
164 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
167 writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
170 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
172 return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
175 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
176 unsigned long reg, int len)
178 writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
181 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
182 unsigned long reg, int len)
184 readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
187 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
189 u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
191 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
194 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
196 u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
198 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
201 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
203 unsigned long timeout = jiffies + HZ;
204 u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL);
205 val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH;
206 i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
208 while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) &
209 (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) {
210 if (time_after(jiffies, timeout)) {
211 dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
219 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
223 u8 *buf = i2c_dev->msg_buf;
224 size_t buf_remaining = i2c_dev->msg_buf_remaining;
225 int words_to_transfer;
227 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
228 rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
229 I2C_FIFO_STATUS_RX_SHIFT;
231 /* Rounds down to not include partial word at the end of buf */
232 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
233 if (words_to_transfer > rx_fifo_avail)
234 words_to_transfer = rx_fifo_avail;
236 i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
238 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
239 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
240 rx_fifo_avail -= words_to_transfer;
243 * If there is a partial word at the end of buf, handle it manually to
244 * prevent overwriting past the end of buf
246 if (rx_fifo_avail > 0 && buf_remaining > 0) {
247 BUG_ON(buf_remaining > 3);
248 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
249 memcpy(buf, &val, buf_remaining);
254 BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0);
255 i2c_dev->msg_buf_remaining = buf_remaining;
256 i2c_dev->msg_buf = buf;
260 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
264 u8 *buf = i2c_dev->msg_buf;
265 size_t buf_remaining = i2c_dev->msg_buf_remaining;
266 int words_to_transfer;
268 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
269 tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
270 I2C_FIFO_STATUS_TX_SHIFT;
272 /* Rounds down to not include partial word at the end of buf */
273 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
275 /* It's very common to have < 4 bytes, so optimize that case. */
276 if (words_to_transfer) {
277 if (words_to_transfer > tx_fifo_avail)
278 words_to_transfer = tx_fifo_avail;
281 * Update state before writing to FIFO. If this casues us
282 * to finish writing all bytes (AKA buf_remaining goes to 0) we
283 * have a potential for an interrupt (PACKET_XFER_COMPLETE is
284 * not maskable). We need to make sure that the isr sees
285 * buf_remaining as 0 and doesn't call us back re-entrantly.
287 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
288 tx_fifo_avail -= words_to_transfer;
289 i2c_dev->msg_buf_remaining = buf_remaining;
290 i2c_dev->msg_buf = buf +
291 words_to_transfer * BYTES_PER_FIFO_WORD;
294 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
296 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
300 * If there is a partial word at the end of buf, handle it manually to
301 * prevent reading past the end of buf, which could cross a page
302 * boundary and fault.
304 if (tx_fifo_avail > 0 && buf_remaining > 0) {
305 BUG_ON(buf_remaining > 3);
306 memcpy(&val, buf, buf_remaining);
308 /* Again update before writing to FIFO to make sure isr sees. */
309 i2c_dev->msg_buf_remaining = 0;
310 i2c_dev->msg_buf = NULL;
313 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
320 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
321 * block. This block is identical to the rest of the I2C blocks, except that
322 * it only supports master mode, it has registers moved around, and it needs
323 * some extra init to get it into I2C mode. The register moves are handled
324 * by i2c_readl and i2c_writel
326 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
329 val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
330 val |= DVC_CTRL_REG3_SW_PROG;
331 val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
332 dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
334 val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
335 val |= DVC_CTRL_REG1_INTR_EN;
336 dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
339 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
344 err = clk_enable(i2c_dev->clk);
346 dev_err(i2c_dev->dev, "Clock enable failed %d\n", err);
350 tegra_periph_reset_assert(i2c_dev->clk);
352 tegra_periph_reset_deassert(i2c_dev->clk);
355 tegra_dvc_init(i2c_dev);
357 val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
358 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
359 i2c_writel(i2c_dev, val, I2C_CNFG);
360 i2c_writel(i2c_dev, 0, I2C_INT_MASK);
361 clk_set_rate(i2c_dev->clk, i2c_dev->bus_clk_rate * 8);
363 if (!i2c_dev->is_dvc) {
364 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
365 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
366 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
367 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
368 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
372 val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
373 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
374 i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
376 if (tegra_i2c_flush_fifos(i2c_dev))
379 clk_disable(i2c_dev->clk);
381 if (i2c_dev->irq_disabled) {
382 i2c_dev->irq_disabled = 0;
383 enable_irq(i2c_dev->irq);
389 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
392 const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
393 struct tegra_i2c_dev *i2c_dev = dev_id;
395 status = i2c_readl(i2c_dev, I2C_INT_STATUS);
398 dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n",
399 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
400 i2c_readl(i2c_dev, I2C_STATUS),
401 i2c_readl(i2c_dev, I2C_CNFG));
402 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
404 if (!i2c_dev->irq_disabled) {
405 disable_irq_nosync(i2c_dev->irq);
406 i2c_dev->irq_disabled = 1;
411 if (unlikely(status & status_err)) {
412 if (status & I2C_INT_NO_ACK)
413 i2c_dev->msg_err |= I2C_ERR_NO_ACK;
414 if (status & I2C_INT_ARBITRATION_LOST)
415 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
419 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
420 if (i2c_dev->msg_buf_remaining)
421 tegra_i2c_empty_rx_fifo(i2c_dev);
426 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
427 if (i2c_dev->msg_buf_remaining)
428 tegra_i2c_fill_tx_fifo(i2c_dev);
430 tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ);
433 i2c_writel(i2c_dev, status, I2C_INT_STATUS);
435 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
437 if (status & I2C_INT_PACKET_XFER_COMPLETE) {
438 BUG_ON(i2c_dev->msg_buf_remaining);
439 complete(&i2c_dev->msg_complete);
443 /* An error occurred, mask all interrupts */
444 tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
445 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
446 I2C_INT_RX_FIFO_DATA_REQ);
447 i2c_writel(i2c_dev, status, I2C_INT_STATUS);
449 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
451 complete(&i2c_dev->msg_complete);
455 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
456 struct i2c_msg *msg, int stop)
462 tegra_i2c_flush_fifos(i2c_dev);
463 i2c_writel(i2c_dev, 0xFF, I2C_INT_STATUS);
468 i2c_dev->msg_buf = msg->buf;
469 i2c_dev->msg_buf_remaining = msg->len;
470 i2c_dev->msg_err = I2C_ERR_NONE;
471 i2c_dev->msg_read = (msg->flags & I2C_M_RD);
472 INIT_COMPLETION(i2c_dev->msg_complete);
474 packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
475 PACKET_HEADER0_PROTOCOL_I2C |
476 (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
477 (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
478 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
480 packet_header = msg->len - 1;
481 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
483 packet_header = msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
484 packet_header |= I2C_HEADER_IE_ENABLE;
486 packet_header |= I2C_HEADER_REPEAT_START;
487 if (msg->flags & I2C_M_TEN)
488 packet_header |= I2C_HEADER_10BIT_ADDR;
489 if (msg->flags & I2C_M_IGNORE_NAK)
490 packet_header |= I2C_HEADER_CONT_ON_NAK;
491 if (msg->flags & I2C_M_RD)
492 packet_header |= I2C_HEADER_READ;
493 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
495 if (!(msg->flags & I2C_M_RD))
496 tegra_i2c_fill_tx_fifo(i2c_dev);
498 int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
499 if (msg->flags & I2C_M_RD)
500 int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
501 else if (i2c_dev->msg_buf_remaining)
502 int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
503 tegra_i2c_unmask_irq(i2c_dev, int_mask);
504 dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
505 i2c_readl(i2c_dev, I2C_INT_MASK));
507 ret = wait_for_completion_timeout(&i2c_dev->msg_complete, TEGRA_I2C_TIMEOUT);
508 tegra_i2c_mask_irq(i2c_dev, int_mask);
510 if (WARN_ON(ret == 0)) {
511 dev_err(i2c_dev->dev, "i2c transfer timed out\n");
513 tegra_i2c_init(i2c_dev);
517 dev_dbg(i2c_dev->dev, "transfer complete: %d %d %d\n",
518 ret, completion_done(&i2c_dev->msg_complete), i2c_dev->msg_err);
520 if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
523 tegra_i2c_init(i2c_dev);
524 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
525 if (msg->flags & I2C_M_IGNORE_NAK)
533 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
536 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
540 if (i2c_dev->is_suspended)
543 ret = clk_enable(i2c_dev->clk);
545 dev_err(i2c_dev->dev, "Clock enable failed %d\n", ret);
549 for (i = 0; i < num; i++) {
550 int stop = (i == (num - 1)) ? 1 : 0;
551 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], stop);
555 clk_disable(i2c_dev->clk);
559 static u32 tegra_i2c_func(struct i2c_adapter *adap)
561 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
564 static const struct i2c_algorithm tegra_i2c_algo = {
565 .master_xfer = tegra_i2c_xfer,
566 .functionality = tegra_i2c_func,
569 static int tegra_i2c_probe(struct platform_device *pdev)
571 struct tegra_i2c_dev *i2c_dev;
572 struct tegra_i2c_platform_data *pdata = pdev->dev.platform_data;
573 struct resource *res;
574 struct resource *iomem;
577 const unsigned int *prop;
582 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
584 dev_err(&pdev->dev, "no mem resource\n");
587 iomem = request_mem_region(res->start, resource_size(res), pdev->name);
589 dev_err(&pdev->dev, "I2C region already claimed\n");
593 base = ioremap(iomem->start, resource_size(iomem));
595 dev_err(&pdev->dev, "Cannot ioremap I2C region\n");
599 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
601 dev_err(&pdev->dev, "no irq resource\n");
607 clk = clk_get(&pdev->dev, NULL);
609 dev_err(&pdev->dev, "missing controller clock");
611 goto err_release_region;
614 i2c_clk = clk_get(&pdev->dev, "i2c");
615 if (IS_ERR(i2c_clk)) {
616 dev_err(&pdev->dev, "missing bus clock");
617 ret = PTR_ERR(i2c_clk);
621 i2c_dev = kzalloc(sizeof(struct tegra_i2c_dev), GFP_KERNEL);
624 goto err_i2c_clk_put;
627 i2c_dev->base = base;
629 i2c_dev->i2c_clk = i2c_clk;
630 i2c_dev->iomem = iomem;
631 i2c_dev->adapter.algo = &tegra_i2c_algo;
633 i2c_dev->cont_id = pdev->id;
634 i2c_dev->dev = &pdev->dev;
636 i2c_dev->bus_clk_rate = 100000; /* default clock rate */
638 i2c_dev->bus_clk_rate = pdata->bus_clk_rate;
640 } else if (i2c_dev->dev->of_node) { /* if there is a device tree node ... */
641 prop = of_get_property(i2c_dev->dev->of_node,
642 "clock-frequency", NULL);
644 i2c_dev->bus_clk_rate = be32_to_cpup(prop);
649 init_completion(&i2c_dev->msg_complete);
651 platform_set_drvdata(pdev, i2c_dev);
653 ret = tegra_i2c_init(i2c_dev);
655 dev_err(&pdev->dev, "Failed to initialize i2c controller");
659 ret = request_irq(i2c_dev->irq, tegra_i2c_isr, 0, pdev->name, i2c_dev);
661 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
665 clk_enable(i2c_dev->i2c_clk);
667 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
668 i2c_dev->adapter.owner = THIS_MODULE;
669 i2c_dev->adapter.class = I2C_CLASS_HWMON;
670 strlcpy(i2c_dev->adapter.name, "Tegra I2C adapter",
671 sizeof(i2c_dev->adapter.name));
672 i2c_dev->adapter.algo = &tegra_i2c_algo;
673 i2c_dev->adapter.dev.parent = &pdev->dev;
674 i2c_dev->adapter.nr = pdev->id;
675 i2c_dev->adapter.dev.of_node = pdev->dev.of_node;
677 ret = i2c_add_numbered_adapter(&i2c_dev->adapter);
679 dev_err(&pdev->dev, "Failed to add I2C adapter\n");
683 of_i2c_register_devices(&i2c_dev->adapter);
687 free_irq(i2c_dev->irq, i2c_dev);
695 release_mem_region(iomem->start, resource_size(iomem));
701 static int tegra_i2c_remove(struct platform_device *pdev)
703 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
704 i2c_del_adapter(&i2c_dev->adapter);
705 free_irq(i2c_dev->irq, i2c_dev);
706 clk_put(i2c_dev->i2c_clk);
707 clk_put(i2c_dev->clk);
708 release_mem_region(i2c_dev->iomem->start,
709 resource_size(i2c_dev->iomem));
710 iounmap(i2c_dev->base);
716 static int tegra_i2c_suspend(struct platform_device *pdev, pm_message_t state)
718 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
720 i2c_lock_adapter(&i2c_dev->adapter);
721 i2c_dev->is_suspended = true;
722 i2c_unlock_adapter(&i2c_dev->adapter);
727 static int tegra_i2c_resume(struct platform_device *pdev)
729 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
732 i2c_lock_adapter(&i2c_dev->adapter);
734 ret = tegra_i2c_init(i2c_dev);
737 i2c_unlock_adapter(&i2c_dev->adapter);
741 i2c_dev->is_suspended = false;
743 i2c_unlock_adapter(&i2c_dev->adapter);
749 #if defined(CONFIG_OF)
750 /* Match table for of_platform binding */
751 static const struct of_device_id tegra_i2c_of_match[] __devinitconst = {
752 { .compatible = "nvidia,tegra20-i2c", },
755 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match);
757 #define tegra_i2c_of_match NULL
760 static struct platform_driver tegra_i2c_driver = {
761 .probe = tegra_i2c_probe,
762 .remove = tegra_i2c_remove,
764 .suspend = tegra_i2c_suspend,
765 .resume = tegra_i2c_resume,
769 .owner = THIS_MODULE,
770 .of_match_table = tegra_i2c_of_match,
774 static int __init tegra_i2c_init_driver(void)
776 return platform_driver_register(&tegra_i2c_driver);
779 static void __exit tegra_i2c_exit_driver(void)
781 platform_driver_unregister(&tegra_i2c_driver);
784 subsys_initcall(tegra_i2c_init_driver);
785 module_exit(tegra_i2c_exit_driver);
787 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
788 MODULE_AUTHOR("Colin Cross");
789 MODULE_LICENSE("GPL v2");