drivers/i2c/busses/i2c-omap.c

   1 /*
   2  * TI OMAP I2C master mode driver
   3  *
   4  * Copyright (C) 2003 MontaVista Software, Inc.
   5  * Copyright (C) 2005 Nokia Corporation
   6  * Copyright (C) 2004 - 2007 Texas Instruments.
   7  *
   8  * Originally written by MontaVista Software, Inc.
   9  * Additional contributions by:
  10  *      Tony Lindgren <tony@atomide.com>
  11  *      Imre Deak <imre.deak@nokia.com>
  12  *      Juha Yrjölä <juha.yrjola@solidboot.com>
  13  *      Syed Khasim <x0khasim@ti.com>
  14  *      Nishant Menon <nm@ti.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License as published by
  18  * the Free Software Foundation; either version 2 of the License, or
  19  * (at your option) any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24  * GNU General Public License for more details.
  25  *
  26  * You should have received a copy of the GNU General Public License
  27  * along with this program; if not, write to the Free Software
  28  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  29  */
  30
  31 #include <linux/module.h>
  32 #include <linux/delay.h>
  33 #include <linux/i2c.h>
  34 #include <linux/err.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/completion.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/clk.h>
  39 #include <linux/io.h>
  40 #include <linux/of.h>
  41 #include <linux/of_i2c.h>
  42 #include <linux/of_device.h>
  43 #include <linux/slab.h>
  44 #include <linux/i2c-omap.h>
  45 #include <linux/pm_runtime.h>
  46
  47 /* I2C controller revisions */
  48 #define OMAP_I2C_OMAP1_REV_2            0x20
  49
  50 /* I2C controller revisions present on specific hardware */
  51 #define OMAP_I2C_REV_ON_2430            0x36
  52 #define OMAP_I2C_REV_ON_3430            0x3C
  53 #define OMAP_I2C_REV_ON_3530_4430       0x40
  54
  55 /* timeout waiting for the controller to respond */
  56 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
  57
  58 /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
  59 enum {
  60         OMAP_I2C_REV_REG = 0,
  61         OMAP_I2C_IE_REG,
  62         OMAP_I2C_STAT_REG,
  63         OMAP_I2C_IV_REG,
  64         OMAP_I2C_WE_REG,
  65         OMAP_I2C_SYSS_REG,
  66         OMAP_I2C_BUF_REG,
  67         OMAP_I2C_CNT_REG,
  68         OMAP_I2C_DATA_REG,
  69         OMAP_I2C_SYSC_REG,
  70         OMAP_I2C_CON_REG,
  71         OMAP_I2C_OA_REG,
  72         OMAP_I2C_SA_REG,
  73         OMAP_I2C_PSC_REG,
  74         OMAP_I2C_SCLL_REG,
  75         OMAP_I2C_SCLH_REG,
  76         OMAP_I2C_SYSTEST_REG,
  77         OMAP_I2C_BUFSTAT_REG,
  78         /* only on OMAP4430 */
  79         OMAP_I2C_IP_V2_REVNB_LO,
  80         OMAP_I2C_IP_V2_REVNB_HI,
  81         OMAP_I2C_IP_V2_IRQSTATUS_RAW,
  82         OMAP_I2C_IP_V2_IRQENABLE_SET,
  83         OMAP_I2C_IP_V2_IRQENABLE_CLR,
  84 };
  85
  86 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
  87 #define OMAP_I2C_IE_XDR         (1 << 14)       /* TX Buffer drain int enable */
  88 #define OMAP_I2C_IE_RDR         (1 << 13)       /* RX Buffer drain int enable */
  89 #define OMAP_I2C_IE_XRDY        (1 << 4)        /* TX data ready int enable */
  90 #define OMAP_I2C_IE_RRDY        (1 << 3)        /* RX data ready int enable */
  91 #define OMAP_I2C_IE_ARDY        (1 << 2)        /* Access ready int enable */
  92 #define OMAP_I2C_IE_NACK        (1 << 1)        /* No ack interrupt enable */
  93 #define OMAP_I2C_IE_AL          (1 << 0)        /* Arbitration lost int ena */
  94
  95 /* I2C Status Register (OMAP_I2C_STAT): */
  96 #define OMAP_I2C_STAT_XDR       (1 << 14)       /* TX Buffer draining */
  97 #define OMAP_I2C_STAT_RDR       (1 << 13)       /* RX Buffer draining */
  98 #define OMAP_I2C_STAT_BB        (1 << 12)       /* Bus busy */
  99 #define OMAP_I2C_STAT_ROVR      (1 << 11)       /* Receive overrun */
 100 #define OMAP_I2C_STAT_XUDF      (1 << 10)       /* Transmit underflow */
 101 #define OMAP_I2C_STAT_AAS       (1 << 9)        /* Address as slave */
 102 #define OMAP_I2C_STAT_AD0       (1 << 8)        /* Address zero */
 103 #define OMAP_I2C_STAT_XRDY      (1 << 4)        /* Transmit data ready */
 104 #define OMAP_I2C_STAT_RRDY      (1 << 3)        /* Receive data ready */
 105 #define OMAP_I2C_STAT_ARDY      (1 << 2)        /* Register access ready */
 106 #define OMAP_I2C_STAT_NACK      (1 << 1)        /* No ack interrupt enable */
 107 #define OMAP_I2C_STAT_AL        (1 << 0)        /* Arbitration lost int ena */
 108
 109 /* I2C WE wakeup enable register */
 110 #define OMAP_I2C_WE_XDR_WE      (1 << 14)       /* TX drain wakup */
 111 #define OMAP_I2C_WE_RDR_WE      (1 << 13)       /* RX drain wakeup */
 112 #define OMAP_I2C_WE_AAS_WE      (1 << 9)        /* Address as slave wakeup*/
 113 #define OMAP_I2C_WE_BF_WE       (1 << 8)        /* Bus free wakeup */
 114 #define OMAP_I2C_WE_STC_WE      (1 << 6)        /* Start condition wakeup */
 115 #define OMAP_I2C_WE_GC_WE       (1 << 5)        /* General call wakeup */
 116 #define OMAP_I2C_WE_DRDY_WE     (1 << 3)        /* TX/RX data ready wakeup */
 117 #define OMAP_I2C_WE_ARDY_WE     (1 << 2)        /* Reg access ready wakeup */
 118 #define OMAP_I2C_WE_NACK_WE     (1 << 1)        /* No acknowledgment wakeup */
 119 #define OMAP_I2C_WE_AL_WE       (1 << 0)        /* Arbitration lost wakeup */
 120
 121 #define OMAP_I2C_WE_ALL         (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
 122                                 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
 123                                 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
 124                                 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
 125                                 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
 126
 127 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
 128 #define OMAP_I2C_BUF_RDMA_EN    (1 << 15)       /* RX DMA channel enable */
 129 #define OMAP_I2C_BUF_RXFIF_CLR  (1 << 14)       /* RX FIFO Clear */
 130 #define OMAP_I2C_BUF_XDMA_EN    (1 << 7)        /* TX DMA channel enable */
 131 #define OMAP_I2C_BUF_TXFIF_CLR  (1 << 6)        /* TX FIFO Clear */
 132
 133 /* I2C Configuration Register (OMAP_I2C_CON): */
 134 #define OMAP_I2C_CON_EN         (1 << 15)       /* I2C module enable */
 135 #define OMAP_I2C_CON_BE         (1 << 14)       /* Big endian mode */
 136 #define OMAP_I2C_CON_OPMODE_HS  (1 << 12)       /* High Speed support */
 137 #define OMAP_I2C_CON_STB        (1 << 11)       /* Start byte mode (master) */
 138 #define OMAP_I2C_CON_MST        (1 << 10)       /* Master/slave mode */
 139 #define OMAP_I2C_CON_TRX        (1 << 9)        /* TX/RX mode (master only) */
 140 #define OMAP_I2C_CON_XA         (1 << 8)        /* Expand address */
 141 #define OMAP_I2C_CON_RM         (1 << 2)        /* Repeat mode (master only) */
 142 #define OMAP_I2C_CON_STP        (1 << 1)        /* Stop cond (master only) */
 143 #define OMAP_I2C_CON_STT        (1 << 0)        /* Start condition (master) */
 144
 145 /* I2C SCL time value when Master */
 146 #define OMAP_I2C_SCLL_HSSCLL    8
 147 #define OMAP_I2C_SCLH_HSSCLH    8
 148
 149 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
 150 #ifdef DEBUG
 151 #define OMAP_I2C_SYSTEST_ST_EN          (1 << 15)       /* System test enable */
 152 #define OMAP_I2C_SYSTEST_FREE           (1 << 14)       /* Free running mode */
 153 #define OMAP_I2C_SYSTEST_TMODE_MASK     (3 << 12)       /* Test mode select */
 154 #define OMAP_I2C_SYSTEST_TMODE_SHIFT    (12)            /* Test mode select */
 155 #define OMAP_I2C_SYSTEST_SCL_I          (1 << 3)        /* SCL line sense in */
 156 #define OMAP_I2C_SYSTEST_SCL_O          (1 << 2)        /* SCL line drive out */
 157 #define OMAP_I2C_SYSTEST_SDA_I          (1 << 1)        /* SDA line sense in */
 158 #define OMAP_I2C_SYSTEST_SDA_O          (1 << 0)        /* SDA line drive out */
 159 #endif
 160
 161 /* OCP_SYSSTATUS bit definitions */
 162 #define SYSS_RESETDONE_MASK             (1 << 0)
 163
 164 /* OCP_SYSCONFIG bit definitions */
 165 #define SYSC_CLOCKACTIVITY_MASK         (0x3 << 8)
 166 #define SYSC_SIDLEMODE_MASK             (0x3 << 3)
 167 #define SYSC_ENAWAKEUP_MASK             (1 << 2)
 168 #define SYSC_SOFTRESET_MASK             (1 << 1)
 169 #define SYSC_AUTOIDLE_MASK              (1 << 0)
 170
 171 #define SYSC_IDLEMODE_SMART             0x2
 172 #define SYSC_CLOCKACTIVITY_FCLK         0x2
 173
 174 /* Errata definitions */
 175 #define I2C_OMAP_ERRATA_I207            (1 << 0)
 176 #define I2C_OMAP3_1P153                 (1 << 1)
 177
 178 struct omap_i2c_dev {
 179         struct device           *dev;
 180         void __iomem            *base;          /* virtual */
 181         int                     irq;
 182         int                     reg_shift;      /* bit shift for I2C register addresses */
 183         struct completion       cmd_complete;
 184         struct resource         *ioarea;
 185         u32                     latency;        /* maximum mpu wkup latency */
 186         void                    (*set_mpu_wkup_lat)(struct device *dev,
 187                                                     long latency);
 188         u32                     speed;          /* Speed of bus in kHz */
 189         u32                     dtrev;          /* extra revision from DT */
 190         u32                     flags;
 191         u16                     cmd_err;
 192         u8                      *buf;
 193         u8                      *regs;
 194         size_t                  buf_len;
 195         struct i2c_adapter      adapter;
 196         u8                      fifo_size;      /* use as flag and value
 197                                                  * fifo_size==0 implies no fifo
 198                                                  * if set, should be trsh+1
 199                                                  */
 200         u8                      rev;
 201         unsigned                b_hw:1;         /* bad h/w fixes */
 202         u16                     iestate;        /* Saved interrupt register */
 203         u16                     pscstate;
 204         u16                     scllstate;
 205         u16                     sclhstate;
 206         u16                     bufstate;
 207         u16                     syscstate;
 208         u16                     westate;
 209         u16                     errata;
 210 };
 211
 212 static const u8 reg_map_ip_v1[] = {
 213         [OMAP_I2C_REV_REG] = 0x00,
 214         [OMAP_I2C_IE_REG] = 0x01,
 215         [OMAP_I2C_STAT_REG] = 0x02,
 216         [OMAP_I2C_IV_REG] = 0x03,
 217         [OMAP_I2C_WE_REG] = 0x03,
 218         [OMAP_I2C_SYSS_REG] = 0x04,
 219         [OMAP_I2C_BUF_REG] = 0x05,
 220         [OMAP_I2C_CNT_REG] = 0x06,
 221         [OMAP_I2C_DATA_REG] = 0x07,
 222         [OMAP_I2C_SYSC_REG] = 0x08,
 223         [OMAP_I2C_CON_REG] = 0x09,
 224         [OMAP_I2C_OA_REG] = 0x0a,
 225         [OMAP_I2C_SA_REG] = 0x0b,
 226         [OMAP_I2C_PSC_REG] = 0x0c,
 227         [OMAP_I2C_SCLL_REG] = 0x0d,
 228         [OMAP_I2C_SCLH_REG] = 0x0e,
 229         [OMAP_I2C_SYSTEST_REG] = 0x0f,
 230         [OMAP_I2C_BUFSTAT_REG] = 0x10,
 231 };
 232
 233 static const u8 reg_map_ip_v2[] = {
 234         [OMAP_I2C_REV_REG] = 0x04,
 235         [OMAP_I2C_IE_REG] = 0x2c,
 236         [OMAP_I2C_STAT_REG] = 0x28,
 237         [OMAP_I2C_IV_REG] = 0x34,
 238         [OMAP_I2C_WE_REG] = 0x34,
 239         [OMAP_I2C_SYSS_REG] = 0x90,
 240         [OMAP_I2C_BUF_REG] = 0x94,
 241         [OMAP_I2C_CNT_REG] = 0x98,
 242         [OMAP_I2C_DATA_REG] = 0x9c,
 243         [OMAP_I2C_SYSC_REG] = 0x10,
 244         [OMAP_I2C_CON_REG] = 0xa4,
 245         [OMAP_I2C_OA_REG] = 0xa8,
 246         [OMAP_I2C_SA_REG] = 0xac,
 247         [OMAP_I2C_PSC_REG] = 0xb0,
 248         [OMAP_I2C_SCLL_REG] = 0xb4,
 249         [OMAP_I2C_SCLH_REG] = 0xb8,
 250         [OMAP_I2C_SYSTEST_REG] = 0xbC,
 251         [OMAP_I2C_BUFSTAT_REG] = 0xc0,
 252         [OMAP_I2C_IP_V2_REVNB_LO] = 0x00,
 253         [OMAP_I2C_IP_V2_REVNB_HI] = 0x04,
 254         [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24,
 255         [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c,
 256         [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30,
 257 };
 258
 259 static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
 260                                       int reg, u16 val)
 261 {
 262         __raw_writew(val, i2c_dev->base +
 263                         (i2c_dev->regs[reg] << i2c_dev->reg_shift));
 264 }
 265
 266 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
 267 {
 268         return __raw_readw(i2c_dev->base +
 269                                 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
 270 }
 271
 272 static void omap_i2c_unidle(struct omap_i2c_dev *dev)
 273 {
 274         if (dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) {
 275                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 276                 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);
 277                 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate);
 278                 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate);
 279                 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, dev->bufstate);
 280                 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, dev->syscstate);
 281                 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
 282                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 283         }
 284
 285         /*
 286          * Don't write to this register if the IE state is 0 as it can
 287          * cause deadlock.
 288          */
 289         if (dev->iestate)
 290                 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
 291 }
 292
 293 static void omap_i2c_idle(struct omap_i2c_dev *dev)
 294 {
 295         u16 iv;
 296
 297         dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
 298         if (dev->dtrev == OMAP_I2C_IP_VERSION_2)
 299                 omap_i2c_write_reg(dev, OMAP_I2C_IP_V2_IRQENABLE_CLR, 1);
 300         else
 301                 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
 302
 303         if (dev->rev < OMAP_I2C_OMAP1_REV_2) {
 304                 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */
 305         } else {
 306                 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);
 307
 308                 /* Flush posted write */
 309                 omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
 310         }
 311 }
 312
 313 static int omap_i2c_init(struct omap_i2c_dev *dev)
 314 {
 315         u16 psc = 0, scll = 0, sclh = 0, buf = 0;
 316         u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
 317         unsigned long fclk_rate = 12000000;
 318         unsigned long timeout;
 319         unsigned long internal_clk = 0;
 320         struct clk *fclk;
 321
 322         if (dev->rev >= OMAP_I2C_OMAP1_REV_2) {
 323                 /* Disable I2C controller before soft reset */
 324                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
 325                         omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) &
 326                                 ~(OMAP_I2C_CON_EN));
 327
 328                 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
 329                 /* For some reason we need to set the EN bit before the
 330                  * reset done bit gets set. */
 331                 timeout = jiffies + OMAP_I2C_TIMEOUT;
 332                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 333                 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
 334                          SYSS_RESETDONE_MASK)) {
 335                         if (time_after(jiffies, timeout)) {
 336                                 dev_warn(dev->dev, "timeout waiting "
 337                                                 "for controller reset\n");
 338                                 return -ETIMEDOUT;
 339                         }
 340                         msleep(1);
 341                 }
 342
 343                 /* SYSC register is cleared by the reset; rewrite it */
 344                 if (dev->rev == OMAP_I2C_REV_ON_2430) {
 345
 346                         omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
 347                                            SYSC_AUTOIDLE_MASK);
 348
 349                 } else if (dev->rev >= OMAP_I2C_REV_ON_3430) {
 350                         dev->syscstate = SYSC_AUTOIDLE_MASK;
 351                         dev->syscstate |= SYSC_ENAWAKEUP_MASK;
 352                         dev->syscstate |= (SYSC_IDLEMODE_SMART <<
 353                               __ffs(SYSC_SIDLEMODE_MASK));
 354                         dev->syscstate |= (SYSC_CLOCKACTIVITY_FCLK <<
 355                               __ffs(SYSC_CLOCKACTIVITY_MASK));
 356
 357                         omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
 358                                                         dev->syscstate);
 359                         /*
 360                          * Enabling all wakup sources to stop I2C freezing on
 361                          * WFI instruction.
 362                          * REVISIT: Some wkup sources might not be needed.
 363                          */
 364                         dev->westate = OMAP_I2C_WE_ALL;
 365                         omap_i2c_write_reg(dev, OMAP_I2C_WE_REG,
 366                                                         dev->westate);
 367                 }
 368         }
 369         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 370
 371         if (dev->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) {
 372                 /*
 373                  * The I2C functional clock is the armxor_ck, so there's
 374                  * no need to get "armxor_ck" separately.  Now, if OMAP2420
 375                  * always returns 12MHz for the functional clock, we can
 376                  * do this bit unconditionally.
 377                  */
 378                 fclk = clk_get(dev->dev, "fck");
 379                 fclk_rate = clk_get_rate(fclk);
 380                 clk_put(fclk);
 381
 382                 /* TRM for 5912 says the I2C clock must be prescaled to be
 383                  * between 7 - 12 MHz. The XOR input clock is typically
 384                  * 12, 13 or 19.2 MHz. So we should have code that produces:
 385                  *
 386                  * XOR MHz      Divider         Prescaler
 387                  * 12           1               0
 388                  * 13           2               1
 389                  * 19.2         2               1
 390                  */
 391                 if (fclk_rate > 12000000)
 392                         psc = fclk_rate / 12000000;
 393         }
 394
 395         if (!(dev->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) {
 396
 397                 /*
 398                  * HSI2C controller internal clk rate should be 19.2 Mhz for
 399                  * HS and for all modes on 2430. On 34xx we can use lower rate
 400                  * to get longer filter period for better noise suppression.
 401                  * The filter is iclk (fclk for HS) period.
 402                  */
 403                 if (dev->speed > 400 ||
 404                                dev->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK)
 405                         internal_clk = 19200;
 406                 else if (dev->speed > 100)
 407                         internal_clk = 9600;
 408                 else
 409                         internal_clk = 4000;
 410                 fclk = clk_get(dev->dev, "fck");
 411                 fclk_rate = clk_get_rate(fclk) / 1000;
 412                 clk_put(fclk);
 413
 414                 /* Compute prescaler divisor */
 415                 psc = fclk_rate / internal_clk;
 416                 psc = psc - 1;
 417
 418                 /* If configured for High Speed */
 419                 if (dev->speed > 400) {
 420                         unsigned long scl;
 421
 422                         /* For first phase of HS mode */
 423                         scl = internal_clk / 400;
 424                         fsscll = scl - (scl / 3) - 7;
 425                         fssclh = (scl / 3) - 5;
 426
 427                         /* For second phase of HS mode */
 428                         scl = fclk_rate / dev->speed;
 429                         hsscll = scl - (scl / 3) - 7;
 430                         hssclh = (scl / 3) - 5;
 431                 } else if (dev->speed > 100) {
 432                         unsigned long scl;
 433
 434                         /* Fast mode */
 435                         scl = internal_clk / dev->speed;
 436                         fsscll = scl - (scl / 3) - 7;
 437                         fssclh = (scl / 3) - 5;
 438                 } else {
 439                         /* Standard mode */
 440                         fsscll = internal_clk / (dev->speed * 2) - 7;
 441                         fssclh = internal_clk / (dev->speed * 2) - 5;
 442                 }
 443                 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
 444                 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
 445         } else {
 446                 /* Program desired operating rate */
 447                 fclk_rate /= (psc + 1) * 1000;
 448                 if (psc > 2)
 449                         psc = 2;
 450                 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
 451                 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
 452         }
 453
 454         /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
 455         omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
 456
 457         /* SCL low and high time values */
 458         omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
 459         omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
 460
 461         if (dev->fifo_size) {
 462                 /* Note: setup required fifo size - 1. RTRSH and XTRSH */
 463                 buf = (dev->fifo_size - 1) << 8 | OMAP_I2C_BUF_RXFIF_CLR |
 464                         (dev->fifo_size - 1) | OMAP_I2C_BUF_TXFIF_CLR;
 465                 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);
 466         }
 467
 468         /* Take the I2C module out of reset: */
 469         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 470
 471         dev->errata = 0;
 472
 473         if (dev->flags & OMAP_I2C_FLAG_APPLY_ERRATA_I207)
 474                 dev->errata |= I2C_OMAP_ERRATA_I207;
 475
 476         /* Enable interrupts */
 477         dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
 478                         OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
 479                         OMAP_I2C_IE_AL)  | ((dev->fifo_size) ?
 480                                 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
 481         omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
 482         if (dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) {
 483                 dev->pscstate = psc;
 484                 dev->scllstate = scll;
 485                 dev->sclhstate = sclh;
 486                 dev->bufstate = buf;
 487         }
 488         return 0;
 489 }
 490
 491 /*
 492  * Waiting on Bus Busy
 493  */
 494 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
 495 {
 496         unsigned long timeout;
 497
 498         timeout = jiffies + OMAP_I2C_TIMEOUT;
 499         while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
 500                 if (time_after(jiffies, timeout)) {
 501                         dev_warn(dev->dev, "timeout waiting for bus ready\n");
 502                         return -ETIMEDOUT;
 503                 }
 504                 msleep(1);
 505         }
 506
 507         return 0;
 508 }
 509
 510 /*
 511  * Low level master read/write transaction.
 512  */
 513 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
 514                              struct i2c_msg *msg, int stop)
 515 {
 516         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
 517         int r;
 518         u16 w;
 519
 520         dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
 521                 msg->addr, msg->len, msg->flags, stop);
 522
 523         if (msg->len == 0)
 524                 return -EINVAL;
 525
 526         omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
 527
 528         /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
 529         dev->buf = msg->buf;
 530         dev->buf_len = msg->len;
 531
 532         omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
 533
 534         /* Clear the FIFO Buffers */
 535         w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
 536         w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
 537         omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
 538
 539         init_completion(&dev->cmd_complete);
 540         dev->cmd_err = 0;
 541
 542         w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
 543
 544         /* High speed configuration */
 545         if (dev->speed > 400)
 546                 w |= OMAP_I2C_CON_OPMODE_HS;
 547
 548         if (msg->flags & I2C_M_TEN)
 549                 w |= OMAP_I2C_CON_XA;
 550         if (!(msg->flags & I2C_M_RD))
 551                 w |= OMAP_I2C_CON_TRX;
 552
 553         if (!dev->b_hw && stop)
 554                 w |= OMAP_I2C_CON_STP;
 555
 556         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 557
 558         /*
 559          * Don't write stt and stp together on some hardware.
 560          */
 561         if (dev->b_hw && stop) {
 562                 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
 563                 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
 564                 while (con & OMAP_I2C_CON_STT) {
 565                         con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
 566
 567                         /* Let the user know if i2c is in a bad state */
 568                         if (time_after(jiffies, delay)) {
 569                                 dev_err(dev->dev, "controller timed out "
 570                                 "waiting for start condition to finish\n");
 571                                 return -ETIMEDOUT;
 572                         }
 573                         cpu_relax();
 574                 }
 575
 576                 w |= OMAP_I2C_CON_STP;
 577                 w &= ~OMAP_I2C_CON_STT;
 578                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 579         }
 580
 581         /*
 582          * REVISIT: We should abort the transfer on signals, but the bus goes
 583          * into arbitration and we're currently unable to recover from it.
 584          */
 585         r = wait_for_completion_timeout(&dev->cmd_complete,
 586                                         OMAP_I2C_TIMEOUT);
 587         dev->buf_len = 0;
 588         if (r < 0)
 589                 return r;
 590         if (r == 0) {
 591                 dev_err(dev->dev, "controller timed out\n");
 592                 omap_i2c_init(dev);
 593                 return -ETIMEDOUT;
 594         }
 595
 596         if (likely(!dev->cmd_err))
 597                 return 0;
 598
 599         /* We have an error */
 600         if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
 601                             OMAP_I2C_STAT_XUDF)) {
 602                 omap_i2c_init(dev);
 603                 return -EIO;
 604         }
 605
 606         if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
 607                 if (msg->flags & I2C_M_IGNORE_NAK)
 608                         return 0;
 609                 if (stop) {
 610                         w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
 611                         w |= OMAP_I2C_CON_STP;
 612                         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 613                 }
 614                 return -EREMOTEIO;
 615         }
 616         return -EIO;
 617 }
 618
 619
 620 /*
 621  * Prepare controller for a transaction and call omap_i2c_xfer_msg
 622  * to do the work during IRQ processing.
 623  */
 624 static int
 625 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 626 {
 627         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
 628         int i;
 629         int r;
 630
 631         pm_runtime_get_sync(dev->dev);
 632
 633         r = omap_i2c_wait_for_bb(dev);
 634         if (r < 0)
 635                 goto out;
 636
 637         if (dev->set_mpu_wkup_lat != NULL)
 638                 dev->set_mpu_wkup_lat(dev->dev, dev->latency);
 639
 640         for (i = 0; i < num; i++) {
 641                 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
 642                 if (r != 0)
 643                         break;
 644         }
 645
 646         if (dev->set_mpu_wkup_lat != NULL)
 647                 dev->set_mpu_wkup_lat(dev->dev, -1);
 648
 649         if (r == 0)
 650                 r = num;
 651
 652         omap_i2c_wait_for_bb(dev);
 653 out:
 654         pm_runtime_put(dev->dev);
 655         return r;
 656 }
 657
 658 static u32
 659 omap_i2c_func(struct i2c_adapter *adap)
 660 {
 661         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
 662 }
 663
 664 static inline void
 665 omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
 666 {
 667         dev->cmd_err |= err;
 668         complete(&dev->cmd_complete);
 669 }
 670
 671 static inline void
 672 omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
 673 {
 674         omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
 675 }
 676
 677 static inline void i2c_omap_errata_i207(struct omap_i2c_dev *dev, u16 stat)
 678 {
 679         /*
 680          * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8)
 681          * Not applicable for OMAP4.
 682          * Under certain rare conditions, RDR could be set again
 683          * when the bus is busy, then ignore the interrupt and
 684          * clear the interrupt.
 685          */
 686         if (stat & OMAP_I2C_STAT_RDR) {
 687                 /* Step 1: If RDR is set, clear it */
 688                 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
 689
 690                 /* Step 2: */
 691                 if (!(omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
 692                                                 & OMAP_I2C_STAT_BB)) {
 693
 694                         /* Step 3: */
 695                         if (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
 696                                                 & OMAP_I2C_STAT_RDR) {
 697                                 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
 698                                 dev_dbg(dev->dev, "RDR when bus is busy.\n");
 699                         }
 700
 701                 }
 702         }
 703 }
 704
 705 /* rev1 devices are apparently only on some 15xx */
 706 #ifdef CONFIG_ARCH_OMAP15XX
 707
 708 static irqreturn_t
 709 omap_i2c_omap1_isr(int this_irq, void *dev_id)
 710 {
 711         struct omap_i2c_dev *dev = dev_id;
 712         u16 iv, w;
 713
 714         if (pm_runtime_suspended(dev->dev))
 715                 return IRQ_NONE;
 716
 717         iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
 718         switch (iv) {
 719         case 0x00:      /* None */
 720                 break;
 721         case 0x01:      /* Arbitration lost */
 722                 dev_err(dev->dev, "Arbitration lost\n");
 723                 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
 724                 break;
 725         case 0x02:      /* No acknowledgement */
 726                 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
 727                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
 728                 break;
 729         case 0x03:      /* Register access ready */
 730                 omap_i2c_complete_cmd(dev, 0);
 731                 break;
 732         case 0x04:      /* Receive data ready */
 733                 if (dev->buf_len) {
 734                         w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
 735                         *dev->buf++ = w;
 736                         dev->buf_len--;
 737                         if (dev->buf_len) {
 738                                 *dev->buf++ = w >> 8;
 739                                 dev->buf_len--;
 740                         }
 741                 } else
 742                         dev_err(dev->dev, "RRDY IRQ while no data requested\n");
 743                 break;
 744         case 0x05:      /* Transmit data ready */
 745                 if (dev->buf_len) {
 746                         w = *dev->buf++;
 747                         dev->buf_len--;
 748                         if (dev->buf_len) {
 749                                 w |= *dev->buf++ << 8;
 750                                 dev->buf_len--;
 751                         }
 752                         omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
 753                 } else
 754                         dev_err(dev->dev, "XRDY IRQ while no data to send\n");
 755                 break;
 756         default:
 757                 return IRQ_NONE;
 758         }
 759
 760         return IRQ_HANDLED;
 761 }
 762 #else
 763 #define omap_i2c_omap1_isr              NULL
 764 #endif
 765
 766 /*
 767  * OMAP3430 Errata 1.153: When an XRDY/XDR is hit, wait for XUDF before writing
 768  * data to DATA_REG. Otherwise some data bytes can be lost while transferring
 769  * them from the memory to the I2C interface.
 770  */
 771 static int errata_omap3_1p153(struct omap_i2c_dev *dev, u16 *stat, int *err)
 772 {
 773         unsigned long timeout = 10000;
 774
 775         while (--timeout && !(*stat & OMAP_I2C_STAT_XUDF)) {
 776                 if (*stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
 777                         omap_i2c_ack_stat(dev, *stat & (OMAP_I2C_STAT_XRDY |
 778                                                         OMAP_I2C_STAT_XDR));
 779                         *err |= OMAP_I2C_STAT_XUDF;
 780                         return -ETIMEDOUT;
 781                 }
 782
 783                 cpu_relax();
 784                 *stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
 785         }
 786
 787         if (!timeout) {
 788                 dev_err(dev->dev, "timeout waiting on XUDF bit\n");
 789                 return 0;
 790         }
 791
 792         return 0;
 793 }
 794
 795 static irqreturn_t
 796 omap_i2c_isr(int this_irq, void *dev_id)
 797 {
 798         struct omap_i2c_dev *dev = dev_id;
 799         u16 bits;
 800         u16 stat, w;
 801         int err, count = 0;
 802
 803         if (pm_runtime_suspended(dev->dev))
 804                 return IRQ_NONE;
 805
 806         bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
 807         while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
 808                 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
 809                 if (count++ == 100) {
 810                         dev_warn(dev->dev, "Too much work in one IRQ\n");
 811                         break;
 812                 }
 813
 814                 err = 0;
 815 complete:
 816                 /*
 817                  * Ack the stat in one go, but [R/X]DR and [R/X]RDY should be
 818                  * acked after the data operation is complete.
 819                  * Ref: TRM SWPU114Q Figure 18-31
 820                  */
 821                 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat &
 822                                 ~(OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
 823                                 OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
 824
 825                 if (stat & OMAP_I2C_STAT_NACK)
 826                         err |= OMAP_I2C_STAT_NACK;
 827
 828                 if (stat & OMAP_I2C_STAT_AL) {
 829                         dev_err(dev->dev, "Arbitration lost\n");
 830                         err |= OMAP_I2C_STAT_AL;
 831                 }
 832                 /*
 833                  * ProDB0017052: Clear ARDY bit twice
 834                  */
 835                 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
 836                                         OMAP_I2C_STAT_AL)) {
 837                         omap_i2c_ack_stat(dev, stat &
 838                                 (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
 839                                 OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR |
 840                                 OMAP_I2C_STAT_ARDY));
 841                         omap_i2c_complete_cmd(dev, err);
 842                         return IRQ_HANDLED;
 843                 }
 844                 if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
 845                         u8 num_bytes = 1;
 846
 847                         if (dev->errata & I2C_OMAP_ERRATA_I207)
 848                                 i2c_omap_errata_i207(dev, stat);
 849
 850                         if (dev->fifo_size) {
 851                                 if (stat & OMAP_I2C_STAT_RRDY)
 852                                         num_bytes = dev->fifo_size;
 853                                 else    /* read RXSTAT on RDR interrupt */
 854                                         num_bytes = (omap_i2c_read_reg(dev,
 855                                                         OMAP_I2C_BUFSTAT_REG)
 856                                                         >> 8) & 0x3F;
 857                         }
 858                         while (num_bytes) {
 859                                 num_bytes--;
 860                                 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
 861                                 if (dev->buf_len) {
 862                                         *dev->buf++ = w;
 863                                         dev->buf_len--;
 864                                         /*
 865                                          * Data reg in 2430, omap3 and
 866                                          * omap4 is 8 bit wide
 867                                          */
 868                                         if (dev->flags &
 869                                                  OMAP_I2C_FLAG_16BIT_DATA_REG) {
 870                                                 if (dev->buf_len) {
 871                                                         *dev->buf++ = w >> 8;
 872                                                         dev->buf_len--;
 873                                                 }
 874                                         }
 875                                 } else {
 876                                         if (stat & OMAP_I2C_STAT_RRDY)
 877                                                 dev_err(dev->dev,
 878                                                         "RRDY IRQ while no data"
 879                                                                 " requested\n");
 880                                         if (stat & OMAP_I2C_STAT_RDR)
 881                                                 dev_err(dev->dev,
 882                                                         "RDR IRQ while no data"
 883                                                                 " requested\n");
 884                                         break;
 885                                 }
 886                         }
 887                         omap_i2c_ack_stat(dev,
 888                                 stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
 889                         continue;
 890                 }
 891                 if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
 892                         u8 num_bytes = 1;
 893                         if (dev->fifo_size) {
 894                                 if (stat & OMAP_I2C_STAT_XRDY)
 895                                         num_bytes = dev->fifo_size;
 896                                 else    /* read TXSTAT on XDR interrupt */
 897                                         num_bytes = omap_i2c_read_reg(dev,
 898                                                         OMAP_I2C_BUFSTAT_REG)
 899                                                         & 0x3F;
 900                         }
 901                         while (num_bytes) {
 902                                 num_bytes--;
 903                                 w = 0;
 904                                 if (dev->buf_len) {
 905                                         w = *dev->buf++;
 906                                         dev->buf_len--;
 907                                         /*
 908                                          * Data reg in 2430, omap3 and
 909                                          * omap4 is 8 bit wide
 910                                          */
 911                                         if (dev->flags &
 912                                                  OMAP_I2C_FLAG_16BIT_DATA_REG) {
 913                                                 if (dev->buf_len) {
 914                                                         w |= *dev->buf++ << 8;
 915                                                         dev->buf_len--;
 916                                                 }
 917                                         }
 918                                 } else {
 919                                         if (stat & OMAP_I2C_STAT_XRDY)
 920                                                 dev_err(dev->dev,
 921                                                         "XRDY IRQ while no "
 922                                                         "data to send\n");
 923                                         if (stat & OMAP_I2C_STAT_XDR)
 924                                                 dev_err(dev->dev,
 925                                                         "XDR IRQ while no "
 926                                                         "data to send\n");
 927                                         break;
 928                                 }
 929
 930                                 if ((dev->errata & I2C_OMAP3_1P153) &&
 931                                     errata_omap3_1p153(dev, &stat, &err))
 932                                         goto complete;
 933
 934                                 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
 935                         }
 936                         omap_i2c_ack_stat(dev,
 937                                 stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
 938                         continue;
 939                 }
 940                 if (stat & OMAP_I2C_STAT_ROVR) {
 941                         dev_err(dev->dev, "Receive overrun\n");
 942                         dev->cmd_err |= OMAP_I2C_STAT_ROVR;
 943                 }
 944                 if (stat & OMAP_I2C_STAT_XUDF) {
 945                         dev_err(dev->dev, "Transmit underflow\n");
 946                         dev->cmd_err |= OMAP_I2C_STAT_XUDF;
 947                 }
 948         }
 949
 950         return count ? IRQ_HANDLED : IRQ_NONE;
 951 }
 952
 953 static const struct i2c_algorithm omap_i2c_algo = {
 954         .master_xfer    = omap_i2c_xfer,
 955         .functionality  = omap_i2c_func,
 956 };
 957
 958 #ifdef CONFIG_OF
 959 static struct omap_i2c_bus_platform_data omap3_pdata = {
 960         .rev = OMAP_I2C_IP_VERSION_1,
 961         .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
 962                  OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
 963                  OMAP_I2C_FLAG_BUS_SHIFT_2,
 964 };
 965
 966 static struct omap_i2c_bus_platform_data omap4_pdata = {
 967         .rev = OMAP_I2C_IP_VERSION_2,
 968 };
 969
 970 static const struct of_device_id omap_i2c_of_match[] = {
 971         {
 972                 .compatible = "ti,omap4-i2c",
 973                 .data = &omap4_pdata,
 974         },
 975         {
 976                 .compatible = "ti,omap3-i2c",
 977                 .data = &omap3_pdata,
 978         },
 979         { },
 980 };
 981 MODULE_DEVICE_TABLE(of, omap_i2c_of_match);
 982 #endif
 983
 984 static int __devinit
 985 omap_i2c_probe(struct platform_device *pdev)
 986 {
 987         struct omap_i2c_dev     *dev;
 988         struct i2c_adapter      *adap;
 989         struct resource         *mem, *irq, *ioarea;
 990         struct omap_i2c_bus_platform_data *pdata = pdev->dev.platform_data;
 991         struct device_node      *node = pdev->dev.of_node;
 992         const struct of_device_id *match;
 993         irq_handler_t isr;
 994         int r;
 995
 996         /* NOTE: driver uses the static register mapping */
 997         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 998         if (!mem) {
 999                 dev_err(&pdev->dev, "no mem resource?\n");
1000                 return -ENODEV;
1001         }
1002         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1003         if (!irq) {
1004                 dev_err(&pdev->dev, "no irq resource?\n");
1005                 return -ENODEV;
1006         }
1007
1008         ioarea = request_mem_region(mem->start, resource_size(mem),
1009                         pdev->name);
1010         if (!ioarea) {
1011                 dev_err(&pdev->dev, "I2C region already claimed\n");
1012                 return -EBUSY;
1013         }
1014
1015         dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
1016         if (!dev) {
1017                 r = -ENOMEM;
1018                 goto err_release_region;
1019         }
1020
1021         match = of_match_device(omap_i2c_of_match, &pdev->dev);
1022         if (match) {
1023                 u32 freq = 100000; /* default to 100000 Hz */
1024
1025                 pdata = match->data;
1026                 dev->dtrev = pdata->rev;
1027                 dev->flags = pdata->flags;
1028
1029                 of_property_read_u32(node, "clock-frequency", &freq);
1030                 /* convert DT freq value in Hz into kHz for speed */
1031                 dev->speed = freq / 1000;
1032         } else if (pdata != NULL) {
1033                 dev->speed = pdata->clkrate;
1034                 dev->flags = pdata->flags;
1035                 dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
1036                 dev->dtrev = pdata->rev;
1037         }
1038
1039         dev->dev = &pdev->dev;
1040         dev->irq = irq->start;
1041         dev->base = ioremap(mem->start, resource_size(mem));
1042         if (!dev->base) {
1043                 r = -ENOMEM;
1044                 goto err_free_mem;
1045         }
1046
1047         platform_set_drvdata(pdev, dev);
1048
1049         dev->reg_shift = (dev->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3;
1050
1051         if (dev->dtrev == OMAP_I2C_IP_VERSION_2)
1052                 dev->regs = (u8 *)reg_map_ip_v2;
1053         else
1054                 dev->regs = (u8 *)reg_map_ip_v1;
1055
1056         pm_runtime_enable(dev->dev);
1057         pm_runtime_get_sync(dev->dev);
1058
1059         dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
1060
1061         if (dev->rev <= OMAP_I2C_REV_ON_3430)
1062                 dev->errata |= I2C_OMAP3_1P153;
1063
1064         if (!(dev->flags & OMAP_I2C_FLAG_NO_FIFO)) {
1065                 u16 s;
1066
1067                 /* Set up the fifo size - Get total size */
1068                 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
1069                 dev->fifo_size = 0x8 << s;
1070
1071                 /*
1072                  * Set up notification threshold as half the total available
1073                  * size. This is to ensure that we can handle the status on int
1074                  * call back latencies.
1075                  */
1076
1077                 dev->fifo_size = (dev->fifo_size / 2);
1078
1079                 if (dev->rev >= OMAP_I2C_REV_ON_3530_4430)
1080                         dev->b_hw = 0; /* Disable hardware fixes */
1081                 else
1082                         dev->b_hw = 1; /* Enable hardware fixes */
1083
1084                 /* calculate wakeup latency constraint for MPU */
1085                 if (dev->set_mpu_wkup_lat != NULL)
1086                         dev->latency = (1000000 * dev->fifo_size) /
1087                                        (1000 * dev->speed / 8);
1088         }
1089
1090         /* reset ASAP, clearing any IRQs */
1091         omap_i2c_init(dev);
1092
1093         isr = (dev->rev < OMAP_I2C_OMAP1_REV_2) ? omap_i2c_omap1_isr :
1094                                                                    omap_i2c_isr;
1095         r = request_irq(dev->irq, isr, 0, pdev->name, dev);
1096
1097         if (r) {
1098                 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
1099                 goto err_unuse_clocks;
1100         }
1101
1102         dev_info(dev->dev, "bus %d rev%d.%d.%d at %d kHz\n", pdev->id,
1103                  dev->dtrev, dev->rev >> 4, dev->rev & 0xf, dev->speed);
1104
1105         pm_runtime_put(dev->dev);
1106
1107         adap = &dev->adapter;
1108         i2c_set_adapdata(adap, dev);
1109         adap->owner = THIS_MODULE;
1110         adap->class = I2C_CLASS_HWMON;
1111         strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
1112         adap->algo = &omap_i2c_algo;
1113         adap->dev.parent = &pdev->dev;
1114         adap->dev.of_node = pdev->dev.of_node;
1115
1116         /* i2c device drivers may be active on return from add_adapter() */
1117         adap->nr = pdev->id;
1118         r = i2c_add_numbered_adapter(adap);
1119         if (r) {
1120                 dev_err(dev->dev, "failure adding adapter\n");
1121                 goto err_free_irq;
1122         }
1123
1124         of_i2c_register_devices(adap);
1125
1126         return 0;
1127
1128 err_free_irq:
1129         free_irq(dev->irq, dev);
1130 err_unuse_clocks:
1131         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
1132         pm_runtime_put(dev->dev);
1133         iounmap(dev->base);
1134 err_free_mem:
1135         platform_set_drvdata(pdev, NULL);
1136         kfree(dev);
1137 err_release_region:
1138         release_mem_region(mem->start, resource_size(mem));
1139
1140         return r;
1141 }
1142
1143 static int
1144 omap_i2c_remove(struct platform_device *pdev)
1145 {
1146         struct omap_i2c_dev     *dev = platform_get_drvdata(pdev);
1147         struct resource         *mem;
1148
1149         platform_set_drvdata(pdev, NULL);
1150
1151         free_irq(dev->irq, dev);
1152         i2c_del_adapter(&dev->adapter);
1153         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
1154         iounmap(dev->base);
1155         kfree(dev);
1156         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1157         release_mem_region(mem->start, resource_size(mem));
1158         return 0;
1159 }
1160
1161 #ifdef CONFIG_PM_RUNTIME
1162 static int omap_i2c_runtime_suspend(struct device *dev)
1163 {
1164         struct platform_device *pdev = to_platform_device(dev);
1165         struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
1166
1167         omap_i2c_idle(_dev);
1168
1169         return 0;
1170 }
1171
1172 static int omap_i2c_runtime_resume(struct device *dev)
1173 {
1174         struct platform_device *pdev = to_platform_device(dev);
1175         struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
1176
1177         omap_i2c_unidle(_dev);
1178
1179         return 0;
1180 }
1181
1182 static struct dev_pm_ops omap_i2c_pm_ops = {
1183         .runtime_suspend = omap_i2c_runtime_suspend,
1184         .runtime_resume = omap_i2c_runtime_resume,
1185 };
1186 #define OMAP_I2C_PM_OPS (&omap_i2c_pm_ops)
1187 #else
1188 #define OMAP_I2C_PM_OPS NULL
1189 #endif
1190
1191 static struct platform_driver omap_i2c_driver = {
1192         .probe          = omap_i2c_probe,
1193         .remove         = omap_i2c_remove,
1194         .driver         = {
1195                 .name   = "omap_i2c",
1196                 .owner  = THIS_MODULE,
1197                 .pm     = OMAP_I2C_PM_OPS,
1198                 .of_match_table = of_match_ptr(omap_i2c_of_match),
1199         },
1200 };
1201
1202 /* I2C may be needed to bring up other drivers */
1203 static int __init
1204 omap_i2c_init_driver(void)
1205 {
1206         return platform_driver_register(&omap_i2c_driver);
1207 }
1208 subsys_initcall(omap_i2c_init_driver);
1209
1210 static void __exit omap_i2c_exit_driver(void)
1211 {
1212         platform_driver_unregister(&omap_i2c_driver);
1213 }
1214 module_exit(omap_i2c_exit_driver);
1215
1216 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
1217 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
1218 MODULE_LICENSE("GPL");
1219 MODULE_ALIAS("platform:omap_i2c");