2 * TI OMAP I2C master mode driver
4 * Copyright (C) 2003 MontaVista Software, Inc.
5 * Copyright (C) 2005 Nokia Corporation
6 * Copyright (C) 2004 - 2007 Texas Instruments.
8 * Originally written by MontaVista Software, Inc.
9 * Additional contributions by:
10 * Tony Lindgren <tony@atomide.com>
11 * Imre Deak <imre.deak@nokia.com>
12 * Juha Yrjölä <juha.yrjola@solidboot.com>
13 * Syed Khasim <x0khasim@ti.com>
14 * Nishant Menon <nm@ti.com>
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
31 #include <linux/module.h>
32 #include <linux/delay.h>
33 #include <linux/i2c.h>
34 #include <linux/err.h>
35 #include <linux/interrupt.h>
36 #include <linux/completion.h>
37 #include <linux/platform_device.h>
38 #include <linux/clk.h>
41 /* timeout waiting for the controller to respond */
42 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
44 #define OMAP_I2C_REV_REG 0x00
45 #define OMAP_I2C_IE_REG 0x04
46 #define OMAP_I2C_STAT_REG 0x08
47 #define OMAP_I2C_IV_REG 0x0c
48 #define OMAP_I2C_SYSS_REG 0x10
49 #define OMAP_I2C_BUF_REG 0x14
50 #define OMAP_I2C_CNT_REG 0x18
51 #define OMAP_I2C_DATA_REG 0x1c
52 #define OMAP_I2C_SYSC_REG 0x20
53 #define OMAP_I2C_CON_REG 0x24
54 #define OMAP_I2C_OA_REG 0x28
55 #define OMAP_I2C_SA_REG 0x2c
56 #define OMAP_I2C_PSC_REG 0x30
57 #define OMAP_I2C_SCLL_REG 0x34
58 #define OMAP_I2C_SCLH_REG 0x38
59 #define OMAP_I2C_SYSTEST_REG 0x3c
60 #define OMAP_I2C_BUFSTAT_REG 0x40
62 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
63 #define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
64 #define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
65 #define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
66 #define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
67 #define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
68 #define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
69 #define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
71 /* I2C Status Register (OMAP_I2C_STAT): */
72 #define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
73 #define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
74 #define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
75 #define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
76 #define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
77 #define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
78 #define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */
79 #define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
80 #define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
81 #define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
82 #define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
83 #define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
85 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
86 #define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
87 #define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
88 #define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
89 #define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
91 /* I2C Configuration Register (OMAP_I2C_CON): */
92 #define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
93 #define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
94 #define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
95 #define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
96 #define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
97 #define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
98 #define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
99 #define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
100 #define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
101 #define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
103 /* I2C SCL time value when Master */
104 #define OMAP_I2C_SCLL_HSSCLL 8
105 #define OMAP_I2C_SCLH_HSSCLH 8
107 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
109 #define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
110 #define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
111 #define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
112 #define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
113 #define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
114 #define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
115 #define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
116 #define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
119 /* I2C System Status register (OMAP_I2C_SYSS): */
120 #define OMAP_I2C_SYSS_RDONE (1 << 0) /* Reset Done */
122 /* I2C System Configuration Register (OMAP_I2C_SYSC): */
123 #define OMAP_I2C_SYSC_SRST (1 << 1) /* Soft Reset */
125 struct omap_i2c_dev {
127 void __iomem *base; /* virtual */
129 struct clk *iclk; /* Interface clock */
130 struct clk *fclk; /* Functional clock */
131 struct completion cmd_complete;
132 struct resource *ioarea;
133 u32 speed; /* Speed of bus in Khz */
137 struct i2c_adapter adapter;
138 u8 fifo_size; /* use as flag and value
139 * fifo_size==0 implies no fifo
140 * if set, should be trsh+1
143 unsigned b_hw:1; /* bad h/w fixes */
145 u16 iestate; /* Saved interrupt register */
148 static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
151 __raw_writew(val, i2c_dev->base + reg);
154 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
156 return __raw_readw(i2c_dev->base + reg);
159 static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev)
161 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
162 dev->iclk = clk_get(dev->dev, "i2c_ick");
163 if (IS_ERR(dev->iclk)) {
168 /* For I2C operations on 2430 we need 96Mhz clock */
169 if (cpu_is_omap2430()) {
170 dev->fclk = clk_get(dev->dev, "i2chs_fck");
171 if (IS_ERR(dev->fclk)) {
172 if (dev->iclk != NULL) {
180 dev->fclk = clk_get(dev->dev, "i2c_fck");
181 if (IS_ERR(dev->fclk)) {
182 if (dev->iclk != NULL) {
193 static void omap_i2c_put_clocks(struct omap_i2c_dev *dev)
197 if (dev->iclk != NULL) {
203 static void omap_i2c_unidle(struct omap_i2c_dev *dev)
205 if (dev->iclk != NULL)
206 clk_enable(dev->iclk);
207 clk_enable(dev->fclk);
210 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
213 static void omap_i2c_idle(struct omap_i2c_dev *dev)
217 dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
218 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
220 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */
222 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);
224 * The wmb() is to ensure that the I2C interrupt mask write
225 * reaches the I2C controller before the dev->idle store
230 clk_disable(dev->fclk);
231 if (dev->iclk != NULL)
232 clk_disable(dev->iclk);
235 static int omap_i2c_init(struct omap_i2c_dev *dev)
237 u16 psc = 0, scll = 0, sclh = 0;
238 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
239 unsigned long fclk_rate = 12000000;
240 unsigned long timeout;
241 unsigned long internal_clk = 0;
244 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, OMAP_I2C_SYSC_SRST);
245 /* For some reason we need to set the EN bit before the
246 * reset done bit gets set. */
247 timeout = jiffies + OMAP_I2C_TIMEOUT;
248 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
249 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
250 OMAP_I2C_SYSS_RDONE)) {
251 if (time_after(jiffies, timeout)) {
252 dev_warn(dev->dev, "timeout waiting "
253 "for controller reset\n");
259 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
261 if (cpu_class_is_omap1()) {
262 struct clk *armxor_ck;
264 armxor_ck = clk_get(NULL, "armxor_ck");
265 if (IS_ERR(armxor_ck))
266 dev_warn(dev->dev, "Could not get armxor_ck\n");
268 fclk_rate = clk_get_rate(armxor_ck);
271 /* TRM for 5912 says the I2C clock must be prescaled to be
272 * between 7 - 12 MHz. The XOR input clock is typically
273 * 12, 13 or 19.2 MHz. So we should have code that produces:
275 * XOR MHz Divider Prescaler
280 if (fclk_rate > 12000000)
281 psc = fclk_rate / 12000000;
284 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
286 /* HSI2C controller internal clk rate should be 19.2 Mhz */
287 internal_clk = 19200;
288 fclk_rate = clk_get_rate(dev->fclk) / 1000;
290 /* Compute prescaler divisor */
291 psc = fclk_rate / internal_clk;
294 /* If configured for High Speed */
295 if (dev->speed > 400) {
296 /* For first phase of HS mode */
297 fsscll = internal_clk / (400 * 2) - 6;
298 fssclh = internal_clk / (400 * 2) - 6;
300 /* For second phase of HS mode */
301 hsscll = fclk_rate / (dev->speed * 2) - 6;
302 hssclh = fclk_rate / (dev->speed * 2) - 6;
304 /* To handle F/S modes */
305 fsscll = internal_clk / (dev->speed * 2) - 6;
306 fssclh = internal_clk / (dev->speed * 2) - 6;
308 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
309 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
311 /* Program desired operating rate */
312 fclk_rate /= (psc + 1) * 1000;
315 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
316 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
319 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
320 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
322 /* SCL low and high time values */
323 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
324 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
327 /* Note: setup required fifo size - 1 */
328 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG,
329 (dev->fifo_size - 1) << 8 | /* RTRSH */
330 OMAP_I2C_BUF_RXFIF_CLR |
331 (dev->fifo_size - 1) | /* XTRSH */
332 OMAP_I2C_BUF_TXFIF_CLR);
334 /* Take the I2C module out of reset: */
335 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
337 /* Enable interrupts */
338 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG,
339 (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
340 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
341 OMAP_I2C_IE_AL) | ((dev->fifo_size) ?
342 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0));
347 * Waiting on Bus Busy
349 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
351 unsigned long timeout;
353 timeout = jiffies + OMAP_I2C_TIMEOUT;
354 while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
355 if (time_after(jiffies, timeout)) {
356 dev_warn(dev->dev, "timeout waiting for bus ready\n");
366 * Low level master read/write transaction.
368 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
369 struct i2c_msg *msg, int stop)
371 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
375 dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
376 msg->addr, msg->len, msg->flags, stop);
381 omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
383 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
385 dev->buf_len = msg->len;
387 omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
389 /* Clear the FIFO Buffers */
390 w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
391 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
392 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
394 init_completion(&dev->cmd_complete);
397 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
399 /* High speed configuration */
400 if (dev->speed > 400)
401 w |= OMAP_I2C_CON_OPMODE_HS;
403 if (msg->flags & I2C_M_TEN)
404 w |= OMAP_I2C_CON_XA;
405 if (!(msg->flags & I2C_M_RD))
406 w |= OMAP_I2C_CON_TRX;
408 if (!dev->b_hw && stop)
409 w |= OMAP_I2C_CON_STP;
411 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
414 * Don't write stt and stp together on some hardware
416 if (dev->b_hw && stop) {
417 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
418 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
419 while (con & OMAP_I2C_CON_STT) {
420 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
422 /* Let the user know if i2c is in a bad state */
423 if (time_after(jiffies, delay)) {
424 dev_err(dev->dev, "controller timed out "
425 "waiting for start condition to finish\n");
431 w |= OMAP_I2C_CON_STP;
432 w &= ~OMAP_I2C_CON_STT;
433 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
435 r = wait_for_completion_timeout(&dev->cmd_complete,
441 dev_err(dev->dev, "controller timed out\n");
446 if (likely(!dev->cmd_err))
449 /* We have an error */
450 if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
451 OMAP_I2C_STAT_XUDF)) {
456 if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
457 if (msg->flags & I2C_M_IGNORE_NAK)
460 w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
461 w |= OMAP_I2C_CON_STP;
462 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
471 * Prepare controller for a transaction and call omap_i2c_xfer_msg
472 * to do the work during IRQ processing.
475 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
477 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
481 omap_i2c_unidle(dev);
483 r = omap_i2c_wait_for_bb(dev);
487 for (i = 0; i < num; i++) {
488 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
501 omap_i2c_func(struct i2c_adapter *adap)
503 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
507 omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
510 complete(&dev->cmd_complete);
514 omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
516 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
519 /* rev1 devices are apparently only on some 15xx */
520 #ifdef CONFIG_ARCH_OMAP15XX
523 omap_i2c_rev1_isr(int this_irq, void *dev_id)
525 struct omap_i2c_dev *dev = dev_id;
531 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
533 case 0x00: /* None */
535 case 0x01: /* Arbitration lost */
536 dev_err(dev->dev, "Arbitration lost\n");
537 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
539 case 0x02: /* No acknowledgement */
540 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
541 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
543 case 0x03: /* Register access ready */
544 omap_i2c_complete_cmd(dev, 0);
546 case 0x04: /* Receive data ready */
548 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
552 *dev->buf++ = w >> 8;
556 dev_err(dev->dev, "RRDY IRQ while no data requested\n");
558 case 0x05: /* Transmit data ready */
563 w |= *dev->buf++ << 8;
566 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
568 dev_err(dev->dev, "XRDY IRQ while no data to send\n");
577 #define omap_i2c_rev1_isr 0
581 omap_i2c_isr(int this_irq, void *dev_id)
583 struct omap_i2c_dev *dev = dev_id;
591 bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
592 while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
593 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
594 if (count++ == 100) {
595 dev_warn(dev->dev, "Too much work in one IRQ\n");
599 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
602 if (stat & OMAP_I2C_STAT_NACK) {
603 err |= OMAP_I2C_STAT_NACK;
604 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
607 if (stat & OMAP_I2C_STAT_AL) {
608 dev_err(dev->dev, "Arbitration lost\n");
609 err |= OMAP_I2C_STAT_AL;
611 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
613 omap_i2c_complete_cmd(dev, err);
614 if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
616 if (dev->fifo_size) {
617 if (stat & OMAP_I2C_STAT_RRDY)
618 num_bytes = dev->fifo_size;
620 num_bytes = omap_i2c_read_reg(dev,
621 OMAP_I2C_BUFSTAT_REG);
625 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
629 /* Data reg from 2430 is 8 bit wide */
630 if (!cpu_is_omap2430() &&
631 !cpu_is_omap34xx()) {
633 *dev->buf++ = w >> 8;
638 if (stat & OMAP_I2C_STAT_RRDY)
640 "RRDY IRQ while no data"
642 if (stat & OMAP_I2C_STAT_RDR)
644 "RDR IRQ while no data"
649 omap_i2c_ack_stat(dev,
650 stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
653 if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
655 if (dev->fifo_size) {
656 if (stat & OMAP_I2C_STAT_XRDY)
657 num_bytes = dev->fifo_size;
659 num_bytes = omap_i2c_read_reg(dev,
660 OMAP_I2C_BUFSTAT_REG);
668 /* Data reg from 2430 is 8 bit wide */
669 if (!cpu_is_omap2430() &&
670 !cpu_is_omap34xx()) {
672 w |= *dev->buf++ << 8;
677 if (stat & OMAP_I2C_STAT_XRDY)
681 if (stat & OMAP_I2C_STAT_XDR)
687 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
689 omap_i2c_ack_stat(dev,
690 stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
693 if (stat & OMAP_I2C_STAT_ROVR) {
694 dev_err(dev->dev, "Receive overrun\n");
695 dev->cmd_err |= OMAP_I2C_STAT_ROVR;
697 if (stat & OMAP_I2C_STAT_XUDF) {
698 dev_err(dev->dev, "Transmit underflow\n");
699 dev->cmd_err |= OMAP_I2C_STAT_XUDF;
703 return count ? IRQ_HANDLED : IRQ_NONE;
706 static const struct i2c_algorithm omap_i2c_algo = {
707 .master_xfer = omap_i2c_xfer,
708 .functionality = omap_i2c_func,
712 omap_i2c_probe(struct platform_device *pdev)
714 struct omap_i2c_dev *dev;
715 struct i2c_adapter *adap;
716 struct resource *mem, *irq, *ioarea;
720 /* NOTE: driver uses the static register mapping */
721 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
723 dev_err(&pdev->dev, "no mem resource?\n");
726 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
728 dev_err(&pdev->dev, "no irq resource?\n");
732 ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
735 dev_err(&pdev->dev, "I2C region already claimed\n");
739 dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
742 goto err_release_region;
745 if (pdev->dev.platform_data != NULL)
746 speed = (u32 *) pdev->dev.platform_data;
748 *speed = 100; /* Defualt speed */
751 dev->dev = &pdev->dev;
752 dev->irq = irq->start;
753 dev->base = ioremap(mem->start, mem->end - mem->start + 1);
759 platform_set_drvdata(pdev, dev);
761 r = omap_i2c_get_clocks(dev);
765 omap_i2c_unidle(dev);
767 if (cpu_is_omap15xx())
768 dev->rev1 = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) < 0x20;
770 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
773 /* Set up the fifo size - Get total size */
774 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
775 dev->fifo_size = 0x8 << s;
778 * Set up notification threshold as half the total available
779 * size. This is to ensure that we can handle the status on int
780 * call back latencies.
782 dev->fifo_size = (dev->fifo_size / 2);
783 dev->b_hw = 1; /* Enable hardware fixes */
786 /* reset ASAP, clearing any IRQs */
789 r = request_irq(dev->irq, dev->rev1 ? omap_i2c_rev1_isr : omap_i2c_isr,
793 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
794 goto err_unuse_clocks;
796 r = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
797 dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
798 pdev->id, r >> 4, r & 0xf, dev->speed);
800 adap = &dev->adapter;
801 i2c_set_adapdata(adap, dev);
802 adap->owner = THIS_MODULE;
803 adap->class = I2C_CLASS_HWMON;
804 strncpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
805 adap->algo = &omap_i2c_algo;
806 adap->dev.parent = &pdev->dev;
808 /* i2c device drivers may be active on return from add_adapter() */
810 r = i2c_add_numbered_adapter(adap);
812 dev_err(dev->dev, "failure adding adapter\n");
821 free_irq(dev->irq, dev);
823 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
825 omap_i2c_put_clocks(dev);
829 platform_set_drvdata(pdev, NULL);
832 release_mem_region(mem->start, (mem->end - mem->start) + 1);
838 omap_i2c_remove(struct platform_device *pdev)
840 struct omap_i2c_dev *dev = platform_get_drvdata(pdev);
841 struct resource *mem;
843 platform_set_drvdata(pdev, NULL);
845 free_irq(dev->irq, dev);
846 i2c_del_adapter(&dev->adapter);
847 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
848 omap_i2c_put_clocks(dev);
851 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
852 release_mem_region(mem->start, (mem->end - mem->start) + 1);
856 static struct platform_driver omap_i2c_driver = {
857 .probe = omap_i2c_probe,
858 .remove = omap_i2c_remove,
861 .owner = THIS_MODULE,
865 /* I2C may be needed to bring up other drivers */
867 omap_i2c_init_driver(void)
869 return platform_driver_register(&omap_i2c_driver);
871 subsys_initcall(omap_i2c_init_driver);
873 static void __devexit omap_i2c_exit_driver(void)
875 platform_driver_unregister(&omap_i2c_driver);
877 module_exit(omap_i2c_exit_driver);
879 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
880 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
881 MODULE_LICENSE("GPL");
882 MODULE_ALIAS("platform:i2c_omap");