2 * Copyright (C) 2009 ST-Ericsson SA
3 * Copyright (C) 2009 STMicroelectronics
5 * I2C master mode controller driver, used in Nomadik 8815
8 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
9 * Author: Sachin Verma <sachin.verma@st.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2, as
13 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/delay.h>
19 #include <linux/slab.h>
20 #include <linux/interrupt.h>
21 #include <linux/i2c.h>
22 #include <linux/err.h>
23 #include <linux/clk.h>
28 #define DRIVER_NAME "nmk-i2c"
30 /* I2C Controller register offsets */
31 #define I2C_CR (0x000)
32 #define I2C_SCR (0x004)
33 #define I2C_HSMCR (0x008)
34 #define I2C_MCR (0x00C)
35 #define I2C_TFR (0x010)
36 #define I2C_SR (0x014)
37 #define I2C_RFR (0x018)
38 #define I2C_TFTR (0x01C)
39 #define I2C_RFTR (0x020)
40 #define I2C_DMAR (0x024)
41 #define I2C_BRCR (0x028)
42 #define I2C_IMSCR (0x02C)
43 #define I2C_RISR (0x030)
44 #define I2C_MISR (0x034)
45 #define I2C_ICR (0x038)
47 /* Control registers */
48 #define I2C_CR_PE (0x1 << 0) /* Peripheral Enable */
49 #define I2C_CR_OM (0x3 << 1) /* Operating mode */
50 #define I2C_CR_SAM (0x1 << 3) /* Slave addressing mode */
51 #define I2C_CR_SM (0x3 << 4) /* Speed mode */
52 #define I2C_CR_SGCM (0x1 << 6) /* Slave general call mode */
53 #define I2C_CR_FTX (0x1 << 7) /* Flush Transmit */
54 #define I2C_CR_FRX (0x1 << 8) /* Flush Receive */
55 #define I2C_CR_DMA_TX_EN (0x1 << 9) /* DMA Tx enable */
56 #define I2C_CR_DMA_RX_EN (0x1 << 10) /* DMA Rx Enable */
57 #define I2C_CR_DMA_SLE (0x1 << 11) /* DMA sync. logic enable */
58 #define I2C_CR_LM (0x1 << 12) /* Loopback mode */
59 #define I2C_CR_FON (0x3 << 13) /* Filtering on */
60 #define I2C_CR_FS (0x3 << 15) /* Force stop enable */
62 /* Master controller (MCR) register */
63 #define I2C_MCR_OP (0x1 << 0) /* Operation */
64 #define I2C_MCR_A7 (0x7f << 1) /* 7-bit address */
65 #define I2C_MCR_EA10 (0x7 << 8) /* 10-bit Extended address */
66 #define I2C_MCR_SB (0x1 << 11) /* Extended address */
67 #define I2C_MCR_AM (0x3 << 12) /* Address type */
68 #define I2C_MCR_STOP (0x1 << 14) /* Stop condition */
69 #define I2C_MCR_LENGTH (0x7ff << 15) /* Transaction length */
71 /* Status register (SR) */
72 #define I2C_SR_OP (0x3 << 0) /* Operation */
73 #define I2C_SR_STATUS (0x3 << 2) /* controller status */
74 #define I2C_SR_CAUSE (0x7 << 4) /* Abort cause */
75 #define I2C_SR_TYPE (0x3 << 7) /* Receive type */
76 #define I2C_SR_LENGTH (0x7ff << 9) /* Transfer length */
78 /* Interrupt mask set/clear (IMSCR) bits */
79 #define I2C_IT_TXFE (0x1 << 0)
80 #define I2C_IT_TXFNE (0x1 << 1)
81 #define I2C_IT_TXFF (0x1 << 2)
82 #define I2C_IT_TXFOVR (0x1 << 3)
83 #define I2C_IT_RXFE (0x1 << 4)
84 #define I2C_IT_RXFNF (0x1 << 5)
85 #define I2C_IT_RXFF (0x1 << 6)
86 #define I2C_IT_RFSR (0x1 << 16)
87 #define I2C_IT_RFSE (0x1 << 17)
88 #define I2C_IT_WTSR (0x1 << 18)
89 #define I2C_IT_MTD (0x1 << 19)
90 #define I2C_IT_STD (0x1 << 20)
91 #define I2C_IT_MAL (0x1 << 24)
92 #define I2C_IT_BERR (0x1 << 25)
93 #define I2C_IT_MTDWS (0x1 << 28)
95 #define GEN_MASK(val, mask, sb) (((val) << (sb)) & (mask))
97 /* some bits in ICR are reserved */
98 #define I2C_CLEAR_ALL_INTS 0x131f007f
100 /* first three msb bits are reserved */
101 #define IRQ_MASK(mask) (mask & 0x1fffffff)
103 /* maximum threshold value */
104 #define MAX_I2C_FIFO_THRESHOLD 15
115 I2C_NO_OPERATION = 0xff,
120 /* controller response timeout in ms */
121 #define I2C_TIMEOUT_MS 500
124 * struct i2c_nmk_client - client specific data
125 * @slave_adr: 7-bit slave address
126 * @count: no. bytes to be transfered
127 * @buffer: client data buffer
128 * @xfer_bytes: bytes transfered till now
129 * @operation: current I2C operation
131 struct i2c_nmk_client {
132 unsigned short slave_adr;
134 unsigned char *buffer;
135 unsigned long xfer_bytes;
136 enum i2c_operation operation;
140 * struct nmk_i2c_dev - private data structure of the controller
141 * @pdev: parent platform device
142 * @adap: corresponding I2C adapter
143 * @irq: interrupt line for the controller
144 * @virtbase: virtual io memory area
145 * @clk: hardware i2c block clock
146 * @cfg: machine provided controller configuration
147 * @cli: holder of client specific data
148 * @stop: stop condition
149 * @xfer_complete: acknowledge completion for a I2C message
150 * @result: controller propogated result
153 struct platform_device *pdev;
154 struct i2c_adapter adap;
156 void __iomem *virtbase;
158 struct nmk_i2c_controller cfg;
159 struct i2c_nmk_client cli;
161 struct completion xfer_complete;
165 /* controller's abort causes */
166 static const char *abort_causes[] = {
167 "no ack received after address transmission",
168 "no ack received during data phase",
169 "ack received after xmission of master code",
170 "master lost arbitration",
173 "overflow, maxsize is 2047 bytes",
176 static inline void i2c_set_bit(void __iomem *reg, u32 mask)
178 writel(readl(reg) | mask, reg);
181 static inline void i2c_clr_bit(void __iomem *reg, u32 mask)
183 writel(readl(reg) & ~mask, reg);
187 * flush_i2c_fifo() - This function flushes the I2C FIFO
188 * @dev: private data of I2C Driver
190 * This function flushes the I2C Tx and Rx FIFOs. It returns
191 * 0 on successful flushing of FIFO
193 static int flush_i2c_fifo(struct nmk_i2c_dev *dev)
195 #define LOOP_ATTEMPTS 10
197 unsigned long timeout;
200 * flush the transmit and receive FIFO. The flushing
201 * operation takes several cycles before to be completed.
202 * On the completion, the I2C internal logic clears these
203 * bits, until then no one must access Tx, Rx FIFO and
204 * should poll on these bits waiting for the completion.
206 writel((I2C_CR_FTX | I2C_CR_FRX), dev->virtbase + I2C_CR);
208 for (i = 0; i < LOOP_ATTEMPTS; i++) {
209 timeout = jiffies + msecs_to_jiffies(I2C_TIMEOUT_MS);
211 while (!time_after(jiffies, timeout)) {
212 if ((readl(dev->virtbase + I2C_CR) &
213 (I2C_CR_FTX | I2C_CR_FRX)) == 0)
218 dev_err(&dev->pdev->dev, "flushing operation timed out "
219 "giving up after %d attempts", LOOP_ATTEMPTS);
225 * disable_all_interrupts() - Disable all interrupts of this I2c Bus
226 * @dev: private data of I2C Driver
228 static void disable_all_interrupts(struct nmk_i2c_dev *dev)
230 u32 mask = IRQ_MASK(0);
231 writel(mask, dev->virtbase + I2C_IMSCR);
235 * clear_all_interrupts() - Clear all interrupts of I2C Controller
236 * @dev: private data of I2C Driver
238 static void clear_all_interrupts(struct nmk_i2c_dev *dev)
241 mask = IRQ_MASK(I2C_CLEAR_ALL_INTS);
242 writel(mask, dev->virtbase + I2C_ICR);
246 * init_hw() - initialize the I2C hardware
247 * @dev: private data of I2C Driver
249 static int init_hw(struct nmk_i2c_dev *dev)
253 clk_enable(dev->clk);
255 stat = flush_i2c_fifo(dev);
259 /* disable the controller */
260 i2c_clr_bit(dev->virtbase + I2C_CR , I2C_CR_PE);
262 disable_all_interrupts(dev);
264 clear_all_interrupts(dev);
266 dev->cli.operation = I2C_NO_OPERATION;
268 clk_disable(dev->clk);
273 /* enable peripheral, master mode operation */
274 #define DEFAULT_I2C_REG_CR ((1 << 1) | I2C_CR_PE)
277 * load_i2c_mcr_reg() - load the MCR register
278 * @dev: private data of controller
280 static u32 load_i2c_mcr_reg(struct nmk_i2c_dev *dev)
284 /* 7-bit address transaction */
285 mcr |= GEN_MASK(1, I2C_MCR_AM, 12);
286 mcr |= GEN_MASK(dev->cli.slave_adr, I2C_MCR_A7, 1);
288 /* start byte procedure not applied */
289 mcr |= GEN_MASK(0, I2C_MCR_SB, 11);
291 /* check the operation, master read/write? */
292 if (dev->cli.operation == I2C_WRITE)
293 mcr |= GEN_MASK(I2C_WRITE, I2C_MCR_OP, 0);
295 mcr |= GEN_MASK(I2C_READ, I2C_MCR_OP, 0);
297 /* stop or repeated start? */
299 mcr |= GEN_MASK(1, I2C_MCR_STOP, 14);
301 mcr &= ~(GEN_MASK(1, I2C_MCR_STOP, 14));
303 mcr |= GEN_MASK(dev->cli.count, I2C_MCR_LENGTH, 15);
309 * setup_i2c_controller() - setup the controller
310 * @dev: private data of controller
312 static void setup_i2c_controller(struct nmk_i2c_dev *dev)
317 writel(0x0, dev->virtbase + I2C_CR);
318 writel(0x0, dev->virtbase + I2C_HSMCR);
319 writel(0x0, dev->virtbase + I2C_TFTR);
320 writel(0x0, dev->virtbase + I2C_RFTR);
321 writel(0x0, dev->virtbase + I2C_DMAR);
326 * slsu defines the data setup time after SCL clock
327 * stretching in terms of i2c clk cycles. The
328 * needed setup time for the three modes are 250ns,
329 * 100ns, 10ns repectively thus leading to the values
330 * of 14, 6, 2 for a 48 MHz i2c clk.
332 writel(dev->cfg.slsu << 16, dev->virtbase + I2C_SCR);
334 i2c_clk = clk_get_rate(dev->clk);
336 /* fallback to std. mode if machine has not provided it */
337 if (dev->cfg.clk_freq == 0)
338 dev->cfg.clk_freq = 100000;
341 * The spec says, in case of std. mode the divider is
342 * 2 whereas it is 3 for fast and fastplus mode of
343 * operation. TODO - high speed support.
345 div = (dev->cfg.clk_freq > 100000) ? 3 : 2;
348 * generate the mask for baud rate counters. The controller
349 * has two baud rate counters. One is used for High speed
350 * operation, and the other is for std, fast mode, fast mode
351 * plus operation. Currently we do not supprt high speed mode
355 brcr2 = (i2c_clk/(dev->cfg.clk_freq * div)) & 0xffff;
357 /* set the baud rate counter register */
358 writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR);
361 * set the speed mode. Currently we support
362 * only standard and fast mode of operation
363 * TODO - support for fast mode plus (upto 1Mb/s)
364 * and high speed (up to 3.4 Mb/s)
366 if (dev->cfg.sm > I2C_FREQ_MODE_FAST) {
367 dev_err(&dev->pdev->dev, "do not support this mode "
368 "defaulting to std. mode\n");
369 brcr2 = i2c_clk/(100000 * 2) & 0xffff;
370 writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR);
371 writel(I2C_FREQ_MODE_STANDARD << 4,
372 dev->virtbase + I2C_CR);
374 writel(dev->cfg.sm << 4, dev->virtbase + I2C_CR);
376 /* set the Tx and Rx FIFO threshold */
377 writel(dev->cfg.tft, dev->virtbase + I2C_TFTR);
378 writel(dev->cfg.rft, dev->virtbase + I2C_RFTR);
382 * read_i2c() - Read from I2C client device
383 * @dev: private data of I2C Driver
385 * This function reads from i2c client device when controller is in
386 * master mode. There is a completion timeout. If there is no transfer
387 * before timeout error is returned.
389 static int read_i2c(struct nmk_i2c_dev *dev)
396 mcr = load_i2c_mcr_reg(dev);
397 writel(mcr, dev->virtbase + I2C_MCR);
399 /* load the current CR value */
400 writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
401 dev->virtbase + I2C_CR);
403 /* enable the controller */
404 i2c_set_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
406 init_completion(&dev->xfer_complete);
408 /* enable interrupts by setting the mask */
409 irq_mask = (I2C_IT_RXFNF | I2C_IT_RXFF |
410 I2C_IT_MAL | I2C_IT_BERR);
413 irq_mask |= I2C_IT_MTD;
415 irq_mask |= I2C_IT_MTDWS;
417 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask);
419 writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask,
420 dev->virtbase + I2C_IMSCR);
422 timeout = wait_for_completion_interruptible_timeout(
423 &dev->xfer_complete, msecs_to_jiffies(I2C_TIMEOUT_MS));
426 dev_err(&dev->pdev->dev,
427 "wait_for_completion_interruptible_timeout"
428 "returned %d waiting for event\n", timeout);
433 /* controler has timedout, re-init the h/w */
434 dev_err(&dev->pdev->dev, "controller timed out, re-init h/w\n");
442 * write_i2c() - Write data to I2C client.
443 * @dev: private data of I2C Driver
445 * This function writes data to I2C client
447 static int write_i2c(struct nmk_i2c_dev *dev)
454 mcr = load_i2c_mcr_reg(dev);
456 writel(mcr, dev->virtbase + I2C_MCR);
458 /* load the current CR value */
459 writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
460 dev->virtbase + I2C_CR);
462 /* enable the controller */
463 i2c_set_bit(dev->virtbase + I2C_CR , I2C_CR_PE);
465 init_completion(&dev->xfer_complete);
467 /* enable interrupts by settings the masks */
468 irq_mask = (I2C_IT_TXFNE | I2C_IT_TXFOVR |
469 I2C_IT_MAL | I2C_IT_BERR);
472 * check if we want to transfer a single or multiple bytes, if so
473 * set the MTDWS bit (Master Transaction Done Without Stop)
474 * to start repeated start operation
477 irq_mask |= I2C_IT_MTD;
479 irq_mask |= I2C_IT_MTDWS;
481 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask);
483 writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask,
484 dev->virtbase + I2C_IMSCR);
486 timeout = wait_for_completion_interruptible_timeout(
487 &dev->xfer_complete, msecs_to_jiffies(I2C_TIMEOUT_MS));
490 dev_err(&dev->pdev->dev,
491 "wait_for_completion_interruptible_timeout"
492 "returned %d waiting for event\n", timeout);
497 /* controler has timedout, re-init the h/w */
498 dev_err(&dev->pdev->dev, "controller timed out, re-init h/w\n");
507 * nmk_i2c_xfer() - I2C transfer function used by kernel framework
508 * @i2c_adap: Adapter pointer to the controller
509 * @msgs: Pointer to data to be written.
510 * @num_msgs: Number of messages to be executed
512 * This is the function called by the generic kernel i2c_transfer()
513 * or i2c_smbus...() API calls. Note that this code is protected by the
514 * semaphore set in the kernel i2c_transfer() function.
517 * READ TRANSFER : We impose a restriction of the first message to be the
518 * index message for any read transaction.
519 * - a no index is coded as '0',
520 * - 2byte big endian index is coded as '3'
521 * !!! msg[0].buf holds the actual index.
522 * This is compatible with generic messages of smbus emulator
523 * that send a one byte index.
524 * eg. a I2C transation to read 2 bytes from index 0
526 * msg[0].addr = client->addr;
527 * msg[0].flags = 0x0;
531 * msg[1].addr = client->addr;
532 * msg[1].flags = I2C_M_RD;
534 * msg[1].buf = rd_buff
535 * i2c_transfer(adap, msg, 2);
537 * WRITE TRANSFER : The I2C standard interface interprets all data as payload.
538 * If you want to emulate an SMBUS write transaction put the
539 * index as first byte(or first and second) in the payload.
540 * eg. a I2C transation to write 2 bytes from index 1
544 * msg[0].flags = 0x0;
546 * msg[0].buf = wr_buff;
547 * i2c_transfer(adap, msg, 1);
549 * To read or write a block of data (multiple bytes) using SMBUS emulation
550 * please use the i2c_smbus_read_i2c_block_data()
551 * or i2c_smbus_write_i2c_block_data() API
553 static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap,
554 struct i2c_msg msgs[], int num_msgs)
559 struct nmk_i2c_dev *dev = i2c_get_adapdata(i2c_adap);
561 status = init_hw(dev);
565 clk_enable(dev->clk);
567 /* setup the i2c controller */
568 setup_i2c_controller(dev);
570 for (i = 0; i < num_msgs; i++) {
571 if (unlikely(msgs[i].flags & I2C_M_TEN)) {
572 dev_err(&dev->pdev->dev, "10 bit addressing"
576 dev->cli.slave_adr = msgs[i].addr;
577 dev->cli.buffer = msgs[i].buf;
578 dev->cli.count = msgs[i].len;
579 dev->stop = (i < (num_msgs - 1)) ? 0 : 1;
582 if (msgs[i].flags & I2C_M_RD) {
583 /* it is a read operation */
584 dev->cli.operation = I2C_READ;
585 status = read_i2c(dev);
587 /* write operation */
588 dev->cli.operation = I2C_WRITE;
589 status = write_i2c(dev);
591 if (status || (dev->result)) {
592 /* get the abort cause */
593 cause = (readl(dev->virtbase + I2C_SR) >> 4) & 0x7;
594 dev_err(&dev->pdev->dev, "error during I2C"
595 "message xfer: %d\n", cause);
596 dev_err(&dev->pdev->dev, "%s\n",
597 cause >= ARRAY_SIZE(abort_causes)
598 ? "unknown reason" : abort_causes[cause]);
599 clk_disable(dev->clk);
604 clk_disable(dev->clk);
606 /* return the no. messages processed */
614 * disable_interrupts() - disable the interrupts
615 * @dev: private data of controller
616 * @irq: interrupt number
618 static int disable_interrupts(struct nmk_i2c_dev *dev, u32 irq)
621 writel(readl(dev->virtbase + I2C_IMSCR) & ~(I2C_CLEAR_ALL_INTS & irq),
622 dev->virtbase + I2C_IMSCR);
627 * i2c_irq_handler() - interrupt routine
628 * @irq: interrupt number
629 * @arg: data passed to the handler
631 * This is the interrupt handler for the i2c driver. Currently
632 * it handles the major interrupts like Rx & Tx FIFO management
633 * interrupts, master transaction interrupts, arbitration and
634 * bus error interrupts. The rest of the interrupts are treated as
637 static irqreturn_t i2c_irq_handler(int irq, void *arg)
639 struct nmk_i2c_dev *dev = arg;
645 /* load Tx FIFO and Rx FIFO threshold values */
646 tft = readl(dev->virtbase + I2C_TFTR);
647 rft = readl(dev->virtbase + I2C_RFTR);
649 /* read interrupt status register */
650 misr = readl(dev->virtbase + I2C_MISR);
653 switch ((1 << src)) {
655 /* Transmit FIFO nearly empty interrupt */
658 if (dev->cli.operation == I2C_READ) {
660 * in read operation why do we care for writing?
661 * so disable the Transmit FIFO interrupt
663 disable_interrupts(dev, I2C_IT_TXFNE);
665 for (count = (MAX_I2C_FIFO_THRESHOLD - tft - 2);
667 (dev->cli.count != 0);
669 /* write to the Tx FIFO */
670 writeb(*dev->cli.buffer,
671 dev->virtbase + I2C_TFR);
674 dev->cli.xfer_bytes++;
677 * if done, close the transfer by disabling the
678 * corresponding TXFNE interrupt
680 if (dev->cli.count == 0)
681 disable_interrupts(dev, I2C_IT_TXFNE);
687 * Rx FIFO nearly full interrupt.
688 * This is set when the numer of entries in Rx FIFO is
689 * greater or equal than the threshold value programmed
693 for (count = rft; count > 0; count--) {
694 /* Read the Rx FIFO */
695 *dev->cli.buffer = readb(dev->virtbase + I2C_RFR);
698 dev->cli.count -= rft;
699 dev->cli.xfer_bytes += rft;
704 for (count = MAX_I2C_FIFO_THRESHOLD; count > 0; count--) {
705 *dev->cli.buffer = readb(dev->virtbase + I2C_RFR);
708 dev->cli.count -= MAX_I2C_FIFO_THRESHOLD;
709 dev->cli.xfer_bytes += MAX_I2C_FIFO_THRESHOLD;
712 /* Master Transaction Done with/without stop */
715 if (dev->cli.operation == I2C_READ) {
716 while (!(readl(dev->virtbase + I2C_RISR)
718 if (dev->cli.count == 0)
721 readb(dev->virtbase + I2C_RFR);
724 dev->cli.xfer_bytes++;
728 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MTD);
729 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MTDWS);
731 disable_interrupts(dev,
732 (I2C_IT_TXFNE | I2C_IT_TXFE | I2C_IT_TXFF
733 | I2C_IT_TXFOVR | I2C_IT_RXFNF
734 | I2C_IT_RXFF | I2C_IT_RXFE));
736 if (dev->cli.count) {
738 dev_err(&dev->pdev->dev, "%lu bytes still remain to be"
739 "xfered\n", dev->cli.count);
742 complete(&dev->xfer_complete);
746 /* Master Arbitration lost interrupt */
751 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MAL);
752 complete(&dev->xfer_complete);
757 * Bus Error interrupt.
758 * This happens when an unexpected start/stop condition occurs
759 * during the transaction.
764 if (((readl(dev->virtbase + I2C_SR) >> 2) & 0x3) == I2C_ABORT)
767 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_BERR);
768 complete(&dev->xfer_complete);
773 * Tx FIFO overrun interrupt.
774 * This is set when a write operation in Tx FIFO is performed and
775 * the Tx FIFO is full.
781 dev_err(&dev->pdev->dev, "Tx Fifo Over run\n");
782 complete(&dev->xfer_complete);
786 /* unhandled interrupts by this driver - TODO*/
794 dev_err(&dev->pdev->dev, "unhandled Interrupt\n");
797 dev_err(&dev->pdev->dev, "spurious Interrupt..\n");
804 static unsigned int nmk_i2c_functionality(struct i2c_adapter *adap)
806 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
809 static const struct i2c_algorithm nmk_i2c_algo = {
810 .master_xfer = nmk_i2c_xfer,
811 .functionality = nmk_i2c_functionality
814 static int __devinit nmk_i2c_probe(struct platform_device *pdev)
817 struct resource *res;
818 struct nmk_i2c_controller *pdata =
819 pdev->dev.platform_data;
820 struct nmk_i2c_dev *dev;
821 struct i2c_adapter *adap;
823 dev = kzalloc(sizeof(struct nmk_i2c_dev), GFP_KERNEL);
825 dev_err(&pdev->dev, "cannot allocate memory\n");
831 platform_set_drvdata(pdev, dev);
833 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
836 goto err_no_resource;
839 if (request_mem_region(res->start, resource_size(res),
840 DRIVER_NAME "I/O region") == NULL) {
845 dev->virtbase = ioremap(res->start, resource_size(res));
846 if (!dev->virtbase) {
851 dev->irq = platform_get_irq(pdev, 0);
852 ret = request_irq(dev->irq, i2c_irq_handler, IRQF_DISABLED,
855 dev_err(&pdev->dev, "cannot claim the irq %d\n", dev->irq);
859 dev->clk = clk_get(&pdev->dev, NULL);
860 if (IS_ERR(dev->clk)) {
861 dev_err(&pdev->dev, "could not get i2c clock\n");
862 ret = PTR_ERR(dev->clk);
867 adap->dev.parent = &pdev->dev;
868 adap->owner = THIS_MODULE;
869 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
870 adap->algo = &nmk_i2c_algo;
872 /* fetch the controller id */
875 /* fetch the controller configuration from machine */
876 dev->cfg.clk_freq = pdata->clk_freq;
877 dev->cfg.slsu = pdata->slsu;
878 dev->cfg.tft = pdata->tft;
879 dev->cfg.rft = pdata->rft;
880 dev->cfg.sm = pdata->sm;
882 i2c_set_adapdata(adap, dev);
886 dev_err(&pdev->dev, "error in initializing i2c hardware\n");
890 dev_dbg(&pdev->dev, "initialize I2C%d bus on virtual "
891 "base %p\n", pdev->id, dev->virtbase);
893 ret = i2c_add_numbered_adapter(adap);
895 dev_err(&pdev->dev, "failed to add adapter\n");
905 free_irq(dev->irq, dev);
907 iounmap(dev->virtbase);
909 release_mem_region(res->start, resource_size(res));
911 platform_set_drvdata(pdev, NULL);
919 static int __devexit nmk_i2c_remove(struct platform_device *pdev)
921 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
922 struct nmk_i2c_dev *dev = platform_get_drvdata(pdev);
924 i2c_del_adapter(&dev->adap);
926 disable_all_interrupts(dev);
927 clear_all_interrupts(dev);
928 /* disable the controller */
929 i2c_clr_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
930 free_irq(dev->irq, dev);
931 iounmap(dev->virtbase);
933 release_mem_region(res->start, resource_size(res));
935 platform_set_drvdata(pdev, NULL);
941 static struct platform_driver nmk_i2c_driver = {
943 .owner = THIS_MODULE,
946 .probe = nmk_i2c_probe,
947 .remove = __devexit_p(nmk_i2c_remove),
950 static int __init nmk_i2c_init(void)
952 return platform_driver_register(&nmk_i2c_driver);
955 static void __exit nmk_i2c_exit(void)
957 platform_driver_unregister(&nmk_i2c_driver);
960 subsys_initcall(nmk_i2c_init);
961 module_exit(nmk_i2c_exit);
963 MODULE_AUTHOR("Sachin Verma, Srinidhi KASAGAR");
964 MODULE_DESCRIPTION("Nomadik/Ux500 I2C driver");
965 MODULE_LICENSE("GPL");
966 MODULE_ALIAS("platform:" DRIVER_NAME);