drivers/i2c/busses/i2c-mxs.c

   1 /*
   2  * Freescale MXS I2C bus driver
   3  *
   4  * Copyright (C) 2011-2012 Wolfram Sang, Pengutronix e.K.
   5  *
   6  * based on a (non-working) driver which was:
   7  *
   8  * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  */
  16
  17 #include <linux/slab.h>
  18 #include <linux/device.h>
  19 #include <linux/module.h>
  20 #include <linux/i2c.h>
  21 #include <linux/err.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/completion.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/jiffies.h>
  26 #include <linux/io.h>
  27 #include <linux/pinctrl/consumer.h>
  28 #include <linux/stmp_device.h>
  29 #include <linux/of.h>
  30 #include <linux/of_device.h>
  31 #include <linux/of_i2c.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/dmaengine.h>
  34 #include <linux/fsl/mxs-dma.h>
  35
  36 #define DRIVER_NAME "mxs-i2c"
  37
  38 #define MXS_I2C_CTRL0           (0x00)
  39 #define MXS_I2C_CTRL0_SET       (0x04)
  40
  41 #define MXS_I2C_CTRL0_SFTRST                    0x80000000
  42 #define MXS_I2C_CTRL0_SEND_NAK_ON_LAST          0x02000000
  43 #define MXS_I2C_CTRL0_RETAIN_CLOCK              0x00200000
  44 #define MXS_I2C_CTRL0_POST_SEND_STOP            0x00100000
  45 #define MXS_I2C_CTRL0_PRE_SEND_START            0x00080000
  46 #define MXS_I2C_CTRL0_MASTER_MODE               0x00020000
  47 #define MXS_I2C_CTRL0_DIRECTION                 0x00010000
  48 #define MXS_I2C_CTRL0_XFER_COUNT(v)             ((v) & 0x0000FFFF)
  49
  50 #define MXS_I2C_TIMING0         (0x10)
  51 #define MXS_I2C_TIMING1         (0x20)
  52 #define MXS_I2C_TIMING2         (0x30)
  53
  54 #define MXS_I2C_CTRL1           (0x40)
  55 #define MXS_I2C_CTRL1_SET       (0x44)
  56 #define MXS_I2C_CTRL1_CLR       (0x48)
  57
  58 #define MXS_I2C_CTRL1_BUS_FREE_IRQ              0x80
  59 #define MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ     0x40
  60 #define MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ          0x20
  61 #define MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ    0x10
  62 #define MXS_I2C_CTRL1_EARLY_TERM_IRQ            0x08
  63 #define MXS_I2C_CTRL1_MASTER_LOSS_IRQ           0x04
  64 #define MXS_I2C_CTRL1_SLAVE_STOP_IRQ            0x02
  65 #define MXS_I2C_CTRL1_SLAVE_IRQ                 0x01
  66
  67 #define MXS_I2C_IRQ_MASK        (MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | \
  68                                  MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ | \
  69                                  MXS_I2C_CTRL1_EARLY_TERM_IRQ | \
  70                                  MXS_I2C_CTRL1_MASTER_LOSS_IRQ | \
  71                                  MXS_I2C_CTRL1_SLAVE_STOP_IRQ | \
  72                                  MXS_I2C_CTRL1_SLAVE_IRQ)
  73
  74
  75 #define MXS_CMD_I2C_SELECT      (MXS_I2C_CTRL0_RETAIN_CLOCK |   \
  76                                  MXS_I2C_CTRL0_PRE_SEND_START | \
  77                                  MXS_I2C_CTRL0_MASTER_MODE |    \
  78                                  MXS_I2C_CTRL0_DIRECTION |      \
  79                                  MXS_I2C_CTRL0_XFER_COUNT(1))
  80
  81 #define MXS_CMD_I2C_WRITE       (MXS_I2C_CTRL0_PRE_SEND_START | \
  82                                  MXS_I2C_CTRL0_MASTER_MODE |    \
  83                                  MXS_I2C_CTRL0_DIRECTION)
  84
  85 #define MXS_CMD_I2C_READ        (MXS_I2C_CTRL0_SEND_NAK_ON_LAST | \
  86                                  MXS_I2C_CTRL0_MASTER_MODE)
  87
  88 struct mxs_i2c_speed_config {
  89         uint32_t        timing0;
  90         uint32_t        timing1;
  91         uint32_t        timing2;
  92 };
  93
  94 /*
  95  * Timing values for the default 24MHz clock supplied into the i2c block.
  96  *
  97  * The bus can operate at 95kHz or at 400kHz with the following timing
  98  * register configurations. The 100kHz mode isn't present because it's
  99  * values are not stated in the i.MX233/i.MX28 datasheet. The 95kHz mode
 100  * shall be close enough replacement. Therefore when the bus is configured
 101  * for 100kHz operation, 95kHz timing settings are actually loaded.
 102  *
 103  * For details, see i.MX233 [25.4.2 - 25.4.4] and i.MX28 [27.5.2 - 27.5.4].
 104  */
 105 static const struct mxs_i2c_speed_config mxs_i2c_95kHz_config = {
 106         .timing0        = 0x00780030,
 107         .timing1        = 0x00800030,
 108         .timing2        = 0x00300030,
 109 };
 110
 111 static const struct mxs_i2c_speed_config mxs_i2c_400kHz_config = {
 112         .timing0        = 0x000f0007,
 113         .timing1        = 0x001f000f,
 114         .timing2        = 0x00300030,
 115 };
 116
 117 /**
 118  * struct mxs_i2c_dev - per device, private MXS-I2C data
 119  *
 120  * @dev: driver model device node
 121  * @regs: IO registers pointer
 122  * @cmd_complete: completion object for transaction wait
 123  * @cmd_err: error code for last transaction
 124  * @adapter: i2c subsystem adapter node
 125  */
 126 struct mxs_i2c_dev {
 127         struct device *dev;
 128         void __iomem *regs;
 129         struct completion cmd_complete;
 130         int cmd_err;
 131         struct i2c_adapter adapter;
 132         const struct mxs_i2c_speed_config *speed;
 133
 134         /* DMA support components */
 135         int                             dma_channel;
 136         struct dma_chan                 *dmach;
 137         struct mxs_dma_data             dma_data;
 138         uint32_t                        pio_data[2];
 139         uint32_t                        addr_data;
 140         struct scatterlist              sg_io[2];
 141         bool                            dma_read;
 142 };
 143
 144 static void mxs_i2c_reset(struct mxs_i2c_dev *i2c)
 145 {
 146         stmp_reset_block(i2c->regs);
 147
 148         writel(i2c->speed->timing0, i2c->regs + MXS_I2C_TIMING0);
 149         writel(i2c->speed->timing1, i2c->regs + MXS_I2C_TIMING1);
 150         writel(i2c->speed->timing2, i2c->regs + MXS_I2C_TIMING2);
 151
 152         writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
 153 }
 154
 155 static void mxs_i2c_dma_finish(struct mxs_i2c_dev *i2c)
 156 {
 157         if (i2c->dma_read) {
 158                 dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
 159                 dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
 160         } else {
 161                 dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
 162         }
 163 }
 164
 165 static void mxs_i2c_dma_irq_callback(void *param)
 166 {
 167         struct mxs_i2c_dev *i2c = param;
 168
 169         complete(&i2c->cmd_complete);
 170         mxs_i2c_dma_finish(i2c);
 171 }
 172
 173 static int mxs_i2c_dma_setup_xfer(struct i2c_adapter *adap,
 174                         struct i2c_msg *msg, uint32_t flags)
 175 {
 176         struct dma_async_tx_descriptor *desc;
 177         struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
 178
 179         if (msg->flags & I2C_M_RD) {
 180                 i2c->dma_read = 1;
 181                 i2c->addr_data = (msg->addr << 1) | I2C_SMBUS_READ;
 182
 183                 /*
 184                  * SELECT command.
 185                  */
 186
 187                 /* Queue the PIO register write transfer. */
 188                 i2c->pio_data[0] = MXS_CMD_I2C_SELECT;
 189                 desc = dmaengine_prep_slave_sg(i2c->dmach,
 190                                         (struct scatterlist *)&i2c->pio_data[0],
 191                                         1, DMA_TRANS_NONE, 0);
 192                 if (!desc) {
 193                         dev_err(i2c->dev,
 194                                 "Failed to get PIO reg. write descriptor.\n");
 195                         goto select_init_pio_fail;
 196                 }
 197
 198                 /* Queue the DMA data transfer. */
 199                 sg_init_one(&i2c->sg_io[0], &i2c->addr_data, 1);
 200                 dma_map_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
 201                 desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[0], 1,
 202                                         DMA_MEM_TO_DEV,
 203                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 204                 if (!desc) {
 205                         dev_err(i2c->dev,
 206                                 "Failed to get DMA data write descriptor.\n");
 207                         goto select_init_dma_fail;
 208                 }
 209
 210                 /*
 211                  * READ command.
 212                  */
 213
 214                 /* Queue the PIO register write transfer. */
 215                 i2c->pio_data[1] = flags | MXS_CMD_I2C_READ |
 216                                 MXS_I2C_CTRL0_XFER_COUNT(msg->len);
 217                 desc = dmaengine_prep_slave_sg(i2c->dmach,
 218                                         (struct scatterlist *)&i2c->pio_data[1],
 219                                         1, DMA_TRANS_NONE, DMA_PREP_INTERRUPT);
 220                 if (!desc) {
 221                         dev_err(i2c->dev,
 222                                 "Failed to get PIO reg. write descriptor.\n");
 223                         goto select_init_dma_fail;
 224                 }
 225
 226                 /* Queue the DMA data transfer. */
 227                 sg_init_one(&i2c->sg_io[1], msg->buf, msg->len);
 228                 dma_map_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
 229                 desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[1], 1,
 230                                         DMA_DEV_TO_MEM,
 231                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 232                 if (!desc) {
 233                         dev_err(i2c->dev,
 234                                 "Failed to get DMA data write descriptor.\n");
 235                         goto read_init_dma_fail;
 236                 }
 237         } else {
 238                 i2c->dma_read = 0;
 239                 i2c->addr_data = (msg->addr << 1) | I2C_SMBUS_WRITE;
 240
 241                 /*
 242                  * WRITE command.
 243                  */
 244
 245                 /* Queue the PIO register write transfer. */
 246                 i2c->pio_data[0] = flags | MXS_CMD_I2C_WRITE |
 247                                 MXS_I2C_CTRL0_XFER_COUNT(msg->len + 1);
 248                 desc = dmaengine_prep_slave_sg(i2c->dmach,
 249                                         (struct scatterlist *)&i2c->pio_data[0],
 250                                         1, DMA_TRANS_NONE, 0);
 251                 if (!desc) {
 252                         dev_err(i2c->dev,
 253                                 "Failed to get PIO reg. write descriptor.\n");
 254                         goto write_init_pio_fail;
 255                 }
 256
 257                 /* Queue the DMA data transfer. */
 258                 sg_init_table(i2c->sg_io, 2);
 259                 sg_set_buf(&i2c->sg_io[0], &i2c->addr_data, 1);
 260                 sg_set_buf(&i2c->sg_io[1], msg->buf, msg->len);
 261                 dma_map_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
 262                 desc = dmaengine_prep_slave_sg(i2c->dmach, i2c->sg_io, 2,
 263                                         DMA_MEM_TO_DEV,
 264                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 265                 if (!desc) {
 266                         dev_err(i2c->dev,
 267                                 "Failed to get DMA data write descriptor.\n");
 268                         goto write_init_dma_fail;
 269                 }
 270         }
 271
 272         /*
 273          * The last descriptor must have this callback,
 274          * to finish the DMA transaction.
 275          */
 276         desc->callback = mxs_i2c_dma_irq_callback;
 277         desc->callback_param = i2c;
 278
 279         /* Start the transfer. */
 280         dmaengine_submit(desc);
 281         dma_async_issue_pending(i2c->dmach);
 282         return 0;
 283
 284 /* Read failpath. */
 285 read_init_dma_fail:
 286         dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
 287 select_init_dma_fail:
 288         dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
 289 select_init_pio_fail:
 290         dmaengine_terminate_all(i2c->dmach);
 291         return -EINVAL;
 292
 293 /* Write failpath. */
 294 write_init_dma_fail:
 295         dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
 296 write_init_pio_fail:
 297         dmaengine_terminate_all(i2c->dmach);
 298         return -EINVAL;
 299 }
 300
 301 /*
 302  * Low level master read/write transaction.
 303  */
 304 static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,
 305                                 int stop)
 306 {
 307         struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
 308         int ret;
 309         int flags;
 310
 311         flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0;
 312
 313         dev_dbg(i2c->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
 314                 msg->addr, msg->len, msg->flags, stop);
 315
 316         if (msg->len == 0)
 317                 return -EINVAL;
 318
 319         INIT_COMPLETION(i2c->cmd_complete);
 320         i2c->cmd_err = 0;
 321
 322         ret = mxs_i2c_dma_setup_xfer(adap, msg, flags);
 323         if (ret)
 324                 return ret;
 325
 326         ret = wait_for_completion_timeout(&i2c->cmd_complete,
 327                                                 msecs_to_jiffies(1000));
 328         if (ret == 0)
 329                 goto timeout;
 330
 331         if (i2c->cmd_err == -ENXIO)
 332                 mxs_i2c_reset(i2c);
 333
 334         dev_dbg(i2c->dev, "Done with err=%d\n", i2c->cmd_err);
 335
 336         return i2c->cmd_err;
 337
 338 timeout:
 339         dev_dbg(i2c->dev, "Timeout!\n");
 340         mxs_i2c_dma_finish(i2c);
 341         mxs_i2c_reset(i2c);
 342         return -ETIMEDOUT;
 343 }
 344
 345 static int mxs_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
 346                         int num)
 347 {
 348         int i;
 349         int err;
 350
 351         for (i = 0; i < num; i++) {
 352                 err = mxs_i2c_xfer_msg(adap, &msgs[i], i == (num - 1));
 353                 if (err)
 354                         return err;
 355         }
 356
 357         return num;
 358 }
 359
 360 static u32 mxs_i2c_func(struct i2c_adapter *adap)
 361 {
 362         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 363 }
 364
 365 static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id)
 366 {
 367         struct mxs_i2c_dev *i2c = dev_id;
 368         u32 stat = readl(i2c->regs + MXS_I2C_CTRL1) & MXS_I2C_IRQ_MASK;
 369
 370         if (!stat)
 371                 return IRQ_NONE;
 372
 373         if (stat & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)
 374                 i2c->cmd_err = -ENXIO;
 375         else if (stat & (MXS_I2C_CTRL1_EARLY_TERM_IRQ |
 376                     MXS_I2C_CTRL1_MASTER_LOSS_IRQ |
 377                     MXS_I2C_CTRL1_SLAVE_STOP_IRQ | MXS_I2C_CTRL1_SLAVE_IRQ))
 378                 /* MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ is only for slaves */
 379                 i2c->cmd_err = -EIO;
 380
 381         writel(stat, i2c->regs + MXS_I2C_CTRL1_CLR);
 382
 383         return IRQ_HANDLED;
 384 }
 385
 386 static const struct i2c_algorithm mxs_i2c_algo = {
 387         .master_xfer = mxs_i2c_xfer,
 388         .functionality = mxs_i2c_func,
 389 };
 390
 391 static bool mxs_i2c_dma_filter(struct dma_chan *chan, void *param)
 392 {
 393         struct mxs_i2c_dev *i2c = param;
 394
 395         if (!mxs_dma_is_apbx(chan))
 396                 return false;
 397
 398         if (chan->chan_id != i2c->dma_channel)
 399                 return false;
 400
 401         chan->private = &i2c->dma_data;
 402
 403         return true;
 404 }
 405
 406 static int mxs_i2c_get_ofdata(struct mxs_i2c_dev *i2c)
 407 {
 408         uint32_t speed;
 409         struct device *dev = i2c->dev;
 410         struct device_node *node = dev->of_node;
 411         int ret;
 412
 413         /*
 414          * TODO: This is a temporary solution and should be changed
 415          * to use generic DMA binding later when the helpers get in.
 416          */
 417         ret = of_property_read_u32(node, "fsl,i2c-dma-channel",
 418                                    &i2c->dma_channel);
 419         if (ret) {
 420                 dev_err(dev, "Failed to get DMA channel!\n");
 421                 return -ENODEV;
 422         }
 423
 424         ret = of_property_read_u32(node, "clock-frequency", &speed);
 425         if (ret)
 426                 dev_warn(dev, "No I2C speed selected, using 100kHz\n");
 427         else if (speed == 400000)
 428                 i2c->speed = &mxs_i2c_400kHz_config;
 429         else if (speed != 100000)
 430                 dev_warn(dev, "Unsupported I2C speed selected, using 100kHz\n");
 431
 432         return 0;
 433 }
 434
 435 static int mxs_i2c_probe(struct platform_device *pdev)
 436 {
 437         struct device *dev = &pdev->dev;
 438         struct mxs_i2c_dev *i2c;
 439         struct i2c_adapter *adap;
 440         struct pinctrl *pinctrl;
 441         struct resource *res;
 442         resource_size_t res_size;
 443         int err, irq, dmairq;
 444         dma_cap_mask_t mask;
 445
 446         pinctrl = devm_pinctrl_get_select_default(dev);
 447         if (IS_ERR(pinctrl))
 448                 return PTR_ERR(pinctrl);
 449
 450         i2c = devm_kzalloc(dev, sizeof(struct mxs_i2c_dev), GFP_KERNEL);
 451         if (!i2c)
 452                 return -ENOMEM;
 453
 454         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 455         irq = platform_get_irq(pdev, 0);
 456         dmairq = platform_get_irq(pdev, 1);
 457
 458         if (!res || irq < 0 || dmairq < 0)
 459                 return -ENOENT;
 460
 461         res_size = resource_size(res);
 462         if (!devm_request_mem_region(dev, res->start, res_size, res->name))
 463                 return -EBUSY;
 464
 465         i2c->regs = devm_ioremap_nocache(dev, res->start, res_size);
 466         if (!i2c->regs)
 467                 return -EBUSY;
 468
 469         err = devm_request_irq(dev, irq, mxs_i2c_isr, 0, dev_name(dev), i2c);
 470         if (err)
 471                 return err;
 472
 473         i2c->dev = dev;
 474         i2c->speed = &mxs_i2c_95kHz_config;
 475
 476         init_completion(&i2c->cmd_complete);
 477
 478         if (dev->of_node) {
 479                 err = mxs_i2c_get_ofdata(i2c);
 480                 if (err)
 481                         return err;
 482         }
 483
 484         /* Setup the DMA */
 485         dma_cap_zero(mask);
 486         dma_cap_set(DMA_SLAVE, mask);
 487         i2c->dma_data.chan_irq = dmairq;
 488         i2c->dmach = dma_request_channel(mask, mxs_i2c_dma_filter, i2c);
 489         if (!i2c->dmach) {
 490                 dev_err(dev, "Failed to request dma\n");
 491                 return -ENODEV;
 492         }
 493
 494         platform_set_drvdata(pdev, i2c);
 495
 496         /* Do reset to enforce correct startup after pinmuxing */
 497         mxs_i2c_reset(i2c);
 498
 499         adap = &i2c->adapter;
 500         strlcpy(adap->name, "MXS I2C adapter", sizeof(adap->name));
 501         adap->owner = THIS_MODULE;
 502         adap->algo = &mxs_i2c_algo;
 503         adap->dev.parent = dev;
 504         adap->nr = pdev->id;
 505         adap->dev.of_node = pdev->dev.of_node;
 506         i2c_set_adapdata(adap, i2c);
 507         err = i2c_add_numbered_adapter(adap);
 508         if (err) {
 509                 dev_err(dev, "Failed to add adapter (%d)\n", err);
 510                 writel(MXS_I2C_CTRL0_SFTRST,
 511                                 i2c->regs + MXS_I2C_CTRL0_SET);
 512                 return err;
 513         }
 514
 515         of_i2c_register_devices(adap);
 516
 517         return 0;
 518 }
 519
 520 static int mxs_i2c_remove(struct platform_device *pdev)
 521 {
 522         struct mxs_i2c_dev *i2c = platform_get_drvdata(pdev);
 523         int ret;
 524
 525         ret = i2c_del_adapter(&i2c->adapter);
 526         if (ret)
 527                 return -EBUSY;
 528
 529         if (i2c->dmach)
 530                 dma_release_channel(i2c->dmach);
 531
 532         writel(MXS_I2C_CTRL0_SFTRST, i2c->regs + MXS_I2C_CTRL0_SET);
 533
 534         platform_set_drvdata(pdev, NULL);
 535
 536         return 0;
 537 }
 538
 539 static const struct of_device_id mxs_i2c_dt_ids[] = {
 540         { .compatible = "fsl,imx28-i2c", },
 541         { /* sentinel */ }
 542 };
 543 MODULE_DEVICE_TABLE(of, mxs_i2c_dt_ids);
 544
 545 static struct platform_driver mxs_i2c_driver = {
 546         .driver = {
 547                    .name = DRIVER_NAME,
 548                    .owner = THIS_MODULE,
 549                    .of_match_table = mxs_i2c_dt_ids,
 550                    },
 551         .remove = mxs_i2c_remove,
 552 };
 553
 554 static int __init mxs_i2c_init(void)
 555 {
 556         return platform_driver_probe(&mxs_i2c_driver, mxs_i2c_probe);
 557 }
 558 subsys_initcall(mxs_i2c_init);
 559
 560 static void __exit mxs_i2c_exit(void)
 561 {
 562         platform_driver_unregister(&mxs_i2c_driver);
 563 }
 564 module_exit(mxs_i2c_exit);
 565
 566 MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>");
 567 MODULE_DESCRIPTION("MXS I2C Bus Driver");
 568 MODULE_LICENSE("GPL");
 569 MODULE_ALIAS("platform:" DRIVER_NAME);