drivers/i2c/busses/i2c-eg20t.c

   1 /*
   2  * Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, write to the Free Software
  15  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/delay.h>
  21 #include <linux/init.h>
  22 #include <linux/errno.h>
  23 #include <linux/i2c.h>
  24 #include <linux/fs.h>
  25 #include <linux/io.h>
  26 #include <linux/types.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/jiffies.h>
  29 #include <linux/pci.h>
  30 #include <linux/mutex.h>
  31 #include <linux/ktime.h>
  32 #include <linux/slab.h>
  33
  34 #define PCH_EVENT_SET   0       /* I2C Interrupt Event Set Status */
  35 #define PCH_EVENT_NONE  1       /* I2C Interrupt Event Clear Status */
  36 #define PCH_MAX_CLK             100000  /* Maximum Clock speed in MHz */
  37 #define PCH_BUFFER_MODE_ENABLE  0x0002  /* flag for Buffer mode enable */
  38 #define PCH_EEPROM_SW_RST_MODE_ENABLE   0x0008  /* EEPROM SW RST enable flag */
  39
  40 #define PCH_I2CSADR     0x00    /* I2C slave address register */
  41 #define PCH_I2CCTL      0x04    /* I2C control register */
  42 #define PCH_I2CSR       0x08    /* I2C status register */
  43 #define PCH_I2CDR       0x0C    /* I2C data register */
  44 #define PCH_I2CMON      0x10    /* I2C bus monitor register */
  45 #define PCH_I2CBC       0x14    /* I2C bus transfer rate setup counter */
  46 #define PCH_I2CMOD      0x18    /* I2C mode register */
  47 #define PCH_I2CBUFSLV   0x1C    /* I2C buffer mode slave address register */
  48 #define PCH_I2CBUFSUB   0x20    /* I2C buffer mode subaddress register */
  49 #define PCH_I2CBUFFOR   0x24    /* I2C buffer mode format register */
  50 #define PCH_I2CBUFCTL   0x28    /* I2C buffer mode control register */
  51 #define PCH_I2CBUFMSK   0x2C    /* I2C buffer mode interrupt mask register */
  52 #define PCH_I2CBUFSTA   0x30    /* I2C buffer mode status register */
  53 #define PCH_I2CBUFLEV   0x34    /* I2C buffer mode level register */
  54 #define PCH_I2CESRFOR   0x38    /* EEPROM software reset mode format register */
  55 #define PCH_I2CESRCTL   0x3C    /* EEPROM software reset mode ctrl register */
  56 #define PCH_I2CESRMSK   0x40    /* EEPROM software reset mode */
  57 #define PCH_I2CESRSTA   0x44    /* EEPROM software reset mode status register */
  58 #define PCH_I2CTMR      0x48    /* I2C timer register */
  59 #define PCH_I2CSRST     0xFC    /* I2C reset register */
  60 #define PCH_I2CNF       0xF8    /* I2C noise filter register */
  61
  62 #define BUS_IDLE_TIMEOUT        20
  63 #define PCH_I2CCTL_I2CMEN       0x0080
  64 #define TEN_BIT_ADDR_DEFAULT    0xF000
  65 #define TEN_BIT_ADDR_MASK       0xF0
  66 #define PCH_START               0x0020
  67 #define PCH_RESTART             0x0004
  68 #define PCH_ESR_START           0x0001
  69 #define PCH_BUFF_START          0x1
  70 #define PCH_REPSTART            0x0004
  71 #define PCH_ACK                 0x0008
  72 #define PCH_GETACK              0x0001
  73 #define CLR_REG                 0x0
  74 #define I2C_RD                  0x1
  75 #define I2CMCF_BIT              0x0080
  76 #define I2CMIF_BIT              0x0002
  77 #define I2CMAL_BIT              0x0010
  78 #define I2CBMFI_BIT             0x0001
  79 #define I2CBMAL_BIT             0x0002
  80 #define I2CBMNA_BIT             0x0004
  81 #define I2CBMTO_BIT             0x0008
  82 #define I2CBMIS_BIT             0x0010
  83 #define I2CESRFI_BIT            0X0001
  84 #define I2CESRTO_BIT            0x0002
  85 #define I2CESRFIIE_BIT          0x1
  86 #define I2CESRTOIE_BIT          0x2
  87 #define I2CBMDZ_BIT             0x0040
  88 #define I2CBMAG_BIT             0x0020
  89 #define I2CMBB_BIT              0x0020
  90 #define BUFFER_MODE_MASK        (I2CBMFI_BIT | I2CBMAL_BIT | I2CBMNA_BIT | \
  91                                 I2CBMTO_BIT | I2CBMIS_BIT)
  92 #define I2C_ADDR_MSK            0xFF
  93 #define I2C_MSB_2B_MSK          0x300
  94 #define FAST_MODE_CLK           400
  95 #define FAST_MODE_EN            0x0001
  96 #define SUB_ADDR_LEN_MAX        4
  97 #define BUF_LEN_MAX             32
  98 #define PCH_BUFFER_MODE         0x1
  99 #define EEPROM_SW_RST_MODE      0x0002
 100 #define NORMAL_INTR_ENBL        0x0300
 101 #define EEPROM_RST_INTR_ENBL    (I2CESRFIIE_BIT | I2CESRTOIE_BIT)
 102 #define EEPROM_RST_INTR_DISBL   0x0
 103 #define BUFFER_MODE_INTR_ENBL   0x001F
 104 #define BUFFER_MODE_INTR_DISBL  0x0
 105 #define NORMAL_MODE             0x0
 106 #define BUFFER_MODE             0x1
 107 #define EEPROM_SR_MODE          0x2
 108 #define I2C_TX_MODE             0x0010
 109 #define PCH_BUF_TX              0xFFF7
 110 #define PCH_BUF_RD              0x0008
 111 #define I2C_ERROR_MASK  (I2CESRTO_EVENT | I2CBMIS_EVENT | I2CBMTO_EVENT | \
 112                         I2CBMNA_EVENT | I2CBMAL_EVENT | I2CMAL_EVENT)
 113 #define I2CMAL_EVENT            0x0001
 114 #define I2CMCF_EVENT            0x0002
 115 #define I2CBMFI_EVENT           0x0004
 116 #define I2CBMAL_EVENT           0x0008
 117 #define I2CBMNA_EVENT           0x0010
 118 #define I2CBMTO_EVENT           0x0020
 119 #define I2CBMIS_EVENT           0x0040
 120 #define I2CESRFI_EVENT          0x0080
 121 #define I2CESRTO_EVENT          0x0100
 122 #define PCI_DEVICE_ID_PCH_I2C   0x8817
 123
 124 #define pch_dbg(adap, fmt, arg...)  \
 125         dev_dbg(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
 126
 127 #define pch_err(adap, fmt, arg...)  \
 128         dev_err(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
 129
 130 #define pch_pci_err(pdev, fmt, arg...)  \
 131         dev_err(&pdev->dev, "%s :" fmt, __func__, ##arg)
 132
 133 #define pch_pci_dbg(pdev, fmt, arg...)  \
 134         dev_dbg(&pdev->dev, "%s :" fmt, __func__, ##arg)
 135
 136 /*
 137 Set the number of I2C instance max
 138 Intel EG20T PCH :               1ch
 139 OKI SEMICONDUCTOR ML7213 IOH :  2ch
 140 */
 141 #define PCH_I2C_MAX_DEV                 2
 142
 143 /**
 144  * struct i2c_algo_pch_data - for I2C driver functionalities
 145  * @pch_adapter:                stores the reference to i2c_adapter structure
 146  * @p_adapter_info:             stores the reference to adapter_info structure
 147  * @pch_base_address:           specifies the remapped base address
 148  * @pch_buff_mode_en:           specifies if buffer mode is enabled
 149  * @pch_event_flag:             specifies occurrence of interrupt events
 150  * @pch_i2c_xfer_in_progress:   specifies whether the transfer is completed
 151  */
 152 struct i2c_algo_pch_data {
 153         struct i2c_adapter pch_adapter;
 154         struct adapter_info *p_adapter_info;
 155         void __iomem *pch_base_address;
 156         int pch_buff_mode_en;
 157         u32 pch_event_flag;
 158         bool pch_i2c_xfer_in_progress;
 159 };
 160
 161 /**
 162  * struct adapter_info - This structure holds the adapter information for the
 163                          PCH i2c controller
 164  * @pch_data:           stores a list of i2c_algo_pch_data
 165  * @pch_i2c_suspended:  specifies whether the system is suspended or not
 166  *                      perhaps with more lines and words.
 167  * @ch_num:             specifies the number of i2c instance
 168  *
 169  * pch_data has as many elements as maximum I2C channels
 170  */
 171 struct adapter_info {
 172         struct i2c_algo_pch_data pch_data[PCH_I2C_MAX_DEV];
 173         bool pch_i2c_suspended;
 174         int ch_num;
 175 };
 176
 177
 178 static int pch_i2c_speed = 100; /* I2C bus speed in Kbps */
 179 static int pch_clk = 50000;     /* specifies I2C clock speed in KHz */
 180 static wait_queue_head_t pch_event;
 181 static DEFINE_MUTEX(pch_mutex);
 182
 183 /* Definition for ML7213 by OKI SEMICONDUCTOR */
 184 #define PCI_VENDOR_ID_ROHM              0x10DB
 185 #define PCI_DEVICE_ID_ML7213_I2C        0x802D
 186 #define PCI_DEVICE_ID_ML7223_I2C        0x8010
 187
 188 static struct pci_device_id __devinitdata pch_pcidev_id[] = {
 189         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH_I2C),   1, },
 190         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_I2C), 2, },
 191         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_I2C), 1, },
 192         {0,}
 193 };
 194
 195 static irqreturn_t pch_i2c_handler(int irq, void *pData);
 196
 197 static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask)
 198 {
 199         u32 val;
 200         val = ioread32(addr + offset);
 201         val |= bitmask;
 202         iowrite32(val, addr + offset);
 203 }
 204
 205 static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask)
 206 {
 207         u32 val;
 208         val = ioread32(addr + offset);
 209         val &= (~bitmask);
 210         iowrite32(val, addr + offset);
 211 }
 212
 213 /**
 214  * pch_i2c_init() - hardware initialization of I2C module
 215  * @adap:       Pointer to struct i2c_algo_pch_data.
 216  */
 217 static void pch_i2c_init(struct i2c_algo_pch_data *adap)
 218 {
 219         void __iomem *p = adap->pch_base_address;
 220         u32 pch_i2cbc;
 221         u32 pch_i2ctmr;
 222         u32 reg_value;
 223
 224         /* reset I2C controller */
 225         iowrite32(0x01, p + PCH_I2CSRST);
 226         msleep(20);
 227         iowrite32(0x0, p + PCH_I2CSRST);
 228
 229         /* Initialize I2C registers */
 230         iowrite32(0x21, p + PCH_I2CNF);
 231
 232         pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_I2CCTL_I2CMEN);
 233
 234         if (pch_i2c_speed != 400)
 235                 pch_i2c_speed = 100;
 236
 237         reg_value = PCH_I2CCTL_I2CMEN;
 238         if (pch_i2c_speed == FAST_MODE_CLK) {
 239                 reg_value |= FAST_MODE_EN;
 240                 pch_dbg(adap, "Fast mode enabled\n");
 241         }
 242
 243         if (pch_clk > PCH_MAX_CLK)
 244                 pch_clk = 62500;
 245
 246         pch_i2cbc = (pch_clk + (pch_i2c_speed * 4)) / pch_i2c_speed * 8;
 247         /* Set transfer speed in I2CBC */
 248         iowrite32(pch_i2cbc, p + PCH_I2CBC);
 249
 250         pch_i2ctmr = (pch_clk) / 8;
 251         iowrite32(pch_i2ctmr, p + PCH_I2CTMR);
 252
 253         reg_value |= NORMAL_INTR_ENBL;  /* Enable interrupts in normal mode */
 254         iowrite32(reg_value, p + PCH_I2CCTL);
 255
 256         pch_dbg(adap,
 257                 "I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
 258                 ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr);
 259
 260         init_waitqueue_head(&pch_event);
 261 }
 262
 263 static inline bool ktime_lt(const ktime_t cmp1, const ktime_t cmp2)
 264 {
 265         return cmp1.tv64 < cmp2.tv64;
 266 }
 267
 268 /**
 269  * pch_i2c_wait_for_bus_idle() - check the status of bus.
 270  * @adap:       Pointer to struct i2c_algo_pch_data.
 271  * @timeout:    waiting time counter (us).
 272  */
 273 static s32 pch_i2c_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
 274                                      s32 timeout)
 275 {
 276         void __iomem *p = adap->pch_base_address;
 277         ktime_t ns_val;
 278
 279         if ((ioread32(p + PCH_I2CSR) & I2CMBB_BIT) == 0)
 280                 return 0;
 281
 282         /* MAX timeout value is timeout*1000*1000nsec */
 283         ns_val = ktime_add_ns(ktime_get(), timeout*1000*1000);
 284         do {
 285                 msleep(20);
 286                 if ((ioread32(p + PCH_I2CSR) & I2CMBB_BIT) == 0)
 287                         return 0;
 288         } while (ktime_lt(ktime_get(), ns_val));
 289
 290         pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR));
 291         pch_err(adap, "%s: Timeout Error.return%d\n", __func__, -ETIME);
 292
 293         return -ETIME;
 294 }
 295
 296 /**
 297  * pch_i2c_start() - Generate I2C start condition in normal mode.
 298  * @adap:       Pointer to struct i2c_algo_pch_data.
 299  *
 300  * Generate I2C start condition in normal mode by setting I2CCTL.I2CMSTA to 1.
 301  */
 302 static void pch_i2c_start(struct i2c_algo_pch_data *adap)
 303 {
 304         void __iomem *p = adap->pch_base_address;
 305         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 306         pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
 307 }
 308
 309 /**
 310  * pch_i2c_wait_for_xfer_complete() - initiates a wait for the tx complete event
 311  * @adap:       Pointer to struct i2c_algo_pch_data.
 312  */
 313 static s32 pch_i2c_wait_for_xfer_complete(struct i2c_algo_pch_data *adap)
 314 {
 315         long ret;
 316         ret = wait_event_timeout(pch_event,
 317                         (adap->pch_event_flag != 0), msecs_to_jiffies(50));
 318
 319         if (ret == 0) {
 320                 pch_err(adap, "timeout: %x\n", adap->pch_event_flag);
 321                 return -ETIMEDOUT;
 322         }
 323
 324         if (adap->pch_event_flag & I2C_ERROR_MASK) {
 325                 pch_err(adap, "error bits set: %x\n", adap->pch_event_flag);
 326                 return -EIO;
 327         }
 328
 329         adap->pch_event_flag = 0;
 330
 331         return 0;
 332 }
 333
 334 /**
 335  * pch_i2c_getack() - to confirm ACK/NACK
 336  * @adap:       Pointer to struct i2c_algo_pch_data.
 337  */
 338 static s32 pch_i2c_getack(struct i2c_algo_pch_data *adap)
 339 {
 340         u32 reg_val;
 341         void __iomem *p = adap->pch_base_address;
 342         reg_val = ioread32(p + PCH_I2CSR) & PCH_GETACK;
 343
 344         if (reg_val != 0) {
 345                 pch_err(adap, "return%d\n", -EPROTO);
 346                 return -EPROTO;
 347         }
 348
 349         return 0;
 350 }
 351
 352 /**
 353  * pch_i2c_stop() - generate stop condition in normal mode.
 354  * @adap:       Pointer to struct i2c_algo_pch_data.
 355  */
 356 static void pch_i2c_stop(struct i2c_algo_pch_data *adap)
 357 {
 358         void __iomem *p = adap->pch_base_address;
 359         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 360         /* clear the start bit */
 361         pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
 362 }
 363
 364 /**
 365  * pch_i2c_repstart() - generate repeated start condition in normal mode
 366  * @adap:       Pointer to struct i2c_algo_pch_data.
 367  */
 368 static void pch_i2c_repstart(struct i2c_algo_pch_data *adap)
 369 {
 370         void __iomem *p = adap->pch_base_address;
 371         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 372         pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_REPSTART);
 373 }
 374
 375 /**
 376  * pch_i2c_writebytes() - write data to I2C bus in normal mode
 377  * @i2c_adap:   Pointer to the struct i2c_adapter.
 378  * @last:       specifies whether last message or not.
 379  *              In the case of compound mode it will be 1 for last message,
 380  *              otherwise 0.
 381  * @first:      specifies whether first message or not.
 382  *              1 for first message otherwise 0.
 383  */
 384 static s32 pch_i2c_writebytes(struct i2c_adapter *i2c_adap,
 385                               struct i2c_msg *msgs, u32 last, u32 first)
 386 {
 387         struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
 388         u8 *buf;
 389         u32 length;
 390         u32 addr;
 391         u32 addr_2_msb;
 392         u32 addr_8_lsb;
 393         s32 wrcount;
 394         s32 rtn;
 395         void __iomem *p = adap->pch_base_address;
 396
 397         length = msgs->len;
 398         buf = msgs->buf;
 399         addr = msgs->addr;
 400
 401         /* enable master tx */
 402         pch_setbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
 403
 404         pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n", ioread32(p + PCH_I2CCTL),
 405                 length);
 406
 407         if (first) {
 408                 if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
 409                         return -ETIME;
 410         }
 411
 412         if (msgs->flags & I2C_M_TEN) {
 413                 addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7) & 0x06;
 414                 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
 415                 if (first)
 416                         pch_i2c_start(adap);
 417
 418                 rtn = pch_i2c_wait_for_xfer_complete(adap);
 419                 if (rtn == 0) {
 420                         if (pch_i2c_getack(adap)) {
 421                                 pch_dbg(adap, "Receive NACK for slave address"
 422                                         "setting\n");
 423                                 return -EIO;
 424                         }
 425                         addr_8_lsb = (addr & I2C_ADDR_MSK);
 426                         iowrite32(addr_8_lsb, p + PCH_I2CDR);
 427                 } else if (rtn == -EIO) { /* Arbitration Lost */
 428                         pch_err(adap, "Lost Arbitration\n");
 429                         pch_clrbit(adap->pch_base_address, PCH_I2CSR,
 430                                    I2CMAL_BIT);
 431                         pch_clrbit(adap->pch_base_address, PCH_I2CSR,
 432                                    I2CMIF_BIT);
 433                         pch_i2c_init(adap);
 434                         return -EAGAIN;
 435                 } else { /* wait-event timeout */
 436                         pch_i2c_stop(adap);
 437                         return -ETIME;
 438                 }
 439         } else {
 440                 /* set 7 bit slave address and R/W bit as 0 */
 441                 iowrite32(addr << 1, p + PCH_I2CDR);
 442                 if (first)
 443                         pch_i2c_start(adap);
 444         }
 445
 446         rtn = pch_i2c_wait_for_xfer_complete(adap);
 447         if (rtn == 0) {
 448                 if (pch_i2c_getack(adap)) {
 449                         pch_dbg(adap, "Receive NACK for slave address"
 450                                 "setting\n");
 451                         return -EIO;
 452                 }
 453         } else if (rtn == -EIO) { /* Arbitration Lost */
 454                 pch_err(adap, "Lost Arbitration\n");
 455                 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMAL_BIT);
 456                 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT);
 457                 return -EAGAIN;
 458         } else { /* wait-event timeout */
 459                 return -ETIME;
 460         }
 461
 462         for (wrcount = 0; wrcount < length; ++wrcount) {
 463                 /* write buffer value to I2C data register */
 464                 iowrite32(buf[wrcount], p + PCH_I2CDR);
 465                 pch_dbg(adap, "writing %x to Data register\n", buf[wrcount]);
 466
 467                 rtn = pch_i2c_wait_for_xfer_complete(adap);
 468                 if (rtn == 0) {
 469                         if (pch_i2c_getack(adap)) {
 470                                 pch_dbg(adap, "Receive NACK for slave address"
 471                                         "setting\n");
 472                                 return -EIO;
 473                         }
 474                         pch_clrbit(adap->pch_base_address, PCH_I2CSR,
 475                                    I2CMCF_BIT);
 476                         pch_clrbit(adap->pch_base_address, PCH_I2CSR,
 477                                    I2CMIF_BIT);
 478                 } else { /* wait-event timeout */
 479                         return -ETIME;
 480                 }
 481         }
 482
 483         /* check if this is the last message */
 484         if (last)
 485                 pch_i2c_stop(adap);
 486         else
 487                 pch_i2c_repstart(adap);
 488
 489         pch_dbg(adap, "return=%d\n", wrcount);
 490
 491         return wrcount;
 492 }
 493
 494 /**
 495  * pch_i2c_sendack() - send ACK
 496  * @adap:       Pointer to struct i2c_algo_pch_data.
 497  */
 498 static void pch_i2c_sendack(struct i2c_algo_pch_data *adap)
 499 {
 500         void __iomem *p = adap->pch_base_address;
 501         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 502         pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
 503 }
 504
 505 /**
 506  * pch_i2c_sendnack() - send NACK
 507  * @adap:       Pointer to struct i2c_algo_pch_data.
 508  */
 509 static void pch_i2c_sendnack(struct i2c_algo_pch_data *adap)
 510 {
 511         void __iomem *p = adap->pch_base_address;
 512         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 513         pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
 514 }
 515
 516 /**
 517  * pch_i2c_restart() - Generate I2C restart condition in normal mode.
 518  * @adap:       Pointer to struct i2c_algo_pch_data.
 519  *
 520  * Generate I2C restart condition in normal mode by setting I2CCTL.I2CRSTA.
 521  */
 522 static void pch_i2c_restart(struct i2c_algo_pch_data *adap)
 523 {
 524         void __iomem *p = adap->pch_base_address;
 525         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 526         pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_RESTART);
 527 }
 528
 529 /**
 530  * pch_i2c_readbytes() - read data  from I2C bus in normal mode.
 531  * @i2c_adap:   Pointer to the struct i2c_adapter.
 532  * @msgs:       Pointer to i2c_msg structure.
 533  * @last:       specifies whether last message or not.
 534  * @first:      specifies whether first message or not.
 535  */
 536 static s32 pch_i2c_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
 537                              u32 last, u32 first)
 538 {
 539         struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
 540
 541         u8 *buf;
 542         u32 count;
 543         u32 length;
 544         u32 addr;
 545         u32 addr_2_msb;
 546         u32 addr_8_lsb;
 547         void __iomem *p = adap->pch_base_address;
 548         s32 rtn;
 549
 550         length = msgs->len;
 551         buf = msgs->buf;
 552         addr = msgs->addr;
 553
 554         /* enable master reception */
 555         pch_clrbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
 556
 557         if (first) {
 558                 if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
 559                         return -ETIME;
 560         }
 561
 562         if (msgs->flags & I2C_M_TEN) {
 563                 addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7);
 564                 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
 565                 if (first)
 566                         pch_i2c_start(adap);
 567
 568                 rtn = pch_i2c_wait_for_xfer_complete(adap);
 569                 if (rtn == 0) {
 570                         if (pch_i2c_getack(adap)) {
 571                                 pch_dbg(adap, "Receive NACK for slave address"
 572                                         "setting\n");
 573                                 return -EIO;
 574                         }
 575                         addr_8_lsb = (addr & I2C_ADDR_MSK);
 576                         iowrite32(addr_8_lsb, p + PCH_I2CDR);
 577                 } else if (rtn == -EIO) { /* Arbitration Lost */
 578                         pch_err(adap, "Lost Arbitration\n");
 579                         pch_clrbit(adap->pch_base_address, PCH_I2CSR,
 580                                    I2CMAL_BIT);
 581                         pch_clrbit(adap->pch_base_address, PCH_I2CSR,
 582                                    I2CMIF_BIT);
 583                         pch_i2c_init(adap);
 584                         return -EAGAIN;
 585                 } else { /* wait-event timeout */
 586                         pch_i2c_stop(adap);
 587                         return -ETIME;
 588                 }
 589                 pch_i2c_restart(adap);
 590                 rtn = pch_i2c_wait_for_xfer_complete(adap);
 591                 if (rtn == 0) {
 592                         if (pch_i2c_getack(adap)) {
 593                                 pch_dbg(adap, "Receive NACK for slave address"
 594                                         "setting\n");
 595                                 return -EIO;
 596                         }
 597                         addr_2_msb |= I2C_RD;
 598                         iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK,
 599                                   p + PCH_I2CDR);
 600                 } else if (rtn == -EIO) { /* Arbitration Lost */
 601                         pch_err(adap, "Lost Arbitration\n");
 602                         pch_clrbit(adap->pch_base_address, PCH_I2CSR,
 603                                    I2CMAL_BIT);
 604                         pch_clrbit(adap->pch_base_address, PCH_I2CSR,
 605                                    I2CMIF_BIT);
 606                         pch_i2c_init(adap);
 607                         return -EAGAIN;
 608                 } else { /* wait-event timeout */
 609                         pch_i2c_stop(adap);
 610                         return -ETIME;
 611                 }
 612         } else {
 613                 /* 7 address bits + R/W bit */
 614                 addr = (((addr) << 1) | (I2C_RD));
 615                 iowrite32(addr, p + PCH_I2CDR);
 616         }
 617
 618         /* check if it is the first message */
 619         if (first)
 620                 pch_i2c_start(adap);
 621
 622         rtn = pch_i2c_wait_for_xfer_complete(adap);
 623         if (rtn == 0) {
 624                 if (pch_i2c_getack(adap)) {
 625                         pch_dbg(adap, "Receive NACK for slave address"
 626                                 "setting\n");
 627                         return -EIO;
 628                 }
 629         } else if (rtn == -EIO) { /* Arbitration Lost */
 630                 pch_err(adap, "Lost Arbitration\n");
 631                 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMAL_BIT);
 632                 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT);
 633                 return -EAGAIN;
 634         } else { /* wait-event timeout */
 635                 return -ETIME;
 636         }
 637
 638         if (length == 0) {
 639                 pch_i2c_stop(adap);
 640                 ioread32(p + PCH_I2CDR); /* Dummy read needs */
 641
 642                 count = length;
 643         } else {
 644                 int read_index;
 645                 int loop;
 646                 pch_i2c_sendack(adap);
 647
 648                 /* Dummy read */
 649                 for (loop = 1, read_index = 0; loop < length; loop++) {
 650                         buf[read_index] = ioread32(p + PCH_I2CDR);
 651
 652                         if (loop != 1)
 653                                 read_index++;
 654
 655                         rtn = pch_i2c_wait_for_xfer_complete(adap);
 656                         if (rtn == 0) {
 657                                 if (pch_i2c_getack(adap)) {
 658                                         pch_dbg(adap, "Receive NACK for slave"
 659                                                 "address setting\n");
 660                                         return -EIO;
 661                                 }
 662                         } else { /* wait-event timeout */
 663                                 pch_i2c_stop(adap);
 664                                 return -ETIME;
 665                         }
 666
 667                 }       /* end for */
 668
 669                 pch_i2c_sendnack(adap);
 670
 671                 buf[read_index] = ioread32(p + PCH_I2CDR); /* Read final - 1 */
 672
 673                 if (length != 1)
 674                         read_index++;
 675
 676                 rtn = pch_i2c_wait_for_xfer_complete(adap);
 677                 if (rtn == 0) {
 678                         if (pch_i2c_getack(adap)) {
 679                                 pch_dbg(adap, "Receive NACK for slave"
 680                                         "address setting\n");
 681                                 return -EIO;
 682                         }
 683                 } else { /* wait-event timeout */
 684                         pch_i2c_stop(adap);
 685                         return -ETIME;
 686                 }
 687
 688                 if (last)
 689                         pch_i2c_stop(adap);
 690                 else
 691                         pch_i2c_repstart(adap);
 692
 693                 buf[read_index++] = ioread32(p + PCH_I2CDR); /* Read Final */
 694                 count = read_index;
 695         }
 696
 697         return count;
 698 }
 699
 700 /**
 701  * pch_i2c_cb() - Interrupt handler Call back function
 702  * @adap:       Pointer to struct i2c_algo_pch_data.
 703  */
 704 static void pch_i2c_cb(struct i2c_algo_pch_data *adap)
 705 {
 706         u32 sts;
 707         void __iomem *p = adap->pch_base_address;
 708
 709         sts = ioread32(p + PCH_I2CSR);
 710         sts &= (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT);
 711         if (sts & I2CMAL_BIT)
 712                 adap->pch_event_flag |= I2CMAL_EVENT;
 713
 714         if (sts & I2CMCF_BIT)
 715                 adap->pch_event_flag |= I2CMCF_EVENT;
 716
 717         /* clear the applicable bits */
 718         pch_clrbit(adap->pch_base_address, PCH_I2CSR, sts);
 719
 720         pch_dbg(adap, "PCH_I2CSR = %x\n", ioread32(p + PCH_I2CSR));
 721
 722         wake_up(&pch_event);
 723 }
 724
 725 /**
 726  * pch_i2c_handler() - interrupt handler for the PCH I2C controller
 727  * @irq:        irq number.
 728  * @pData:      cookie passed back to the handler function.
 729  */
 730 static irqreturn_t pch_i2c_handler(int irq, void *pData)
 731 {
 732         u32 reg_val;
 733         int flag;
 734         int i;
 735         struct adapter_info *adap_info = pData;
 736         void __iomem *p;
 737         u32 mode;
 738
 739         for (i = 0, flag = 0; i < adap_info->ch_num; i++) {
 740                 p = adap_info->pch_data[i].pch_base_address;
 741                 mode = ioread32(p + PCH_I2CMOD);
 742                 mode &= BUFFER_MODE | EEPROM_SR_MODE;
 743                 if (mode != NORMAL_MODE) {
 744                         pch_err(adap_info->pch_data,
 745                                 "I2C-%d mode(%d) is not supported\n", mode, i);
 746                         continue;
 747                 }
 748                 reg_val = ioread32(p + PCH_I2CSR);
 749                 if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT)) {
 750                         pch_i2c_cb(&adap_info->pch_data[i]);
 751                         flag = 1;
 752                 }
 753         }
 754
 755         return flag ? IRQ_HANDLED : IRQ_NONE;
 756 }
 757
 758 /**
 759  * pch_i2c_xfer() - Reading adnd writing data through I2C bus
 760  * @i2c_adap:   Pointer to the struct i2c_adapter.
 761  * @msgs:       Pointer to i2c_msg structure.
 762  * @num:        number of messages.
 763  */
 764 static s32 pch_i2c_xfer(struct i2c_adapter *i2c_adap,
 765                         struct i2c_msg *msgs, s32 num)
 766 {
 767         struct i2c_msg *pmsg;
 768         u32 i = 0;
 769         u32 status;
 770         u32 msglen;
 771         u32 subaddrlen;
 772         s32 ret;
 773
 774         struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
 775
 776         ret = mutex_lock_interruptible(&pch_mutex);
 777         if (ret)
 778                 return -ERESTARTSYS;
 779
 780         if (adap->p_adapter_info->pch_i2c_suspended) {
 781                 mutex_unlock(&pch_mutex);
 782                 return -EBUSY;
 783         }
 784
 785         pch_dbg(adap, "adap->p_adapter_info->pch_i2c_suspended is %d\n",
 786                 adap->p_adapter_info->pch_i2c_suspended);
 787         /* transfer not completed */
 788         adap->pch_i2c_xfer_in_progress = true;
 789
 790         for (i = 0; i < num && ret >= 0; i++) {
 791                 pmsg = &msgs[i];
 792                 pmsg->flags |= adap->pch_buff_mode_en;
 793                 status = pmsg->flags;
 794                 pch_dbg(adap,
 795                         "After invoking I2C_MODE_SEL :flag= 0x%x\n", status);
 796                 /* calculate sub address length and message length */
 797                 /* these are applicable only for buffer mode */
 798                 subaddrlen = pmsg->buf[0];
 799                 /* calculate actual message length excluding
 800                  * the sub address fields */
 801                 msglen = (pmsg->len) - (subaddrlen + 1);
 802
 803                 if ((status & (I2C_M_RD)) != false) {
 804                         ret = pch_i2c_readbytes(i2c_adap, pmsg, (i + 1 == num),
 805                                                 (i == 0));
 806                 } else {
 807                         ret = pch_i2c_writebytes(i2c_adap, pmsg, (i + 1 == num),
 808                                                  (i == 0));
 809                 }
 810         }
 811
 812         adap->pch_i2c_xfer_in_progress = false; /* transfer completed */
 813
 814         mutex_unlock(&pch_mutex);
 815
 816         return (ret < 0) ? ret : num;
 817 }
 818
 819 /**
 820  * pch_i2c_func() - return the functionality of the I2C driver
 821  * @adap:       Pointer to struct i2c_algo_pch_data.
 822  */
 823 static u32 pch_i2c_func(struct i2c_adapter *adap)
 824 {
 825         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
 826 }
 827
 828 static struct i2c_algorithm pch_algorithm = {
 829         .master_xfer = pch_i2c_xfer,
 830         .functionality = pch_i2c_func
 831 };
 832
 833 /**
 834  * pch_i2c_disbl_int() - Disable PCH I2C interrupts
 835  * @adap:       Pointer to struct i2c_algo_pch_data.
 836  */
 837 static void pch_i2c_disbl_int(struct i2c_algo_pch_data *adap)
 838 {
 839         void __iomem *p = adap->pch_base_address;
 840
 841         pch_clrbit(adap->pch_base_address, PCH_I2CCTL, NORMAL_INTR_ENBL);
 842
 843         iowrite32(EEPROM_RST_INTR_DISBL, p + PCH_I2CESRMSK);
 844
 845         iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK);
 846 }
 847
 848 static int __devinit pch_i2c_probe(struct pci_dev *pdev,
 849                                    const struct pci_device_id *id)
 850 {
 851         void __iomem *base_addr;
 852         int ret;
 853         int i, j;
 854         struct adapter_info *adap_info;
 855         struct i2c_adapter *pch_adap;
 856
 857         pch_pci_dbg(pdev, "Entered.\n");
 858
 859         adap_info = kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
 860         if (adap_info == NULL) {
 861                 pch_pci_err(pdev, "Memory allocation FAILED\n");
 862                 return -ENOMEM;
 863         }
 864
 865         ret = pci_enable_device(pdev);
 866         if (ret) {
 867                 pch_pci_err(pdev, "pci_enable_device FAILED\n");
 868                 goto err_pci_enable;
 869         }
 870
 871         ret = pci_request_regions(pdev, KBUILD_MODNAME);
 872         if (ret) {
 873                 pch_pci_err(pdev, "pci_request_regions FAILED\n");
 874                 goto err_pci_req;
 875         }
 876
 877         base_addr = pci_iomap(pdev, 1, 0);
 878
 879         if (base_addr == NULL) {
 880                 pch_pci_err(pdev, "pci_iomap FAILED\n");
 881                 ret = -ENOMEM;
 882                 goto err_pci_iomap;
 883         }
 884
 885         /* Set the number of I2C channel instance */
 886         adap_info->ch_num = id->driver_data;
 887
 888         for (i = 0; i < adap_info->ch_num; i++) {
 889                 pch_adap = &adap_info->pch_data[i].pch_adapter;
 890                 adap_info->pch_i2c_suspended = false;
 891
 892                 adap_info->pch_data[i].p_adapter_info = adap_info;
 893
 894                 pch_adap->owner = THIS_MODULE;
 895                 pch_adap->class = I2C_CLASS_HWMON;
 896                 strcpy(pch_adap->name, KBUILD_MODNAME);
 897                 pch_adap->algo = &pch_algorithm;
 898                 pch_adap->algo_data = &adap_info->pch_data[i];
 899
 900                 /* base_addr + offset; */
 901                 adap_info->pch_data[i].pch_base_address = base_addr + 0x100 * i;
 902
 903                 pch_adap->dev.parent = &pdev->dev;
 904
 905                 ret = i2c_add_adapter(pch_adap);
 906                 if (ret) {
 907                         pch_pci_err(pdev, "i2c_add_adapter[ch:%d] FAILED\n", i);
 908                         goto err_i2c_add_adapter;
 909                 }
 910
 911                 pch_i2c_init(&adap_info->pch_data[i]);
 912         }
 913         ret = request_irq(pdev->irq, pch_i2c_handler, IRQF_SHARED,
 914                   KBUILD_MODNAME, adap_info);
 915         if (ret) {
 916                 pch_pci_err(pdev, "request_irq FAILED\n");
 917                 goto err_i2c_add_adapter;
 918         }
 919
 920         pci_set_drvdata(pdev, adap_info);
 921         pch_pci_dbg(pdev, "returns %d.\n", ret);
 922         return 0;
 923
 924 err_i2c_add_adapter:
 925         for (j = 0; j < i; j++)
 926                 i2c_del_adapter(&adap_info->pch_data[j].pch_adapter);
 927         pci_iounmap(pdev, base_addr);
 928 err_pci_iomap:
 929         pci_release_regions(pdev);
 930 err_pci_req:
 931         pci_disable_device(pdev);
 932 err_pci_enable:
 933         kfree(adap_info);
 934         return ret;
 935 }
 936
 937 static void __devexit pch_i2c_remove(struct pci_dev *pdev)
 938 {
 939         int i;
 940         struct adapter_info *adap_info = pci_get_drvdata(pdev);
 941
 942         free_irq(pdev->irq, adap_info);
 943
 944         for (i = 0; i < adap_info->ch_num; i++) {
 945                 pch_i2c_disbl_int(&adap_info->pch_data[i]);
 946                 i2c_del_adapter(&adap_info->pch_data[i].pch_adapter);
 947         }
 948
 949         if (adap_info->pch_data[0].pch_base_address)
 950                 pci_iounmap(pdev, adap_info->pch_data[0].pch_base_address);
 951
 952         for (i = 0; i < adap_info->ch_num; i++)
 953                 adap_info->pch_data[i].pch_base_address = 0;
 954
 955         pci_set_drvdata(pdev, NULL);
 956
 957         pci_release_regions(pdev);
 958
 959         pci_disable_device(pdev);
 960         kfree(adap_info);
 961 }
 962
 963 #ifdef CONFIG_PM
 964 static int pch_i2c_suspend(struct pci_dev *pdev, pm_message_t state)
 965 {
 966         int ret;
 967         int i;
 968         struct adapter_info *adap_info = pci_get_drvdata(pdev);
 969         void __iomem *p = adap_info->pch_data[0].pch_base_address;
 970
 971         adap_info->pch_i2c_suspended = true;
 972
 973         for (i = 0; i < adap_info->ch_num; i++) {
 974                 while ((adap_info->pch_data[i].pch_i2c_xfer_in_progress)) {
 975                         /* Wait until all channel transfers are completed */
 976                         msleep(20);
 977                 }
 978         }
 979
 980         /* Disable the i2c interrupts */
 981         for (i = 0; i < adap_info->ch_num; i++)
 982                 pch_i2c_disbl_int(&adap_info->pch_data[i]);
 983
 984         pch_pci_dbg(pdev, "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
 985                 "invoked function pch_i2c_disbl_int successfully\n",
 986                 ioread32(p + PCH_I2CSR), ioread32(p + PCH_I2CBUFSTA),
 987                 ioread32(p + PCH_I2CESRSTA));
 988
 989         ret = pci_save_state(pdev);
 990
 991         if (ret) {
 992                 pch_pci_err(pdev, "pci_save_state\n");
 993                 return ret;
 994         }
 995
 996         pci_enable_wake(pdev, PCI_D3hot, 0);
 997         pci_disable_device(pdev);
 998         pci_set_power_state(pdev, pci_choose_state(pdev, state));
 999
1000         return 0;
1001 }
1002
1003 static int pch_i2c_resume(struct pci_dev *pdev)
1004 {
1005         int i;
1006         struct adapter_info *adap_info = pci_get_drvdata(pdev);
1007
1008         pci_set_power_state(pdev, PCI_D0);
1009         pci_restore_state(pdev);
1010
1011         if (pci_enable_device(pdev) < 0) {
1012                 pch_pci_err(pdev, "pch_i2c_resume:pci_enable_device FAILED\n");
1013                 return -EIO;
1014         }
1015
1016         pci_enable_wake(pdev, PCI_D3hot, 0);
1017
1018         for (i = 0; i < adap_info->ch_num; i++)
1019                 pch_i2c_init(&adap_info->pch_data[i]);
1020
1021         adap_info->pch_i2c_suspended = false;
1022
1023         return 0;
1024 }
1025 #else
1026 #define pch_i2c_suspend NULL
1027 #define pch_i2c_resume NULL
1028 #endif
1029
1030 static struct pci_driver pch_pcidriver = {
1031         .name = KBUILD_MODNAME,
1032         .id_table = pch_pcidev_id,
1033         .probe = pch_i2c_probe,
1034         .remove = __devexit_p(pch_i2c_remove),
1035         .suspend = pch_i2c_suspend,
1036         .resume = pch_i2c_resume
1037 };
1038
1039 static int __init pch_pci_init(void)
1040 {
1041         return pci_register_driver(&pch_pcidriver);
1042 }
1043 module_init(pch_pci_init);
1044
1045 static void __exit pch_pci_exit(void)
1046 {
1047         pci_unregister_driver(&pch_pcidriver);
1048 }
1049 module_exit(pch_pci_exit);
1050
1051 MODULE_DESCRIPTION("Intel EG20T PCH/OKI SEMICONDUCTOR ML7213 IOH I2C Driver");
1052 MODULE_LICENSE("GPL");
1053 MODULE_AUTHOR("Tomoya MORINAGA. <tomoya-linux@dsn.okisemi.com>");
1054 module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR));
1055 module_param(pch_clk, int, (S_IRUSR | S_IWUSR));