2 * Freescale CPM1/CPM2 I2C interface.
3 * Copyright (c) 1999 Dan Malek (dmalek@jlc.net).
5 * moved into proper i2c interface;
6 * Brad Parker (brad@heeltoe.com)
8 * Parts from dbox2_i2c.c (cvs.tuxbox.org)
9 * (C) 2000-2001 Felix Domke (tmbinc@gmx.net), Gillem (htoa@gmx.net)
11 * (C) 2007 Montavista Software, Inc.
12 * Vitaly Bordug <vitb@kernel.crashing.org>
14 * Converted to of_platform_device. Renamed to i2c-cpm.c.
15 * (C) 2007,2008 Jochen Friedrich <jochen@scram.de>
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License as published by
19 * the Free Software Foundation; either version 2 of the License, or
20 * (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
32 #include <linux/kernel.h>
33 #include <linux/module.h>
34 #include <linux/delay.h>
35 #include <linux/slab.h>
36 #include <linux/init.h>
37 #include <linux/interrupt.h>
38 #include <linux/errno.h>
39 #include <linux/stddef.h>
40 #include <linux/i2c.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/of_device.h>
44 #include <linux/of_platform.h>
45 #include <linux/of_i2c.h>
46 #include <sysdev/fsl_soc.h>
49 /* Try to define this if you have an older CPU (earlier than rev D4) */
50 /* However, better use a GPIO based bitbang driver in this case :/ */
51 #undef I2C_CHIP_ERRATA
53 #define CPM_MAX_READ 513
56 #define I2C_EB (0x10) /* Big endian mode */
57 #define I2C_EB_CPM2 (0x30) /* Big endian mode, memory snoop */
59 #define DPRAM_BASE ((u8 __iomem __force *)cpm_muram_addr(0))
61 /* I2C parameter RAM. */
63 ushort rbase; /* Rx Buffer descriptor base address */
64 ushort tbase; /* Tx Buffer descriptor base address */
65 u_char rfcr; /* Rx function code */
66 u_char tfcr; /* Tx function code */
67 ushort mrblr; /* Max receive buffer length */
68 uint rstate; /* Internal */
69 uint rdp; /* Internal */
70 ushort rbptr; /* Rx Buffer descriptor pointer */
71 ushort rbc; /* Internal */
72 uint rxtmp; /* Internal */
73 uint tstate; /* Internal */
74 uint tdp; /* Internal */
75 ushort tbptr; /* Tx Buffer descriptor pointer */
76 ushort tbc; /* Internal */
77 uint txtmp; /* Internal */
78 char res1[4]; /* Reserved */
79 ushort rpbase; /* Relocation pointer */
80 char res2[2]; /* Reserved */
83 #define I2COM_START 0x80
84 #define I2COM_MASTER 0x01
85 #define I2CER_TXE 0x10
86 #define I2CER_BUSY 0x04
87 #define I2CER_TXB 0x02
88 #define I2CER_RXB 0x01
108 struct platform_device *ofdev;
109 struct i2c_adapter adap;
111 int version; /* CPM1=1, CPM2=2 */
115 struct i2c_reg __iomem *i2c_reg;
116 struct i2c_ram __iomem *i2c_ram;
118 wait_queue_head_t i2c_wait;
119 cbd_t __iomem *tbase;
120 cbd_t __iomem *rbase;
121 u_char *txbuf[CPM_MAXBD];
122 u_char *rxbuf[CPM_MAXBD];
123 u32 txdma[CPM_MAXBD];
124 u32 rxdma[CPM_MAXBD];
127 static irqreturn_t cpm_i2c_interrupt(int irq, void *dev_id)
130 struct i2c_reg __iomem *i2c_reg;
131 struct i2c_adapter *adap = dev_id;
134 cpm = i2c_get_adapdata(dev_id);
135 i2c_reg = cpm->i2c_reg;
137 /* Clear interrupt. */
138 i = in_8(&i2c_reg->i2cer);
139 out_8(&i2c_reg->i2cer, i);
141 dev_dbg(&adap->dev, "Interrupt: %x\n", i);
143 wake_up(&cpm->i2c_wait);
145 return i ? IRQ_HANDLED : IRQ_NONE;
148 static void cpm_reset_i2c_params(struct cpm_i2c *cpm)
150 struct i2c_ram __iomem *i2c_ram = cpm->i2c_ram;
152 /* Set up the I2C parameters in the parameter ram. */
153 out_be16(&i2c_ram->tbase, (u8 __iomem *)cpm->tbase - DPRAM_BASE);
154 out_be16(&i2c_ram->rbase, (u8 __iomem *)cpm->rbase - DPRAM_BASE);
156 if (cpm->version == 1) {
157 out_8(&i2c_ram->tfcr, I2C_EB);
158 out_8(&i2c_ram->rfcr, I2C_EB);
160 out_8(&i2c_ram->tfcr, I2C_EB_CPM2);
161 out_8(&i2c_ram->rfcr, I2C_EB_CPM2);
164 out_be16(&i2c_ram->mrblr, CPM_MAX_READ);
166 out_be32(&i2c_ram->rstate, 0);
167 out_be32(&i2c_ram->rdp, 0);
168 out_be16(&i2c_ram->rbptr, 0);
169 out_be16(&i2c_ram->rbc, 0);
170 out_be32(&i2c_ram->rxtmp, 0);
171 out_be32(&i2c_ram->tstate, 0);
172 out_be32(&i2c_ram->tdp, 0);
173 out_be16(&i2c_ram->tbptr, 0);
174 out_be16(&i2c_ram->tbc, 0);
175 out_be32(&i2c_ram->txtmp, 0);
178 static void cpm_i2c_force_close(struct i2c_adapter *adap)
180 struct cpm_i2c *cpm = i2c_get_adapdata(adap);
181 struct i2c_reg __iomem *i2c_reg = cpm->i2c_reg;
183 dev_dbg(&adap->dev, "cpm_i2c_force_close()\n");
185 cpm_command(cpm->cp_command, CPM_CR_CLOSE_RX_BD);
187 out_8(&i2c_reg->i2cmr, 0x00); /* Disable all interrupts */
188 out_8(&i2c_reg->i2cer, 0xff);
191 static void cpm_i2c_parse_message(struct i2c_adapter *adap,
192 struct i2c_msg *pmsg, int num, int tx, int rx)
199 struct cpm_i2c *cpm = i2c_get_adapdata(adap);
201 tbdf = cpm->tbase + tx;
202 rbdf = cpm->rbase + rx;
204 addr = pmsg->addr << 1;
205 if (pmsg->flags & I2C_M_RD)
211 /* Align read buffer */
212 rb = (u_char *) (((ulong) rb + 1) & ~1);
214 tb[0] = addr; /* Device address byte w/rw flag */
216 out_be16(&tbdf->cbd_datlen, pmsg->len + 1);
217 out_be16(&tbdf->cbd_sc, 0);
219 if (!(pmsg->flags & I2C_M_NOSTART))
220 setbits16(&tbdf->cbd_sc, BD_I2C_START);
223 setbits16(&tbdf->cbd_sc, BD_SC_LAST | BD_SC_WRAP);
225 if (pmsg->flags & I2C_M_RD) {
227 * To read, we need an empty buffer of the proper length.
228 * All that is used is the first byte for address, the remainder
229 * is just used for timing (and doesn't really have to exist).
232 dev_dbg(&adap->dev, "cpm_i2c_read(abyte=0x%x)\n", addr);
234 out_be16(&rbdf->cbd_datlen, 0);
235 out_be16(&rbdf->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT);
237 if (rx + 1 == CPM_MAXBD)
238 setbits16(&rbdf->cbd_sc, BD_SC_WRAP);
241 setbits16(&tbdf->cbd_sc, BD_SC_READY);
243 dev_dbg(&adap->dev, "cpm_i2c_write(abyte=0x%x)\n", addr);
245 memcpy(tb+1, pmsg->buf, pmsg->len);
248 setbits16(&tbdf->cbd_sc, BD_SC_READY | BD_SC_INTRPT);
252 static int cpm_i2c_check_message(struct i2c_adapter *adap,
253 struct i2c_msg *pmsg, int tx, int rx)
259 struct cpm_i2c *cpm = i2c_get_adapdata(adap);
261 tbdf = cpm->tbase + tx;
262 rbdf = cpm->rbase + rx;
267 /* Align read buffer */
268 rb = (u_char *) (((uint) rb + 1) & ~1);
271 if (pmsg->flags & I2C_M_RD) {
272 dev_dbg(&adap->dev, "tx sc 0x%04x, rx sc 0x%04x\n",
273 in_be16(&tbdf->cbd_sc), in_be16(&rbdf->cbd_sc));
275 if (in_be16(&tbdf->cbd_sc) & BD_SC_NAK) {
276 dev_dbg(&adap->dev, "I2C read; No ack\n");
279 if (in_be16(&rbdf->cbd_sc) & BD_SC_EMPTY) {
281 "I2C read; complete but rbuf empty\n");
284 if (in_be16(&rbdf->cbd_sc) & BD_SC_OV) {
285 dev_err(&adap->dev, "I2C read; Overrun\n");
288 memcpy(pmsg->buf, rb, pmsg->len);
290 dev_dbg(&adap->dev, "tx sc %d 0x%04x\n", tx,
291 in_be16(&tbdf->cbd_sc));
293 if (in_be16(&tbdf->cbd_sc) & BD_SC_NAK) {
294 dev_dbg(&adap->dev, "I2C write; No ack\n");
297 if (in_be16(&tbdf->cbd_sc) & BD_SC_UN) {
298 dev_err(&adap->dev, "I2C write; Underrun\n");
301 if (in_be16(&tbdf->cbd_sc) & BD_SC_CL) {
302 dev_err(&adap->dev, "I2C write; Collision\n");
309 static int cpm_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
311 struct cpm_i2c *cpm = i2c_get_adapdata(adap);
312 struct i2c_reg __iomem *i2c_reg = cpm->i2c_reg;
313 struct i2c_ram __iomem *i2c_ram = cpm->i2c_ram;
314 struct i2c_msg *pmsg;
324 /* Check if we have any oversized READ requests */
325 for (i = 0; i < num; i++) {
327 if (pmsg->len >= CPM_MAX_READ)
331 /* Reset to use first buffer */
332 out_be16(&i2c_ram->rbptr, in_be16(&i2c_ram->rbase));
333 out_be16(&i2c_ram->tbptr, in_be16(&i2c_ram->tbase));
343 dev_dbg(&adap->dev, "R: %d T: %d\n", rptr, tptr);
345 cpm_i2c_parse_message(adap, pmsg, num, tptr, rptr);
346 if (pmsg->flags & I2C_M_RD)
350 /* Start transfer now */
351 /* Enable RX/TX/Error interupts */
352 out_8(&i2c_reg->i2cmr, I2CER_TXE | I2CER_TXB | I2CER_RXB);
353 out_8(&i2c_reg->i2cer, 0xff); /* Clear interrupt status */
354 /* Chip bug, set enable here */
355 setbits8(&i2c_reg->i2mod, I2MOD_EN); /* Enable */
356 /* Begin transmission */
357 setbits8(&i2c_reg->i2com, I2COM_START);
363 /* Check for outstanding messages */
364 dev_dbg(&adap->dev, "test ready.\n");
366 if (pmsg->flags & I2C_M_RD)
367 ret = wait_event_timeout(cpm->i2c_wait,
368 (in_be16(&tbdf[tptr].cbd_sc) & BD_SC_NAK) ||
369 !(in_be16(&rbdf[rptr].cbd_sc) & BD_SC_EMPTY),
372 ret = wait_event_timeout(cpm->i2c_wait,
373 !(in_be16(&tbdf[tptr].cbd_sc) & BD_SC_READY),
377 dev_err(&adap->dev, "I2C transfer: timeout\n");
381 dev_dbg(&adap->dev, "ready.\n");
382 ret = cpm_i2c_check_message(adap, pmsg, tptr, rptr);
384 if (pmsg->flags & I2C_M_RD)
390 #ifdef I2C_CHIP_ERRATA
392 * Chip errata, clear enable. This is not needed on rev D4 CPUs.
393 * Disabling I2C too early may cause too short stop condition
396 clrbits8(&i2c_reg->i2mod, I2MOD_EN);
401 cpm_i2c_force_close(adap);
402 #ifdef I2C_CHIP_ERRATA
404 * Chip errata, clear enable. This is not needed on rev D4 CPUs.
406 clrbits8(&i2c_reg->i2mod, I2MOD_EN);
411 static u32 cpm_i2c_func(struct i2c_adapter *adap)
413 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
416 /* -----exported algorithm data: ------------------------------------- */
418 static const struct i2c_algorithm cpm_i2c_algo = {
419 .master_xfer = cpm_i2c_xfer,
420 .functionality = cpm_i2c_func,
423 static const struct i2c_adapter cpm_ops = {
424 .owner = THIS_MODULE,
426 .algo = &cpm_i2c_algo,
429 static int __devinit cpm_i2c_setup(struct cpm_i2c *cpm)
431 struct platform_device *ofdev = cpm->ofdev;
434 void __iomem *i2c_base;
439 dev_dbg(&cpm->ofdev->dev, "cpm_i2c_setup()\n");
441 init_waitqueue_head(&cpm->i2c_wait);
443 cpm->irq = of_irq_to_resource(ofdev->dev.of_node, 0, NULL);
447 /* Install interrupt handler. */
448 ret = request_irq(cpm->irq, cpm_i2c_interrupt, 0, "cpm_i2c",
453 /* I2C parameter RAM */
454 i2c_base = of_iomap(ofdev->dev.of_node, 1);
455 if (i2c_base == NULL) {
460 if (of_device_is_compatible(ofdev->dev.of_node, "fsl,cpm1-i2c")) {
462 /* Check for and use a microcode relocation patch. */
463 cpm->i2c_ram = i2c_base;
464 cpm->i2c_addr = in_be16(&cpm->i2c_ram->rpbase);
467 * Maybe should use cpm_muram_alloc instead of hardcoding
468 * this in micropatch.c
471 cpm->i2c_ram = cpm_muram_addr(cpm->i2c_addr);
477 } else if (of_device_is_compatible(ofdev->dev.of_node, "fsl,cpm2-i2c")) {
478 cpm->i2c_addr = cpm_muram_alloc(sizeof(struct i2c_ram), 64);
479 cpm->i2c_ram = cpm_muram_addr(cpm->i2c_addr);
480 out_be16(i2c_base, cpm->i2c_addr);
491 /* I2C control/status registers */
492 cpm->i2c_reg = of_iomap(ofdev->dev.of_node, 0);
493 if (cpm->i2c_reg == NULL) {
498 data = of_get_property(ofdev->dev.of_node, "fsl,cpm-command", &len);
499 if (!data || len != 4) {
503 cpm->cp_command = *data;
505 data = of_get_property(ofdev->dev.of_node, "linux,i2c-class", &len);
506 if (data && len == 4)
507 cpm->adap.class = *data;
509 data = of_get_property(ofdev->dev.of_node, "clock-frequency", &len);
510 if (data && len == 4)
513 cpm->freq = 60000; /* use 60kHz i2c clock by default */
516 * Allocate space for CPM_MAXBD transmit and receive buffer
517 * descriptors in the DP ram.
519 cpm->dp_addr = cpm_muram_alloc(sizeof(cbd_t) * 2 * CPM_MAXBD, 8);
525 cpm->tbase = cpm_muram_addr(cpm->dp_addr);
526 cpm->rbase = cpm_muram_addr(cpm->dp_addr + sizeof(cbd_t) * CPM_MAXBD);
528 /* Allocate TX and RX buffers */
533 for (i = 0; i < CPM_MAXBD; i++) {
534 cpm->rxbuf[i] = dma_alloc_coherent(&cpm->ofdev->dev,
536 &cpm->rxdma[i], GFP_KERNEL);
537 if (!cpm->rxbuf[i]) {
541 out_be32(&rbdf[i].cbd_bufaddr, ((cpm->rxdma[i] + 1) & ~1));
543 cpm->txbuf[i] = (unsigned char *)dma_alloc_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1, &cpm->txdma[i], GFP_KERNEL);
544 if (!cpm->txbuf[i]) {
548 out_be32(&tbdf[i].cbd_bufaddr, cpm->txdma[i]);
551 /* Initialize Tx/Rx parameters. */
553 cpm_reset_i2c_params(cpm);
555 dev_dbg(&cpm->ofdev->dev, "i2c_ram 0x%p, i2c_addr 0x%04x, freq %d\n",
556 cpm->i2c_ram, cpm->i2c_addr, cpm->freq);
557 dev_dbg(&cpm->ofdev->dev, "tbase 0x%04x, rbase 0x%04x\n",
558 (u8 __iomem *)cpm->tbase - DPRAM_BASE,
559 (u8 __iomem *)cpm->rbase - DPRAM_BASE);
561 cpm_command(cpm->cp_command, CPM_CR_INIT_TRX);
564 * Select an invalid address. Just make sure we don't use loopback mode
566 out_8(&cpm->i2c_reg->i2add, 0x7f << 1);
569 * PDIV is set to 00 in i2mod, so brgclk/32 is used as input to the
570 * i2c baud rate generator. This is divided by 2 x (DIV + 3) to get
571 * the actual i2c bus frequency.
573 brg = get_brgfreq() / (32 * 2 * cpm->freq) - 3;
574 out_8(&cpm->i2c_reg->i2brg, brg);
576 out_8(&cpm->i2c_reg->i2mod, 0x00);
577 out_8(&cpm->i2c_reg->i2com, I2COM_MASTER); /* Master mode */
579 /* Disable interrupts. */
580 out_8(&cpm->i2c_reg->i2cmr, 0);
581 out_8(&cpm->i2c_reg->i2cer, 0xff);
586 for (i = 0; i < CPM_MAXBD; i++) {
588 dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
589 cpm->rxbuf[i], cpm->rxdma[i]);
591 dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
592 cpm->txbuf[i], cpm->txdma[i]);
594 cpm_muram_free(cpm->dp_addr);
596 iounmap(cpm->i2c_reg);
598 if ((cpm->version == 1) && (!cpm->i2c_addr))
599 iounmap(cpm->i2c_ram);
600 if (cpm->version == 2)
601 cpm_muram_free(cpm->i2c_addr);
603 free_irq(cpm->irq, &cpm->adap);
607 static void cpm_i2c_shutdown(struct cpm_i2c *cpm)
612 clrbits8(&cpm->i2c_reg->i2mod, I2MOD_EN);
614 /* Disable interrupts */
615 out_8(&cpm->i2c_reg->i2cmr, 0);
616 out_8(&cpm->i2c_reg->i2cer, 0xff);
618 free_irq(cpm->irq, &cpm->adap);
620 /* Free all memory */
621 for (i = 0; i < CPM_MAXBD; i++) {
622 dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
623 cpm->rxbuf[i], cpm->rxdma[i]);
624 dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
625 cpm->txbuf[i], cpm->txdma[i]);
628 cpm_muram_free(cpm->dp_addr);
629 iounmap(cpm->i2c_reg);
631 if ((cpm->version == 1) && (!cpm->i2c_addr))
632 iounmap(cpm->i2c_ram);
633 if (cpm->version == 2)
634 cpm_muram_free(cpm->i2c_addr);
637 static int __devinit cpm_i2c_probe(struct platform_device *ofdev)
643 cpm = kzalloc(sizeof(struct cpm_i2c), GFP_KERNEL);
649 dev_set_drvdata(&ofdev->dev, cpm);
652 i2c_set_adapdata(&cpm->adap, cpm);
653 cpm->adap.dev.parent = &ofdev->dev;
654 cpm->adap.dev.of_node = of_node_get(ofdev->dev.of_node);
656 result = cpm_i2c_setup(cpm);
658 dev_err(&ofdev->dev, "Unable to init hardware\n");
662 /* register new adapter to i2c module... */
664 data = of_get_property(ofdev->dev.of_node, "linux,i2c-index", &len);
665 if (data && len == 4) {
666 cpm->adap.nr = *data;
667 result = i2c_add_numbered_adapter(&cpm->adap);
669 result = i2c_add_adapter(&cpm->adap);
672 dev_err(&ofdev->dev, "Unable to register with I2C\n");
676 dev_dbg(&ofdev->dev, "hw routines for %s registered.\n",
680 * register OF I2C devices
682 of_i2c_register_devices(&cpm->adap);
686 cpm_i2c_shutdown(cpm);
688 dev_set_drvdata(&ofdev->dev, NULL);
694 static int __devexit cpm_i2c_remove(struct platform_device *ofdev)
696 struct cpm_i2c *cpm = dev_get_drvdata(&ofdev->dev);
698 i2c_del_adapter(&cpm->adap);
700 cpm_i2c_shutdown(cpm);
702 dev_set_drvdata(&ofdev->dev, NULL);
708 static const struct of_device_id cpm_i2c_match[] = {
710 .compatible = "fsl,cpm1-i2c",
713 .compatible = "fsl,cpm2-i2c",
718 MODULE_DEVICE_TABLE(of, cpm_i2c_match);
720 static struct platform_driver cpm_i2c_driver = {
721 .probe = cpm_i2c_probe,
722 .remove = __devexit_p(cpm_i2c_remove),
724 .name = "fsl-i2c-cpm",
725 .owner = THIS_MODULE,
726 .of_match_table = cpm_i2c_match,
730 static int __init cpm_i2c_init(void)
732 return platform_driver_register(&cpm_i2c_driver);
735 static void __exit cpm_i2c_exit(void)
737 platform_driver_unregister(&cpm_i2c_driver);
740 module_init(cpm_i2c_init);
741 module_exit(cpm_i2c_exit);
743 MODULE_AUTHOR("Jochen Friedrich <jochen@scram.de>");
744 MODULE_DESCRIPTION("I2C-Bus adapter routines for CPM boards");
745 MODULE_LICENSE("GPL");