2 * Blackfin On-Chip Two Wire Interface Driver
4 * Copyright 2005-2007 Analog Devices Inc.
6 * Enter bugs at http://blackfin.uclinux.org/
8 * Licensed under the GPL-2 or later.
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/i2c.h>
16 #include <linux/timer.h>
17 #include <linux/spinlock.h>
18 #include <linux/completion.h>
19 #include <linux/interrupt.h>
20 #include <linux/platform_device.h>
22 #include <asm/blackfin.h>
23 #include <asm/portmux.h>
26 #define POLL_TIMEOUT (2 * HZ)
29 #define TWI_I2C_MODE_STANDARD 1
30 #define TWI_I2C_MODE_STANDARDSUB 2
31 #define TWI_I2C_MODE_COMBINED 3
32 #define TWI_I2C_MODE_REPEAT 4
34 struct bfin_twi_iface {
46 struct timer_list timeout_timer;
47 struct i2c_adapter adap;
48 struct completion complete;
54 void __iomem *regs_base;
58 #define DEFINE_TWI_REG(reg, off) \
59 static inline u16 read_##reg(struct bfin_twi_iface *iface) \
60 { return bfin_read16(iface->regs_base + (off)); } \
61 static inline void write_##reg(struct bfin_twi_iface *iface, u16 v) \
62 { bfin_write16(iface->regs_base + (off), v); }
64 DEFINE_TWI_REG(CLKDIV, 0x00)
65 DEFINE_TWI_REG(CONTROL, 0x04)
66 DEFINE_TWI_REG(SLAVE_CTL, 0x08)
67 DEFINE_TWI_REG(SLAVE_STAT, 0x0C)
68 DEFINE_TWI_REG(SLAVE_ADDR, 0x10)
69 DEFINE_TWI_REG(MASTER_CTL, 0x14)
70 DEFINE_TWI_REG(MASTER_STAT, 0x18)
71 DEFINE_TWI_REG(MASTER_ADDR, 0x1C)
72 DEFINE_TWI_REG(INT_STAT, 0x20)
73 DEFINE_TWI_REG(INT_MASK, 0x24)
74 DEFINE_TWI_REG(FIFO_CTL, 0x28)
75 DEFINE_TWI_REG(FIFO_STAT, 0x2C)
76 DEFINE_TWI_REG(XMT_DATA8, 0x80)
77 DEFINE_TWI_REG(XMT_DATA16, 0x84)
78 DEFINE_TWI_REG(RCV_DATA8, 0x88)
79 DEFINE_TWI_REG(RCV_DATA16, 0x8C)
81 static const u16 pin_req[2][3] = {
82 {P_TWI0_SCL, P_TWI0_SDA, 0},
83 {P_TWI1_SCL, P_TWI1_SDA, 0},
86 static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface)
88 unsigned short twi_int_status = read_INT_STAT(iface);
89 unsigned short mast_stat = read_MASTER_STAT(iface);
91 if (twi_int_status & XMTSERV) {
92 /* Transmit next data */
93 if (iface->writeNum > 0) {
94 write_XMT_DATA8(iface, *(iface->transPtr++));
97 /* start receive immediately after complete sending in
100 else if (iface->cur_mode == TWI_I2C_MODE_COMBINED)
101 write_MASTER_CTL(iface,
102 read_MASTER_CTL(iface) | MDIR | RSTART);
103 else if (iface->manual_stop)
104 write_MASTER_CTL(iface,
105 read_MASTER_CTL(iface) | STOP);
106 else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
107 iface->cur_msg+1 < iface->msg_num)
108 write_MASTER_CTL(iface,
109 read_MASTER_CTL(iface) | RSTART);
112 write_INT_STAT(iface, XMTSERV);
115 if (twi_int_status & RCVSERV) {
116 if (iface->readNum > 0) {
117 /* Receive next data */
118 *(iface->transPtr) = read_RCV_DATA8(iface);
119 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
120 /* Change combine mode into sub mode after
123 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
124 /* Get read number from first byte in block
127 if (iface->readNum == 1 && iface->manual_stop)
128 iface->readNum = *iface->transPtr + 1;
132 } else if (iface->manual_stop) {
133 write_MASTER_CTL(iface,
134 read_MASTER_CTL(iface) | STOP);
136 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
137 iface->cur_msg+1 < iface->msg_num) {
138 write_MASTER_CTL(iface,
139 read_MASTER_CTL(iface) | RSTART);
142 /* Clear interrupt source */
143 write_INT_STAT(iface, RCVSERV);
146 if (twi_int_status & MERR) {
147 write_INT_STAT(iface, MERR);
148 write_INT_MASK(iface, 0);
149 write_MASTER_STAT(iface, 0x3e);
150 write_MASTER_CTL(iface, 0);
152 iface->result = -EIO;
153 /* if both err and complete int stats are set, return proper
156 if (twi_int_status & MCOMP) {
157 write_INT_STAT(iface, MCOMP);
158 write_INT_MASK(iface, 0);
159 write_MASTER_CTL(iface, 0);
161 /* If it is a quick transfer, only address bug no data,
162 * not an err, return 1.
164 if (iface->writeNum == 0 && (mast_stat & BUFRDERR))
166 /* If address not acknowledged return -1,
169 else if (!(mast_stat & ANAK))
172 complete(&iface->complete);
175 if (twi_int_status & MCOMP) {
176 write_INT_STAT(iface, MCOMP);
178 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
179 if (iface->readNum == 0) {
180 /* set the read number to 1 and ask for manual
181 * stop in block combine mode
184 iface->manual_stop = 1;
185 write_MASTER_CTL(iface,
186 read_MASTER_CTL(iface) | (0xff << 6));
188 /* set the readd number in other
191 write_MASTER_CTL(iface,
192 (read_MASTER_CTL(iface) &
194 (iface->readNum << 6));
196 /* remove restart bit and enable master receive */
197 write_MASTER_CTL(iface,
198 read_MASTER_CTL(iface) & ~RSTART);
200 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
201 iface->cur_msg+1 < iface->msg_num) {
203 iface->transPtr = iface->pmsg[iface->cur_msg].buf;
204 iface->writeNum = iface->readNum =
205 iface->pmsg[iface->cur_msg].len;
206 /* Set Transmit device address */
207 write_MASTER_ADDR(iface,
208 iface->pmsg[iface->cur_msg].addr);
209 if (iface->pmsg[iface->cur_msg].flags & I2C_M_RD)
210 iface->read_write = I2C_SMBUS_READ;
212 iface->read_write = I2C_SMBUS_WRITE;
213 /* Transmit first data */
214 if (iface->writeNum > 0) {
215 write_XMT_DATA8(iface,
216 *(iface->transPtr++));
222 if (iface->pmsg[iface->cur_msg].len <= 255)
223 write_MASTER_CTL(iface,
224 (read_MASTER_CTL(iface) &
226 (iface->pmsg[iface->cur_msg].len << 6));
228 write_MASTER_CTL(iface,
229 (read_MASTER_CTL(iface) |
231 iface->manual_stop = 1;
233 /* remove restart bit and enable master receive */
234 write_MASTER_CTL(iface,
235 read_MASTER_CTL(iface) & ~RSTART);
239 write_INT_MASK(iface, 0);
240 write_MASTER_CTL(iface, 0);
242 complete(&iface->complete);
247 /* Interrupt handler */
248 static irqreturn_t bfin_twi_interrupt_entry(int irq, void *dev_id)
250 struct bfin_twi_iface *iface = dev_id;
253 spin_lock_irqsave(&iface->lock, flags);
254 del_timer(&iface->timeout_timer);
255 bfin_twi_handle_interrupt(iface);
256 spin_unlock_irqrestore(&iface->lock, flags);
260 static void bfin_twi_timeout(unsigned long data)
262 struct bfin_twi_iface *iface = (struct bfin_twi_iface *)data;
265 spin_lock_irqsave(&iface->lock, flags);
266 bfin_twi_handle_interrupt(iface);
267 if (iface->result == 0) {
268 iface->timeout_count--;
269 if (iface->timeout_count > 0) {
270 iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
271 add_timer(&iface->timeout_timer);
274 complete(&iface->complete);
277 spin_unlock_irqrestore(&iface->lock, flags);
281 * Generic i2c master transfer entrypoint
283 static int bfin_twi_master_xfer(struct i2c_adapter *adap,
284 struct i2c_msg *msgs, int num)
286 struct bfin_twi_iface *iface = adap->algo_data;
287 struct i2c_msg *pmsg;
290 if (!(read_CONTROL(iface) & TWI_ENA))
293 while (read_MASTER_STAT(iface) & BUSBUSY)
297 iface->msg_num = num;
301 if (pmsg->flags & I2C_M_TEN) {
302 dev_err(&adap->dev, "10 bits addr not supported!\n");
306 iface->cur_mode = TWI_I2C_MODE_REPEAT;
307 iface->manual_stop = 0;
308 iface->transPtr = pmsg->buf;
309 iface->writeNum = iface->readNum = pmsg->len;
311 iface->timeout_count = 10;
312 init_completion(&(iface->complete));
313 /* Set Transmit device address */
314 write_MASTER_ADDR(iface, pmsg->addr);
316 /* FIFO Initiation. Data in FIFO should be
317 * discarded before start a new operation.
319 write_FIFO_CTL(iface, 0x3);
321 write_FIFO_CTL(iface, 0);
324 if (pmsg->flags & I2C_M_RD)
325 iface->read_write = I2C_SMBUS_READ;
327 iface->read_write = I2C_SMBUS_WRITE;
328 /* Transmit first data */
329 if (iface->writeNum > 0) {
330 write_XMT_DATA8(iface, *(iface->transPtr++));
337 write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
339 /* Interrupt mask . Enable XMT, RCV interrupt */
340 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
343 if (pmsg->len <= 255)
344 write_MASTER_CTL(iface, pmsg->len << 6);
346 write_MASTER_CTL(iface, 0xff << 6);
347 iface->manual_stop = 1;
350 iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
351 add_timer(&iface->timeout_timer);
354 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
355 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
356 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
359 wait_for_completion(&iface->complete);
370 * SMBus type transfer entrypoint
373 int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
374 unsigned short flags, char read_write,
375 u8 command, int size, union i2c_smbus_data *data)
377 struct bfin_twi_iface *iface = adap->algo_data;
380 if (!(read_CONTROL(iface) & TWI_ENA))
383 while (read_MASTER_STAT(iface) & BUSBUSY)
389 /* Prepare datas & select mode */
391 case I2C_SMBUS_QUICK:
392 iface->transPtr = NULL;
393 iface->cur_mode = TWI_I2C_MODE_STANDARD;
397 iface->transPtr = NULL;
399 if (read_write == I2C_SMBUS_READ)
403 iface->transPtr = &data->byte;
405 iface->cur_mode = TWI_I2C_MODE_STANDARD;
407 case I2C_SMBUS_BYTE_DATA:
408 if (read_write == I2C_SMBUS_READ) {
410 iface->cur_mode = TWI_I2C_MODE_COMBINED;
413 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
415 iface->transPtr = &data->byte;
417 case I2C_SMBUS_WORD_DATA:
418 if (read_write == I2C_SMBUS_READ) {
420 iface->cur_mode = TWI_I2C_MODE_COMBINED;
423 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
425 iface->transPtr = (u8 *)&data->word;
427 case I2C_SMBUS_PROC_CALL:
430 iface->cur_mode = TWI_I2C_MODE_COMBINED;
431 iface->transPtr = (u8 *)&data->word;
433 case I2C_SMBUS_BLOCK_DATA:
434 if (read_write == I2C_SMBUS_READ) {
436 iface->cur_mode = TWI_I2C_MODE_COMBINED;
438 iface->writeNum = data->block[0] + 1;
439 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
441 iface->transPtr = data->block;
448 iface->manual_stop = 0;
449 iface->read_write = read_write;
450 iface->command = command;
451 iface->timeout_count = 10;
452 init_completion(&(iface->complete));
454 /* FIFO Initiation. Data in FIFO should be discarded before
455 * start a new operation.
457 write_FIFO_CTL(iface, 0x3);
459 write_FIFO_CTL(iface, 0);
462 write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
464 /* Set Transmit device address */
465 write_MASTER_ADDR(iface, addr);
468 iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
469 add_timer(&iface->timeout_timer);
471 switch (iface->cur_mode) {
472 case TWI_I2C_MODE_STANDARDSUB:
473 write_XMT_DATA8(iface, iface->command);
474 write_INT_MASK(iface, MCOMP | MERR |
475 ((iface->read_write == I2C_SMBUS_READ) ?
479 if (iface->writeNum + 1 <= 255)
480 write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
482 write_MASTER_CTL(iface, 0xff << 6);
483 iface->manual_stop = 1;
486 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
487 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
489 case TWI_I2C_MODE_COMBINED:
490 write_XMT_DATA8(iface, iface->command);
491 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
494 if (iface->writeNum > 0)
495 write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
497 write_MASTER_CTL(iface, 0x1 << 6);
499 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
500 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
503 write_MASTER_CTL(iface, 0);
504 if (size != I2C_SMBUS_QUICK) {
505 /* Don't access xmit data register when this is a
508 if (iface->read_write != I2C_SMBUS_READ) {
509 if (iface->writeNum > 0) {
510 write_XMT_DATA8(iface,
511 *(iface->transPtr++));
512 if (iface->writeNum <= 255)
513 write_MASTER_CTL(iface,
514 iface->writeNum << 6);
516 write_MASTER_CTL(iface,
518 iface->manual_stop = 1;
522 write_XMT_DATA8(iface, iface->command);
523 write_MASTER_CTL(iface, 1 << 6);
526 if (iface->readNum > 0 && iface->readNum <= 255)
527 write_MASTER_CTL(iface,
528 iface->readNum << 6);
529 else if (iface->readNum > 255) {
530 write_MASTER_CTL(iface, 0xff << 6);
531 iface->manual_stop = 1;
533 del_timer(&iface->timeout_timer);
538 write_INT_MASK(iface, MCOMP | MERR |
539 ((iface->read_write == I2C_SMBUS_READ) ?
544 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
545 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
546 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
551 wait_for_completion(&iface->complete);
553 rc = (iface->result >= 0) ? 0 : -1;
559 * Return what the adapter supports
561 static u32 bfin_twi_functionality(struct i2c_adapter *adap)
563 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
564 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
565 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL |
569 static struct i2c_algorithm bfin_twi_algorithm = {
570 .master_xfer = bfin_twi_master_xfer,
571 .smbus_xfer = bfin_twi_smbus_xfer,
572 .functionality = bfin_twi_functionality,
575 static int i2c_bfin_twi_suspend(struct platform_device *pdev, pm_message_t state)
577 struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
579 iface->saved_clkdiv = read_CLKDIV(iface);
580 iface->saved_control = read_CONTROL(iface);
582 free_irq(iface->irq, iface);
585 write_CONTROL(iface, iface->saved_control & ~TWI_ENA);
590 static int i2c_bfin_twi_resume(struct platform_device *pdev)
592 struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
594 int rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
595 IRQF_DISABLED, pdev->name, iface);
597 dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
601 /* Resume TWI interface clock as specified */
602 write_CLKDIV(iface, iface->saved_clkdiv);
605 write_CONTROL(iface, iface->saved_control);
610 static int i2c_bfin_twi_probe(struct platform_device *pdev)
612 struct bfin_twi_iface *iface;
613 struct i2c_adapter *p_adap;
614 struct resource *res;
616 unsigned int clkhilow;
618 iface = kzalloc(sizeof(struct bfin_twi_iface), GFP_KERNEL);
620 dev_err(&pdev->dev, "Cannot allocate memory\n");
622 goto out_error_nomem;
625 spin_lock_init(&(iface->lock));
627 /* Find and map our resources */
628 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
630 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
632 goto out_error_get_res;
635 iface->regs_base = ioremap(res->start, res->end - res->start + 1);
636 if (iface->regs_base == NULL) {
637 dev_err(&pdev->dev, "Cannot map IO\n");
639 goto out_error_ioremap;
642 iface->irq = platform_get_irq(pdev, 0);
643 if (iface->irq < 0) {
644 dev_err(&pdev->dev, "No IRQ specified\n");
646 goto out_error_no_irq;
649 init_timer(&(iface->timeout_timer));
650 iface->timeout_timer.function = bfin_twi_timeout;
651 iface->timeout_timer.data = (unsigned long)iface;
653 p_adap = &iface->adap;
654 p_adap->nr = pdev->id;
655 strlcpy(p_adap->name, pdev->name, sizeof(p_adap->name));
656 p_adap->algo = &bfin_twi_algorithm;
657 p_adap->algo_data = iface;
658 p_adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
659 p_adap->dev.parent = &pdev->dev;
661 rc = peripheral_request_list(pin_req[pdev->id], "i2c-bfin-twi");
663 dev_err(&pdev->dev, "Can't setup pin mux!\n");
664 goto out_error_pin_mux;
667 rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
668 IRQF_DISABLED, pdev->name, iface);
670 dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
672 goto out_error_req_irq;
675 /* Set TWI internal clock as 10MHz */
676 write_CONTROL(iface, ((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F);
679 * We will not end up with a CLKDIV=0 because no one will specify
680 * 20kHz SCL or less in Kconfig now. (5 * 1024 / 20 = 0x100)
682 clkhilow = 5 * 1024 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ;
684 /* Set Twi interface clock as specified */
685 write_CLKDIV(iface, (clkhilow << 8) | clkhilow);
688 write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA);
691 rc = i2c_add_numbered_adapter(p_adap);
693 dev_err(&pdev->dev, "Can't add i2c adapter!\n");
694 goto out_error_add_adapter;
697 platform_set_drvdata(pdev, iface);
699 dev_info(&pdev->dev, "Blackfin BF5xx on-chip I2C TWI Contoller, "
700 "regs_base@%p\n", iface->regs_base);
704 out_error_add_adapter:
705 free_irq(iface->irq, iface);
708 peripheral_free_list(pin_req[pdev->id]);
710 iounmap(iface->regs_base);
718 static int i2c_bfin_twi_remove(struct platform_device *pdev)
720 struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
722 platform_set_drvdata(pdev, NULL);
724 i2c_del_adapter(&(iface->adap));
725 free_irq(iface->irq, iface);
726 peripheral_free_list(pin_req[pdev->id]);
727 iounmap(iface->regs_base);
733 static struct platform_driver i2c_bfin_twi_driver = {
734 .probe = i2c_bfin_twi_probe,
735 .remove = i2c_bfin_twi_remove,
736 .suspend = i2c_bfin_twi_suspend,
737 .resume = i2c_bfin_twi_resume,
739 .name = "i2c-bfin-twi",
740 .owner = THIS_MODULE,
744 static int __init i2c_bfin_twi_init(void)
746 return platform_driver_register(&i2c_bfin_twi_driver);
749 static void __exit i2c_bfin_twi_exit(void)
751 platform_driver_unregister(&i2c_bfin_twi_driver);
754 module_init(i2c_bfin_twi_init);
755 module_exit(i2c_bfin_twi_exit);
757 MODULE_AUTHOR("Bryan Wu, Sonic Zhang");
758 MODULE_DESCRIPTION("Blackfin BF5xx on-chip I2C TWI Contoller Driver");
759 MODULE_LICENSE("GPL");
760 MODULE_ALIAS("platform:i2c-bfin-twi");