drivers/i2c/busses/i2c-bfin-twi.c

   1 /*
   2  * Blackfin On-Chip Two Wire Interface Driver
   3  *
   4  * Copyright 2005-2007 Analog Devices Inc.
   5  *
   6  * Enter bugs at http://blackfin.uclinux.org/
   7  *
   8  * Licensed under the GPL-2 or later.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/kernel.h>
  13 #include <linux/init.h>
  14 #include <linux/i2c.h>
  15 #include <linux/slab.h>
  16 #include <linux/io.h>
  17 #include <linux/mm.h>
  18 #include <linux/timer.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/completion.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/platform_device.h>
  23
  24 #include <asm/blackfin.h>
  25 #include <asm/portmux.h>
  26 #include <asm/irq.h>
  27
  28 /* SMBus mode*/
  29 #define TWI_I2C_MODE_STANDARD           1
  30 #define TWI_I2C_MODE_STANDARDSUB        2
  31 #define TWI_I2C_MODE_COMBINED           3
  32 #define TWI_I2C_MODE_REPEAT             4
  33
  34 struct bfin_twi_iface {
  35         int                     irq;
  36         spinlock_t              lock;
  37         char                    read_write;
  38         u8                      command;
  39         u8                      *transPtr;
  40         int                     readNum;
  41         int                     writeNum;
  42         int                     cur_mode;
  43         int                     manual_stop;
  44         int                     result;
  45         struct i2c_adapter      adap;
  46         struct completion       complete;
  47         struct i2c_msg          *pmsg;
  48         int                     msg_num;
  49         int                     cur_msg;
  50         u16                     saved_clkdiv;
  51         u16                     saved_control;
  52         void __iomem            *regs_base;
  53 };
  54
  55
  56 #define DEFINE_TWI_REG(reg, off) \
  57 static inline u16 read_##reg(struct bfin_twi_iface *iface) \
  58         { return bfin_read16(iface->regs_base + (off)); } \
  59 static inline void write_##reg(struct bfin_twi_iface *iface, u16 v) \
  60         { bfin_write16(iface->regs_base + (off), v); }
  61
  62 DEFINE_TWI_REG(CLKDIV, 0x00)
  63 DEFINE_TWI_REG(CONTROL, 0x04)
  64 DEFINE_TWI_REG(SLAVE_CTL, 0x08)
  65 DEFINE_TWI_REG(SLAVE_STAT, 0x0C)
  66 DEFINE_TWI_REG(SLAVE_ADDR, 0x10)
  67 DEFINE_TWI_REG(MASTER_CTL, 0x14)
  68 DEFINE_TWI_REG(MASTER_STAT, 0x18)
  69 DEFINE_TWI_REG(MASTER_ADDR, 0x1C)
  70 DEFINE_TWI_REG(INT_STAT, 0x20)
  71 DEFINE_TWI_REG(INT_MASK, 0x24)
  72 DEFINE_TWI_REG(FIFO_CTL, 0x28)
  73 DEFINE_TWI_REG(FIFO_STAT, 0x2C)
  74 DEFINE_TWI_REG(XMT_DATA8, 0x80)
  75 DEFINE_TWI_REG(XMT_DATA16, 0x84)
  76 DEFINE_TWI_REG(RCV_DATA8, 0x88)
  77 DEFINE_TWI_REG(RCV_DATA16, 0x8C)
  78
  79 static const u16 pin_req[2][3] = {
  80         {P_TWI0_SCL, P_TWI0_SDA, 0},
  81         {P_TWI1_SCL, P_TWI1_SDA, 0},
  82 };
  83
  84 static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface,
  85                                         unsigned short twi_int_status)
  86 {
  87         unsigned short mast_stat = read_MASTER_STAT(iface);
  88
  89         if (twi_int_status & XMTSERV) {
  90                 /* Transmit next data */
  91                 if (iface->writeNum > 0) {
  92                         SSYNC();
  93                         write_XMT_DATA8(iface, *(iface->transPtr++));
  94                         iface->writeNum--;
  95                 }
  96                 /* start receive immediately after complete sending in
  97                  * combine mode.
  98                  */
  99                 else if (iface->cur_mode == TWI_I2C_MODE_COMBINED)
 100                         write_MASTER_CTL(iface,
 101                                 read_MASTER_CTL(iface) | MDIR | RSTART);
 102                 else if (iface->manual_stop)
 103                         write_MASTER_CTL(iface,
 104                                 read_MASTER_CTL(iface) | STOP);
 105                 else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
 106                          iface->cur_msg + 1 < iface->msg_num) {
 107                         if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD)
 108                                 write_MASTER_CTL(iface,
 109                                         read_MASTER_CTL(iface) | RSTART | MDIR);
 110                         else
 111                                 write_MASTER_CTL(iface,
 112                                         (read_MASTER_CTL(iface) | RSTART) & ~MDIR);
 113                 }
 114         }
 115         if (twi_int_status & RCVSERV) {
 116                 if (iface->readNum > 0) {
 117                         /* Receive next data */
 118                         *(iface->transPtr) = read_RCV_DATA8(iface);
 119                         if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
 120                                 /* Change combine mode into sub mode after
 121                                  * read first data.
 122                                  */
 123                                 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 124                                 /* Get read number from first byte in block
 125                                  * combine mode.
 126                                  */
 127                                 if (iface->readNum == 1 && iface->manual_stop)
 128                                         iface->readNum = *iface->transPtr + 1;
 129                         }
 130                         iface->transPtr++;
 131                         iface->readNum--;
 132                 } else if (iface->manual_stop) {
 133                         write_MASTER_CTL(iface,
 134                                 read_MASTER_CTL(iface) | STOP);
 135                 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
 136                            iface->cur_msg + 1 < iface->msg_num) {
 137                         if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD)
 138                                 write_MASTER_CTL(iface,
 139                                         read_MASTER_CTL(iface) | RSTART | MDIR);
 140                         else
 141                                 write_MASTER_CTL(iface,
 142                                         (read_MASTER_CTL(iface) | RSTART) & ~MDIR);
 143                 }
 144         }
 145         if (twi_int_status & MERR) {
 146                 write_INT_MASK(iface, 0);
 147                 write_MASTER_STAT(iface, 0x3e);
 148                 write_MASTER_CTL(iface, 0);
 149                 iface->result = -EIO;
 150
 151                 if (mast_stat & LOSTARB)
 152                         dev_dbg(&iface->adap.dev, "Lost Arbitration\n");
 153                 if (mast_stat & ANAK)
 154                         dev_dbg(&iface->adap.dev, "Address Not Acknowledged\n");
 155                 if (mast_stat & DNAK)
 156                         dev_dbg(&iface->adap.dev, "Data Not Acknowledged\n");
 157                 if (mast_stat & BUFRDERR)
 158                         dev_dbg(&iface->adap.dev, "Buffer Read Error\n");
 159                 if (mast_stat & BUFWRERR)
 160                         dev_dbg(&iface->adap.dev, "Buffer Write Error\n");
 161
 162                 /* if both err and complete int stats are set, return proper
 163                  * results.
 164                  */
 165                 if (twi_int_status & MCOMP) {
 166                         /* If it is a quick transfer, only address without data,
 167                          * not an err, return 1.
 168                          * If address is acknowledged return 1.
 169                          */
 170                         if ((iface->writeNum == 0 && (mast_stat & BUFRDERR))
 171                                 || !(mast_stat & ANAK))
 172                                 iface->result = 1;
 173                 }
 174                 complete(&iface->complete);
 175                 return;
 176         }
 177         if (twi_int_status & MCOMP) {
 178                 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
 179                         if (iface->readNum == 0) {
 180                                 /* set the read number to 1 and ask for manual
 181                                  * stop in block combine mode
 182                                  */
 183                                 iface->readNum = 1;
 184                                 iface->manual_stop = 1;
 185                                 write_MASTER_CTL(iface,
 186                                         read_MASTER_CTL(iface) | (0xff << 6));
 187                         } else {
 188                                 /* set the readd number in other
 189                                  * combine mode.
 190                                  */
 191                                 write_MASTER_CTL(iface,
 192                                         (read_MASTER_CTL(iface) &
 193                                         (~(0xff << 6))) |
 194                                         (iface->readNum << 6));
 195                         }
 196                         /* remove restart bit and enable master receive */
 197                         write_MASTER_CTL(iface,
 198                                 read_MASTER_CTL(iface) & ~RSTART);
 199                 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
 200                                 iface->cur_msg+1 < iface->msg_num) {
 201                         iface->cur_msg++;
 202                         iface->transPtr = iface->pmsg[iface->cur_msg].buf;
 203                         iface->writeNum = iface->readNum =
 204                                 iface->pmsg[iface->cur_msg].len;
 205                         /* Set Transmit device address */
 206                         write_MASTER_ADDR(iface,
 207                                 iface->pmsg[iface->cur_msg].addr);
 208                         if (iface->pmsg[iface->cur_msg].flags & I2C_M_RD)
 209                                 iface->read_write = I2C_SMBUS_READ;
 210                         else {
 211                                 iface->read_write = I2C_SMBUS_WRITE;
 212                                 /* Transmit first data */
 213                                 if (iface->writeNum > 0) {
 214                                         write_XMT_DATA8(iface,
 215                                                 *(iface->transPtr++));
 216                                         iface->writeNum--;
 217                                 }
 218                         }
 219
 220                         if (iface->pmsg[iface->cur_msg].len <= 255)
 221                                         write_MASTER_CTL(iface,
 222                                         (read_MASTER_CTL(iface) &
 223                                         (~(0xff << 6))) |
 224                                 (iface->pmsg[iface->cur_msg].len << 6));
 225                         else {
 226                                 write_MASTER_CTL(iface,
 227                                         (read_MASTER_CTL(iface) |
 228                                         (0xff << 6)));
 229                                 iface->manual_stop = 1;
 230                         }
 231                         /* remove restart bit and enable master receive */
 232                         write_MASTER_CTL(iface,
 233                                 read_MASTER_CTL(iface) & ~RSTART);
 234                 } else {
 235                         iface->result = 1;
 236                         write_INT_MASK(iface, 0);
 237                         write_MASTER_CTL(iface, 0);
 238                 }
 239         }
 240         complete(&iface->complete);
 241 }
 242
 243 /* Interrupt handler */
 244 static irqreturn_t bfin_twi_interrupt_entry(int irq, void *dev_id)
 245 {
 246         struct bfin_twi_iface *iface = dev_id;
 247         unsigned long flags;
 248         unsigned short twi_int_status;
 249
 250         spin_lock_irqsave(&iface->lock, flags);
 251         while (1) {
 252                 twi_int_status = read_INT_STAT(iface);
 253                 if (!twi_int_status)
 254                         break;
 255                 /* Clear interrupt status */
 256                 write_INT_STAT(iface, twi_int_status);
 257                 bfin_twi_handle_interrupt(iface, twi_int_status);
 258                 SSYNC();
 259         }
 260         spin_unlock_irqrestore(&iface->lock, flags);
 261         return IRQ_HANDLED;
 262 }
 263
 264 /*
 265  * One i2c master transfer
 266  */
 267 static int bfin_twi_do_master_xfer(struct i2c_adapter *adap,
 268                                 struct i2c_msg *msgs, int num)
 269 {
 270         struct bfin_twi_iface *iface = adap->algo_data;
 271         struct i2c_msg *pmsg;
 272         int rc = 0;
 273
 274         if (!(read_CONTROL(iface) & TWI_ENA))
 275                 return -ENXIO;
 276
 277         while (read_MASTER_STAT(iface) & BUSBUSY)
 278                 yield();
 279
 280         iface->pmsg = msgs;
 281         iface->msg_num = num;
 282         iface->cur_msg = 0;
 283
 284         pmsg = &msgs[0];
 285         if (pmsg->flags & I2C_M_TEN) {
 286                 dev_err(&adap->dev, "10 bits addr not supported!\n");
 287                 return -EINVAL;
 288         }
 289
 290         iface->cur_mode = TWI_I2C_MODE_REPEAT;
 291         iface->manual_stop = 0;
 292         iface->transPtr = pmsg->buf;
 293         iface->writeNum = iface->readNum = pmsg->len;
 294         iface->result = 0;
 295         init_completion(&(iface->complete));
 296         /* Set Transmit device address */
 297         write_MASTER_ADDR(iface, pmsg->addr);
 298
 299         /* FIFO Initiation. Data in FIFO should be
 300          *  discarded before start a new operation.
 301          */
 302         write_FIFO_CTL(iface, 0x3);
 303         SSYNC();
 304         write_FIFO_CTL(iface, 0);
 305         SSYNC();
 306
 307         if (pmsg->flags & I2C_M_RD)
 308                 iface->read_write = I2C_SMBUS_READ;
 309         else {
 310                 iface->read_write = I2C_SMBUS_WRITE;
 311                 /* Transmit first data */
 312                 if (iface->writeNum > 0) {
 313                         write_XMT_DATA8(iface, *(iface->transPtr++));
 314                         iface->writeNum--;
 315                         SSYNC();
 316                 }
 317         }
 318
 319         /* clear int stat */
 320         write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
 321
 322         /* Interrupt mask . Enable XMT, RCV interrupt */
 323         write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
 324         SSYNC();
 325
 326         if (pmsg->len <= 255)
 327                 write_MASTER_CTL(iface, pmsg->len << 6);
 328         else {
 329                 write_MASTER_CTL(iface, 0xff << 6);
 330                 iface->manual_stop = 1;
 331         }
 332
 333         /* Master enable */
 334         write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
 335                 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
 336                 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
 337         SSYNC();
 338
 339         while (!iface->result) {
 340                 if (!wait_for_completion_timeout(&iface->complete,
 341                         adap->timeout)) {
 342                         iface->result = -1;
 343                         dev_err(&adap->dev, "master transfer timeout\n");
 344                 }
 345         }
 346
 347         if (iface->result == 1)
 348                 rc = iface->cur_msg + 1;
 349         else
 350                 rc = iface->result;
 351
 352         return rc;
 353 }
 354
 355 /*
 356  * Generic i2c master transfer entrypoint
 357  */
 358 static int bfin_twi_master_xfer(struct i2c_adapter *adap,
 359                                 struct i2c_msg *msgs, int num)
 360 {
 361         int i, ret = 0;
 362
 363         for (i = 0; i < adap->retries; i++) {
 364                 ret = bfin_twi_do_master_xfer(adap, msgs, num);
 365                 if (ret > 0)
 366                         break;
 367         }
 368
 369         return ret;
 370 }
 371
 372 /*
 373  * One I2C SMBus transfer
 374  */
 375 int bfin_twi_do_smbus_xfer(struct i2c_adapter *adap, u16 addr,
 376                         unsigned short flags, char read_write,
 377                         u8 command, int size, union i2c_smbus_data *data)
 378 {
 379         struct bfin_twi_iface *iface = adap->algo_data;
 380         int rc = 0;
 381
 382         if (!(read_CONTROL(iface) & TWI_ENA))
 383                 return -ENXIO;
 384
 385         while (read_MASTER_STAT(iface) & BUSBUSY)
 386                 yield();
 387
 388         iface->writeNum = 0;
 389         iface->readNum = 0;
 390
 391         /* Prepare datas & select mode */
 392         switch (size) {
 393         case I2C_SMBUS_QUICK:
 394                 iface->transPtr = NULL;
 395                 iface->cur_mode = TWI_I2C_MODE_STANDARD;
 396                 break;
 397         case I2C_SMBUS_BYTE:
 398                 if (data == NULL)
 399                         iface->transPtr = NULL;
 400                 else {
 401                         if (read_write == I2C_SMBUS_READ)
 402                                 iface->readNum = 1;
 403                         else
 404                                 iface->writeNum = 1;
 405                         iface->transPtr = &data->byte;
 406                 }
 407                 iface->cur_mode = TWI_I2C_MODE_STANDARD;
 408                 break;
 409         case I2C_SMBUS_BYTE_DATA:
 410                 if (read_write == I2C_SMBUS_READ) {
 411                         iface->readNum = 1;
 412                         iface->cur_mode = TWI_I2C_MODE_COMBINED;
 413                 } else {
 414                         iface->writeNum = 1;
 415                         iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 416                 }
 417                 iface->transPtr = &data->byte;
 418                 break;
 419         case I2C_SMBUS_WORD_DATA:
 420                 if (read_write == I2C_SMBUS_READ) {
 421                         iface->readNum = 2;
 422                         iface->cur_mode = TWI_I2C_MODE_COMBINED;
 423                 } else {
 424                         iface->writeNum = 2;
 425                         iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 426                 }
 427                 iface->transPtr = (u8 *)&data->word;
 428                 break;
 429         case I2C_SMBUS_PROC_CALL:
 430                 iface->writeNum = 2;
 431                 iface->readNum = 2;
 432                 iface->cur_mode = TWI_I2C_MODE_COMBINED;
 433                 iface->transPtr = (u8 *)&data->word;
 434                 break;
 435         case I2C_SMBUS_BLOCK_DATA:
 436                 if (read_write == I2C_SMBUS_READ) {
 437                         iface->readNum = 0;
 438                         iface->cur_mode = TWI_I2C_MODE_COMBINED;
 439                 } else {
 440                         iface->writeNum = data->block[0] + 1;
 441                         iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 442                 }
 443                 iface->transPtr = data->block;
 444                 break;
 445         case I2C_SMBUS_I2C_BLOCK_DATA:
 446                 if (read_write == I2C_SMBUS_READ) {
 447                         iface->readNum = data->block[0];
 448                         iface->cur_mode = TWI_I2C_MODE_COMBINED;
 449                 } else {
 450                         iface->writeNum = data->block[0];
 451                         iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 452                 }
 453                 iface->transPtr = (u8 *)&data->block[1];
 454                 break;
 455         default:
 456                 return -1;
 457         }
 458
 459         iface->result = 0;
 460         iface->manual_stop = 0;
 461         iface->read_write = read_write;
 462         iface->command = command;
 463         init_completion(&(iface->complete));
 464
 465         /* FIFO Initiation. Data in FIFO should be discarded before
 466          * start a new operation.
 467          */
 468         write_FIFO_CTL(iface, 0x3);
 469         SSYNC();
 470         write_FIFO_CTL(iface, 0);
 471
 472         /* clear int stat */
 473         write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
 474
 475         /* Set Transmit device address */
 476         write_MASTER_ADDR(iface, addr);
 477         SSYNC();
 478
 479         switch (iface->cur_mode) {
 480         case TWI_I2C_MODE_STANDARDSUB:
 481                 write_XMT_DATA8(iface, iface->command);
 482                 write_INT_MASK(iface, MCOMP | MERR |
 483                         ((iface->read_write == I2C_SMBUS_READ) ?
 484                         RCVSERV : XMTSERV));
 485                 SSYNC();
 486
 487                 if (iface->writeNum + 1 <= 255)
 488                         write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
 489                 else {
 490                         write_MASTER_CTL(iface, 0xff << 6);
 491                         iface->manual_stop = 1;
 492                 }
 493                 /* Master enable */
 494                 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
 495                         ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
 496                 break;
 497         case TWI_I2C_MODE_COMBINED:
 498                 write_XMT_DATA8(iface, iface->command);
 499                 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
 500                 SSYNC();
 501
 502                 if (iface->writeNum > 0)
 503                         write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
 504                 else
 505                         write_MASTER_CTL(iface, 0x1 << 6);
 506                 /* Master enable */
 507                 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
 508                         ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
 509                 break;
 510         default:
 511                 write_MASTER_CTL(iface, 0);
 512                 if (size != I2C_SMBUS_QUICK) {
 513                         /* Don't access xmit data register when this is a
 514                          * read operation.
 515                          */
 516                         if (iface->read_write != I2C_SMBUS_READ) {
 517                                 if (iface->writeNum > 0) {
 518                                         write_XMT_DATA8(iface,
 519                                                 *(iface->transPtr++));
 520                                         if (iface->writeNum <= 255)
 521                                                 write_MASTER_CTL(iface,
 522                                                         iface->writeNum << 6);
 523                                         else {
 524                                                 write_MASTER_CTL(iface,
 525                                                         0xff << 6);
 526                                                 iface->manual_stop = 1;
 527                                         }
 528                                         iface->writeNum--;
 529                                 } else {
 530                                         write_XMT_DATA8(iface, iface->command);
 531                                         write_MASTER_CTL(iface, 1 << 6);
 532                                 }
 533                         } else {
 534                                 if (iface->readNum > 0 && iface->readNum <= 255)
 535                                         write_MASTER_CTL(iface,
 536                                                 iface->readNum << 6);
 537                                 else if (iface->readNum > 255) {
 538                                         write_MASTER_CTL(iface, 0xff << 6);
 539                                         iface->manual_stop = 1;
 540                                 } else
 541                                         break;
 542                         }
 543                 }
 544                 write_INT_MASK(iface, MCOMP | MERR |
 545                         ((iface->read_write == I2C_SMBUS_READ) ?
 546                         RCVSERV : XMTSERV));
 547                 SSYNC();
 548
 549                 /* Master enable */
 550                 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
 551                         ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
 552                         ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
 553                 break;
 554         }
 555         SSYNC();
 556
 557         while (!iface->result) {
 558                 if (!wait_for_completion_timeout(&iface->complete,
 559                         adap->timeout)) {
 560                         iface->result = -1;
 561                         dev_err(&adap->dev, "smbus transfer timeout\n");
 562                 }
 563         }
 564
 565         rc = (iface->result >= 0) ? 0 : -1;
 566
 567         return rc;
 568 }
 569
 570 /*
 571  * Generic I2C SMBus transfer entrypoint
 572  */
 573 int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
 574                         unsigned short flags, char read_write,
 575                         u8 command, int size, union i2c_smbus_data *data)
 576 {
 577         int i, ret = 0;
 578
 579         for (i = 0; i < adap->retries; i++) {
 580                 ret = bfin_twi_do_smbus_xfer(adap, addr, flags,
 581                         read_write, command, size, data);
 582                 if (ret == 0)
 583                         break;
 584         }
 585
 586         return ret;
 587 }
 588
 589 /*
 590  * Return what the adapter supports
 591  */
 592 static u32 bfin_twi_functionality(struct i2c_adapter *adap)
 593 {
 594         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 595                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 596                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL |
 597                I2C_FUNC_I2C | I2C_FUNC_SMBUS_I2C_BLOCK;
 598 }
 599
 600 static struct i2c_algorithm bfin_twi_algorithm = {
 601         .master_xfer   = bfin_twi_master_xfer,
 602         .smbus_xfer    = bfin_twi_smbus_xfer,
 603         .functionality = bfin_twi_functionality,
 604 };
 605
 606 static int i2c_bfin_twi_suspend(struct platform_device *pdev, pm_message_t state)
 607 {
 608         struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
 609
 610         iface->saved_clkdiv = read_CLKDIV(iface);
 611         iface->saved_control = read_CONTROL(iface);
 612
 613         free_irq(iface->irq, iface);
 614
 615         /* Disable TWI */
 616         write_CONTROL(iface, iface->saved_control & ~TWI_ENA);
 617
 618         return 0;
 619 }
 620
 621 static int i2c_bfin_twi_resume(struct platform_device *pdev)
 622 {
 623         struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
 624
 625         int rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
 626                 IRQF_DISABLED, pdev->name, iface);
 627         if (rc) {
 628                 dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
 629                 return -ENODEV;
 630         }
 631
 632         /* Resume TWI interface clock as specified */
 633         write_CLKDIV(iface, iface->saved_clkdiv);
 634
 635         /* Resume TWI */
 636         write_CONTROL(iface, iface->saved_control);
 637
 638         return 0;
 639 }
 640
 641 static int i2c_bfin_twi_probe(struct platform_device *pdev)
 642 {
 643         struct bfin_twi_iface *iface;
 644         struct i2c_adapter *p_adap;
 645         struct resource *res;
 646         int rc;
 647         unsigned int clkhilow;
 648
 649         iface = kzalloc(sizeof(struct bfin_twi_iface), GFP_KERNEL);
 650         if (!iface) {
 651                 dev_err(&pdev->dev, "Cannot allocate memory\n");
 652                 rc = -ENOMEM;
 653                 goto out_error_nomem;
 654         }
 655
 656         spin_lock_init(&(iface->lock));
 657
 658         /* Find and map our resources */
 659         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 660         if (res == NULL) {
 661                 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
 662                 rc = -ENOENT;
 663                 goto out_error_get_res;
 664         }
 665
 666         iface->regs_base = ioremap(res->start, resource_size(res));
 667         if (iface->regs_base == NULL) {
 668                 dev_err(&pdev->dev, "Cannot map IO\n");
 669                 rc = -ENXIO;
 670                 goto out_error_ioremap;
 671         }
 672
 673         iface->irq = platform_get_irq(pdev, 0);
 674         if (iface->irq < 0) {
 675                 dev_err(&pdev->dev, "No IRQ specified\n");
 676                 rc = -ENOENT;
 677                 goto out_error_no_irq;
 678         }
 679
 680         p_adap = &iface->adap;
 681         p_adap->nr = pdev->id;
 682         strlcpy(p_adap->name, pdev->name, sizeof(p_adap->name));
 683         p_adap->algo = &bfin_twi_algorithm;
 684         p_adap->algo_data = iface;
 685         p_adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
 686         p_adap->dev.parent = &pdev->dev;
 687         p_adap->timeout = 5 * HZ;
 688         p_adap->retries = 3;
 689
 690         rc = peripheral_request_list(pin_req[pdev->id], "i2c-bfin-twi");
 691         if (rc) {
 692                 dev_err(&pdev->dev, "Can't setup pin mux!\n");
 693                 goto out_error_pin_mux;
 694         }
 695
 696         rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
 697                 IRQF_DISABLED, pdev->name, iface);
 698         if (rc) {
 699                 dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
 700                 rc = -ENODEV;
 701                 goto out_error_req_irq;
 702         }
 703
 704         /* Set TWI internal clock as 10MHz */
 705         write_CONTROL(iface, ((get_sclk() / 1000 / 1000 + 5) / 10) & 0x7F);
 706
 707         /*
 708          * We will not end up with a CLKDIV=0 because no one will specify
 709          * 20kHz SCL or less in Kconfig now. (5 * 1000 / 20 = 250)
 710          */
 711         clkhilow = ((10 * 1000 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ) + 1) / 2;
 712
 713         /* Set Twi interface clock as specified */
 714         write_CLKDIV(iface, (clkhilow << 8) | clkhilow);
 715
 716         /* Enable TWI */
 717         write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA);
 718         SSYNC();
 719
 720         rc = i2c_add_numbered_adapter(p_adap);
 721         if (rc < 0) {
 722                 dev_err(&pdev->dev, "Can't add i2c adapter!\n");
 723                 goto out_error_add_adapter;
 724         }
 725
 726         platform_set_drvdata(pdev, iface);
 727
 728         dev_info(&pdev->dev, "Blackfin BF5xx on-chip I2C TWI Contoller, "
 729                 "regs_base@%p\n", iface->regs_base);
 730
 731         return 0;
 732
 733 out_error_add_adapter:
 734         free_irq(iface->irq, iface);
 735 out_error_req_irq:
 736 out_error_no_irq:
 737         peripheral_free_list(pin_req[pdev->id]);
 738 out_error_pin_mux:
 739         iounmap(iface->regs_base);
 740 out_error_ioremap:
 741 out_error_get_res:
 742         kfree(iface);
 743 out_error_nomem:
 744         return rc;
 745 }
 746
 747 static int i2c_bfin_twi_remove(struct platform_device *pdev)
 748 {
 749         struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
 750
 751         platform_set_drvdata(pdev, NULL);
 752
 753         i2c_del_adapter(&(iface->adap));
 754         free_irq(iface->irq, iface);
 755         peripheral_free_list(pin_req[pdev->id]);
 756         iounmap(iface->regs_base);
 757         kfree(iface);
 758
 759         return 0;
 760 }
 761
 762 static struct platform_driver i2c_bfin_twi_driver = {
 763         .probe          = i2c_bfin_twi_probe,
 764         .remove         = i2c_bfin_twi_remove,
 765         .suspend        = i2c_bfin_twi_suspend,
 766         .resume         = i2c_bfin_twi_resume,
 767         .driver         = {
 768                 .name   = "i2c-bfin-twi",
 769                 .owner  = THIS_MODULE,
 770         },
 771 };
 772
 773 static int __init i2c_bfin_twi_init(void)
 774 {
 775         return platform_driver_register(&i2c_bfin_twi_driver);
 776 }
 777
 778 static void __exit i2c_bfin_twi_exit(void)
 779 {
 780         platform_driver_unregister(&i2c_bfin_twi_driver);
 781 }
 782
 783 module_init(i2c_bfin_twi_init);
 784 module_exit(i2c_bfin_twi_exit);
 785
 786 MODULE_AUTHOR("Bryan Wu, Sonic Zhang");
 787 MODULE_DESCRIPTION("Blackfin BF5xx on-chip I2C TWI Contoller Driver");
 788 MODULE_LICENSE("GPL");
 789 MODULE_ALIAS("platform:i2c-bfin-twi");